OpenCores
URL https://opencores.org/ocsvn/minsoc/minsoc/trunk

Subversion Repositories minsoc

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Rev 1 → Rev 109

/rc-1.0/prj/scripts/simvhdl.sh
0,0 → 1,58
#!/bin/bash
 
#system workings
MINSOC_DIR=`pwd`/..
 
PROJECT=$1
OUTPUT=$2
 
ENV=`uname -o`
 
function adaptpath
{
if [ "$ENV" == "Cygwin" ]
then
local cygpath=`cygpath -w $1`
local result=`echo $cygpath | sed 's/\\\\/\\//g'`
echo "$result"
else
echo "$1"
fi
}
 
if [ ! -f $PROJECT ]
then
echo "Unexistent project file."
exit 1
fi
 
if [ -z "$OUTPUT" ]
then
echo "Second argument should be the destintion file for the file and directory inclusions."
exit 1
fi
echo -n "" > $OUTPUT
 
source $PROJECT
 
for file in "${PROJECT_SRC[@]}"
do
FOUND=0
 
for dir in "${PROJECT_DIR[@]}"
do
if [ -f $MINSOC_DIR/$dir/$file ]
then
adapted_file=`adaptpath $MINSOC_DIR/$dir/$file`
echo "$adapted_file" >> $OUTPUT
FOUND=1
break
fi
done
 
if [ $FOUND != 1 ]
then
echo "FILE NOT FOUND"
exit 1
fi
done
rc-1.0/prj/scripts/simvhdl.sh Property changes : Added: svn:executable ## -0,0 +1 ## +* \ No newline at end of property Index: rc-1.0/prj/scripts/xilinxprj.sh =================================================================== --- rc-1.0/prj/scripts/xilinxprj.sh (nonexistent) +++ rc-1.0/prj/scripts/xilinxprj.sh (revision 109) @@ -0,0 +1,72 @@ +#!/bin/bash + +#system workings +MINSOC_DIR=`pwd`/.. + +PROJECT=$1 +SRC_OUTPUT=$2 +TOP_MODULE=$3 + +ENV=`uname -o` + +function adaptpath +{ + if [ "$ENV" == "Cygwin" ] + then + local cygpath=`cygpath -w $1` + echo "$cygpath" + else + echo "$1" + fi +} + +if [ ! -f $PROJECT ] +then + echo "Unexistent project file." + exit 1 +fi + +if [ -z "$SRC_OUTPUT" ] +then + echo "Third argument should be the destintion file for the source inclusions." + exit 1 +fi +echo -n "" > $SRC_OUTPUT + +source $PROJECT + +for file in "${PROJECT_SRC[@]}" +do + FOUND=0 + + for dir in "${PROJECT_DIR[@]}" + do + if [ -f $MINSOC_DIR/$dir/$file ] + then + adapted_file=`adaptpath $MINSOC_DIR/$dir/$file` + echo -n '`include "' >> $SRC_OUTPUT + echo -n "$adapted_file" >> $SRC_OUTPUT + echo '"' >> $SRC_OUTPUT + FOUND=1 + break + fi + done + + if [ $FOUND != 1 ] + then + echo "FILE NOT FOUND" + exit 1 + fi +done + +if [ -n "$TOP_MODULE" ] +then + for file in src/blackboxes/*.v + do + dir=`pwd` + adapted_file=`adaptpath $dir/$file` + echo -n '`include "' >> $SRC_OUTPUT + echo -n "$adapted_file" >> $SRC_OUTPUT + echo '"' >> $SRC_OUTPUT + done +fi
rc-1.0/prj/scripts/xilinxprj.sh Property changes : Added: svn:executable ## -0,0 +1 ## +* \ No newline at end of property Index: rc-1.0/prj/scripts/xilinxxst.sh =================================================================== --- rc-1.0/prj/scripts/xilinxxst.sh (nonexistent) +++ rc-1.0/prj/scripts/xilinxxst.sh (revision 109) @@ -0,0 +1,68 @@ +#!/bin/bash + +#system workings +MINSOC_DIR=`pwd`/.. + +PROJECT=$1 +DIR_OUTPUT=$2 +PROJECT_FILE=$3 +TOP_MODULE_NAME=$4 +TOP_MODULE=$5 + +ENV=`uname -o` + +function adaptpath +{ + if [ "$ENV" == "Cygwin" ] + then + local cygpath=`cygpath -w $1` + echo "$cygpath" + else + echo "$1" + fi +} + +if [ ! -f $PROJECT ] +then + echo "Unexistent project file." + exit 1 +fi + +if [ -z "$DIR_OUTPUT" ] +then + echo "Second argument should be the destintion file for the directory inclusions." + exit 1 +fi +echo -n "" > $DIR_OUTPUT + +source $PROJECT + +echo "set -tmpdir "./xst"" >> $DIR_OUTPUT +echo "run" >> $DIR_OUTPUT + +DIR_PATH="-vlgincdir {" + +for dir in "${PROJECT_DIR[@]}" +do + adapted_dir=`adaptpath $MINSOC_DIR/$dir` + DIR_PATH="$DIR_PATH \"$adapted_dir\" " +done + +DIR_PATH="$DIR_PATH }" +echo $DIR_PATH >> $DIR_OUTPUT + +adapted_project_file=`adaptpath $MINSOC_DIR/prj/xilinx/${PROJECT_FILE}` +echo "-ifn $adapted_project_file" >> $DIR_OUTPUT +echo "-ifmt Verilog" >> $DIR_OUTPUT +echo "-ofn ${TOP_MODULE_NAME}" >> $DIR_OUTPUT +echo "-ofmt NGC" >> $DIR_OUTPUT +echo "-p DEVICE_PART" >> $DIR_OUTPUT +echo "-top ${TOP_MODULE_NAME}" >> $DIR_OUTPUT +echo "-opt_mode Speed" >> $DIR_OUTPUT +echo "-opt_level 1" >> $DIR_OUTPUT +if [ -n "$TOP_MODULE" ] +then + echo "-iobuf yes" >> $DIR_OUTPUT +else + echo "-iobuf no" >> $DIR_OUTPUT +fi
rc-1.0/prj/scripts/xilinxxst.sh Property changes : Added: svn:executable ## -0,0 +1 ## +* \ No newline at end of property Index: rc-1.0/prj/scripts/simverilog.sh =================================================================== --- rc-1.0/prj/scripts/simverilog.sh (nonexistent) +++ rc-1.0/prj/scripts/simverilog.sh (revision 109) @@ -0,0 +1,64 @@ +#!/bin/bash + +#system workings +MINSOC_DIR=`pwd`/.. + +PROJECT=$1 +OUTPUT=$2 + +ENV=`uname -o` + +function adaptpath +{ + if [ "$ENV" == "Cygwin" ] + then + local cygpath=`cygpath -w $1` + local result=`echo $cygpath | sed 's/\\\\/\\//g'` + echo "$result" + else + echo "$1" + fi +} + +if [ ! -f $PROJECT ] +then + echo "Unexistent project file." + exit 1 +fi + +if [ -z "$OUTPUT" ] +then + echo "Second argument should be the destintion file for the file and directory inclusions." + exit 1 +fi +echo -n "" > $OUTPUT + +source $PROJECT + +for dir in "${PROJECT_DIR[@]}" +do + adapted_dir=`adaptpath $MINSOC_DIR/$dir` + echo "+incdir+$adapted_dir" >> $OUTPUT +done + +for file in "${PROJECT_SRC[@]}" +do + FOUND=0 + + for dir in "${PROJECT_DIR[@]}" + do + if [ -f $MINSOC_DIR/$dir/$file ] + then + adapted_file=`adaptpath $MINSOC_DIR/$dir/$file` + echo "$adapted_file" >> $OUTPUT + FOUND=1 + break + fi + done + + if [ $FOUND != 1 ] + then + echo "FILE NOT FOUND" + exit 1 + fi +done
rc-1.0/prj/scripts/simverilog.sh Property changes : Added: svn:executable ## -0,0 +1 ## +* \ No newline at end of property Index: rc-1.0/prj/scripts/altprj.sh =================================================================== --- rc-1.0/prj/scripts/altprj.sh (nonexistent) +++ rc-1.0/prj/scripts/altprj.sh (revision 109) @@ -0,0 +1,70 @@ +#!/bin/bash + +#system workings +MINSOC_DIR=`pwd`/.. + +PROJECT=$1 +OUTPUT=$2 + +ENV=`uname -o` + +function adaptpath +{ + if [ "$ENV" == "Cygwin" ] + then + local cygpath=`cygpath -w $1` + local result=`echo $cygpath | sed 's/\\\\/\\//g'` + echo "$result" + else + echo "$1" + fi +} + +if [ ! -f $PROJECT ] +then + echo "Unexistent project file." + exit 1 +fi + +if [ -z "$OUTPUT" ] +then + echo "Second argument should be the destintion file for the file and directory inclusions." + exit 1 +fi +echo -n "" > $OUTPUT + +source $PROJECT + +for dir in "${PROJECT_DIR[@]}" +do + adapted_dir=`adaptpath $MINSOC_DIR/$dir` + echo "set_global_assignment -name SEARCH_PATH $adapted_dir" >> $OUTPUT +done + +for file in "${PROJECT_SRC[@]}" +do + FOUND=0 + + for dir in "${PROJECT_DIR[@]}" + do + if [ -f $MINSOC_DIR/$dir/$file ] + then + adapted_file=`adaptpath $MINSOC_DIR/$dir/$file` + is_vhdl=`ls $MINSOC_DIR/$dir/$file | grep vhd` + if [ -z $is_vhdl ] + then + echo "set_global_assignment -name VERILOG_FILE $adapted_file" >> $OUTPUT + else + echo "set_global_assignment -name VHDL_FILE $adapted_file" >> $OUTPUT + fi + FOUND=1 + break + fi + done + + if [ $FOUND != 1 ] + then + echo "FILE NOT FOUND" + exit 1 + fi +done
rc-1.0/prj/scripts/altprj.sh Property changes : Added: svn:executable ## -0,0 +1 ## +* \ No newline at end of property Index: rc-1.0/prj/Makefile =================================================================== --- rc-1.0/prj/Makefile (nonexistent) +++ rc-1.0/prj/Makefile (revision 109) @@ -0,0 +1,49 @@ +VERILOG_PROJECTS = minsoc_bench.prj minsoc_top.prj or1200_top.prj adbg_top.prj jtag_top.prj uart_top.prj ethmac.prj +VHDL_PROJECTS = altera_virtual_jtag.prj + +PROJECTS = $(VERILOG_PROJECTS) $(VHDL_PROJECTS) +SRC_DIR = src +SCRIPTS_DIR = scripts + +SIMULATION_DIR = sim +XILINX_DIR = xilinx +ALTERA_DIR = altera + +SIM_VERILOG_FILES = $(addprefix $(SIMULATION_DIR)/, $(addsuffix .verilog, $(basename $(VERILOG_PROJECTS)))) +SIM_VHDL_FILES = $(addprefix $(SIMULATION_DIR)/, $(addsuffix .vhdl, $(basename $(VHDL_PROJECTS)))) +XILINX_PRJ_FILES = $(addprefix $(XILINX_DIR)/, $(addsuffix .prj, $(basename $(PROJECTS)))) +XILINX_XST_FILES = $(addprefix $(XILINX_DIR)/, $(addsuffix .xst, $(basename $(PROJECTS)))) +ALTERA_PRJ_FILES = $(addprefix $(ALTERA_DIR)/, $(addsuffix .prj, $(basename $(PROJECTS)))) + +all: $(SIMULATION_DIR)/minsoc_verilog.src $(SIMULATION_DIR)/minsoc_vhdl.src $(XILINX_PRJ_FILES) $(XILINX_XST_FILES) $(ALTERA_PRJ_FILES) + +clean: + rm -rf $(SIMULATION_DIR)/*.verilog $(SIMULATION_DIR)/*.vhdl $(SIMULATION_DIR)/*.src $(XILINX_DIR)/*.prj $(XILINX_DIR)/*.xst $(ALTERA_DIR)/*.prj + +$(XILINX_DIR)/minsoc_top.xst: $(SRC_DIR)/minsoc_top.prj + bash $(SCRIPTS_DIR)/xilinxxst.sh $^ $@ minsoc_top.prj minsoc_top topmodule + +$(XILINX_DIR)/minsoc_top.prj: $(SRC_DIR)/minsoc_top.prj + bash $(SCRIPTS_DIR)/xilinxprj.sh $^ $@ topmodule + +$(XILINX_DIR)/%.xst: $(SRC_DIR)/%.prj + bash $(SCRIPTS_DIR)/xilinxxst.sh $^ $@ $*.prj $* + +$(XILINX_DIR)/%.prj: $(SRC_DIR)/%.prj + bash $(SCRIPTS_DIR)/xilinxprj.sh $^ $@ + +$(ALTERA_DIR)/%.prj: $(SRC_DIR)/%.prj + bash $(SCRIPTS_DIR)/altprj.sh $^ $@ + +$(SIMULATION_DIR)/minsoc_verilog.src: $(SIM_VERILOG_FILES) + cat $(SIM_VERILOG_FILES) > $(SIMULATION_DIR)/minsoc_verilog.src + +$(SIMULATION_DIR)/minsoc_vhdl.src: $(SIM_VHDL_FILES) + cat $(SIM_VHDL_FILES) > $(SIMULATION_DIR)/minsoc_vhdl.src + +$(SIMULATION_DIR)/%.verilog: $(SRC_DIR)/%.prj + bash $(SCRIPTS_DIR)/simverilog.sh $^ $@ + +$(SIMULATION_DIR)/%.vhdl: $(SRC_DIR)/%.prj + bash $(SCRIPTS_DIR)/simvhdl.sh $^ $@ + Index: rc-1.0/prj/src/altera_virtual_jtag.prj =================================================================== --- rc-1.0/prj/src/altera_virtual_jtag.prj (nonexistent) +++ rc-1.0/prj/src/altera_virtual_jtag.prj (revision 109) @@ -0,0 +1,2 @@ +PROJECT_DIR=rtl/verilog/adv_debug_sys/Hardware/altera_virtual_jtag/rtl/vhdl/ +PROJECT_SRC=altera_virtual_jtag.vhd Index: rc-1.0/prj/src/minsoc_top.prj =================================================================== --- rc-1.0/prj/src/minsoc_top.prj (nonexistent) +++ rc-1.0/prj/src/minsoc_top.prj (revision 109) @@ -0,0 +1,17 @@ +PROJECT_DIR=(backend rtl/verilog rtl/verilog/minsoc_startup rtl/verilog/or1200/rtl/verilog rtl/verilog/adv_debug_sys/Hardware/adv_dbg_if/rtl/verilog rtl/verilog/ethmac/rtl/verilog rtl/verilog/uart16550/rtl/verilog) +PROJECT_SRC=(minsoc_defines.v +timescale.v +minsoc_top.v +minsoc_tc_top.v +minsoc_onchip_ram.v +minsoc_onchip_ram_top.v +minsoc_clock_manager.v +altera_pll.v +xilinx_dcm.v +minsoc_xilinx_internal_jtag.v +spi_top.v +spi_defines.v +spi_shift.v +spi_clgen.v +OR1K_startup_generic.v) + Index: rc-1.0/prj/src/minsoc_bench.prj =================================================================== --- rc-1.0/prj/src/minsoc_bench.prj (nonexistent) +++ rc-1.0/prj/src/minsoc_bench.prj (revision 109) @@ -0,0 +1,8 @@ +PROJECT_DIR=(backend bench/verilog bench/verilog/vpi bench/verilog/sim_lib rtl/verilog) +PROJECT_SRC=(minsoc_bench_defines.v +minsoc_bench.v +minsoc_memory_model.v +dbg_comm_vpi.v +fpga_memory_primitives.v +timescale.v) + Index: rc-1.0/prj/src/or1200_top.prj =================================================================== --- rc-1.0/prj/src/or1200_top.prj (nonexistent) +++ rc-1.0/prj/src/or1200_top.prj (revision 109) @@ -0,0 +1,64 @@ +PROJECT_DIR=rtl/verilog/or1200/rtl/verilog +PROJECT_SRC=(or1200_spram_512x20.v +or1200_spram_64x24.v +or1200_du.v +or1200_spram_2048x32_bw.v +or1200_rf.v +or1200_alu.v +or1200_dmmu_top.v +or1200_lsu.v +or1200_spram_1024x32.v +or1200_dc_top.v +or1200_cpu.v +or1200_gmultp2_32x32.v +or1200_immu_top.v +or1200_dpram_256x32.v +or1200_tt.v +or1200_iwb_biu.v +or1200_rfram_generic.v +or1200_dc_tag.v +or1200_spram_2048x8.v +or1200_immu_tlb.v +or1200_ic_tag.v +or1200_spram_64x14.v +or1200_spram_32x24.v +or1200_dpram_32x32.v +or1200_xcv_ram32x8d.v +or1200_spram_1024x8.v +or1200_mem2reg.v +or1200_pm.v +or1200_spram_256x21.v +or1200_operandmuxes.v +or1200_pic.v +or1200_cfgr.v +or1200_if.v +or1200_qmem_top.v +or1200_genpc.v +or1200_defines.v +or1200_wbmux.v +or1200_ic_ram.v +or1200_dmmu_tlb.v +or1200_sb_fifo.v +or1200_sprs.v +or1200_tpram_32x32.v +or1200_ctrl.v +or1200_sb.v +or1200_mult_mac.v +or1200_ic_fsm.v +or1200_amultp2_32x32.v +or1200_reg2mem.v +or1200_spram_2048x32.v +or1200_except.v +or1200_top.v +or1200_ic_top.v +or1200_dc_ram.v +or1200_spram_1024x32_bw.v +or1200_freeze.v +or1200_spram_128x32.v +or1200_dc_fsm.v +or1200_wb_biu.v +or1200_spram_64x22.v +or1200_fpu.v +or1200_spram.v +or1200_spram_32_bw.v +or1200_dpram.v) Index: rc-1.0/prj/src/jtag_top.prj =================================================================== --- rc-1.0/prj/src/jtag_top.prj (nonexistent) +++ rc-1.0/prj/src/jtag_top.prj (revision 109) @@ -0,0 +1,3 @@ +PROJECT_DIR=rtl/verilog/adv_debug_sys/Hardware/jtag/tap/rtl/verilog +PROJECT_SRC=(tap_top.v +tap_defines.v) Index: rc-1.0/prj/src/uart_top.prj =================================================================== --- rc-1.0/prj/src/uart_top.prj (nonexistent) +++ rc-1.0/prj/src/uart_top.prj (revision 109) @@ -0,0 +1,12 @@ +PROJECT_DIR=rtl/verilog/uart16550/rtl/verilog +PROJECT_SRC=(uart_top.v +uart_sync_flops.v +uart_transmitter.v +uart_debug_if.v +uart_wb.v +uart_receiver.v +uart_tfifo.v +uart_regs.v +uart_rfifo.v +uart_defines.v +raminfr.v) Index: rc-1.0/prj/src/adbg_top.prj =================================================================== --- rc-1.0/prj/src/adbg_top.prj (nonexistent) +++ rc-1.0/prj/src/adbg_top.prj (revision 109) @@ -0,0 +1,11 @@ +PROJECT_DIR=rtl/verilog/adv_debug_sys/Hardware/adv_dbg_if/rtl/verilog +PROJECT_SRC=(adbg_wb_biu.v +adbg_wb_module.v +adbg_or1k_module.v +adbg_wb_defines.v +adbg_defines.v +adbg_crc32.v +adbg_or1k_biu.v +adbg_or1k_defines.v +adbg_or1k_status_reg.v +adbg_top.v) Index: rc-1.0/prj/src/ethmac.prj =================================================================== --- rc-1.0/prj/src/ethmac.prj (nonexistent) +++ rc-1.0/prj/src/ethmac.prj (revision 109) @@ -0,0 +1,26 @@ +PROJECT_DIR=rtl/verilog/ethmac/rtl/verilog +PROJECT_SRC=(eth_cop.v +eth_registers.v +eth_rxethmac.v +eth_miim.v +ethmac.v +eth_rxaddrcheck.v +eth_outputcontrol.v +eth_rxstatem.v +eth_txethmac.v +eth_wishbone.v +eth_maccontrol.v +eth_txstatem.v +ethmac_defines.v +eth_spram_256x32.v +eth_shiftreg.v +eth_clockgen.v +eth_crc.v +eth_rxcounters.v +eth_macstatus.v +eth_random.v +eth_register.v +eth_fifo.v +eth_receivecontrol.v +eth_transmitcontrol.v +eth_txcounters.v) Index: rc-1.0/prj/src/blackboxes/ethmac.v =================================================================== --- rc-1.0/prj/src/blackboxes/ethmac.v (nonexistent) +++ rc-1.0/prj/src/blackboxes/ethmac.v (revision 109) @@ -0,0 +1,113 @@ + + +`include "ethmac_defines.v" + +module ethmac +( + // WISHBONE common + wb_clk_i, wb_rst_i, wb_dat_i, wb_dat_o, + + // WISHBONE slave + wb_adr_i, wb_sel_i, wb_we_i, wb_cyc_i, wb_stb_i, wb_ack_o, wb_err_o, + + // WISHBONE master + m_wb_adr_o, m_wb_sel_o, m_wb_we_o, + m_wb_dat_o, m_wb_dat_i, m_wb_cyc_o, + m_wb_stb_o, m_wb_ack_i, m_wb_err_i, + +`ifdef ETH_WISHBONE_B3 + m_wb_cti_o, m_wb_bte_o, +`endif + + //TX + mtx_clk_pad_i, mtxd_pad_o, mtxen_pad_o, mtxerr_pad_o, + + //RX + mrx_clk_pad_i, mrxd_pad_i, mrxdv_pad_i, mrxerr_pad_i, mcoll_pad_i, mcrs_pad_i, + + // MIIM + mdc_pad_o, md_pad_i, md_pad_o, md_padoe_o, + + int_o + + // Bist +`ifdef ETH_BIST + , + // debug chain signals + mbist_si_i, // bist scan serial in + mbist_so_o, // bist scan serial out + mbist_ctrl_i // bist chain shift control +`endif + +); + + +parameter Tp = 1; + + +// WISHBONE common +input wb_clk_i; // WISHBONE clock +input wb_rst_i; // WISHBONE reset +input [31:0] wb_dat_i; // WISHBONE data input +output [31:0] wb_dat_o; // WISHBONE data output +output wb_err_o; // WISHBONE error output + +// WISHBONE slave +input [11:2] wb_adr_i; // WISHBONE address input +input [3:0] wb_sel_i; // WISHBONE byte select input +input wb_we_i; // WISHBONE write enable input +input wb_cyc_i; // WISHBONE cycle input +input wb_stb_i; // WISHBONE strobe input +output wb_ack_o; // WISHBONE acknowledge output + +// WISHBONE master +output [31:0] m_wb_adr_o; +output [3:0] m_wb_sel_o; +output m_wb_we_o; +input [31:0] m_wb_dat_i; +output [31:0] m_wb_dat_o; +output m_wb_cyc_o; +output m_wb_stb_o; +input m_wb_ack_i; +input m_wb_err_i; + +wire [29:0] m_wb_adr_tmp; + +`ifdef ETH_WISHBONE_B3 +output [2:0] m_wb_cti_o; // Cycle Type Identifier +output [1:0] m_wb_bte_o; // Burst Type Extension +`endif + +// Tx +input mtx_clk_pad_i; // Transmit clock (from PHY) +output [3:0] mtxd_pad_o; // Transmit nibble (to PHY) +output mtxen_pad_o; // Transmit enable (to PHY) +output mtxerr_pad_o; // Transmit error (to PHY) + +// Rx +input mrx_clk_pad_i; // Receive clock (from PHY) +input [3:0] mrxd_pad_i; // Receive nibble (from PHY) +input mrxdv_pad_i; // Receive data valid (from PHY) +input mrxerr_pad_i; // Receive data error (from PHY) + +// Common Tx and Rx +input mcoll_pad_i; // Collision (from PHY) +input mcrs_pad_i; // Carrier sense (from PHY) + +// MII Management interface +input md_pad_i; // MII data input (from I/O cell) +output mdc_pad_o; // MII Management data clock (to PHY) +output md_pad_o; // MII data output (to I/O cell) +output md_padoe_o; // MII data output enable (to I/O cell) + +output int_o; // Interrupt output + +// Bist +`ifdef ETH_BIST +input mbist_si_i; // bist scan serial in +output mbist_so_o; // bist scan serial out +input [`ETH_MBIST_CTRL_WIDTH - 1:0] mbist_ctrl_i; // bist chain shift control +`endif + + +endmodule Index: rc-1.0/prj/src/blackboxes/uart_top.v =================================================================== --- rc-1.0/prj/src/blackboxes/uart_top.v (nonexistent) +++ rc-1.0/prj/src/blackboxes/uart_top.v (revision 109) @@ -0,0 +1,58 @@ + + +`include "uart_defines.v" + +module uart_top ( + wb_clk_i, + + // Wishbone signals + wb_rst_i, wb_adr_i, wb_dat_i, wb_dat_o, wb_we_i, wb_stb_i, wb_cyc_i, wb_ack_o, wb_sel_i, + int_o, // interrupt request + + // UART signals + // serial input/output + stx_pad_o, srx_pad_i, + + // modem signals + rts_pad_o, cts_pad_i, dtr_pad_o, dsr_pad_i, ri_pad_i, dcd_pad_i +`ifdef UART_HAS_BAUDRATE_OUTPUT + , baud_o +`endif + ); + +parameter uart_data_width = `UART_DATA_WIDTH; +parameter uart_addr_width = `UART_ADDR_WIDTH; + +input wb_clk_i; + +// WISHBONE interface +input wb_rst_i; +input [uart_addr_width-1:0] wb_adr_i; +input [uart_data_width-1:0] wb_dat_i; +output [uart_data_width-1:0] wb_dat_o; +input wb_we_i; +input wb_stb_i; +input wb_cyc_i; +input [3:0] wb_sel_i; +output wb_ack_o; +output int_o; + +// UART signals +input srx_pad_i; +output stx_pad_o; +output rts_pad_o; +input cts_pad_i; +output dtr_pad_o; +input dsr_pad_i; +input ri_pad_i; +input dcd_pad_i; + +// optional baudrate output +`ifdef UART_HAS_BAUDRATE_OUTPUT +output baud_o; +`endif + + +endmodule + + Index: rc-1.0/prj/src/blackboxes/adbg_top.v =================================================================== --- rc-1.0/prj/src/blackboxes/adbg_top.v (nonexistent) +++ rc-1.0/prj/src/blackboxes/adbg_top.v (revision 109) @@ -0,0 +1,180 @@ + + +`include "adbg_defines.v" + +module adbg_top( + // JTAG signals + tck_i, + tdi_i, + tdo_o, + rst_i, + + + // TAP states + shift_dr_i, + pause_dr_i, + update_dr_i, + capture_dr_i, + + // Instructions + debug_select_i + + + `ifdef DBG_WISHBONE_SUPPORTED + // WISHBONE common signals + , + wb_clk_i, + wb_rst_i, + + // WISHBONE master interface + wb_adr_o, + wb_dat_o, + wb_dat_i, + wb_cyc_o, + wb_stb_o, + wb_sel_o, + wb_we_o, + wb_ack_i, + wb_cab_o, + wb_err_i, + wb_cti_o, + wb_bte_o + `endif + + `ifdef DBG_CPU0_SUPPORTED + // CPU signals + , + cpu0_clk_i, + cpu0_addr_o, + cpu0_data_i, + cpu0_data_o, + cpu0_bp_i, + cpu0_stall_o, + cpu0_stb_o, + cpu0_we_o, + cpu0_ack_i, + cpu0_rst_o + `endif + + `ifdef DBG_CPU1_SUPPORTED + // CPU signals + , + cpu1_clk_i, + cpu1_addr_o, + cpu1_data_i, + cpu1_data_o, + cpu1_bp_i, + cpu1_stall_o, + cpu1_stb_o, + cpu1_we_o, + cpu1_ack_i, + cpu1_rst_o + `endif + + `ifdef DBG_JSP_SUPPORTED + , + `ifndef DBG_WISHBONE_SUPPORTED + wb_clk_i, + wb_rst_i, + `endif + + // WISHBONE target interface + wb_jsp_adr_i, + wb_jsp_dat_o, + wb_jsp_dat_i, + wb_jsp_cyc_i, + wb_jsp_stb_i, + wb_jsp_sel_i, + wb_jsp_we_i, + wb_jsp_ack_o, + wb_jsp_cab_i, + wb_jsp_err_o, + wb_jsp_cti_i, + wb_jsp_bte_i, + int_o + `endif + + ); + + + // JTAG signals + input tck_i; + input tdi_i; + output tdo_o; + input rst_i; + + // TAP states + input shift_dr_i; + input pause_dr_i; + input update_dr_i; + input capture_dr_i; + + // Module select from TAP + input debug_select_i; + +`ifdef DBG_WISHBONE_SUPPORTED + input wb_clk_i; + input wb_rst_i; + output [31:0] wb_adr_o; + output [31:0] wb_dat_o; + input [31:0] wb_dat_i; + output wb_cyc_o; + output wb_stb_o; + output [3:0] wb_sel_o; + output wb_we_o; + input wb_ack_i; + output wb_cab_o; + input wb_err_i; + output [2:0] wb_cti_o; + output [1:0] wb_bte_o; +`endif + +`ifdef DBG_CPU0_SUPPORTED + // CPU signals + input cpu0_clk_i; + output [31:0] cpu0_addr_o; + input [31:0] cpu0_data_i; + output [31:0] cpu0_data_o; + input cpu0_bp_i; + output cpu0_stall_o; + output cpu0_stb_o; + output cpu0_we_o; + input cpu0_ack_i; + output cpu0_rst_o; +`endif + +`ifdef DBG_CPU1_SUPPORTED + input cpu1_clk_i; + output [31:0] cpu1_addr_o; + input [31:0] cpu1_data_i; + output [31:0] cpu1_data_o; + input cpu1_bp_i; + output cpu1_stall_o; + output cpu1_stb_o; + output cpu1_we_o; + input cpu1_ack_i; + output cpu1_rst_o; +`endif + +`ifdef DBG_JSP_SUPPORTED + `ifndef DBG_WISHBONE_SUPPORTED + input wb_clk_i; + input wb_rst_i; + `endif + input [31:0] wb_jsp_adr_i; + output [31:0] wb_jsp_dat_o; + input [31:0] wb_jsp_dat_i; + input wb_jsp_cyc_i; + input wb_jsp_stb_i; + input [3:0] wb_jsp_sel_i; + input wb_jsp_we_i; + output wb_jsp_ack_o; + input wb_jsp_cab_i; + output wb_jsp_err_o; + input [2:0] wb_jsp_cti_i; + input [1:0] wb_jsp_bte_i; + output int_o; +`endif + + +endmodule Index: rc-1.0/prj/src/blackboxes/or1200_top.v =================================================================== --- rc-1.0/prj/src/blackboxes/or1200_top.v (nonexistent) +++ rc-1.0/prj/src/blackboxes/or1200_top.v (revision 109) @@ -0,0 +1,152 @@ + + +`include "or1200_defines.v" + +module or1200_top( + // System + clk_i, rst_i, pic_ints_i, clmode_i, + + // Instruction WISHBONE INTERFACE + iwb_clk_i, iwb_rst_i, iwb_ack_i, iwb_err_i, iwb_rty_i, iwb_dat_i, + iwb_cyc_o, iwb_adr_o, iwb_stb_o, iwb_we_o, iwb_sel_o, iwb_dat_o, +`ifdef OR1200_WB_CAB + iwb_cab_o, +`endif +`ifdef OR1200_WB_B3 + iwb_cti_o, iwb_bte_o, +`endif + // Data WISHBONE INTERFACE + dwb_clk_i, dwb_rst_i, dwb_ack_i, dwb_err_i, dwb_rty_i, dwb_dat_i, + dwb_cyc_o, dwb_adr_o, dwb_stb_o, dwb_we_o, dwb_sel_o, dwb_dat_o, +`ifdef OR1200_WB_CAB + dwb_cab_o, +`endif +`ifdef OR1200_WB_B3 + dwb_cti_o, dwb_bte_o, +`endif + + // External Debug Interface + dbg_stall_i, dbg_ewt_i, dbg_lss_o, dbg_is_o, dbg_wp_o, dbg_bp_o, + dbg_stb_i, dbg_we_i, dbg_adr_i, dbg_dat_i, dbg_dat_o, dbg_ack_o, + +`ifdef OR1200_BIST + // RAM BIST + mbist_si_i, mbist_so_o, mbist_ctrl_i, +`endif + // Power Management + pm_cpustall_i, + pm_clksd_o, pm_dc_gate_o, pm_ic_gate_o, pm_dmmu_gate_o, + pm_immu_gate_o, pm_tt_gate_o, pm_cpu_gate_o, pm_wakeup_o, pm_lvolt_o + +,sig_tick + +); + +parameter dw = `OR1200_OPERAND_WIDTH; +parameter aw = `OR1200_OPERAND_WIDTH; +parameter ppic_ints = `OR1200_PIC_INTS; + +// +// I/O +// + +// +// System +// +input clk_i; +input rst_i; +input [1:0] clmode_i; // 00 WB=RISC, 01 WB=RISC/2, 10 N/A, 11 WB=RISC/4 +input [ppic_ints-1:0] pic_ints_i; + +// +// Instruction WISHBONE interface +// +input iwb_clk_i; // clock input +input iwb_rst_i; // reset input +input iwb_ack_i; // normal termination +input iwb_err_i; // termination w/ error +input iwb_rty_i; // termination w/ retry +input [dw-1:0] iwb_dat_i; // input data bus +output iwb_cyc_o; // cycle valid output +output [aw-1:0] iwb_adr_o; // address bus outputs +output iwb_stb_o; // strobe output +output iwb_we_o; // indicates write transfer +output [3:0] iwb_sel_o; // byte select outputs +output [dw-1:0] iwb_dat_o; // output data bus +`ifdef OR1200_WB_CAB +output iwb_cab_o; // indicates consecutive address burst +`endif +`ifdef OR1200_WB_B3 +output [2:0] iwb_cti_o; // cycle type identifier +output [1:0] iwb_bte_o; // burst type extension +`endif + +// +// Data WISHBONE interface +// +input dwb_clk_i; // clock input +input dwb_rst_i; // reset input +input dwb_ack_i; // normal termination +input dwb_err_i; // termination w/ error +input dwb_rty_i; // termination w/ retry +input [dw-1:0] dwb_dat_i; // input data bus +output dwb_cyc_o; // cycle valid output +output [aw-1:0] dwb_adr_o; // address bus outputs +output dwb_stb_o; // strobe output +output dwb_we_o; // indicates write transfer +output [3:0] dwb_sel_o; // byte select outputs +output [dw-1:0] dwb_dat_o; // output data bus +`ifdef OR1200_WB_CAB +output dwb_cab_o; // indicates consecutive address burst +`endif +`ifdef OR1200_WB_B3 +output [2:0] dwb_cti_o; // cycle type identifier +output [1:0] dwb_bte_o; // burst type extension +`endif + +// +// External Debug Interface +// +input dbg_stall_i; // External Stall Input +input dbg_ewt_i; // External Watchpoint Trigger Input +output [3:0] dbg_lss_o; // External Load/Store Unit Status +output [1:0] dbg_is_o; // External Insn Fetch Status +output [10:0] dbg_wp_o; // Watchpoints Outputs +output dbg_bp_o; // Breakpoint Output +input dbg_stb_i; // External Address/Data Strobe +input dbg_we_i; // External Write Enable +input [aw-1:0] dbg_adr_i; // External Address Input +input [dw-1:0] dbg_dat_i; // External Data Input +output [dw-1:0] dbg_dat_o; // External Data Output +output dbg_ack_o; // External Data Acknowledge (not WB compatible) + +`ifdef OR1200_BIST +// +// RAM BIST +// +input mbist_si_i; +input [`OR1200_MBIST_CTRL_WIDTH - 1:0] mbist_ctrl_i; +output mbist_so_o; +`endif + +// +// Power Management +// +input pm_cpustall_i; +output [3:0] pm_clksd_o; +output pm_dc_gate_o; +output pm_ic_gate_o; +output pm_dmmu_gate_o; +output pm_immu_gate_o; +output pm_tt_gate_o; +output pm_cpu_gate_o; +output pm_wakeup_o; +output pm_lvolt_o; + +// +// CPU and TT +// +output sig_tick; // jb + + +endmodule Index: rc-1.0/syn/altera/setup.bat =================================================================== --- rc-1.0/syn/altera/setup.bat (nonexistent) +++ rc-1.0/syn/altera/setup.bat (revision 109) @@ -0,0 +1,12 @@ +@echo off +set /p quartus_path=Input the path to Quartus e.g. C:\altera\11.0sp1\quartus: +if EXIST %quartus_path% ( +set path=%path%;%quartus_path%\bin\cygwin\bin;%quartus_path%\bin +make all +echo Finished... +set /p exit=Press ENTER to close this window... +make clean +) ELSE ( +echo %quartus_path% could not be found. +set /p exit=Press ENTER to close this window... +) \ No newline at end of file
rc-1.0/syn/altera/setup.bat Property changes : Added: svn:executable ## -0,0 +1 ## +* \ No newline at end of property Index: rc-1.0/syn/altera/minsoc_top.qsf =================================================================== --- rc-1.0/syn/altera/minsoc_top.qsf (nonexistent) +++ rc-1.0/syn/altera/minsoc_top.qsf (revision 109) @@ -0,0 +1,37 @@ +set_global_assignment -name FAMILY "FAMILY_PART" +set_global_assignment -name DEVICE DEVICE_PART +set_global_assignment -name TOP_LEVEL_ENTITY minsoc_top +#set_global_assignment -name ORIGINAL_QUARTUS_VERSION SW_VERSION +#set_global_assignment -name LAST_QUARTUS_VERSION SW_VERSION +set_global_assignment -name MIN_CORE_JUNCTION_TEMP 0 +set_global_assignment -name MAX_CORE_JUNCTION_TEMP 85 +set_global_assignment -name DEVICE_FILTER_PIN_COUNT 240 +set_global_assignment -name ERROR_CHECK_FREQUENCY_DIVISOR 2 +set_global_assignment -name PARTITION_NETLIST_TYPE SOURCE -section_id Top +set_global_assignment -name PARTITION_FITTER_PRESERVATION_LEVEL PLACEMENT_AND_ROUTING -section_id Top +set_global_assignment -name PARTITION_COLOR 16764057 -section_id Top +set_global_assignment -name STRATIX_DEVICE_IO_STANDARD "2.5 V" +#set_global_assignment -name MISC_FILE ./minsoc_top.dpf +set_global_assignment -name USE_CONFIGURATION_DEVICE OFF +set_global_assignment -name CRC_ERROR_OPEN_DRAIN OFF +set_global_assignment -name FORCE_CONFIGURATION_VCCIO ON +set_global_assignment -name OUTPUT_IO_TIMING_NEAR_END_VMEAS "HALF VCCIO" -rise +set_global_assignment -name OUTPUT_IO_TIMING_NEAR_END_VMEAS "HALF VCCIO" -fall +set_global_assignment -name OUTPUT_IO_TIMING_FAR_END_VMEAS "HALF SIGNAL SWING" -rise +set_global_assignment -name OUTPUT_IO_TIMING_FAR_END_VMEAS "HALF SIGNAL SWING" -fall +set_global_assignment -name RESERVE_DATA1_AFTER_CONFIGURATION "USE AS REGULAR IO" +set_global_assignment -name RESERVE_FLASH_NCE_AFTER_CONFIGURATION "USE AS REGULAR IO" +set_global_assignment -name EDA_BOARD_DESIGN_BOUNDARY_SCAN_TOOL "BSDL (Boundary Scan)" +set_global_assignment -name EDA_OUTPUT_DATA_FORMAT BSDL -section_id eda_board_design_boundary_scan +set_global_assignment -name EDA_BOARD_BOUNDARY_SCAN_OPERATION POST_CONFIG -section_id eda_board_design_boundary_scan +set_global_assignment -name POWER_PRESET_COOLING_SOLUTION "23 MM HEAT SINK WITH 200 LFPM AIRFLOW" +set_global_assignment -name POWER_BOARD_THERMAL_MODEL "NONE (CONSERVATIVE)" +set_global_assignment -name EDA_TIMING_ANALYSIS_TOOL "" +set_global_assignment -name EDA_TIME_SCALE "1 ps" -section_id eda_timing_analysis +set_global_assignment -name EDA_RUN_TOOL_AUTOMATICALLY OFF -section_id eda_timing_analysis +set_global_assignment -name EDA_OUTPUT_DATA_FORMAT NONE -section_id eda_timing_analysis +set_global_assignment -name EDA_LAUNCH_CMD_LINE_TOOL OFF -section_id eda_timing_analysis + +set_global_assignment -name SDC_FILE minsoc_top.sdc +set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -section_id Top + Index: rc-1.0/syn/altera/Makefile =================================================================== --- rc-1.0/syn/altera/Makefile (nonexistent) +++ rc-1.0/syn/altera/Makefile (revision 109) @@ -0,0 +1,60 @@ +MINSOC = .. +MINSOC_DEFINES = ${MINSOC}/backend +MINSOC_RTL = ${MINSOC}/rtl/verilog +MINSOC_STARTUP_RTL = ${MINSOC_RTL}/minsoc_startup +UART_RTL = ${MINSOC_RTL}/uart16550/rtl/verilog +ADV_DEBUG_ROOT = ${MINSOC_RTL}/adv_debug_sys/Hardware +DEBUG_RTL = ${ADV_DEBUG_ROOT}/adv_dbg_if/rtl/verilog +OR1200_RTL = ${MINSOC_RTL}/or1200/rtl/verilog +ETH_RTL = ${MINSOC_RTL}/ethmac/rtl/verilog +BUILD_SUPPORT = $(MINSOC)/syn/buildSupport +PROJECT_DIR = $(MINSOC)/prj/altera +QSF_FILE = $(BUILD_SUPPORT)/minsoc_top +help: + @echo " all: Synthesize and implement the SoC, then generate a bit stream" + @echo "" + @echo " bitgen: Generate a programming file for the target FPGA" + @echo " map: Express the SoC netlist in the target hardware" + @echo " fit: Place the target hardware, then route the wires" + @echo " sta: Perfom a timming analysis" + @echo " eda: Generate a netlist of the hardware" + @echo " config: Load the bitstream into the device using ALTERA USB Blaster and JTAG configuration" + @echo "" + @echo " clean: Delete all superfluous files generated by Altera tools" + @echo " distclean: Delete all generated files" + +all: bitgen eda sta +map: $(BUILD_SUPPORT)/minsoc_top.map.summary +fit: $(BUILD_SUPPORT)/minsoc_top.fit.summary +bitgen: minsoc_top.sof +eda: $(BUILD_SUPPORT)/minsoc_top.eda.summary +sta: $(BUILD_SUPPORT)/minsoc_top.sta.summary + +#minsoc_top.map.summary: ${MINSOC_RTL}/*.v $(UART_RTL)/*.v $(ADV_DEBUG_ROOT)/*.v $(DEBUG_RTL)/*.v $(OR1200_RTL)/*.v $(ETH_RTL)/*.v ${MINSOC_DEFINES}/minsoc_defines.v minsoc_top.qsf +$(BUILD_SUPPORT)/minsoc_top.map.summary: ${MINSOC_DEFINES}/minsoc_defines.v $(BUILD_SUPPORT)/minsoc_top.qsf + + quartus_map $(QSF_FILE) --write_settings_files=off + +$(BUILD_SUPPORT)/minsoc_top.fit.summary: $(BUILD_SUPPORT)/minsoc_top.map.summary + quartus_fit $(QSF_FILE) --write_Settings_files=off --pack_register=minimize_area + +minsoc_top.sof: $(BUILD_SUPPORT)/minsoc_top.fit.summary + quartus_asm $(QSF_FILE) + mv $(BUILD_SUPPORT)/*.sof . + +$(BUILD_SUPPORT)/minsoc_top.sta.summary: $(BUILD_SUPPORT)/minsoc_top.fit.summary + quartus_sta $(QSF_FILE) + +$(BUILD_SUPPORT)/minsoc_top.eda.summary: $(BUILD_SUPPORT)/minsoc_top.fit.summary + quartus_eda $(QSF_FILE) --write_settings_files=off + +config: minsoc_top.sof + quartus_pgm -c USB-Blaster -m jtag -o "p;minsoc_top.sof" + +distclean: + $(RM) *.sof + make clean + +clean: + $(RM) $(BUILD_SUPPORT)/*.rpt $(BUILD_SUPPORT)/*.summary $(BUILD_SUPPORT)/*.jdi $(BUILD_SUPPORT)/*.smsg $(BUILD_SUPPORT)/*.pin $(BUILD_SUPPORT)/*.qpf + $(RM) -r $(BUILD_SUPPORT)/db $(BUILD_SUPPORT)/incremental_db Index: rc-1.0/syn/xilinx/setup.bat =================================================================== --- rc-1.0/syn/xilinx/setup.bat (nonexistent) +++ rc-1.0/syn/xilinx/setup.bat (revision 109) @@ -0,0 +1,12 @@ +@echo off +set /p xilinx_settings=Input the Xilinx "settings32|64.bat" file along with its absolute path: +if EXIST %xilinx_settings% ( +%xilinx_settings% +make all +echo Finished... +set /p exit=Press ENTER to close this window... +make clean +) ELSE ( +echo %xilinx_settings% could not be found. +set /p exit=Press ENTER to close this window... +) \ No newline at end of file Index: rc-1.0/syn/xilinx/Makefile =================================================================== --- rc-1.0/syn/xilinx/Makefile (nonexistent) +++ rc-1.0/syn/xilinx/Makefile (revision 109) @@ -0,0 +1,84 @@ +MINSOC = ../ +MINSOC_DEFINES = ${MINSOC}/backend +MINSOC_RTL = ${MINSOC}/rtl/verilog +MINSOC_STARTUP_RTL = ${MINSOC_RTL}/minsoc_startup +UART_RTL = ${MINSOC_RTL}/uart16550/rtl/verilog +ADV_DEBUG_ROOT = ${MINSOC_RTL}/adv_debug_sys/Hardware +DEBUG_RTL = ${ADV_DEBUG_ROOT}/adv_dbg_if/rtl/verilog +OR1200_RTL = ${MINSOC_RTL}/or1200/rtl/verilog +ETH_RTL = ${MINSOC_RTL}/ethmac/rtl/verilog +BUILD_SUPPORT = $(MINSOC)/syn/buildSupport +PROJECT_DIR = $(MINSOC)/prj/xilinx + +help: + @echo " all: Synthesize and implement the SoC, then generate a bit stream" + @echo "" + @echo " soc: Synthesize the SoC" + @echo " translate: Convert the SoC's ngc file to an ngd file for mapping" + @echo " map: Express the SoC netlist in the target hardware" + @echo " par: Place the target hardware, then route the wires" + @echo " bitgen: Generate a programming file for the target FPGA" + @echo "" + @echo " modules: Synthesize OR1200 processor, debug interface, UART and Ethernet controllers" + @echo " or1200: Synthesize the OR1200 processor" + @echo " debug: Synthesize the debug interface" + @echo " uart: Synthesize the UART" + @echo " eth: Synthesize the Ethernet controller" + @echo "" + @echo " clean: Delete all superfluous files generated by Xilinx tools" + @echo " distclean: Delete all generated files" + +all: minsoc.bit +soc: minsoc_top.ngc +translate: minsoc.ngd +map: minsoc.ncd +par: minsoc_par.ncd +bitgen: minsoc.bit +modules: or1200 debug uart eth +MODULES = or1200_top.ngc adbg_top.ngc uart_top.ngc ethmac.ngc + +prepare: + rm -rf xst + mkdir xst +clean: + rm -rf _xmsgs xst xlnx_auto_0_xdb + rm -rf *.xst *.xrpt *.srp *.lso *.log *.bld *.lst *.twr *.ise *.map *.mrp *.ngm *.pcf *.psr *.xml *.pad *.par *.ptwx *.bgn *.unroutes *.xpi minsoc_par_pad* *.xwbt *.html +distclean: + rm -rf *.ngc *.ncd *.ngd *.bit + make clean + +minsoc_top.ngc: ${MINSOC_RTL}/*.v ${MINSOC_DEFINES}/minsoc_defines.v $(BUILD_SUPPORT)/minsoc_top.xst $(PROJECT_DIR)/minsoc_top.prj + make prepare + xst -ifn "$(BUILD_SUPPORT)/minsoc_top.xst" + +uart: uart_top.ngc +uart_top.ngc: ${UART_RTL}/*.v $(BUILD_SUPPORT)/uart_top.xst $(PROJECT_DIR)/uart_top.prj + make prepare + xst -ifn "$(BUILD_SUPPORT)/uart_top.xst" + +eth: ethmac.ngc +ethmac.ngc: ${ETH_RTL}/*.v $(BUILD_SUPPORT)/ethmac.xst $(PROJECT_DIR)/ethmac.prj + make prepare + xst -ifn "$(BUILD_SUPPORT)/ethmac.xst" + +debug: adbg_top.ngc +adbg_top.ngc: ${DEBUG_RTL}/*.v $(BUILD_SUPPORT)/adbg_top.xst $(PROJECT_DIR)/adbg_top.prj + make prepare + xst -ifn "$(BUILD_SUPPORT)/adbg_top.xst" + +or1200: or1200_top.ngc +or1200_top.ngc: ${OR1200_RTL}/*.v $(BUILD_SUPPORT)/or1200_top.xst $(PROJECT_DIR)/or1200_top.prj + make prepare + xst -ifn "$(BUILD_SUPPORT)/or1200_top.xst" + +minsoc.ngd: ${MINSOC}/backend/CONSTRAINT_FILE minsoc_top.ngc $(MODULES) + ngdbuild -p DEVICE_PART -uc ${MINSOC}/backend/CONSTRAINT_FILE -aul minsoc_top.ngc minsoc.ngd + +minsoc.ncd: minsoc.ngd + map -bp -timing -cm speed -equivalent_register_removal on -logic_opt on -ol high -power off -register_duplication on -retiming on -w -xe n minsoc.ngd + +minsoc_par.ncd: minsoc.ncd + par -ol high -w -xe n minsoc.ncd minsoc_par.ncd + +minsoc.bit: minsoc_par.ncd + bitgen -d -w minsoc_par.ncd minsoc.bit Index: rc-1.0/syn/doc/guideTop.pdf =================================================================== Cannot display: file marked as a binary type. svn:mime-type = application/octet-stream Index: rc-1.0/syn/doc/guideTop.pdf =================================================================== --- rc-1.0/syn/doc/guideTop.pdf (nonexistent) +++ rc-1.0/syn/doc/guideTop.pdf (revision 109)
rc-1.0/syn/doc/guideTop.pdf Property changes : Added: svn:mime-type ## -0,0 +1 ## +application/octet-stream \ No newline at end of property Index: rc-1.0/utils/setup/minsoc-install.sh =================================================================== --- rc-1.0/utils/setup/minsoc-install.sh (nonexistent) +++ rc-1.0/utils/setup/minsoc-install.sh (revision 109) @@ -0,0 +1,286 @@ +#!/bin/bash +# Author: Constantinos Xanthopoulos +# This script install MinSOC tree +# under a specific directory. + +# ===== CONFIGURATIONS ===== +# ========================== + +# Where should I put the dir. minsoc? +# ex. /home/conx/Thesis/ +DIR_TO_INSTALL=`pwd` + +# This variable should be set to trunk +# or to stable. +VERSION="" + +# This variable should take one of +# the following values depending +# to your system: linux, cygwin, freebsd +ENV="" + +# !!! DO NOT EDIT BELLOW THIS LINE !!! +# =================================== + +# ===== SCRIPT ====== +# =================== + + +# Debug ? +export DEBUG=0; +. beautify.sh + +function testtool +{ + # is_missing=`which $1 2>&1 | grep no` + is_missing=`whereis -b $1 2>&1 | grep :$` + if [ -z "$is_missing" ] + then + cecho "$1 is installed, pass" + else + errormsg "$1 is not installed, install it and re-run this installation script." + fi +} + + +#Setting environment +ENV=`uname -o` +if [ "$ENV" != "GNU/Linux" ] && [ "$ENV" != "Cygwin" ] +then + errormsg "Environment $ENV not supported by this script." +fi +cecho "Building tools for ${ENV} system" + +is_arch64=`uname -m | grep 64` +if [ -z $is_arch64 ] +then + KERNEL_ARCH="32" +else + KERNEL_ARCH="64" +fi + + +# User check! +if [ `whoami` = "root" ]; +then + errormsg "You shouldn't be root for this script to run."; +fi; + + +# Testing necessary tools +cecho "Testing if necessary tools are installed, program "whereis" is required." +testtool wget +testtool svn +testtool bzip2 +testtool tar +testtool sed +testtool patch +testtool gcc +testtool make +testtool libncurses +testtool flex +testtool bison +if [ "$ENV" == "Cygwin" ] +then + testtool ioperm + testtool libusb +fi + + +# Wizard +if [ -z "${ALTDIR}" ] +then + cnecho "Give full path (ex. /home/foo/) for installation directory or leave empty for "${DIR_TO_INSTALL}": "; + read ALTDIR; + if [ ! -z "${ALTDIR}" ] + then + DIR_TO_INSTALL=${ALTDIR} + fi + cecho "${DIR_TO_INSTALL} selected"; +fi + +if [ ! -d ${DIR_TO_INSTALL} ] +then + errormsg "Directory doesn't exist. Please create it"; +fi; + + +#Creating directory structure +cecho "\nCreating directory structure" +cd ${DIR_TO_INSTALL} +execcmd "Creating directory ./download for downloaded packages" "mkdir -p download" +execcmd "Creating directory ./tools for package binaries" "mkdir -p tools" + + +#Downloading everything we need +cecho "\nDownloading packages" +cd ${DIR_TO_INSTALL} +cecho "Download MinSoC" +svn co -q http://opencores.org/ocsvn/minsoc/minsoc/trunk/ minsoc #user need to input password, execcmd omits command output and should be this way +execcmd "cd ${DIR_TO_INSTALL}/download" +if [ "$ENV" == "Cygwin" ] +then + execcmd "Downloading GNU Toolchain" "wget ftp://ocuser:ocuser@openrisc.opencores.org/toolchain/or32-elf-cygwin-1.7.tar.bz2"; +else + if [ $KERNEL_ARCH == "32" ]; + then + execcmd "Downloading GNU Toolchain" "wget ftp://ocuser:ocuser@openrisc.opencores.org/toolchain/or32-elf-linux-x86.tar.bz2"; + elif [ $KERNEL_ARCH == "64" ]; + then + execcmd "Downloading GNU Toolchain" "wget ftp://ocuser:ocuser@openrisc.opencores.org/toolchain/or32-elf-linux-x86_64.tar.bz2"; + fi +fi +execcmd "Downloading GDB" "wget ftp://anonymous:anonymous@ftp.gnu.org/gnu/gdb/gdb-6.8a.tar.bz2" +execcmd "wget ftp://ocuser:ocuser@openrisc.opencores.org/toolchain/or32-gdb-6.8-patch-2.4.bz2" +execcmd "svn export -q http://opencores.org/ocsvn/adv_debug_sys/adv_debug_sys/trunk/Patches/GDB6.8/gdb-6.8-bz436037-reg-no-longer-active.patch" +if [ "$ENV" != "Cygwin" ] +then + execcmd "Downloading libusb-0.1 for Advanced Debug System" "wget http://sourceforge.net/projects/libusb/files/libusb-0.1%20%28LEGACY%29/0.1.12/libusb-0.1.12.tar.gz" +fi +execcmd "Downloading libftdi for Advanced Debug System" "wget http://www.intra2net.com/en/developer/libftdi/download/libftdi-0.19.tar.gz" +execcmd "Downloading Icarus Verilog" "wget ftp://icarus.com/pub/eda/verilog/v0.9/verilog-0.9.4.tar.gz" + + +#Uncompressing everything +cecho "\nUncompressing packages" +if [ "$ENV" == "Cygwin" ] +then + execcmd "tar xf or32-elf-cygwin-1.7.tar.bz2"; +else + if [ $KERNEL_ARCH == "32" ]; + then + execcmd "tar xf or32-elf-linux-x86.tar.bz2"; + elif [ $KERNEL_ARCH == "64" ]; + then + execcmd "tar xf or32-elf-linux-x86_64.tar.bz2"; + fi +fi +execcmd "tar -jxf gdb-6.8a.tar.bz2" +execcmd "bzip2 -d or32-gdb-6.8-patch-2.4.bz2" +if [ "$ENV" != "Cygwin" ] +then + execcmd "tar zxf libusb-0.1.12.tar.gz" +fi +execcmd "tar zxf libftdi-0.19.tar.gz" +execcmd "tar zxf verilog-0.9.4.tar.gz" + + +#Compiling and Installing all packages +cecho "\nCompiling and installing packages" +# Installing the GNU Toolchain +if [ "$ENV" == "Cygwin" ] +then + execcmd "Installing GNU Toolchain" "tar xf or32-elf-cygwin-1.7.tar.bz2 -C $DIR_TO_INSTALL/tools"; +else + if [ $KERNEL_ARCH == "32" ]; + then + execcmd "Installing GNU Toolchain" "tar xf or32-elf-linux-x86.tar.bz2 -C $DIR_TO_INSTALL/tools"; + elif [ $KERNEL_ARCH == "64" ]; + then + execcmd "Installing GNU Toolchain" "tar xf or32-elf-linux-x86_64.tar.bz2 -C $DIR_TO_INSTALL/tools"; + fi +fi +PATH=$PATH:$DIR_TO_INSTALL/tools/or32-elf/bin + + +#Installing GDB +execcmd "cd gdb-6.8" +execcmd "patch -p1 < ../or32-gdb-6.8-patch-2.4" +execcmd "patch -p1 < ../gdb-6.8-bz436037-reg-no-longer-active.patch" + +execcmd "mkdir -p build" +execcmd "cd build" +execcmd "../configure --target=or32-elf --disable-werror --prefix=$DIR_TO_INSTALL/tools" +execcmd "Compiling GDB" "make" +make install 1>>${DIR_TO_INSTALL}/progress.log 2>>${DIR_TO_INSTALL}/error.log #avoid Fedora failing due to missing Makeinfo +PATH=$PATH:${DIR_TO_INSTALL}/tools/bin + + +#Installing Advanced JTAG Bridge support libraries +if [ "$ENV" != "Cygwin" ] +then + execcmd "cd ${DIR_TO_INSTALL}/download/libusb-0.1.12" + execcmd "./configure --prefix=${DIR_TO_INSTALL}/tools" + execcmd "Installing libusb-0.1" "make" + execcmd "make install" +fi + +execcmd "cd ${DIR_TO_INSTALL}/download/libftdi-0.19" +execcmd "./configure --prefix=${DIR_TO_INSTALL}/tools" +execcmd "Compiling libftdi" "make" +execcmd "make install" + + +#Installing Advanced JTAG Bridge +execcmd "cd ${DIR_TO_INSTALL}/minsoc/rtl/verilog/adv_debug_sys/Software/adv_jtag_bridge" +if [ `grep "INCLUDE_JSP_SERVER=true" Makefile` != "" ] +then + #Switching off the adv_jtag_bridge JSP_SERVER option + sed 's/INCLUDE_JSP_SERVER=true/INCLUDE_JSP_SERVER=false/' Makefile > TMPFILE && mv TMPFILE Makefile +fi + +if [ "${ENV}" == "GNU/Linux" ] +then + #Setting the right build environment + sed 's/BUILD_ENVIRONMENT=cygwin/BUILD_ENVIRONMENT=linux/' Makefile > TMPFILE && mv TMPFILE Makefile +fi + +#preparing the Makefile to find and link libraries +sed "s%prefix = /usr/local%prefix = ${DIR_TO_INSTALL}/tools%" Makefile > TMPFILE && mv TMPFILE Makefile +sed "s%\$(CC) \$(CFLAGS)%\$(CC) \$(CFLAGS) \$(INCLUDEDIRS)%" Makefile > TMPFILE && mv TMPFILE Makefile +sed "s%INCLUDEDIRS =%INCLUDEDIRS = -I${DIR_TO_INSTALL}/tools/include%" Makefile > TMPFILE && mv TMPFILE Makefile +sed "s%LIBS =%LIBS = -L${DIR_TO_INSTALL}/tools/lib -Wl,-R${DIR_TO_INSTALL}/tools/lib%" Makefile > TMPFILE && mv TMPFILE Makefile + +#properly installing Advanced JTAG Bridge +execcmd "Compiling Advanced JTAG Bridge" "make" +execcmd "make install" + + +#Installing Icarus Verilog +execcmd "cd ${DIR_TO_INSTALL}/download/verilog-0.9.4" +execcmd "./configure --prefix=${DIR_TO_INSTALL}/tools" +execcmd "Compiling Icarus Verilog" "make" +execcmd "make install" + + +#Configuring MinSoC +cecho "\nConfiguring MinSoC" +execcmd "cd ${DIR_TO_INSTALL}/minsoc/backend/std" +execcmd "Configuring MinSoC as standard board (simulatable but not synthesizable)" "./configure" +execcmd "cd ${DIR_TO_INSTALL}" + + +#Configuring Advanced Debug System to work with MinSoC +cecho "\nConfiguring Advanced Debug System to work with MinSoC" +execcmd "cd ${DIR_TO_INSTALL}/minsoc/rtl/verilog/adv_debug_sys/Hardware/adv_dbg_if/rtl/verilog" +sed "s%\`define DBG_JSP_SUPPORTED%//\`define DBG_JSP_SUPPORTED%" adbg_defines.v > TMPFILE && mv TMPFILE adbg_defines.v + +#Compiling and moving adv_jtag_bridge debug modules for simulation +execcmd "cd ${DIR_TO_INSTALL}/minsoc/rtl/verilog/adv_debug_sys/Software/adv_jtag_bridge/sim_lib/icarus" +execcmd "make" +execcmd "cp jp-io-vpi.vpi ${DIR_TO_INSTALL}/minsoc/bench/verilog/vpi" + + +#Precompiling firmwares +cecho "\nPrecompiling delivered firmwares"; +execcmd "cd ${DIR_TO_INSTALL}/minsoc/sw/utils" +execcmd "Make utils" "make" + +execcmd "cd ${DIR_TO_INSTALL}/minsoc/sw/support" +execcmd "Make support tools" "make" + +execcmd "cd ${DIR_TO_INSTALL}/minsoc/sw/drivers" +execcmd "Make drivers" "make" + +execcmd "cd ${DIR_TO_INSTALL}/minsoc/sw/uart" +execcmd "Make UART" "make" + + +#Setting-up new variables +cecho "\nSystem configurations" +execcmd "Adding MinSoC tools to PATH" "echo \"PATH=\\\$PATH:$DIR_TO_INSTALL/tools/bin\" >> /home/$(whoami)/.bashrc;"; +execcmd "Adding OpenRISC toolchain to PATH" "echo \"PATH=\\\$PATH:$DIR_TO_INSTALL/tools/or32-elf/bin/\" >> /home/$(whoami)/.bashrc;"; + +cecho "\nInstallation Complete!" +cecho "Before using the system, load the new environment variables doing this: source /home/$(whoami)/.bashrc" +cecho "You may remove the ${DIR_TO_INSTALL}/download directory if you wish."
rc-1.0/utils/setup/minsoc-install.sh Property changes : Added: svn:executable ## -0,0 +1 ## +* \ No newline at end of property Index: rc-1.0/utils/setup/install_time.txt =================================================================== --- rc-1.0/utils/setup/install_time.txt (nonexistent) +++ rc-1.0/utils/setup/install_time.txt (revision 109) @@ -0,0 +1,5 @@ +Debian Linux | Intel Q6600 2.4 GHz | single core compilation + 7 minutes + +Cygwin on Windows XP | VMware virtual machine | Intel Q6600 2.4 GHz | single core compilation + 50 minutes \ No newline at end of file Index: rc-1.0/utils/setup/beautify.sh =================================================================== --- rc-1.0/utils/setup/beautify.sh (nonexistent) +++ rc-1.0/utils/setup/beautify.sh (revision 109) @@ -0,0 +1,64 @@ +#!/bin/bash +# Xanthopoulos Constantinos +# Some useful function for my scripts + +function cecho +{ + echo -e "\033[1m\033[33m$1\033[0m" + echo -e "\033[1m\033[33m$1\033[0m" >> ${DIR_TO_INSTALL}/progress.log +} + +function cnecho +{ + echo -e -n "\033[0m\033[33m$1\033[0m" + echo -e -n "\033[0m\033[33m$1\033[0m" >> ${DIR_TO_INSTALL}/progress.log +} + +function errormsg +{ + echo -e "\033[1m\033[31mError: $1\033[0m\n"; + echo -e "\033[1m\033[31mError: $1\033[0m\n" >> ${DIR_TO_INSTALL}/error.log + exit 1; +} + +function _execcmd +{ + # Print Message + echo -e "\033[35m$1...\033[0m\n" >> ${DIR_TO_INSTALL}/progress.log + if [ -n "$1" ] + then + echo -e -n "\033[35m$1...\033[0m" + fi + # Execute command + if [ $DEBUG -ne 1 ]; + then + eval $2 1>>${DIR_TO_INSTALL}/progress.log 2>>${DIR_TO_INSTALL}/error.log; + fi; + # Check Execution + if [ $? -eq 0 ] + then + if [ -n "$1" ] + then + echo -e "\033[32mcomplete\033[0m"; + echo -e "\033[32mcomplete\033[0m" >> ${DIR_TO_INSTALL}/progress.log + fi + else + errormsg "Command: $2 Description: $1"; + exit 1; + fi +} + +function execcmd +{ + if [ -z "$2" ] + then + _execcmd "" "$1" + else + _execcmd "$1" "$2" + fi +} + +if [ $DEBUG -eq 1 ] +then + cecho "Debug mode on! Nothing will actually run"; +fi Index: rc-1.0/utils/setup/required-cygwin-tools.txt =================================================================== --- rc-1.0/utils/setup/required-cygwin-tools.txt (nonexistent) +++ rc-1.0/utils/setup/required-cygwin-tools.txt (revision 109) @@ -0,0 +1,12 @@ +packages: +util-linux (for whereis) +wget +subversion +patch +gcc +make +libncurses-devel +ioperm +libusb-win32 +flex +bison \ No newline at end of file
rc-1.0/utils/setup/required-cygwin-tools.txt Property changes : Added: svn:executable ## -0,0 +1 ## +* \ No newline at end of property Index: rc-1.0/utils/contributions/gpio/todo.txt =================================================================== --- rc-1.0/utils/contributions/gpio/todo.txt (nonexistent) +++ rc-1.0/utils/contributions/gpio/todo.txt (revision 109) @@ -0,0 +1,38 @@ +I still have some important hints to you regarding this. + +minsoc_top.v: on line 817 you should also include: +assign wb_gpio_err_o = 1'b0; (otherwise simulation might drive crazy and prob real life if it doesn't "automatically" be set to 0. + +You probably missed it since these are gathered together around line 358 for uart, spi and start_up. And I forgot myself to add it for Ethernet. + +On gpio_defines.v, the GPIO_IOS definition I'd set directly to 32. Instantiation would be instead of GPIO_IOS + 1, GPIO_IOS only. Is there any problem regarding this? The definitions generally are more human friendly than coding, so the register definitions of reg [GPIOS_IOS-1:0] which considers 0 to be something is let for the implementation. That's more or less standard I'd say. It is the same as when you define the address width on minsoc_defines.v you define it and I implement it considering the necessary -1s. + +GPIO_LINES32 instead of GPIO_LINES31. + +I'd substitute the whole minsoc_spartan_3a_starter_kit_ios.v. Instead of it, place a bidirectional port on minsoc_top if GPIO is enabled. +`ifdef GPIO +, gpio_io +`endif + +// +// GPIO +// +inout [GPIO_IOS-1:0] gpio_io; + +// +// GPIO tri-state +// +// I hope this works without generate, otherwise it is also easy but I'd first try this way +integer iterate; +for (iterate = 0; iterate < GPIO_IOS; iterate = iterate + 1) + assign gpio_io[iterate] = ext_pad_oe_o[iterate] ? ext_pad_o[iterate] : 1'bZ; + +assign ext_pad_i = gpio_io; + +And then only define the pins for the inout port on the ucf file. Like this: +NET "gpio_io(31)" LOC = "a1(pin number)" | DRIVE = 12 | SLEW = SLOW; +NET "gpio_io(30)" LOC = "a1(pin number)" | DRIVE = 12 | SLEW = SLOW; +... +NET "gpio_io(0)" LOC = "a1(pin number)" | DRIVE = 12 | SLEW = SLOW; + +After that you only need the definition GPIO on minsoc_defines.v. Of course, interrupt and address you also still need. \ No newline at end of file Index: rc-1.0/utils/contributions/gpio/rtl/gpio_defines.v =================================================================== --- rc-1.0/utils/contributions/gpio/rtl/gpio_defines.v (nonexistent) +++ rc-1.0/utils/contributions/gpio/rtl/gpio_defines.v (revision 109) @@ -0,0 +1,326 @@ +////////////////////////////////////////////////////////////////////// +//// //// +//// WISHBONE GPIO Definitions //// +//// //// +//// This file is part of the GPIO project //// +//// http://www.opencores.org/cores/gpio/ //// +//// //// +//// Description //// +//// GPIO IP Definitions. //// +//// //// +//// To Do: //// +//// Nothing //// +//// //// +//// Author(s): //// +//// - Damjan Lampret, lampret@opencores.org //// +//// //// +////////////////////////////////////////////////////////////////////// +//// //// +//// Copyright (C) 2000 Authors and OPENCORES.ORG //// +//// //// +//// This source file may be used and distributed without //// +//// restriction provided that this copyright statement is not //// +//// removed from the file and that any derivative work contains //// +//// the original copyright notice and the associated disclaimer. //// +//// //// +//// This source file is free software; you can redistribute it //// +//// and/or modify it under the terms of the GNU Lesser General //// +//// Public License as published by the Free Software Foundation; //// +//// either version 2.1 of the License, or (at your option) any //// +//// later version. //// +//// //// +//// This source is distributed in the hope that it will be //// +//// useful, but WITHOUT ANY WARRANTY; without even the implied //// +//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR //// +//// PURPOSE. See the GNU Lesser General Public License for more //// +//// details. //// +//// //// +//// You should have received a copy of the GNU Lesser General //// +//// Public License along with this source; if not, download it //// +//// from http://www.opencores.org/lgpl.shtml //// +//// //// +////////////////////////////////////////////////////////////////////// +// +// CVS Revision History +// +// $Log: not supported by cvs2svn $ +// Revision 1.8 2003/12/17 13:00:52 gorand +// added ECLK and NEC registers, all tests passed. +// +// Revision 1.7 2003/12/01 17:10:44 simons +// ifndef directive is not supported by all tools. +// +// Revision 1.6 2003/11/06 13:59:07 gorand +// added support for 8-bit access to registers. +// +// Revision 1.2 2003/10/02 18:54:35 simons +// GPIO signals muxed with other peripherals, higland_board fixed. +// +// Revision 1.1.1.1 2003/06/24 09:09:23 simons +// This files were moved here from toplevel folder. +// +// Revision 1.1.1.1 2003/06/11 18:51:13 simons +// Initial import. +// +// Revision 1.5 2002/11/11 21:36:28 lampret +// Added ifdef to remove mux from clk_pad_i if mux is not allowed. This also removes RGPIO_CTRL[NEC]. +// +// Revision 1.4 2002/05/06 18:25:31 lampret +// negedge flops are enabled by default. +// +// Revision 1.3 2001/12/25 17:12:35 lampret +// Added RGPIO_INTS. +// +// Revision 1.2 2001/11/15 02:24:37 lampret +// Added GPIO_REGISTERED_WB_OUTPUTS, GPIO_REGISTERED_IO_OUTPUTS and GPIO_NO_NEGEDGE_FLOPS. +// +// Revision 1.1 2001/09/18 18:49:07 lampret +// Changed top level ptc into gpio_top. Changed defines.v into gpio_defines.v. +// +// Revision 1.1 2001/08/21 21:39:28 lampret +// Changed directory structure, port names and drfines. +// +// Revision 1.3 2001/07/15 00:21:10 lampret +// Registers can be omitted and will have certain default values +// +// Revision 1.2 2001/07/14 20:39:26 lampret +// Better configurability. +// +// Revision 1.1 2001/06/05 07:45:26 lampret +// Added initial RTL and test benches. There are still some issues with these files. +// +// + +// +// Number of GPIO I/O signals +// +// This is the most important parameter of the GPIO IP core. It defines how many +// I/O signals core has. Range is from 1 to 32. If more than 32 I/O signals are +// required, use several instances of GPIO IP core. +// +// Default is 16. +// +`define GPIO_IOS 31 + +//depending on number of GPIO_IOS, define this... +// for example: if there is 26 GPIO_IOS, define GPIO_LINES26 +// + +`define GPIO_LINES31 + +// +// Undefine this one if you don't want to remove GPIO block from your design +// but you also don't need it. When it is undefined, all GPIO ports still +// remain valid and the core can be synthesized however internally there is +// no GPIO funationality. +// +// Defined by default (duhh !). +// +`define GPIO_IMPLEMENTED + +// +// Define to register all WISHBONE outputs. +// +// Register outputs if you are using GPIO core as a block and synthesizing +// and place&routing it separately from the rest of the system. +// +// If you do not need registered outputs, you can save some area by not defining +// this macro. By default it is defined. +// +`define GPIO_REGISTERED_WB_OUTPUTS + +// +// Define to register all GPIO pad outputs. +// +// Register outputs if you are using GPIO core as a block and synthesizing +// and place&routing it separately from the rest of the system. +// +// If you do not need registered outputs, you can save some area by not defining +// this macro. By default it is defined. +// +`define GPIO_REGISTERED_IO_OUTPUTS + +// +// Implement aux feature. If this define is not defined also aux_i port and +// RGPIO_AUX register will be removed +// +// Defined by default. +// +//`define GPIO_AUX_IMPLEMENT + +// +// If this is not defined clk_pad_i will be removed. Input lines will be lached on +// positive edge of system clock +// if disabled defines GPIO_NO_NEGEDGE_FLOPS, GPIO_NO_CLKPAD_LOGIC will have no effect. +// +// Defined by default. +// +//`define GPIO_CLKPAD + +// +// Define to avoid using negative edge clock flip-flops for external clock +// (caused by NEC register. Instead an inverted external clock with +// positive edge clock flip-flops will be used. +// This define don't have any effect if GPIO_CLKPAD is not defined and if GPIO_SYNC_IN_CLK is defined +// +// By default it is not defined. +// +//`define GPIO_NO_NEGEDGE_FLOPS + +// +// If GPIO_NO_NEGEDGE_FLOPS is defined, a mux needs to be placed on external clock +// clk_pad_i to implement RGPIO_CTRL[NEC] functionality. If no mux is allowed on +// clock signal, enable the following define. +// This define don't have any effect if GPIO_CLKPAD is not defined and if GPIO_SYNC_IN_CLK is defined +// +// By default it is not defined. +// +//`define GPIO_NO_CLKPAD_LOGIC + + +// +// synchronization defines +// +// Two synchronization flops to input lineis added. +// system clock synchronization. +// +`define GPIO_SYNC_IN_WB + +// +// Add synchronization flops to external clock input line. Gpio will have just one clock domain, +// everithing will be synchronized to wishbone clock. External clock muas be at least 2-3x slower +// as systam clock. +// +`define GPIO_SYNC_CLK_WB + +// +// Add synchronization to input pads. synchronization to external clock. +// Don't hawe any effect if GPIO_SYNC_CLK_WB is defined. +// +//`define GPIO_SYNC_IN_CLK + +// +// Add synchronization flops between system clock and external clock. +// Only possible if external clock is enabled and clock synchroization is disabled. +// +//`define GPIO_SYNC_IN_CLK_WB + + + +// +// Undefine if you don't need to read GPIO registers except for RGPIO_IN register. +// When it is undefined all reads of GPIO registers return RGPIO_IN register. This +// is usually useful if you want really small area (for example when implemented in +// FPGA). +// +// To follow GPIO IP core specification document this one must be defined. Also to +// successfully run the test bench it must be defined. By default it is defined. +// +`define GPIO_READREGS + +// +// Full WISHBONE address decoding +// +// It is is undefined, partial WISHBONE address decoding is performed. +// Undefine it if you need to save some area. +// +// By default it is defined. +// +`define GPIO_FULL_DECODE + +// +// Strict 32-bit WISHBONE access +// +// If this one is defined, all WISHBONE accesses must be 32-bit. If it is +// not defined, err_o is asserted whenever 8- or 16-bit access is made. +// Undefine it if you need to save some area. +// +// By default it is defined. +// +//`define GPIO_STRICT_32BIT_ACCESS +// +`ifdef GPIO_STRICT_32BIT_ACCESS +`else +// added by gorand : +// if GPIO_STRICT_32BIT_ACCESS is not defined, +// depending on number of gpio I/O lines, the following are defined : +// if the number of I/O lines is in range 1-8, GPIO_WB_BYTES1 is defined, +// if the number of I/O lines is in range 9-16, GPIO_WB_BYTES2 is defined, +// if the number of I/O lines is in range 17-24, GPIO_WB_BYTES3 is defined, +// if the number of I/O lines is in range 25-32, GPIO_WB_BYTES4 is defined, + +`define GPIO_WB_BYTES4 +//`define GPIO_WB_BYTES3 +//`define GPIO_WB_BYTES2 +//`define GPIO_WB_BYTES1 + +`endif + +// +// WISHBONE address bits used for full decoding of GPIO registers. +// +`define GPIO_ADDRHH 7 +`define GPIO_ADDRHL 6 +`define GPIO_ADDRLH 1 +`define GPIO_ADDRLL 0 + +// +// Bits of WISHBONE address used for partial decoding of GPIO registers. +// +// Default 5:2. +// +`define GPIO_OFS_BITS `GPIO_ADDRHL-1:`GPIO_ADDRLH+1 + +// +// Addresses of GPIO registers +// +// To comply with GPIO IP core specification document they must go from +// address 0 to address 0x18 in the following order: RGPIO_IN, RGPIO_OUT, +// RGPIO_OE, RGPIO_INTE, RGPIO_PTRIG, RGPIO_AUX and RGPIO_CTRL +// +// If particular register is not needed, it's address definition can be omitted +// and the register will not be implemented. Instead a fixed default value will +// be used. +// +`define GPIO_RGPIO_IN 4'h0 // Address 0x00 +`define GPIO_RGPIO_OUT 4'h1 // Address 0x04 +`define GPIO_RGPIO_OE 4'h2 // Address 0x08 +`define GPIO_RGPIO_INTE 4'h3 // Address 0x0c +`define GPIO_RGPIO_PTRIG 4'h4 // Address 0x10 + +`ifdef GPIO_AUX_IMPLEMENT +`define GPIO_RGPIO_AUX 4'h5 // Address 0x14 +`endif // GPIO_AUX_IMPLEMENT + +`define GPIO_RGPIO_CTRL 4'h6 // Address 0x18 +`define GPIO_RGPIO_INTS 4'h7 // Address 0x1c + +`ifdef GPIO_CLKPAD +`define GPIO_RGPIO_ECLK 4'h8 // Address 0x20 +`define GPIO_RGPIO_NEC 4'h9 // Address 0x24 +`endif // GPIO_CLKPAD + +// +// Default values for unimplemented GPIO registers +// +`define GPIO_DEF_RGPIO_IN `GPIO_IOS'h0 +`define GPIO_DEF_RGPIO_OUT `GPIO_IOS'h0 +`define GPIO_DEF_RGPIO_OE `GPIO_IOS'h0 +`define GPIO_DEF_RGPIO_INTE `GPIO_IOS'h0 +`define GPIO_DEF_RGPIO_PTRIG `GPIO_IOS'h0 +`define GPIO_DEF_RGPIO_AUX `GPIO_IOS'h0 +`define GPIO_DEF_RGPIO_CTRL `GPIO_IOS'h0 +`define GPIO_DEF_RGPIO_ECLK `GPIO_IOS'h0 +`define GPIO_DEF_RGPIO_NEC `GPIO_IOS'h0 + + +// +// RGPIO_CTRL bits +// +// To comply with the GPIO IP core specification document they must go from +// bit 0 to bit 1 in the following order: INTE, INT +// +`define GPIO_RGPIO_CTRL_INTE 0 +`define GPIO_RGPIO_CTRL_INTS 1 + + Index: rc-1.0/utils/contributions/gpio/rtl/gpio_top.v =================================================================== --- rc-1.0/utils/contributions/gpio/rtl/gpio_top.v (nonexistent) +++ rc-1.0/utils/contributions/gpio/rtl/gpio_top.v (revision 109) @@ -0,0 +1,1135 @@ +////////////////////////////////////////////////////////////////////// +//// //// +//// WISHBONE General-Purpose I/O //// +//// //// +//// This file is part of the GPIO project //// +//// http://www.opencores.org/cores/gpio/ //// +//// //// +//// Description //// +//// Implementation of GPIO IP core according to //// +//// GPIO IP core specification document. //// +//// //// +//// To Do: //// +//// Nothing //// +//// //// +//// Author(s): //// +//// - Damjan Lampret, lampret@opencores.org //// +//// //// +////////////////////////////////////////////////////////////////////// +//// //// +//// Copyright (C) 2000 Authors and OPENCORES.ORG //// +//// //// +//// This source file may be used and distributed without //// +//// restriction provided that this copyright statement is not //// +//// removed from the file and that any derivative work contains //// +//// the original copyright notice and the associated disclaimer. //// +//// //// +//// This source file is free software; you can redistribute it //// +//// and/or modify it under the terms of the GNU Lesser General //// +//// Public License as published by the Free Software Foundation; //// +//// either version 2.1 of the License, or (at your option) any //// +//// later version. //// +//// //// +//// This source is distributed in the hope that it will be //// +//// useful, but WITHOUT ANY WARRANTY; without even the implied //// +//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR //// +//// PURPOSE. See the GNU Lesser General Public License for more //// +//// details. //// +//// //// +//// You should have received a copy of the GNU Lesser General //// +//// Public License along with this source; if not, download it //// +//// from http://www.opencores.org/lgpl.shtml //// +//// //// +////////////////////////////////////////////////////////////////////// +// +// CVS Revision History +// +// $Log: not supported by cvs2svn $ +// Revision 1.17 2004/05/05 08:21:00 andreje +// Bugfixes when GPIO_RGPIO_ECLK/GPIO_RGPIO_NEC disabled, gpio oe name change and set to active-high according to spec +// +// Revision 1.16 2003/12/17 13:00:52 gorand +// added ECLK and NEC registers, all tests passed. +// +// Revision 1.15 2003/11/10 23:21:22 gorand +// bug fixed. all tests passed. +// +// Revision 1.14 2003/11/06 13:59:07 gorand +// added support for 8-bit access to registers. +// +// Revision 1.13 2002/11/18 22:35:18 lampret +// Bug fix. Interrupts were also asserted when condition was not met. +// +// Revision 1.12 2002/11/11 21:36:28 lampret +// Added ifdef to remove mux from clk_pad_i if mux is not allowed. This also removes RGPIO_CTRL[NEC]. +// +// Revision 1.11 2002/03/13 20:56:28 lampret +// Removed zero padding as per Avi Shamli suggestion. +// +// Revision 1.10 2002/03/13 20:47:57 lampret +// Ports changed per Ran Aviram suggestions. +// +// Revision 1.9 2002/03/09 03:43:27 lampret +// Interrupt is asserted only when an input changes (code patch by Jacob Gorban) +// +// Revision 1.8 2002/01/14 19:06:28 lampret +// Changed registered WISHBONE outputs wb_ack_o/wb_err_o to follow WB specification. +// +// Revision 1.7 2001/12/25 17:21:21 lampret +// Fixed two typos. +// +// Revision 1.6 2001/12/25 17:12:35 lampret +// Added RGPIO_INTS. +// +// Revision 1.5 2001/12/12 20:35:53 lampret +// Fixing style. +// +// Revision 1.4 2001/12/12 07:12:58 lampret +// Fixed bug when wb_inta_o is registered (GPIO_WB_REGISTERED_OUTPUTS) +// +// Revision 1.3 2001/11/15 02:24:37 lampret +// Added GPIO_REGISTERED_WB_OUTPUTS, GPIO_REGISTERED_IO_OUTPUTS and GPIO_NO_NEGEDGE_FLOPS. +// +// Revision 1.2 2001/10/31 02:26:51 lampret +// Fixed wb_err_o. +// +// Revision 1.1 2001/09/18 18:49:07 lampret +// Changed top level ptc into gpio_top. Changed defines.v into gpio_defines.v. +// +// Revision 1.1 2001/08/21 21:39:28 lampret +// Changed directory structure, port names and drfines. +// +// Revision 1.2 2001/07/14 20:39:26 lampret +// Better configurability. +// +// Revision 1.1 2001/06/05 07:45:26 lampret +// Added initial RTL and test benches. There are still some issues with these files. +// +// + +// synopsys translate_off +`include "timescale.v" +// synopsys translate_on +`include "gpio_defines.v" + +module gpio_top( + // WISHBONE Interface + wb_clk_i, wb_rst_i, wb_cyc_i, wb_adr_i, wb_dat_i, wb_sel_i, wb_we_i, wb_stb_i, + wb_dat_o, wb_ack_o, wb_err_o, wb_inta_o, + +`ifdef GPIO_AUX_IMPLEMENT + // Auxiliary inputs interface + aux_i, +`endif // GPIO_AUX_IMPLEMENT + + // External GPIO Interface + ext_pad_i, ext_pad_o, ext_padoe_o +`ifdef GPIO_CLKPAD + , clk_pad_i +`endif +); + +parameter dw = 32; +parameter aw = `GPIO_ADDRHH+1; +parameter gw = `GPIO_IOS; +// +// WISHBONE Interface +// +input wb_clk_i; // Clock +input wb_rst_i; // Reset +input wb_cyc_i; // cycle valid input +input [aw-1:0] wb_adr_i; // address bus inputs +input [dw-1:0] wb_dat_i; // input data bus +input [3:0] wb_sel_i; // byte select inputs +input wb_we_i; // indicates write transfer +input wb_stb_i; // strobe input +output [dw-1:0] wb_dat_o; // output data bus +output wb_ack_o; // normal termination +output wb_err_o; // termination w/ error +output wb_inta_o; // Interrupt request output + +`ifdef GPIO_AUX_IMPLEMENT +// Auxiliary Inputs Interface +input [gw-1:0] aux_i; // Auxiliary inputs +`endif // GPIO_AUX_IMPLEMENT + +// +// External GPIO Interface +// +input [gw-1:0] ext_pad_i; // GPIO Inputs +`ifdef GPIO_CLKPAD +input clk_pad_i; // GPIO Eclk +`endif // GPIO_CLKPAD +output [gw-1:0] ext_pad_o; // GPIO Outputs +output [gw-1:0] ext_padoe_o; // GPIO output drivers enables + +`ifdef GPIO_IMPLEMENTED + +// +// GPIO Input Register (or no register) +// +`ifdef GPIO_RGPIO_IN +reg [gw-1:0] rgpio_in; // RGPIO_IN register +`else +wire [gw-1:0] rgpio_in; // No register +`endif + +// +// GPIO Output Register (or no register) +// +`ifdef GPIO_RGPIO_OUT +reg [gw-1:0] rgpio_out; // RGPIO_OUT register +`else +wire [gw-1:0] rgpio_out; // No register +`endif + +// +// GPIO Output Driver Enable Register (or no register) +// +`ifdef GPIO_RGPIO_OE +reg [gw-1:0] rgpio_oe; // RGPIO_OE register +`else +wire [gw-1:0] rgpio_oe; // No register +`endif + +// +// GPIO Interrupt Enable Register (or no register) +// +`ifdef GPIO_RGPIO_INTE +reg [gw-1:0] rgpio_inte; // RGPIO_INTE register +`else +wire [gw-1:0] rgpio_inte; // No register +`endif + +// +// GPIO Positive edge Triggered Register (or no register) +// +`ifdef GPIO_RGPIO_PTRIG +reg [gw-1:0] rgpio_ptrig; // RGPIO_PTRIG register +`else +wire [gw-1:0] rgpio_ptrig; // No register +`endif + +// +// GPIO Auxiliary select Register (or no register) +// +`ifdef GPIO_RGPIO_AUX +reg [gw-1:0] rgpio_aux; // RGPIO_AUX register +`else +wire [gw-1:0] rgpio_aux; // No register +`endif + +// +// GPIO Control Register (or no register) +// +`ifdef GPIO_RGPIO_CTRL +reg [1:0] rgpio_ctrl; // RGPIO_CTRL register +`else +wire [1:0] rgpio_ctrl; // No register +`endif + +// +// GPIO Interrupt Status Register (or no register) +// +`ifdef GPIO_RGPIO_INTS +reg [gw-1:0] rgpio_ints; // RGPIO_INTS register +`else +wire [gw-1:0] rgpio_ints; // No register +`endif + +// +// GPIO Enable Clock Register (or no register) +// +`ifdef GPIO_RGPIO_ECLK +reg [gw-1:0] rgpio_eclk; // RGPIO_ECLK register +`else +wire [gw-1:0] rgpio_eclk; // No register +`endif + +// +// GPIO Active Negative Edge Register (or no register) +// +`ifdef GPIO_RGPIO_NEC +reg [gw-1:0] rgpio_nec; // RGPIO_NEC register +`else +wire [gw-1:0] rgpio_nec; // No register +`endif + + +// +// Synchronization flops for input signals +// +`ifdef GPIO_SYNC_IN_WB +reg [gw-1:0] sync , + ext_pad_s ; +`else +wire [gw-1:0] ext_pad_s ; +`endif + + + +// +// Internal wires & regs +// +wire rgpio_out_sel; // RGPIO_OUT select +wire rgpio_oe_sel; // RGPIO_OE select +wire rgpio_inte_sel; // RGPIO_INTE select +wire rgpio_ptrig_sel;// RGPIO_PTRIG select +wire rgpio_aux_sel; // RGPIO_AUX select +wire rgpio_ctrl_sel; // RGPIO_CTRL select +wire rgpio_ints_sel; // RGPIO_INTS select +wire rgpio_eclk_sel ; +wire rgpio_nec_sel ; +wire full_decoding; // Full address decoding qualification +wire [gw-1:0] in_muxed; // Muxed inputs +wire wb_ack; // WB Acknowledge +wire wb_err; // WB Error +wire wb_inta; // WB Interrupt +reg [dw-1:0] wb_dat; // WB Data out +`ifdef GPIO_REGISTERED_WB_OUTPUTS +reg wb_ack_o; // WB Acknowledge +reg wb_err_o; // WB Error +reg wb_inta_o; // WB Interrupt +reg [dw-1:0] wb_dat_o; // WB Data out +`endif +wire [gw-1:0] out_pad; // GPIO Outputs +`ifdef GPIO_REGISTERED_IO_OUTPUTS +reg [gw-1:0] ext_pad_o; // GPIO Outputs +`endif +`ifdef GPIO_CLKPAD +wire [gw-1:0] extc_in; // Muxed inputs sampled by external clock +wire [gw-1:0] pext_clk; // External clock for posedge flops +reg [gw-1:0] pextc_sampled; // Posedge external clock sampled inputs +`ifdef GPIO_NO_NEGEDGE_FLOPS +`ifdef GPIO_NO_CLKPAD_LOGIC +`else +reg [gw-1:0] nextc_sampled; // Negedge external clock sampled inputs +`endif // GPIO_NO_CLKPAD_LOGIC +`else +reg [gw-1:0] nextc_sampled; // Negedge external clock sampled inputs +`endif +`endif // GPIO_CLKPAD + + +// +// All WISHBONE transfer terminations are successful except when: +// a) full address decoding is enabled and address doesn't match +// any of the GPIO registers +// b) wb_sel_i evaluation is enabled and one of the wb_sel_i inputs is zero +// + +// +// WB Acknowledge +// +assign wb_ack = wb_cyc_i & wb_stb_i & !wb_err_o; + +// +// Optional registration of WB Ack +// +`ifdef GPIO_REGISTERED_WB_OUTPUTS +always @(posedge wb_clk_i or posedge wb_rst_i) + if (wb_rst_i) + wb_ack_o <= #1 1'b0; + else + wb_ack_o <= #1 wb_ack & ~wb_ack_o & (!wb_err) ; +`else +assign wb_ack_o = wb_ack; +`endif + +// +// WB Error +// +`ifdef GPIO_FULL_DECODE +`ifdef GPIO_STRICT_32BIT_ACCESS +assign wb_err = wb_cyc_i & wb_stb_i & (!full_decoding | (wb_sel_i != 4'b1111)); +`else +assign wb_err = wb_cyc_i & wb_stb_i & !full_decoding; +`endif +`else +`ifdef GPIO_STRICT_32BIT_ACCESS +assign wb_err = wb_cyc_i & wb_stb_i & (wb_sel_i != 4'b1111); +`else +assign wb_err = 1'b0; +`endif +`endif + +// +// Optional registration of WB error +// +`ifdef GPIO_REGISTERED_WB_OUTPUTS +always @(posedge wb_clk_i or posedge wb_rst_i) + if (wb_rst_i) + wb_err_o <= #1 1'b0; + else + wb_err_o <= #1 wb_err & ~wb_err_o; +`else +assign wb_err_o = wb_err; +`endif + +// +// Full address decoder +// +`ifdef GPIO_FULL_DECODE +assign full_decoding = (wb_adr_i[`GPIO_ADDRHH:`GPIO_ADDRHL] == {`GPIO_ADDRHH-`GPIO_ADDRHL+1{1'b0}}) & + (wb_adr_i[`GPIO_ADDRLH:`GPIO_ADDRLL] == {`GPIO_ADDRLH-`GPIO_ADDRLL+1{1'b0}}); +`else +assign full_decoding = 1'b1; +`endif + +// +// GPIO registers address decoder +// +`ifdef GPIO_RGPIO_OUT +assign rgpio_out_sel = wb_cyc_i & wb_stb_i & (wb_adr_i[`GPIO_OFS_BITS] == `GPIO_RGPIO_OUT) & full_decoding; +`endif +`ifdef GPIO_RGPIO_OE +assign rgpio_oe_sel = wb_cyc_i & wb_stb_i & (wb_adr_i[`GPIO_OFS_BITS] == `GPIO_RGPIO_OE) & full_decoding; +`endif +`ifdef GPIO_RGPIO_INTE +assign rgpio_inte_sel = wb_cyc_i & wb_stb_i & (wb_adr_i[`GPIO_OFS_BITS] == `GPIO_RGPIO_INTE) & full_decoding; +`endif +`ifdef GPIO_RGPIO_PTRIG +assign rgpio_ptrig_sel = wb_cyc_i & wb_stb_i & (wb_adr_i[`GPIO_OFS_BITS] == `GPIO_RGPIO_PTRIG) & full_decoding; +`endif +`ifdef GPIO_RGPIO_AUX +assign rgpio_aux_sel = wb_cyc_i & wb_stb_i & (wb_adr_i[`GPIO_OFS_BITS] == `GPIO_RGPIO_AUX) & full_decoding; +`endif +`ifdef GPIO_RGPIO_CTRL +assign rgpio_ctrl_sel = wb_cyc_i & wb_stb_i & (wb_adr_i[`GPIO_OFS_BITS] == `GPIO_RGPIO_CTRL) & full_decoding; +`endif +`ifdef GPIO_RGPIO_INTS +assign rgpio_ints_sel = wb_cyc_i & wb_stb_i & (wb_adr_i[`GPIO_OFS_BITS] == `GPIO_RGPIO_INTS) & full_decoding; +`endif +`ifdef GPIO_RGPIO_ECLK +assign rgpio_eclk_sel = wb_cyc_i & wb_stb_i & (wb_adr_i[`GPIO_OFS_BITS] == `GPIO_RGPIO_ECLK) & full_decoding; +`endif +`ifdef GPIO_RGPIO_NEC +assign rgpio_nec_sel = wb_cyc_i & wb_stb_i & (wb_adr_i[`GPIO_OFS_BITS] == `GPIO_RGPIO_NEC) & full_decoding; +`endif + + +// +// Write to RGPIO_CTRL or update of RGPIO_CTRL[INT] bit +// +`ifdef GPIO_RGPIO_CTRL +always @(posedge wb_clk_i or posedge wb_rst_i) + if (wb_rst_i) + rgpio_ctrl <= #1 2'b0; + else if (rgpio_ctrl_sel && wb_we_i) + rgpio_ctrl <= #1 wb_dat_i[1:0]; + else if (rgpio_ctrl[`GPIO_RGPIO_CTRL_INTE]) + rgpio_ctrl[`GPIO_RGPIO_CTRL_INTS] <= #1 rgpio_ctrl[`GPIO_RGPIO_CTRL_INTS] | wb_inta_o; +`else +assign rgpio_ctrl = 2'h01; // RGPIO_CTRL[EN] = 1 +`endif + +// +// Write to RGPIO_OUT +// +`ifdef GPIO_RGPIO_OUT +always @(posedge wb_clk_i or posedge wb_rst_i) + if (wb_rst_i) + rgpio_out <= #1 {gw{1'b0}}; + else if (rgpio_out_sel && wb_we_i) + begin +`ifdef GPIO_STRICT_32BIT_ACCESS + rgpio_out <= #1 wb_dat_i[gw-1:0]; +`endif + +`ifdef GPIO_WB_BYTES4 + if ( wb_sel_i [3] == 1'b1 ) + rgpio_out [gw-1:24] <= #1 wb_dat_i [gw-1:24] ; + if ( wb_sel_i [2] == 1'b1 ) + rgpio_out [23:16] <= #1 wb_dat_i [23:16] ; + if ( wb_sel_i [1] == 1'b1 ) + rgpio_out [15:8] <= #1 wb_dat_i [15:8] ; + if ( wb_sel_i [0] == 1'b1 ) + rgpio_out [7:0] <= #1 wb_dat_i [7:0] ; +`endif +`ifdef GPIO_WB_BYTES3 + if ( wb_sel_i [2] == 1'b1 ) + rgpio_out [gw-1:16] <= #1 wb_dat_i [gw-1:16] ; + if ( wb_sel_i [1] == 1'b1 ) + rgpio_out [15:8] <= #1 wb_dat_i [15:8] ; + if ( wb_sel_i [0] == 1'b1 ) + rgpio_out [7:0] <= #1 wb_dat_i [7:0] ; +`endif +`ifdef GPIO_WB_BYTES2 + if ( wb_sel_i [1] == 1'b1 ) + rgpio_out [gw-1:8] <= #1 wb_dat_i [gw-1:8] ; + if ( wb_sel_i [0] == 1'b1 ) + rgpio_out [7:0] <= #1 wb_dat_i [7:0] ; +`endif +`ifdef GPIO_WB_BYTES1 + if ( wb_sel_i [0] == 1'b1 ) + rgpio_out [gw-1:0] <= #1 wb_dat_i [gw-1:0] ; +`endif + end + +`else +assign rgpio_out = `GPIO_DEF_RGPIO_OUT; // RGPIO_OUT = 0x0 +`endif + +// +// Write to RGPIO_OE. +// +`ifdef GPIO_RGPIO_OE +always @(posedge wb_clk_i or posedge wb_rst_i) + if (wb_rst_i) + rgpio_oe <= #1 {gw{1'b0}}; + else if (rgpio_oe_sel && wb_we_i) + begin +`ifdef GPIO_STRICT_32BIT_ACCESS + rgpio_oe <= #1 wb_dat_i[gw-1:0]; +`endif + +`ifdef GPIO_WB_BYTES4 + if ( wb_sel_i [3] == 1'b1 ) + rgpio_oe [gw-1:24] <= #1 wb_dat_i [gw-1:24] ; + if ( wb_sel_i [2] == 1'b1 ) + rgpio_oe [23:16] <= #1 wb_dat_i [23:16] ; + if ( wb_sel_i [1] == 1'b1 ) + rgpio_oe [15:8] <= #1 wb_dat_i [15:8] ; + if ( wb_sel_i [0] == 1'b1 ) + rgpio_oe [7:0] <= #1 wb_dat_i [7:0] ; +`endif +`ifdef GPIO_WB_BYTES3 + if ( wb_sel_i [2] == 1'b1 ) + rgpio_oe [gw-1:16] <= #1 wb_dat_i [gw-1:16] ; + if ( wb_sel_i [1] == 1'b1 ) + rgpio_oe [15:8] <= #1 wb_dat_i [15:8] ; + if ( wb_sel_i [0] == 1'b1 ) + rgpio_oe [7:0] <= #1 wb_dat_i [7:0] ; +`endif +`ifdef GPIO_WB_BYTES2 + if ( wb_sel_i [1] == 1'b1 ) + rgpio_oe [gw-1:8] <= #1 wb_dat_i [gw-1:8] ; + if ( wb_sel_i [0] == 1'b1 ) + rgpio_oe [7:0] <= #1 wb_dat_i [7:0] ; +`endif +`ifdef GPIO_WB_BYTES1 + if ( wb_sel_i [0] == 1'b1 ) + rgpio_oe [gw-1:0] <= #1 wb_dat_i [gw-1:0] ; +`endif + end + +`else +assign rgpio_oe = `GPIO_DEF_RGPIO_OE; // RGPIO_OE = 0x0 +`endif + +// +// Write to RGPIO_INTE +// +`ifdef GPIO_RGPIO_INTE +always @(posedge wb_clk_i or posedge wb_rst_i) + if (wb_rst_i) + rgpio_inte <= #1 {gw{1'b0}}; + else if (rgpio_inte_sel && wb_we_i) + begin +`ifdef GPIO_STRICT_32BIT_ACCESS + rgpio_inte <= #1 wb_dat_i[gw-1:0]; +`endif + +`ifdef GPIO_WB_BYTES4 + if ( wb_sel_i [3] == 1'b1 ) + rgpio_inte [gw-1:24] <= #1 wb_dat_i [gw-1:24] ; + if ( wb_sel_i [2] == 1'b1 ) + rgpio_inte [23:16] <= #1 wb_dat_i [23:16] ; + if ( wb_sel_i [1] == 1'b1 ) + rgpio_inte [15:8] <= #1 wb_dat_i [15:8] ; + if ( wb_sel_i [0] == 1'b1 ) + rgpio_inte [7:0] <= #1 wb_dat_i [7:0] ; +`endif +`ifdef GPIO_WB_BYTES3 + if ( wb_sel_i [2] == 1'b1 ) + rgpio_inte [gw-1:16] <= #1 wb_dat_i [gw-1:16] ; + if ( wb_sel_i [1] == 1'b1 ) + rgpio_inte [15:8] <= #1 wb_dat_i [15:8] ; + if ( wb_sel_i [0] == 1'b1 ) + rgpio_inte [7:0] <= #1 wb_dat_i [7:0] ; +`endif +`ifdef GPIO_WB_BYTES2 + if ( wb_sel_i [1] == 1'b1 ) + rgpio_inte [gw-1:8] <= #1 wb_dat_i [gw-1:8] ; + if ( wb_sel_i [0] == 1'b1 ) + rgpio_inte [7:0] <= #1 wb_dat_i [7:0] ; +`endif +`ifdef GPIO_WB_BYTES1 + if ( wb_sel_i [0] == 1'b1 ) + rgpio_inte [gw-1:0] <= #1 wb_dat_i [gw-1:0] ; +`endif + end + + +`else +assign rgpio_inte = `GPIO_DEF_RGPIO_INTE; // RGPIO_INTE = 0x0 +`endif + +// +// Write to RGPIO_PTRIG +// +`ifdef GPIO_RGPIO_PTRIG +always @(posedge wb_clk_i or posedge wb_rst_i) + if (wb_rst_i) + rgpio_ptrig <= #1 {gw{1'b0}}; + else if (rgpio_ptrig_sel && wb_we_i) + begin +`ifdef GPIO_STRICT_32BIT_ACCESS + rgpio_ptrig <= #1 wb_dat_i[gw-1:0]; +`endif + +`ifdef GPIO_WB_BYTES4 + if ( wb_sel_i [3] == 1'b1 ) + rgpio_ptrig [gw-1:24] <= #1 wb_dat_i [gw-1:24] ; + if ( wb_sel_i [2] == 1'b1 ) + rgpio_ptrig [23:16] <= #1 wb_dat_i [23:16] ; + if ( wb_sel_i [1] == 1'b1 ) + rgpio_ptrig [15:8] <= #1 wb_dat_i [15:8] ; + if ( wb_sel_i [0] == 1'b1 ) + rgpio_ptrig [7:0] <= #1 wb_dat_i [7:0] ; +`endif +`ifdef GPIO_WB_BYTES3 + if ( wb_sel_i [2] == 1'b1 ) + rgpio_ptrig [gw-1:16] <= #1 wb_dat_i [gw-1:16] ; + if ( wb_sel_i [1] == 1'b1 ) + rgpio_ptrig [15:8] <= #1 wb_dat_i [15:8] ; + if ( wb_sel_i [0] == 1'b1 ) + rgpio_ptrig [7:0] <= #1 wb_dat_i [7:0] ; +`endif +`ifdef GPIO_WB_BYTES2 + if ( wb_sel_i [1] == 1'b1 ) + rgpio_ptrig [gw-1:8] <= #1 wb_dat_i [gw-1:8] ; + if ( wb_sel_i [0] == 1'b1 ) + rgpio_ptrig [7:0] <= #1 wb_dat_i [7:0] ; +`endif +`ifdef GPIO_WB_BYTES1 + if ( wb_sel_i [0] == 1'b1 ) + rgpio_ptrig [gw-1:0] <= #1 wb_dat_i [gw-1:0] ; +`endif + end + +`else +assign rgpio_ptrig = `GPIO_DEF_RGPIO_PTRIG; // RGPIO_PTRIG = 0x0 +`endif + +// +// Write to RGPIO_AUX +// +`ifdef GPIO_RGPIO_AUX +always @(posedge wb_clk_i or posedge wb_rst_i) + if (wb_rst_i) + rgpio_aux <= #1 {gw{1'b0}}; + else if (rgpio_aux_sel && wb_we_i) + begin +`ifdef GPIO_STRICT_32BIT_ACCESS + rgpio_aux <= #1 wb_dat_i[gw-1:0]; +`endif + +`ifdef GPIO_WB_BYTES4 + if ( wb_sel_i [3] == 1'b1 ) + rgpio_aux [gw-1:24] <= #1 wb_dat_i [gw-1:24] ; + if ( wb_sel_i [2] == 1'b1 ) + rgpio_aux [23:16] <= #1 wb_dat_i [23:16] ; + if ( wb_sel_i [1] == 1'b1 ) + rgpio_aux [15:8] <= #1 wb_dat_i [15:8] ; + if ( wb_sel_i [0] == 1'b1 ) + rgpio_aux [7:0] <= #1 wb_dat_i [7:0] ; +`endif +`ifdef GPIO_WB_BYTES3 + if ( wb_sel_i [2] == 1'b1 ) + rgpio_aux [gw-1:16] <= #1 wb_dat_i [gw-1:16] ; + if ( wb_sel_i [1] == 1'b1 ) + rgpio_aux [15:8] <= #1 wb_dat_i [15:8] ; + if ( wb_sel_i [0] == 1'b1 ) + rgpio_aux [7:0] <= #1 wb_dat_i [7:0] ; +`endif +`ifdef GPIO_WB_BYTES2 + if ( wb_sel_i [1] == 1'b1 ) + rgpio_aux [gw-1:8] <= #1 wb_dat_i [gw-1:8] ; + if ( wb_sel_i [0] == 1'b1 ) + rgpio_aux [7:0] <= #1 wb_dat_i [7:0] ; +`endif +`ifdef GPIO_WB_BYTES1 + if ( wb_sel_i [0] == 1'b1 ) + rgpio_aux [gw-1:0] <= #1 wb_dat_i [gw-1:0] ; +`endif + end + +`else +assign rgpio_aux = `GPIO_DEF_RGPIO_AUX; // RGPIO_AUX = 0x0 +`endif + + +// +// Write to RGPIO_ECLK +// +`ifdef GPIO_RGPIO_ECLK +always @(posedge wb_clk_i or posedge wb_rst_i) + if (wb_rst_i) + rgpio_eclk <= #1 {gw{1'b0}}; + else if (rgpio_eclk_sel && wb_we_i) + begin +`ifdef GPIO_STRICT_32BIT_ACCESS + rgpio_eclk <= #1 wb_dat_i[gw-1:0]; +`endif + +`ifdef GPIO_WB_BYTES4 + if ( wb_sel_i [3] == 1'b1 ) + rgpio_eclk [gw-1:24] <= #1 wb_dat_i [gw-1:24] ; + if ( wb_sel_i [2] == 1'b1 ) + rgpio_eclk [23:16] <= #1 wb_dat_i [23:16] ; + if ( wb_sel_i [1] == 1'b1 ) + rgpio_eclk [15:8] <= #1 wb_dat_i [15:8] ; + if ( wb_sel_i [0] == 1'b1 ) + rgpio_eclk [7:0] <= #1 wb_dat_i [7:0] ; +`endif +`ifdef GPIO_WB_BYTES3 + if ( wb_sel_i [2] == 1'b1 ) + rgpio_eclk [gw-1:16] <= #1 wb_dat_i [gw-1:16] ; + if ( wb_sel_i [1] == 1'b1 ) + rgpio_eclk [15:8] <= #1 wb_dat_i [15:8] ; + if ( wb_sel_i [0] == 1'b1 ) + rgpio_eclk [7:0] <= #1 wb_dat_i [7:0] ; +`endif +`ifdef GPIO_WB_BYTES2 + if ( wb_sel_i [1] == 1'b1 ) + rgpio_eclk [gw-1:8] <= #1 wb_dat_i [gw-1:8] ; + if ( wb_sel_i [0] == 1'b1 ) + rgpio_eclk [7:0] <= #1 wb_dat_i [7:0] ; +`endif +`ifdef GPIO_WB_BYTES1 + if ( wb_sel_i [0] == 1'b1 ) + rgpio_eclk [gw-1:0] <= #1 wb_dat_i [gw-1:0] ; +`endif + end + + +`else +assign rgpio_eclk = `GPIO_DEF_RGPIO_ECLK; // RGPIO_ECLK = 0x0 +`endif + + + +// +// Write to RGPIO_NEC +// +`ifdef GPIO_RGPIO_NEC +always @(posedge wb_clk_i or posedge wb_rst_i) + if (wb_rst_i) + rgpio_nec <= #1 {gw{1'b0}}; + else if (rgpio_nec_sel && wb_we_i) + begin +`ifdef GPIO_STRICT_32BIT_ACCESS + rgpio_nec <= #1 wb_dat_i[gw-1:0]; +`endif + +`ifdef GPIO_WB_BYTES4 + if ( wb_sel_i [3] == 1'b1 ) + rgpio_nec [gw-1:24] <= #1 wb_dat_i [gw-1:24] ; + if ( wb_sel_i [2] == 1'b1 ) + rgpio_nec [23:16] <= #1 wb_dat_i [23:16] ; + if ( wb_sel_i [1] == 1'b1 ) + rgpio_nec [15:8] <= #1 wb_dat_i [15:8] ; + if ( wb_sel_i [0] == 1'b1 ) + rgpio_nec [7:0] <= #1 wb_dat_i [7:0] ; +`endif +`ifdef GPIO_WB_BYTES3 + if ( wb_sel_i [2] == 1'b1 ) + rgpio_nec [gw-1:16] <= #1 wb_dat_i [gw-1:16] ; + if ( wb_sel_i [1] == 1'b1 ) + rgpio_nec [15:8] <= #1 wb_dat_i [15:8] ; + if ( wb_sel_i [0] == 1'b1 ) + rgpio_nec [7:0] <= #1 wb_dat_i [7:0] ; +`endif +`ifdef GPIO_WB_BYTES2 + if ( wb_sel_i [1] == 1'b1 ) + rgpio_nec [gw-1:8] <= #1 wb_dat_i [gw-1:8] ; + if ( wb_sel_i [0] == 1'b1 ) + rgpio_nec [7:0] <= #1 wb_dat_i [7:0] ; +`endif +`ifdef GPIO_WB_BYTES1 + if ( wb_sel_i [0] == 1'b1 ) + rgpio_nec [gw-1:0] <= #1 wb_dat_i [gw-1:0] ; +`endif + end + + +`else +assign rgpio_nec = `GPIO_DEF_RGPIO_NEC; // RGPIO_NEC = 0x0 +`endif + +// +// synchronize inputs to systam clock +// +`ifdef GPIO_SYNC_IN_WB +always @(posedge wb_clk_i or posedge wb_rst_i) + if (wb_rst_i) begin + sync <= #1 {gw{1'b0}} ; + ext_pad_s <= #1 {gw{1'b0}} ; + end else begin + sync <= #1 ext_pad_i ; + ext_pad_s <= #1 sync ; + end +`else +assign ext_pad_s = ext_pad_i; +`endif // GPIO_SYNC_IN_WB + +// +// Latch into RGPIO_IN +// +`ifdef GPIO_RGPIO_IN +always @(posedge wb_clk_i or posedge wb_rst_i) + if (wb_rst_i) + rgpio_in <= #1 {gw{1'b0}}; + else + rgpio_in <= #1 in_muxed; +`else +assign rgpio_in = in_muxed; +`endif + +`ifdef GPIO_CLKPAD + +`ifdef GPIO_SYNC_CLK_WB +// +// external clock enabled +// synchronized to system clock +// (one clock domain) +// + +reg sync_clk, + clk_s , + clk_r ; +wire pedge , + nedge ; +wire [gw-1:0] pedge_vec , + nedge_vec ; +wire [gw-1:0] in_lach ; + +assign pedge = clk_s & !clk_r ; +assign nedge = !clk_s & clk_r ; +assign pedge_vec = {gw{pedge}} ; +assign nedge_vec = {gw{nedge}} ; + +assign in_lach = (~rgpio_nec & pedge_vec) | (rgpio_nec & nedge_vec) ; +assign extc_in = (in_lach & ext_pad_s) | (~in_lach & pextc_sampled) ; + +always @(posedge wb_clk_i or posedge wb_rst_i) + if (wb_rst_i) begin + sync_clk <= #1 1'b0 ; + clk_s <= #1 1'b0 ; + clk_r <= #1 1'b0 ; + end else begin + sync_clk <= #1 clk_pad_i ; + clk_s <= #1 sync_clk ; + clk_r <= #1 clk_s ; + end + +always @(posedge wb_clk_i or posedge wb_rst_i) + if (wb_rst_i) begin + pextc_sampled <= #1 {gw{1'b0}}; + end else begin + pextc_sampled <= #1 extc_in ; + end + +assign in_muxed = (rgpio_eclk & pextc_sampled) | (~rgpio_eclk & ext_pad_s) ; + +`else +// +// external clock enabled +// not synchronized to system clock +// (two clock domains) +// + +`ifdef GPIO_SYNC_IN_CLK_WB + +reg [gw-1:0] syn_extc , + extc_s ; + +always @(posedge wb_clk_i or posedge wb_rst_i) + if (wb_rst_i) begin + syn_extc <= #1 {gw{1'b0}}; + extc_s <= #1 {gw{1'b0}}; + end else begin + syn_extc <= #1 extc_in ; + extc_s <= #1 syn_extc; + end + +`else + +wire [gw-1:0] extc_s ; +assign extc_s = syn_extc ; + +`endif // GPIO_SYNC_IN_CLK_WB + +`ifdef GPIO_SYNC_IN_CLK +reg [gw-1:0] syn_pclk , + ext_pad_spc ; + +always @(posedge clk_pad_i or posedge wb_rst_i) + if (wb_rst_i) begin + syn_pclk <= #1 {gw{1'b0}} ; + ext_pad_spc <= #1 {gw{1'b0}} ; + end else begin + syn_pclk <= #1 ext_pad_i ; + ext_pad_spc <= #1 syn_pclk ; + end + +`else + +wire [gw-1:0] ext_pad_spc ; +assign ext_pad_spc = ext_pad_i ; + +`endif // GPIO_SYNC_IN_CLK + +always @(posedge clk_pad_i or posedge wb_rst_i) + if (wb_rst_i) begin + pextc_sampled <= #1 {gw{1'b0}}; + end else begin + pextc_sampled <= #1 ext_pad_spc ; + end + + +`ifdef GPIO_NO_NEGEDGE_FLOPS + +`ifdef GPIO_NO_CLKPAD_LOGIC + +assign extc_in = pextc_sampled; + +`else + +wire clk_n; +assign clk_n = !clk_pad_i; + +`ifdef GPIO_SYNC_IN_CLK +reg [gw-1:0] syn_nclk , + ext_pad_snc ; + +always @(posedge clk_n or posedge wb_rst_i) + if (wb_rst_i) begin + syn_nclk <= #1 {gw{1'b0}} ; + ext_pad_snc <= #1 {gw{1'b0}} ; + end else begin + syn_nclk <= #1 ext_pad_i ; + ext_pad_snc <= #1 syn_nclk ; + end + +`else + +wire [gw-1:0] ext_pad_snc ; +assign ext_pad_snc = ext_pad_i ; + +`endif // GPIO_SYNC_IN_CLK + +always @(posedge clk_n or posedge wb_rst_i) + if (wb_rst_i) begin + nextc_sampled <= #1 {gw{1'b0}}; + end else begin + nextc_sampled <= #1 ext_pad_snc ; + end + +assign extc_in = (~rgpio_nec & pextc_sampled) | (rgpio_nec & nextc_sampled) ; + +`endif // GPIO_NO_CLKPAD_LOGIC + + +`else + +`ifdef GPIO_SYNC_IN_CLK +reg [gw-1:0] syn_nclk , + ext_pad_snc ; + +always @(negedge clk_n or posedge wb_rst_i) + if (wb_rst_i) begin + syn_nclk <= #1 {gw{1'b0}} ; + ext_pad_snc <= #1 {gw{1'b0}} ; + end else begin + syn_nclk <= #1 ext_pad_i ; + ext_pad_snc <= #1 syn_nclk ; + end + +`else + +wire [gw-1:0] ext_pad_snc ; +assign ext_pad_snc = ext_pad_i ; + +`endif // GPIO_SYNC_IN_CLK + +always @(negedge clk_pad_i or posedge wb_rst_i) + if (wb_rst_i) begin + nextc_sampled <= #1 {gw{1'b0}}; + end else begin + nextc_sampled <= #1 ext_pad_snc ; + end + +assign extc_in = (~rgpio_nec & pextc_sampled) | (rgpio_nec & nextc_sampled) ; + +`endif // GPIO_NO_NEGEDGE_FLOPS + +assign in_muxed = (rgpio_eclk & extc_s) | (~rgpio_eclk & ext_pad_s) ; + + +`endif // GPIO_SYNC_CLK_WB + + +`else + +assign in_muxed = ext_pad_s ; + +`endif // GPIO_CLKPAD + + + +// +// Mux all registers when doing a read of GPIO registers +// +always @(wb_adr_i or rgpio_in or rgpio_out or rgpio_oe or rgpio_inte or + rgpio_ptrig or rgpio_aux or rgpio_ctrl or rgpio_ints or rgpio_eclk or rgpio_nec) + case (wb_adr_i[`GPIO_OFS_BITS]) // synopsys full_case parallel_case +`ifdef GPIO_READREGS + `ifdef GPIO_RGPIO_OUT + `GPIO_RGPIO_OUT: begin + wb_dat[dw-1:0] = rgpio_out; + end + `endif + `ifdef GPIO_RGPIO_OE + `GPIO_RGPIO_OE: begin + wb_dat[dw-1:0] = rgpio_oe; + end + `endif + `ifdef GPIO_RGPIO_INTE + `GPIO_RGPIO_INTE: begin + wb_dat[dw-1:0] = rgpio_inte; + end + `endif + `ifdef GPIO_RGPIO_PTRIG + `GPIO_RGPIO_PTRIG: begin + wb_dat[dw-1:0] = rgpio_ptrig; + end + `endif + `ifdef GPIO_RGPIO_NEC + `GPIO_RGPIO_NEC: begin + wb_dat[dw-1:0] = rgpio_nec; + end + `endif + `ifdef GPIO_RGPIO_ECLK + `GPIO_RGPIO_ECLK: begin + wb_dat[dw-1:0] = rgpio_eclk; + end + `endif + `ifdef GPIO_RGPIO_AUX + `GPIO_RGPIO_AUX: begin + wb_dat[dw-1:0] = rgpio_aux; + end + `endif + `ifdef GPIO_RGPIO_CTRL + `GPIO_RGPIO_CTRL: begin + wb_dat[1:0] = rgpio_ctrl; + wb_dat[dw-1:2] = {dw-2{1'b0}}; + end + `endif +`endif + `ifdef GPIO_RGPIO_INTS + `GPIO_RGPIO_INTS: begin + wb_dat[dw-1:0] = rgpio_ints; + end + `endif + default: begin + wb_dat[dw-1:0] = rgpio_in; + end + endcase + +// +// WB data output +// +`ifdef GPIO_REGISTERED_WB_OUTPUTS +always @(posedge wb_clk_i or posedge wb_rst_i) + if (wb_rst_i) + wb_dat_o <= #1 {dw{1'b0}}; + else + wb_dat_o <= #1 wb_dat; +`else +assign wb_dat_o = wb_dat; +`endif + +// +// RGPIO_INTS +// +`ifdef GPIO_RGPIO_INTS +always @(posedge wb_clk_i or posedge wb_rst_i) + if (wb_rst_i) + rgpio_ints <= #1 {gw{1'b0}}; + else if (rgpio_ints_sel && wb_we_i) + rgpio_ints <= #1 wb_dat_i[gw-1:0]; + else if (rgpio_ctrl[`GPIO_RGPIO_CTRL_INTE]) + rgpio_ints <= #1 (rgpio_ints | ((in_muxed ^ rgpio_in) & ~(in_muxed ^ rgpio_ptrig)) & rgpio_inte); +`else +assign rgpio_ints = (rgpio_ints | ((in_muxed ^ rgpio_in) & ~(in_muxed ^ rgpio_ptrig)) & rgpio_inte); +`endif + +// +// Generate interrupt request +// +assign wb_inta = |rgpio_ints ? rgpio_ctrl[`GPIO_RGPIO_CTRL_INTE] : 1'b0; + +// +// Optional registration of WB interrupt +// +`ifdef GPIO_REGISTERED_WB_OUTPUTS +always @(posedge wb_clk_i or posedge wb_rst_i) + if (wb_rst_i) + wb_inta_o <= #1 1'b0; + else + wb_inta_o <= #1 wb_inta; +`else +assign wb_inta_o = wb_inta; +`endif // GPIO_REGISTERED_WB_OUTPUTS + +// +// Output enables are RGPIO_OE bits +// +assign ext_padoe_o = rgpio_oe; + +// +// Generate GPIO outputs +// +`ifdef GPIO_AUX_IMPLEMENT +assign out_pad = rgpio_out & ~rgpio_aux | aux_i & rgpio_aux; +`else +assign out_pad = rgpio_out ; +`endif // GPIO_AUX_IMPLEMENT + +// +// Optional registration of GPIO outputs +// +`ifdef GPIO_REGISTERED_IO_OUTPUTS +always @(posedge wb_clk_i or posedge wb_rst_i) + if (wb_rst_i) + ext_pad_o <= #1 {gw{1'b0}}; + else + ext_pad_o <= #1 out_pad; +`else +assign ext_pad_o = out_pad; +`endif // GPIO_REGISTERED_IO_OUTPUTS + + +`else + +// +// When GPIO is not implemented, drive all outputs as would when RGPIO_CTRL +// is cleared and WISHBONE transfers complete with errors +// +assign wb_inta_o = 1'b0; +assign wb_ack_o = 1'b0; +assign wb_err_o = wb_cyc_i & wb_stb_i; +assign ext_padoe_o = {gw{1'b1}}; +assign ext_pad_o = {gw{1'b0}}; + +// +// Read GPIO registers +// +assign wb_dat_o = {dw{1'b0}}; + +`endif // GPIO_IMPLEMENTED + +endmodule + Index: rc-1.0/utils/contributions/gpio/rtl/minsoc_top.ucf =================================================================== --- rc-1.0/utils/contributions/gpio/rtl/minsoc_top.ucf (nonexistent) +++ rc-1.0/utils/contributions/gpio/rtl/minsoc_top.ucf (revision 109) @@ -0,0 +1,36 @@ + +NET "clk" LOC = E12; # 50 MHz on-board clock oscillator +NET "reset" LOC = T14; # Push Button BTN_NORTH + +# UART Peripheral +NET "uart_stx" LOC = E15; # RS232 Serial port ( DTE Connector ) +NET "uart_srx" LOC = F16; # + +# GPIO +NET "io_pins<0>" LOC = R20; +NET "io_pins<1>" LOC = T19; +NET "io_pins<2>" LOC = U20; +NET "io_pins<3>" LOC = U19; +NET "io_pins<4>" LOC = V19; +NET "io_pins<5>" LOC = V20; +NET "io_pins<6>" LOC = Y22; +NET "io_pins<7>" LOC = W21; + +NET "i_pins<0>" LOC = V8; +NET "i_pins<1>" LOC = U10; +NET "i_pins<2>" LOC = U8; +NET "i_pins<3>" LOC = T9; +NET "i_pins<4>" LOC = T16; +NET "i_pins<5>" LOC = U15; +#NET "i_pins<6>" LOC = ; +NET "i_pins<7>" LOC = T15; + +################################################################################# +# Pin constraints including the IOSTANDARD and DRIVE +# Reference : Spartan-3A/3AN FPGA Starter Kit Board User Guide ( UG334 v1.1 ) +################################################################################# + +#NET "clk" LOC = E12 | IOSTANDARD = LVCMOS33; +#NET "uart_stx" LOC = E15 | IOSTANDARD = LVCMOS33 | DRIVE = 8 | SLEW = SLOW ; +#NET "uart_srx" LOC = F16 | IOSTANDARD = LVCMOS33; +#NET "reset" LOC = T14 | IOSTANDARD = LVCMOS33 | PULLDOWN ; Index: rc-1.0/utils/contributions/gpio/rtl/minsoc_defines.v =================================================================== --- rc-1.0/utils/contributions/gpio/rtl/minsoc_defines.v (nonexistent) +++ rc-1.0/utils/contributions/gpio/rtl/minsoc_defines.v (revision 109) @@ -0,0 +1,130 @@ +// +// Define FPGA manufacturer +// +//`define GENERIC_FPGA +//`define ALTERA_FPGA +`define XILINX_FPGA + +// +// Define FPGA Model (comment all out for ALTERA) +// +//`define SPARTAN2 +//`define SPARTAN3 +//`define SPARTAN3E +`define SPARTAN3A +//`define VIRTEX +//`define VIRTEX2 +//`define VIRTEX4 +//`define VIRTEX5 + + +// +// Memory +// +`define MEMORY_ADR_WIDTH 13 //MEMORY_ADR_WIDTH IS NOT ALLOWED TO BE LESS THAN 12, memory is composed by blocks of address width 11 + //Address width of memory -> select memory depth, 2 powers MEMORY_ADR_WIDTH defines the memory depth + //the memory data width is 32 bit, memory amount in Bytes = 4*memory depth + +// +// Memory type (uncomment something if ASIC or generic memory) +// +//`define GENERIC_MEMORY +//`define AVANT_ATP +//`define VIRAGE_SSP +//`define VIRTUALSILICON_SSP + + +// +// TAP selection +// +//`define GENERIC_TAP +`define FPGA_TAP + +// +// Clock Division selection +// +//`define NO_CLOCK_DIVISION +//`define GENERIC_CLOCK_DIVISION +`define FPGA_CLOCK_DIVISION //Altera ALTPLL is not implemented, didn't find the code for its verilog instantiation + //if you selected altera and this, the GENERIC_CLOCK_DIVISION will be automatically taken + +// +// Define division +// +`define CLOCK_DIVISOR 5 //in case of GENERIC_CLOCK_DIVISION the real value will be rounded down to an even value + //in FPGA case, check minsoc_clock_manager for allowed divisors + //DO NOT USE CLOCK_DIVISOR = 1 COMMENT THE CLOCK DIVISION SELECTION INSTEAD + +// +// Reset polarity +// +//`define NEGATIVE_RESET; //rstn +`define POSITIVE_RESET; //rst + +// +// Start-up circuit (only necessary later to load firmware automatically from SPI memory) +// +//`define START_UP + +// +// Connected modules +// +`define UART +//`define ETHERNET +`define GPIO + +// +// Ethernet reset +// +//`define ETH_RESET 1'b0 +`define ETH_RESET 1'b1 + +// +// GPIO Pins +// +`define GPIO_HAS_INPUT_PINS +//`define GPIO_HAS_OUTPUT_PINS +`define GPIO_HAS_BIDIR_PINS + +`define GPIO_NUM_INPUT 4'd8 +`define GPIO_NUM_OUTPUT 4'd0 +`define GPIO_NUM_BIDIR 4'd8 + +// +// Interrupts +// +`define APP_INT_RES1 1:0 +`define APP_INT_UART 2 +`define APP_INT_RES2 3 +`define APP_INT_ETH 4 +`define APP_INT_PS2 5 +`define APP_INT_GPIO 6 +`define APP_INT_RES3 19:7 + +// +// Address map +// +`define APP_ADDR_DEC_W 8 +`define APP_ADDR_SRAM `APP_ADDR_DEC_W'h00 +`define APP_ADDR_FLASH `APP_ADDR_DEC_W'h04 +`define APP_ADDR_DECP_W 4 +`define APP_ADDR_PERIP `APP_ADDR_DECP_W'h9 +`define APP_ADDR_SPI `APP_ADDR_DEC_W'h97 +`define APP_ADDR_ETH `APP_ADDR_DEC_W'h92 +`define APP_ADDR_AUDIO `APP_ADDR_DEC_W'h9d +`define APP_ADDR_UART `APP_ADDR_DEC_W'h90 +`define APP_ADDR_PS2 `APP_ADDR_DEC_W'h94 +`define APP_ADDR_GPIO `APP_ADDR_DEC_W'h9e +`define APP_ADDR_RES2 `APP_ADDR_DEC_W'h9f + +// +// Set-up GENERIC_TAP, GENERIC_MEMORY if GENERIC_FPGA was chosen +// and GENERIC_CLOCK_DIVISION if NO_CLOCK_DIVISION was not set +// +`ifdef GENERIC_FPGA + `define GENERIC_TAP + `define GENERIC_MEMORY + `ifndef NO_CLOCK_DIVISION + `define GENERIC_CLOCK_DIVISION + `endif +`endif Index: rc-1.0/utils/contributions/gpio/rtl/minsoc_spartan_3a_starter_kit_ios.v =================================================================== --- rc-1.0/utils/contributions/gpio/rtl/minsoc_spartan_3a_starter_kit_ios.v (nonexistent) +++ rc-1.0/utils/contributions/gpio/rtl/minsoc_spartan_3a_starter_kit_ios.v (revision 109) @@ -0,0 +1,224 @@ +////////////////////////////////////////////////////////////////////////////////// +// Company: +// Engineer: +// +// Create Date: 11:51:27 10/29/2009 +// Design Name: +// Module Name: minsoc_spartan_3a_starter_kit_ios +// Project Name: +// Target Devices: +// Tool versions: +// Description: +// +// Dependencies: +// +// Revision: +// Revision 0.01 - File Created +// Additional Comments: +// +////////////////////////////////////////////////////////////////////////////////// + +module minsoc_spartan_3a_starter_kit_ios +( + // Signals from GPIO Core + ext_pad_o, + ext_pad_oe, + ext_pad_i, + + // Signals driving external pins + i_pins, + o_pins, + io_pins +); + parameter gpio_num = 32; + parameter i_line_num = 8; + parameter o_line_num = 8; + parameter io_line_num= 8; + + input [gpio_num-1:0] ext_pad_o; + input [gpio_num-1:0] ext_pad_oe; + output [gpio_num-1:0] ext_pad_i; + + input [i_line_num-1:0] i_pins; + output [o_line_num-1:0] o_pins; + inout [io_line_num-1:0] io_pins; + + IOBUF #( + .DRIVE(12), // Specify the output drive strength + .IBUF_DELAY_VALUE("0"), // Specify the amount of added input delay for the buffer, "0"-"16" (Spartan-3E only) + .IFD_DELAY_VALUE("AUTO"), // Specify the amount of added delay for input register, "AUTO", "0"-"8" (Spartan-3E only) + .IOSTANDARD("DEFAULT"), // Specify the I/O standard + .SLEW("SLOW") // Specify the output slew rate + ) IOBUF_inst_0 ( + .O(ext_pad_i[0]), // Buffer output + .IO(io_pins[0]), // Buffer inout port (connect directly to top-level port) + .I(ext_pad_o[0]), // Buffer input + .T(~ext_pad_oe[0]) // 3-state enable input + ); + + IOBUF #( + .DRIVE(12), // Specify the output drive strength + .IBUF_DELAY_VALUE("0"), // Specify the amount of added input delay for the buffer, "0"-"16" (Spartan-3E only) + .IFD_DELAY_VALUE("AUTO"), // Specify the amount of added delay for input register, "AUTO", "0"-"8" (Spartan-3E only) + .IOSTANDARD("DEFAULT"), // Specify the I/O standard + .SLEW("SLOW") // Specify the output slew rate + ) IOBUF_inst_1 ( + .O(ext_pad_i[1]), // Buffer output + .IO(io_pins[1]), // Buffer inout port (connect directly to top-level port) + .I(ext_pad_o[1]), // Buffer input + .T(~ext_pad_oe[1]) // 3-state enable input + ); + + IOBUF #( + .DRIVE(12), // Specify the output drive strength + .IBUF_DELAY_VALUE("0"), // Specify the amount of added input delay for the buffer, "0"-"16" (Spartan-3E only) + .IFD_DELAY_VALUE("AUTO"), // Specify the amount of added delay for input register, "AUTO", "0"-"8" (Spartan-3E only) + .IOSTANDARD("DEFAULT"), // Specify the I/O standard + .SLEW("SLOW") // Specify the output slew rate + ) IOBUF_inst_2 ( + .O(ext_pad_i[2]), // Buffer output + .IO(io_pins[2]), // Buffer inout port (connect directly to top-level port) + .I(ext_pad_o[2]), // Buffer input + .T(~ext_pad_oe[2]) // 3-state enable input + ); + + IOBUF #( + .DRIVE(12), // Specify the output drive strength + .IBUF_DELAY_VALUE("0"), // Specify the amount of added input delay for the buffer, "0"-"16" (Spartan-3E only) + .IFD_DELAY_VALUE("AUTO"), // Specify the amount of added delay for input register, "AUTO", "0"-"8" (Spartan-3E only) + .IOSTANDARD("DEFAULT"), // Specify the I/O standard + .SLEW("SLOW") // Specify the output slew rate + ) IOBUF_inst_3 ( + .O(ext_pad_i[3]), // Buffer output + .IO(io_pins[3]), // Buffer inout port (connect directly to top-level port) + .I(ext_pad_o[3]), // Buffer input + .T(~ext_pad_oe[3]) // 3-state enable input + ); + + IOBUF #( + .DRIVE(12), // Specify the output drive strength + .IBUF_DELAY_VALUE("0"), // Specify the amount of added input delay for the buffer, "0"-"16" (Spartan-3E only) + .IFD_DELAY_VALUE("AUTO"), // Specify the amount of added delay for input register, "AUTO", "0"-"8" (Spartan-3E only) + .IOSTANDARD("DEFAULT"), // Specify the I/O standard + .SLEW("SLOW") // Specify the output slew rate + ) IOBUF_inst_4 ( + .O(ext_pad_i[4]), // Buffer output + .IO(io_pins[4]), // Buffer inout port (connect directly to top-level port) + .I(ext_pad_o[4]), // Buffer input + .T(~ext_pad_oe[4]) // 3-state enable input + ); + + IOBUF #( + .DRIVE(12), // Specify the output drive strength + .IBUF_DELAY_VALUE("0"), // Specify the amount of added input delay for the buffer, "0"-"16" (Spartan-3E only) + .IFD_DELAY_VALUE("AUTO"), // Specify the amount of added delay for input register, "AUTO", "0"-"8" (Spartan-3E only) + .IOSTANDARD("DEFAULT"), // Specify the I/O standard + .SLEW("SLOW") // Specify the output slew rate + ) IOBUF_inst_5 ( + .O(ext_pad_i[5]), // Buffer output + .IO(io_pins[5]), // Buffer inout port (connect directly to top-level port) + .I(ext_pad_o[5]), // Buffer input + .T(~ext_pad_oe[5]) // 3-state enable input + ); + + IOBUF #( + .DRIVE(12), // Specify the output drive strength + .IBUF_DELAY_VALUE("0"), // Specify the amount of added input delay for the buffer, "0"-"16" (Spartan-3E only) + .IFD_DELAY_VALUE("AUTO"), // Specify the amount of added delay for input register, "AUTO", "0"-"8" (Spartan-3E only) + .IOSTANDARD("DEFAULT"), // Specify the I/O standard + .SLEW("SLOW") // Specify the output slew rate + ) IOBUF_inst_6 ( + .O(ext_pad_i[6]), // Buffer output + .IO(io_pins[6]), // Buffer inout port (connect directly to top-level port) + .I(ext_pad_o[6]), // Buffer input + .T(~ext_pad_oe[6]) // 3-state enable input + ); + + IOBUF #( + .DRIVE(12), // Specify the output drive strength + .IBUF_DELAY_VALUE("0"), // Specify the amount of added input delay for the buffer, "0"-"16" (Spartan-3E only) + .IFD_DELAY_VALUE("AUTO"), // Specify the amount of added delay for input register, "AUTO", "0"-"8" (Spartan-3E only) + .IOSTANDARD("DEFAULT"), // Specify the I/O standard + .SLEW("SLOW") // Specify the output slew rate + ) IOBUF_inst_7 ( + .O(ext_pad_i[7]), // Buffer output + .IO(io_pins[7]), // Buffer inout port (connect directly to top-level port) + .I(ext_pad_o[7]), // Buffer input + .T(~ext_pad_oe[7]) // 3-state enable input + ); + + + IBUF #( + .IBUF_DELAY_VALUE("0"), // Specify the amount of added input delay for // the buffer, "0"-"16" (Spartan-3E/3A only) + .IFD_DELAY_VALUE("AUTO"), // Specify the amount of added delay for input // register, "AUTO", "0"-"8" (Spartan-3E/3A only) + .IOSTANDARD("DEFAULT") // Specify the input I/O standard + )IBUF_inst_0 ( + .O(ext_pad_i[8]), // Buffer output + .I(i_pins[0]) // Buffer input (connect directly to top-level port) + ); + + IBUF #( + .IBUF_DELAY_VALUE("0"), // Specify the amount of added input delay for // the buffer, "0"-"16" (Spartan-3E/3A only) + .IFD_DELAY_VALUE("AUTO"), // Specify the amount of added delay for input // register, "AUTO", "0"-"8" (Spartan-3E/3A only) + .IOSTANDARD("DEFAULT") // Specify the input I/O standard + )IBUF_inst_1 ( + .O(ext_pad_i[9]), // Buffer output + .I(i_pins[1]) // Buffer input (connect directly to top-level port) + ); + + IBUF #( + .IBUF_DELAY_VALUE("0"), // Specify the amount of added input delay for // the buffer, "0"-"16" (Spartan-3E/3A only) + .IFD_DELAY_VALUE("AUTO"), // Specify the amount of added delay for input // register, "AUTO", "0"-"8" (Spartan-3E/3A only) + .IOSTANDARD("DEFAULT") // Specify the input I/O standard + )IBUF_inst_2 ( + .O(ext_pad_i[10]), // Buffer output + .I(i_pins[2]) // Buffer input (connect directly to top-level port) + ); + + IBUF #( + .IBUF_DELAY_VALUE("0"), // Specify the amount of added input delay for // the buffer, "0"-"16" (Spartan-3E/3A only) + .IFD_DELAY_VALUE("AUTO"), // Specify the amount of added delay for input // register, "AUTO", "0"-"8" (Spartan-3E/3A only) + .IOSTANDARD("DEFAULT") // Specify the input I/O standard + )IBUF_inst_3 ( + .O(ext_pad_i[11]), // Buffer output + .I(i_pins[3]) // Buffer input (connect directly to top-level port) + ); + + IBUF #( + .IBUF_DELAY_VALUE("0"), // Specify the amount of added input delay for // the buffer, "0"-"16" (Spartan-3E/3A only) + .IFD_DELAY_VALUE("AUTO"), // Specify the amount of added delay for input // register, "AUTO", "0"-"8" (Spartan-3E/3A only) + .IOSTANDARD("DEFAULT") // Specify the input I/O standard + )IBUF_inst_4 ( + .O(ext_pad_i[12]), // Buffer output + .I(i_pins[4]) // Buffer input (connect directly to top-level port) + ); + + IBUF #( + .IBUF_DELAY_VALUE("0"), // Specify the amount of added input delay for // the buffer, "0"-"16" (Spartan-3E/3A only) + .IFD_DELAY_VALUE("AUTO"), // Specify the amount of added delay for input // register, "AUTO", "0"-"8" (Spartan-3E/3A only) + .IOSTANDARD("DEFAULT") // Specify the input I/O standard + )IBUF_inst_5 ( + .O(ext_pad_i[13]), // Buffer output + .I(i_pins[5]) // Buffer input (connect directly to top-level port) + ); + + /* PUSH Button NORTH is RESET. + IBUF #( + .IBUF_DELAY_VALUE("0"), // Specify the amount of added input delay for // the buffer, "0"-"16" (Spartan-3E/3A only) + .IFD_DELAY_VALUE("AUTO"), // Specify the amount of added delay for input // register, "AUTO", "0"-"8" (Spartan-3E/3A only) + .IOSTANDARD("DEFAULT") // Specify the input I/O standard + )IBUF_inst_6 ( + .O(ext_pad_i[14]), // Buffer output + .I(i_pins[6]) // Buffer input (connect directly to top-level port) + ); + */ + + IBUF #( + .IBUF_DELAY_VALUE("0"), // Specify the amount of added input delay for // the buffer, "0"-"16" (Spartan-3E/3A only) + .IFD_DELAY_VALUE("AUTO"), // Specify the amount of added delay for input // register, "AUTO", "0"-"8" (Spartan-3E/3A only) + .IOSTANDARD("DEFAULT") // Specify the input I/O standard + )IBUF_inst_7 ( + .O(ext_pad_i[15]), // Buffer output + .I(i_pins[7]) // Buffer input (connect directly to top-level port) + ); +endmodule Index: rc-1.0/utils/contributions/gpio/rtl/minsoc_top.v =================================================================== --- rc-1.0/utils/contributions/gpio/rtl/minsoc_top.v (nonexistent) +++ rc-1.0/utils/contributions/gpio/rtl/minsoc_top.v (revision 109) @@ -0,0 +1,1105 @@ +`include "minsoc_defines.v" +`include "or1200_defines.v" + +`include "gpio_defines.v" + +module minsoc_top ( + clk,reset + + //JTAG ports +`ifdef GENERIC_TAP + , jtag_tdi,jtag_tms,jtag_tck, + jtag_tdo,jtag_vref,jtag_gnd +`endif + + //SPI ports +`ifdef START_UP + , spi_flash_mosi, spi_flash_miso, spi_flash_sclk, spi_flash_ss +`endif + + //UART ports +`ifdef UART + , uart_stx,uart_srx +`endif + + // Ethernet ports +`ifdef ETHERNET + , eth_col, eth_crs, eth_trste, eth_tx_clk, + eth_tx_en, eth_tx_er, eth_txd, eth_rx_clk, + eth_rx_dv, eth_rx_er, eth_rxd, eth_fds_mdint, + eth_mdc, eth_mdio +`endif + + // GPIO ports +`ifdef GPIO + `ifdef GPIO_HAS_INPUT_PINS + ,i_pins + `endif + `ifdef GPIO_HAS_OUTPUT_PINS + ,o_pins + `endif + `ifdef GPIO_HAS_BIDIR_PINS + ,io_pins + `endif +`endif +); + +// +// I/O Ports +// + + input clk; + input reset; + +// +// SPI controller external i/f wires +// +`ifdef START_UP +output spi_flash_mosi; +input spi_flash_miso; +output spi_flash_sclk; +output [1:0] spi_flash_ss; +`endif + +// +// UART +// +`ifdef UART + output uart_stx; + input uart_srx; +`endif + +// +// Ethernet +// +`ifdef ETHERNET +output eth_tx_er; +input eth_tx_clk; +output eth_tx_en; +output [3:0] eth_txd; +input eth_rx_er; +input eth_rx_clk; +input eth_rx_dv; +input [3:0] eth_rxd; +input eth_col; +input eth_crs; +output eth_trste; +input eth_fds_mdint; +inout eth_mdio; +output eth_mdc; +`endif + +// +// GPIO +// +`ifdef GPIO + `ifdef GPIO_HAS_INPUT_PINS + input [`GPIO_NUM_INPUT-1:0] i_pins; + `endif + `ifdef GPIO_HAS_OUTPUT_PINS + output [`GPIO_NUM_OUTPUT-1:0] o_pins; + `endif + `ifdef GPIO_HAS_BIDIR_PINS + inout [`GPIO_NUM_BIDIR-1:0] io_pins; + `endif +`endif + +// +// JTAG +// +`ifdef GENERIC_TAP + input jtag_tdi; + input jtag_tms; + input jtag_tck; + output jtag_tdo; + output jtag_vref; + output jtag_gnd; + + +assign jtag_vref = 1'b1; +assign jtag_gnd = 1'b0; +`endif + +wire rstn; + +`ifdef POSITIVE_RESET +assign rstn = ~reset; +`elsif NEGATIVE_RESET +assign rstn = reset; +`endif + +// +// Internal wires +// + +// +// Debug core master i/f wires +// +wire [31:0] wb_dm_adr_o; +wire [31:0] wb_dm_dat_i; +wire [31:0] wb_dm_dat_o; +wire [3:0] wb_dm_sel_o; +wire wb_dm_we_o; +wire wb_dm_stb_o; +wire wb_dm_cyc_o; +wire wb_dm_ack_i; +wire wb_dm_err_i; + +// +// Debug <-> RISC wires +// +wire [3:0] dbg_lss; +wire [1:0] dbg_is; +wire [10:0] dbg_wp; +wire dbg_bp; +wire [31:0] dbg_dat_dbg; +wire [31:0] dbg_dat_risc; +wire [31:0] dbg_adr; +wire dbg_ewt; +wire dbg_stall; +wire [2:0] dbg_op; //dbg_op[0] = dbg_we //dbg_op[2] = dbg_stb (didn't change for backward compatibility with DBG_IF_MODEL +wire dbg_ack; + +// +// RISC instruction master i/f wires +// +wire [31:0] wb_rim_adr_o; +wire wb_rim_cyc_o; +wire [31:0] wb_rim_dat_i; +wire [31:0] wb_rim_dat_o; +wire [3:0] wb_rim_sel_o; +wire wb_rim_ack_i; +wire wb_rim_err_i; +wire wb_rim_rty_i = 1'b0; +wire wb_rim_we_o; +wire wb_rim_stb_o; +wire [31:0] wb_rif_dat_i; +wire wb_rif_ack_i; + +// +// RISC data master i/f wires +// +wire [31:0] wb_rdm_adr_o; +wire wb_rdm_cyc_o; +wire [31:0] wb_rdm_dat_i; +wire [31:0] wb_rdm_dat_o; +wire [3:0] wb_rdm_sel_o; +wire wb_rdm_ack_i; +wire wb_rdm_err_i; +wire wb_rdm_rty_i = 1'b0; +wire wb_rdm_we_o; +wire wb_rdm_stb_o; + +// +// RISC misc +// +wire [19:0] pic_ints; + +// +// Flash controller slave i/f wires +// +wire [31:0] wb_fs_dat_i; +wire [31:0] wb_fs_dat_o; +wire [31:0] wb_fs_adr_i; +wire [3:0] wb_fs_sel_i; +wire wb_fs_we_i; +wire wb_fs_cyc_i; +wire wb_fs_stb_i; +wire wb_fs_ack_o; +wire wb_fs_err_o; + +// +// SPI controller slave i/f wires +// +wire [31:0] wb_sp_dat_i; +wire [31:0] wb_sp_dat_o; +wire [31:0] wb_sp_adr_i; +wire [3:0] wb_sp_sel_i; +wire wb_sp_we_i; +wire wb_sp_cyc_i; +wire wb_sp_stb_i; +wire wb_sp_ack_o; +wire wb_sp_err_o; + +// +// SPI controller external i/f wires +// +wire spi_flash_mosi; +wire spi_flash_miso; +wire spi_flash_sclk; +wire [1:0] spi_flash_ss; + +// +// SRAM controller slave i/f wires +// +wire [31:0] wb_ss_dat_i; +wire [31:0] wb_ss_dat_o; +wire [31:0] wb_ss_adr_i; +wire [3:0] wb_ss_sel_i; +wire wb_ss_we_i; +wire wb_ss_cyc_i; +wire wb_ss_stb_i; +wire wb_ss_ack_o; +wire wb_ss_err_o; + +// +// Ethernet core master i/f wires +// +wire [31:0] wb_em_adr_o; +wire [31:0] wb_em_dat_i; +wire [31:0] wb_em_dat_o; +wire [3:0] wb_em_sel_o; +wire wb_em_we_o; +wire wb_em_stb_o; +wire wb_em_cyc_o; +wire wb_em_ack_i; +wire wb_em_err_i; + +// +// Ethernet core slave i/f wires +// +wire [31:0] wb_es_dat_i; +wire [31:0] wb_es_dat_o; +wire [31:0] wb_es_adr_i; +wire [3:0] wb_es_sel_i; +wire wb_es_we_i; +wire wb_es_cyc_i; +wire wb_es_stb_i; +wire wb_es_ack_o; +wire wb_es_err_o; + +// +// Ethernet external i/f wires +// +wire eth_mdo; +wire eth_mdoe; + +// +// UART16550 core slave i/f wires +// +wire [31:0] wb_us_dat_i; +wire [31:0] wb_us_dat_o; +wire [31:0] wb_us_adr_i; +wire [3:0] wb_us_sel_i; +wire wb_us_we_i; +wire wb_us_cyc_i; +wire wb_us_stb_i; +wire wb_us_ack_o; +wire wb_us_err_o; + +// +// UART external i/f wires +// +wire uart_stx; +wire uart_srx; + +// +// GPIO core slave i/f wires +// +wire [31:0] wb_gpio_dat_i; +wire [31:0] wb_gpio_dat_o; +wire [31:0] wb_gpio_adr_i; +wire [3:0] wb_gpio_sel_i; +wire wb_gpio_we_i; +wire wb_gpio_cyc_i; +wire wb_gpio_stb_i; +wire wb_gpio_ack_o; +wire wb_gpio_err_o; + +// +// Interface to GPIO core - Device specific core +// +wire [`GPIO_IOS:0] ext_pad_o; +wire [`GPIO_IOS:0] ext_pad_i; +wire [`GPIO_IOS:0] ext_pad_oe_o; + +// +// Reset debounce +// +reg rst_r; +reg wb_rst; + +// +// Global clock +// +wire wb_clk; + +// +// Reset debounce +// +always @(posedge wb_clk or negedge rstn) + if (~rstn) + rst_r <= 1'b1; + else + rst_r <= #1 1'b0; + +// +// Reset debounce +// +always @(posedge wb_clk) + wb_rst <= #1 rst_r; + +// +// Clock Divider +// +minsoc_clock_manager # +( + .divisor(`CLOCK_DIVISOR) +) +clk_adjust ( + .clk_i(clk), + .clk_o(wb_clk) +); + +// +// Unused WISHBONE signals +// +assign wb_us_err_o = 1'b0; +assign wb_fs_err_o = 1'b0; +assign wb_sp_err_o = 1'b0; + +// +// Unused interrupts +// +assign pic_ints[`APP_INT_RES1] = 'b0; +assign pic_ints[`APP_INT_RES2] = 'b0; +assign pic_ints[`APP_INT_RES3] = 'b0; +assign pic_ints[`APP_INT_PS2] = 'b0; + +// +// Ethernet tri-state +// +`ifdef ETHERNET +assign eth_mdio = eth_mdoe ? eth_mdo : 1'bz; +assign eth_trste = `ETH_RESET; +`endif + + +// +// RISC Instruction address for Flash +// +// Until first access to real Flash area, +// CPU instruction is fixed to jump to the Flash area. +// After Flash area is accessed, CPU instructions +// come from the tc_top (wishbone "switch"). +// +`ifdef START_UP +reg jump_flash; +reg [3:0] rif_counter; +reg [31:0] rif_dat_int; +reg rif_ack_int; + +always @(posedge wb_clk or negedge rstn) +begin + if (!rstn) begin + jump_flash <= #1 1'b1; + rif_counter <= 4'h0; + rif_ack_int <= 1'b0; + end + else begin + rif_ack_int <= 1'b0; + + if (wb_rim_cyc_o && (wb_rim_adr_o[31:32-`APP_ADDR_DEC_W] == `APP_ADDR_FLASH)) + jump_flash <= #1 1'b0; + + if ( jump_flash == 1'b1 ) begin + if ( wb_rim_cyc_o && wb_rim_stb_o && ~wb_rim_we_o ) begin + rif_counter <= rif_counter + 1'b1; + rif_ack_int <= 1'b1; + end + end + end +end + +always @ (rif_counter) +begin + case ( rif_counter ) + 4'h0: rif_dat_int = { `OR1200_OR32_MOVHI , 5'h01 , 4'h0 , 1'b0 , `APP_ADDR_FLASH , 8'h00 }; + 4'h1: rif_dat_int = { `OR1200_OR32_ORI , 5'h01 , 5'h01 , 16'h0000 }; + 4'h2: rif_dat_int = { `OR1200_OR32_JR , 10'h000 , 5'h01 , 11'h000 }; + 4'h3: rif_dat_int = { `OR1200_OR32_NOP , 10'h000 , 16'h0000 }; + default: rif_dat_int = 32'h0000_0000; + endcase +end + +assign wb_rif_dat_i = jump_flash ? rif_dat_int : wb_rim_dat_i; + +assign wb_rif_ack_i = jump_flash ? rif_ack_int : wb_rim_ack_i; + +`else +assign wb_rif_dat_i = wb_rim_dat_i; +assign wb_rif_ack_i = wb_rim_ack_i; +`endif + + +// +// TAP<->dbg_interface +// +wire jtag_tck; +wire debug_tdi; +wire debug_tdo; +wire capture_dr; +wire shift_dr; +wire pause_dr; +wire update_dr; + +wire debug_select; +wire test_logic_reset; + +// +// Instantiation of the development i/f +// +adbg_top dbg_top ( + + // JTAG pins + .tck_i ( jtag_tck ), + .tdi_i ( debug_tdi ), + .tdo_o ( debug_tdo ), + .rst_i ( test_logic_reset ), //cable without rst + + // Boundary Scan signals + .capture_dr_i ( capture_dr ), + .shift_dr_i ( shift_dr ), + .pause_dr_i ( pause_dr ), + .update_dr_i ( update_dr ), + + .debug_select_i( debug_select ), + // WISHBONE common + .wb_clk_i ( wb_clk ), + + // WISHBONE master interface + .wb_adr_o ( wb_dm_adr_o ), + .wb_dat_i ( wb_dm_dat_i ), + .wb_dat_o ( wb_dm_dat_o ), + .wb_sel_o ( wb_dm_sel_o ), + .wb_we_o ( wb_dm_we_o ), + .wb_stb_o ( wb_dm_stb_o ), + .wb_cyc_o ( wb_dm_cyc_o ), + .wb_ack_i ( wb_dm_ack_i ), + .wb_err_i ( wb_dm_err_i ), + .wb_cti_o ( ), + .wb_bte_o ( ), + + // RISC signals + .cpu0_clk_i ( wb_clk ), + .cpu0_addr_o ( dbg_adr ), + .cpu0_data_i ( dbg_dat_risc ), + .cpu0_data_o ( dbg_dat_dbg ), + .cpu0_bp_i ( dbg_bp ), + .cpu0_stall_o( dbg_stall ), + .cpu0_stb_o ( dbg_op[2] ), + .cpu0_we_o ( dbg_op[0] ), + .cpu0_ack_i ( dbg_ack ), + .cpu0_rst_o ( ) + +); + +// +// JTAG TAP controller instantiation +// +`ifdef GENERIC_TAP +tap_top tap_top( + // JTAG pads + .tms_pad_i(jtag_tms), + .tck_pad_i(jtag_tck), + .trstn_pad_i(rstn), + .tdi_pad_i(jtag_tdi), + .tdo_pad_o(jtag_tdo), + .tdo_padoe_o( ), + + // TAP states + .test_logic_reset_o( test_logic_reset ), + .run_test_idle_o(), + .shift_dr_o(shift_dr), + .pause_dr_o(pause_dr), + .update_dr_o(update_dr), + .capture_dr_o(capture_dr), + + // Select signals for boundary scan or mbist + .extest_select_o(), + .sample_preload_select_o(), + .mbist_select_o(), + .debug_select_o(debug_select), + + // TDO signal that is connected to TDI of sub-modules. + .tdi_o(debug_tdi), + + // TDI signals from sub-modules + .debug_tdo_i(debug_tdo), // from debug module + .bs_chain_tdo_i(1'b0), // from Boundary Scan Chain + .mbist_tdo_i(1'b0) // from Mbist Chain +); +`elsif FPGA_TAP +`ifdef ALTERA_FPGA +altera_virtual_jtag tap_top( + .tck_o(jtag_tck), + .debug_tdo_o(debug_tdo), + .tdi_o(debug_tdi), + .test_logic_reset_o(test_logic_reset), + .run_test_idle_o(), + .shift_dr_o(shift_dr), + .capture_dr_o(capture_dr), + .pause_dr_o(pause_dr), + .update_dr_o(update_dr), + .debug_select_o(debug_select) +); +`elsif XILINX_FPGA +minsoc_xilinx_internal_jtag tap_top( + .tck_o( jtag_tck ), + .debug_tdo_i( debug_tdo ), + .tdi_o( debug_tdi ), + + .test_logic_reset_o( test_logic_reset ), + .run_test_idle_o( ), + + .shift_dr_o( shift_dr ), + .capture_dr_o( capture_dr ), + .pause_dr_o( pause_dr ), + .update_dr_o( update_dr ), + .debug_select_o( debug_select ) +); +`endif // !FPGA_TAP + +`endif // !GENERIC_TAP + +// +// Instantiation of the OR1200 RISC +// +or1200_top or1200_top ( + + // Common + .rst_i ( wb_rst ), + .clk_i ( wb_clk ), +`ifdef OR1200_CLMODE_1TO2 + .clmode_i ( 2'b01 ), +`else +`ifdef OR1200_CLMODE_1TO4 + .clmode_i ( 2'b11 ), +`else + .clmode_i ( 2'b00 ), +`endif +`endif + + // WISHBONE Instruction Master + .iwb_clk_i ( wb_clk ), + .iwb_rst_i ( wb_rst ), + .iwb_cyc_o ( wb_rim_cyc_o ), + .iwb_adr_o ( wb_rim_adr_o ), + .iwb_dat_i ( wb_rif_dat_i ), + .iwb_dat_o ( wb_rim_dat_o ), + .iwb_sel_o ( wb_rim_sel_o ), + .iwb_ack_i ( wb_rif_ack_i ), + .iwb_err_i ( wb_rim_err_i ), + .iwb_rty_i ( wb_rim_rty_i ), + .iwb_we_o ( wb_rim_we_o ), + .iwb_stb_o ( wb_rim_stb_o ), + + // WISHBONE Data Master + .dwb_clk_i ( wb_clk ), + .dwb_rst_i ( wb_rst ), + .dwb_cyc_o ( wb_rdm_cyc_o ), + .dwb_adr_o ( wb_rdm_adr_o ), + .dwb_dat_i ( wb_rdm_dat_i ), + .dwb_dat_o ( wb_rdm_dat_o ), + .dwb_sel_o ( wb_rdm_sel_o ), + .dwb_ack_i ( wb_rdm_ack_i ), + .dwb_err_i ( wb_rdm_err_i ), + .dwb_rty_i ( wb_rdm_rty_i ), + .dwb_we_o ( wb_rdm_we_o ), + .dwb_stb_o ( wb_rdm_stb_o ), + + // Debug + .dbg_stall_i ( dbg_stall ), + .dbg_dat_i ( dbg_dat_dbg ), + .dbg_adr_i ( dbg_adr ), + .dbg_ewt_i ( 1'b0 ), + .dbg_lss_o ( dbg_lss ), + .dbg_is_o ( dbg_is ), + .dbg_wp_o ( dbg_wp ), + .dbg_bp_o ( dbg_bp ), + .dbg_dat_o ( dbg_dat_risc ), + .dbg_ack_o ( dbg_ack ), + .dbg_stb_i ( dbg_op[2] ), + .dbg_we_i ( dbg_op[0] ), + + // Power Management + .pm_clksd_o ( ), + .pm_cpustall_i ( 1'b0 ), + .pm_dc_gate_o ( ), + .pm_ic_gate_o ( ), + .pm_dmmu_gate_o ( ), + .pm_immu_gate_o ( ), + .pm_tt_gate_o ( ), + .pm_cpu_gate_o ( ), + .pm_wakeup_o ( ), + .pm_lvolt_o ( ), + + // Interrupts + .pic_ints_i ( pic_ints ) +); + +// +// Startup OR1k +// +`ifdef START_UP +OR1K_startup OR1K_startup0 +( + .wb_adr_i(wb_fs_adr_i[6:2]), + .wb_stb_i(wb_fs_stb_i), + .wb_cyc_i(wb_fs_cyc_i), + .wb_dat_o(wb_fs_dat_o), + .wb_ack_o(wb_fs_ack_o), + .wb_clk(wb_clk), + .wb_rst(wb_rst) +); + +spi_flash_top # +( + .divider(0), + .divider_len(2) +) +spi_flash_top0 +( + .wb_clk_i(wb_clk), + .wb_rst_i(wb_rst), + .wb_adr_i(wb_sp_adr_i[4:2]), + .wb_dat_i(wb_sp_dat_i), + .wb_dat_o(wb_sp_dat_o), + .wb_sel_i(wb_sp_sel_i), + .wb_we_i(wb_sp_we_i), + .wb_stb_i(wb_sp_stb_i), + .wb_cyc_i(wb_sp_cyc_i), + .wb_ack_o(wb_sp_ack_o), + + .mosi_pad_o(spi_flash_mosi), + .miso_pad_i(spi_flash_miso), + .sclk_pad_o(spi_flash_sclk), + .ss_pad_o(spi_flash_ss) +); +`else +assign wb_fs_dat_o = 32'h0000_0000; +assign wb_fs_ack_o = 1'b0; +assign wb_sp_dat_o = 32'h0000_0000; +assign wb_sp_ack_o = 1'b0; +`endif + +// +// Instantiation of the SRAM controller +// +minsoc_onchip_ram_top # +( + .adr_width(`MEMORY_ADR_WIDTH) //16 blocks of 2048 bytes memory 32768 +) +onchip_ram_top ( + + // WISHBONE common + .wb_clk_i ( wb_clk ), + .wb_rst_i ( wb_rst ), + + // WISHBONE slave + .wb_dat_i ( wb_ss_dat_i ), + .wb_dat_o ( wb_ss_dat_o ), + .wb_adr_i ( wb_ss_adr_i ), + .wb_sel_i ( wb_ss_sel_i ), + .wb_we_i ( wb_ss_we_i ), + .wb_cyc_i ( wb_ss_cyc_i ), + .wb_stb_i ( wb_ss_stb_i ), + .wb_ack_o ( wb_ss_ack_o ), + .wb_err_o ( wb_ss_err_o ) +); + +// +// Instantiation of the UART16550 +// +`ifdef UART +uart_top uart_top ( + + // WISHBONE common + .wb_clk_i ( wb_clk ), + .wb_rst_i ( wb_rst ), + + // WISHBONE slave + .wb_adr_i ( wb_us_adr_i[4:0] ), + .wb_dat_i ( wb_us_dat_i ), + .wb_dat_o ( wb_us_dat_o ), + .wb_we_i ( wb_us_we_i ), + .wb_stb_i ( wb_us_stb_i ), + .wb_cyc_i ( wb_us_cyc_i ), + .wb_ack_o ( wb_us_ack_o ), + .wb_sel_i ( wb_us_sel_i ), + + // Interrupt request + .int_o ( pic_ints[`APP_INT_UART] ), + + // UART signals + // serial input/output + .stx_pad_o ( uart_stx ), + .srx_pad_i ( uart_srx ), + + // modem signals + .rts_pad_o ( ), + .cts_pad_i ( 1'b0 ), + .dtr_pad_o ( ), + .dsr_pad_i ( 1'b0 ), + .ri_pad_i ( 1'b0 ), + .dcd_pad_i ( 1'b0 ) +); +`else +assign wb_us_dat_o = 32'h0000_0000; +assign wb_us_ack_o = 1'b0; +`endif + + +// +// Instantiation of the GPIO +// +`ifdef GPIO +gpio_top #( .gw(`GPIO_IOS + 1) ) +gpio_top_inst ( + + // WISHBONE common + .wb_clk_i ( wb_clk ), + .wb_rst_i ( wb_rst ), + + // WISHBONE slave + .wb_adr_i ( wb_gpio_adr_i[4:0] ), + .wb_dat_i ( wb_gpio_dat_i ), + .wb_dat_o ( wb_gpio_dat_o ), + .wb_we_i ( wb_gpio_we_i ), + .wb_stb_i ( wb_gpio_stb_i ), + .wb_cyc_i ( wb_gpio_cyc_i ), + .wb_ack_o ( wb_gpio_ack_o ), + .wb_sel_i ( wb_gpio_sel_i ), + + // Interrupt request + .wb_inta_o ( pic_ints[`APP_INT_GPIO] ), + + // GPIO external signals + .ext_pad_o ( ext_pad_o ), + .ext_pad_i ( ext_pad_i ), + .ext_padoe_o( ext_pad_oe_o ) + +); + +minsoc_spartan_3a_starter_kit_ios #( .gpio_num(`GPIO_IOS + 1), + `ifdef GPIO_HAS_INPUT_PINS + .i_line_num(`GPIO_NUM_INPUT), + `endif + `ifdef GPIO_HAS_OUTPUT_PINS + .o_line_num(`GPIO_NUM_OUTPUT), + `endif + `ifdef GPIO_HAS_BIDIR_PINS + .io_line_num(`GPIO_NUM_BIDIR) + `endif +) minsoc_spartan_3a_starter_kit_ios_inst_0 ( + .ext_pad_o( ext_pad_o ), + .ext_pad_oe( ext_pad_oe_o ), + .ext_pad_i( ext_pad_i ), + `ifdef GPIO_HAS_INPUT_PINS + .i_pins( i_pins ), + `else + .i_pins( ), + `endif + `ifdef GPIO_HAS_OUTPUT_PINS + .o_pins( o_pins ), + `else + .o_pins( ), + `endif + `ifdef GPIO_HAS_BIDIR_PINS + .io_pins( io_pins ) + `else + .io_pins( ) + `endif +); + +`else +assign wb_gpio_dat_o = 32'h0000_0000; +assign wb_gpio_ack_o = 1'b0; +`endif + + + +// +// Instantiation of the Ethernet 10/100 MAC +// +`ifdef ETHERNET +eth_top eth_top ( + + // WISHBONE common + .wb_clk_i ( wb_clk ), + .wb_rst_i ( wb_rst ), + + // WISHBONE slave + .wb_dat_i ( wb_es_dat_i ), + .wb_dat_o ( wb_es_dat_o ), + .wb_adr_i ( wb_es_adr_i[11:2] ), + .wb_sel_i ( wb_es_sel_i ), + .wb_we_i ( wb_es_we_i ), + .wb_cyc_i ( wb_es_cyc_i ), + .wb_stb_i ( wb_es_stb_i ), + .wb_ack_o ( wb_es_ack_o ), + .wb_err_o ( wb_es_err_o ), + + // WISHBONE master + .m_wb_adr_o ( wb_em_adr_o ), + .m_wb_sel_o ( wb_em_sel_o ), + .m_wb_we_o ( wb_em_we_o ), + .m_wb_dat_o ( wb_em_dat_o ), + .m_wb_dat_i ( wb_em_dat_i ), + .m_wb_cyc_o ( wb_em_cyc_o ), + .m_wb_stb_o ( wb_em_stb_o ), + .m_wb_ack_i ( wb_em_ack_i ), + .m_wb_err_i ( wb_em_err_i ), + + // TX + .mtx_clk_pad_i ( eth_tx_clk ), + .mtxd_pad_o ( eth_txd ), + .mtxen_pad_o ( eth_tx_en ), + .mtxerr_pad_o ( eth_tx_er ), + + // RX + .mrx_clk_pad_i ( eth_rx_clk ), + .mrxd_pad_i ( eth_rxd ), + .mrxdv_pad_i ( eth_rx_dv ), + .mrxerr_pad_i ( eth_rx_er ), + .mcoll_pad_i ( eth_col ), + .mcrs_pad_i ( eth_crs ), + + // MIIM + .mdc_pad_o ( eth_mdc ), + .md_pad_i ( eth_mdio ), + .md_pad_o ( eth_mdo ), + .md_padoe_o ( eth_mdoe ), + + // Interrupt + .int_o ( pic_ints[`APP_INT_ETH] ) +); +`else +assign wb_es_dat_o = 32'h0000_0000; +assign wb_es_ack_o = 1'b0; + +assign wb_em_adr_o = 32'h0000_0000; +assign wb_em_sel_o = 4'h0; +assign wb_em_we_o = 1'b0; +assign wb_em_dat_o = 32'h0000_0000; +assign wb_em_cyc_o = 1'b0; +assign wb_em_stb_o = 1'b0; +`endif + +// +// Instantiation of the Traffic COP +// +minsoc_tc_top #(`APP_ADDR_DEC_W, + `APP_ADDR_SRAM, + `APP_ADDR_DEC_W, + `APP_ADDR_FLASH, + `APP_ADDR_DECP_W, + `APP_ADDR_PERIP, + `APP_ADDR_DEC_W, + `APP_ADDR_SPI, + `APP_ADDR_ETH, + `APP_ADDR_AUDIO, + `APP_ADDR_UART, + `APP_ADDR_PS2, + `APP_ADDR_GPIO, + `APP_ADDR_RES2 + ) tc_top ( + + // WISHBONE common + .wb_clk_i ( wb_clk ), + .wb_rst_i ( wb_rst ), + + // WISHBONE Initiator 0 + .i0_wb_cyc_i ( 1'b0 ), + .i0_wb_stb_i ( 1'b0 ), + .i0_wb_adr_i ( 32'h0000_0000 ), + .i0_wb_sel_i ( 4'b0000 ), + .i0_wb_we_i ( 1'b0 ), + .i0_wb_dat_i ( 32'h0000_0000 ), + .i0_wb_dat_o ( ), + .i0_wb_ack_o ( ), + .i0_wb_err_o ( ), + + // WISHBONE Initiator 1 + .i1_wb_cyc_i ( wb_em_cyc_o ), + .i1_wb_stb_i ( wb_em_stb_o ), + .i1_wb_adr_i ( wb_em_adr_o ), + .i1_wb_sel_i ( wb_em_sel_o ), + .i1_wb_we_i ( wb_em_we_o ), + .i1_wb_dat_i ( wb_em_dat_o ), + .i1_wb_dat_o ( wb_em_dat_i ), + .i1_wb_ack_o ( wb_em_ack_i ), + .i1_wb_err_o ( wb_em_err_i ), + + // WISHBONE Initiator 2 + .i2_wb_cyc_i ( 1'b0 ), + .i2_wb_stb_i ( 1'b0 ), + .i2_wb_adr_i ( 32'h0000_0000 ), + .i2_wb_sel_i ( 4'b0000 ), + .i2_wb_we_i ( 1'b0 ), + .i2_wb_dat_i ( 32'h0000_0000 ), + .i2_wb_dat_o ( ), + .i2_wb_ack_o ( ), + .i2_wb_err_o ( ), + + // WISHBONE Initiator 3 + .i3_wb_cyc_i ( wb_dm_cyc_o ), + .i3_wb_stb_i ( wb_dm_stb_o ), + .i3_wb_adr_i ( wb_dm_adr_o ), + .i3_wb_sel_i ( wb_dm_sel_o ), + .i3_wb_we_i ( wb_dm_we_o ), + .i3_wb_dat_i ( wb_dm_dat_o ), + .i3_wb_dat_o ( wb_dm_dat_i ), + .i3_wb_ack_o ( wb_dm_ack_i ), + .i3_wb_err_o ( wb_dm_err_i ), + + // WISHBONE Initiator 4 + .i4_wb_cyc_i ( wb_rdm_cyc_o ), + .i4_wb_stb_i ( wb_rdm_stb_o ), + .i4_wb_adr_i ( wb_rdm_adr_o ), + .i4_wb_sel_i ( wb_rdm_sel_o ), + .i4_wb_we_i ( wb_rdm_we_o ), + .i4_wb_dat_i ( wb_rdm_dat_o ), + .i4_wb_dat_o ( wb_rdm_dat_i ), + .i4_wb_ack_o ( wb_rdm_ack_i ), + .i4_wb_err_o ( wb_rdm_err_i ), + + // WISHBONE Initiator 5 + .i5_wb_cyc_i ( wb_rim_cyc_o ), + .i5_wb_stb_i ( wb_rim_stb_o ), + .i5_wb_adr_i ( wb_rim_adr_o ), + .i5_wb_sel_i ( wb_rim_sel_o ), + .i5_wb_we_i ( wb_rim_we_o ), + .i5_wb_dat_i ( wb_rim_dat_o ), + .i5_wb_dat_o ( wb_rim_dat_i ), + .i5_wb_ack_o ( wb_rim_ack_i ), + .i5_wb_err_o ( wb_rim_err_i ), + + // WISHBONE Initiator 6 + .i6_wb_cyc_i ( 1'b0 ), + .i6_wb_stb_i ( 1'b0 ), + .i6_wb_adr_i ( 32'h0000_0000 ), + .i6_wb_sel_i ( 4'b0000 ), + .i6_wb_we_i ( 1'b0 ), + .i6_wb_dat_i ( 32'h0000_0000 ), + .i6_wb_dat_o ( ), + .i6_wb_ack_o ( ), + .i6_wb_err_o ( ), + + // WISHBONE Initiator 7 + .i7_wb_cyc_i ( 1'b0 ), + .i7_wb_stb_i ( 1'b0 ), + .i7_wb_adr_i ( 32'h0000_0000 ), + .i7_wb_sel_i ( 4'b0000 ), + .i7_wb_we_i ( 1'b0 ), + .i7_wb_dat_i ( 32'h0000_0000 ), + .i7_wb_dat_o ( ), + .i7_wb_ack_o ( ), + .i7_wb_err_o ( ), + + // WISHBONE Target 0 + .t0_wb_cyc_o ( wb_ss_cyc_i ), + .t0_wb_stb_o ( wb_ss_stb_i ), + .t0_wb_adr_o ( wb_ss_adr_i ), + .t0_wb_sel_o ( wb_ss_sel_i ), + .t0_wb_we_o ( wb_ss_we_i ), + .t0_wb_dat_o ( wb_ss_dat_i ), + .t0_wb_dat_i ( wb_ss_dat_o ), + .t0_wb_ack_i ( wb_ss_ack_o ), + .t0_wb_err_i ( wb_ss_err_o ), + + // WISHBONE Target 1 + .t1_wb_cyc_o ( wb_fs_cyc_i ), + .t1_wb_stb_o ( wb_fs_stb_i ), + .t1_wb_adr_o ( wb_fs_adr_i ), + .t1_wb_sel_o ( wb_fs_sel_i ), + .t1_wb_we_o ( wb_fs_we_i ), + .t1_wb_dat_o ( wb_fs_dat_i ), + .t1_wb_dat_i ( wb_fs_dat_o ), + .t1_wb_ack_i ( wb_fs_ack_o ), + .t1_wb_err_i ( wb_fs_err_o ), + + // WISHBONE Target 2 + .t2_wb_cyc_o ( wb_sp_cyc_i ), + .t2_wb_stb_o ( wb_sp_stb_i ), + .t2_wb_adr_o ( wb_sp_adr_i ), + .t2_wb_sel_o ( wb_sp_sel_i ), + .t2_wb_we_o ( wb_sp_we_i ), + .t2_wb_dat_o ( wb_sp_dat_i ), + .t2_wb_dat_i ( wb_sp_dat_o ), + .t2_wb_ack_i ( wb_sp_ack_o ), + .t2_wb_err_i ( wb_sp_err_o ), + + // WISHBONE Target 3 + .t3_wb_cyc_o ( wb_es_cyc_i ), + .t3_wb_stb_o ( wb_es_stb_i ), + .t3_wb_adr_o ( wb_es_adr_i ), + .t3_wb_sel_o ( wb_es_sel_i ), + .t3_wb_we_o ( wb_es_we_i ), + .t3_wb_dat_o ( wb_es_dat_i ), + .t3_wb_dat_i ( wb_es_dat_o ), + .t3_wb_ack_i ( wb_es_ack_o ), + .t3_wb_err_i ( wb_es_err_o ), + + // WISHBONE Target 4 + .t4_wb_cyc_o ( ), + .t4_wb_stb_o ( ), + .t4_wb_adr_o ( ), + .t4_wb_sel_o ( ), + .t4_wb_we_o ( ), + .t4_wb_dat_o ( ), + .t4_wb_dat_i ( 32'h0000_0000 ), + .t4_wb_ack_i ( 1'b0 ), + .t4_wb_err_i ( 1'b1 ), + + // WISHBONE Target 5 + .t5_wb_cyc_o ( wb_us_cyc_i ), + .t5_wb_stb_o ( wb_us_stb_i ), + .t5_wb_adr_o ( wb_us_adr_i ), + .t5_wb_sel_o ( wb_us_sel_i ), + .t5_wb_we_o ( wb_us_we_i ), + .t5_wb_dat_o ( wb_us_dat_i ), + .t5_wb_dat_i ( wb_us_dat_o ), + .t5_wb_ack_i ( wb_us_ack_o ), + .t5_wb_err_i ( wb_us_err_o ), + + // WISHBONE Target 6 + .t6_wb_cyc_o ( ), + .t6_wb_stb_o ( ), + .t6_wb_adr_o ( ), + .t6_wb_sel_o ( ), + .t6_wb_we_o ( ), + .t6_wb_dat_o ( ), + .t6_wb_dat_i ( 32'h0000_0000 ), + .t6_wb_ack_i ( 1'b0 ), + .t6_wb_err_i ( 1'b1 ), + + // WISHBONE Target 7 + .t7_wb_cyc_o ( wb_gpio_cyc_i ), + .t7_wb_stb_o ( wb_gpio_stb_i ), + .t7_wb_adr_o ( wb_gpio_adr_i ), + .t7_wb_sel_o ( wb_gpio_sel_i ), + .t7_wb_we_o ( wb_gpio_we_i ), + .t7_wb_dat_o ( wb_gpio_dat_i ), + .t7_wb_dat_i ( wb_gpio_dat_o ), + .t7_wb_ack_i ( wb_gpio_ack_o ), + .t7_wb_err_i ( wb_gpio_err_o ), + + // WISHBONE Target 8 + .t8_wb_cyc_o ( ), + .t8_wb_stb_o ( ), + .t8_wb_adr_o ( ), + .t8_wb_sel_o ( ), + .t8_wb_we_o ( ), + .t8_wb_dat_o ( ), + .t8_wb_dat_i ( 32'h0000_0000 ), + .t8_wb_ack_i ( 1'b0 ), + .t8_wb_err_i ( 1'b1 ) +); + +//initial begin +// $dumpvars(0); +// $dumpfile("dump.vcd"); +//end + +endmodule Index: rc-1.0/utils/contributions/gpio/sw/gpio.c =================================================================== --- rc-1.0/utils/contributions/gpio/sw/gpio.c (nonexistent) +++ rc-1.0/utils/contributions/gpio/sw/gpio.c (revision 109) @@ -0,0 +1,225 @@ +#include "../support/support.h" +#include "../support/board.h" + +#include "../support/spr_defs.h" + +#include "../drivers/uart.h" + +#include "gpio.h" + +void gpio_init(gpio_t *gpio, long instance_num, unsigned long base_addr) +{ + int i = MIN_GPIO_BIT; + + if ( gpio != NULL ) { + gpio->instance_num = instance_num; + gpio->base_addr = (unsigned char*)base_addr; + for ( ;i<=MAX_GPIO_BIT;i++) + gpio->vectors[i].vec = NULL; + return; + } else { + // Print the error msgs here + // + uart_print_str("gpio inst in NULL.\n"); + return; + } +} + +void gpio_config_bit(gpio_t *gpio, unsigned long bit, iotype_t io) +{ + if ( gpio != NULL ) { + if ( io == IO_INPUT ) { + gpio->io_config |= (1 << bit); + *(unsigned long*)(gpio->base_addr + OE_REG_OFFSET) &= (~(1 << bit)); + } else { + gpio->io_config &= (~(1 << bit)); + *(unsigned long*)(gpio->base_addr + OE_REG_OFFSET) |= (1 << bit); + } + return; + } else { + // Print the error msgs here + // + uart_print_str("gpio inst in NULL.\n"); + return; + } +} + +void gpio_set_bit(gpio_t *gpio, unsigned long bit, unsigned long val) +{ + if ( gpio != NULL ) { + if ( val != 0 ) + *(unsigned long*)(gpio->base_addr + OUT_REG_OFFSET) |= (1 << bit); + else + *(unsigned long*)(gpio->base_addr + OUT_REG_OFFSET) &= (~(1 << bit)); + return; + } else { + // Print the error msgs here + // + uart_print_str("gpio inst in NULL.\n"); + return; + } +} + +void gpio_get_bit(gpio_t *gpio, unsigned long bit, unsigned long *val) +{ + unsigned long temp; + + if ( gpio != NULL ) { + temp = *(unsigned long*)(gpio->base_addr + IN_REG_OFFSET); + *val = (temp & (1 << bit))? 1 : 0; + return; + } else { + // Print the error msgs here + // + uart_print_str("gpio inst in NULL.\n"); + return; + } +} + + +void gpio_add_interrupt(gpio_t *gpio, unsigned int bit, edge_t edge,void (*func)() ) +{ + if ( gpio != NULL ) { + if ( ( gpio->io_config &(1 << bit)) != 0 ) { // Port bit is configured as IO_INPUT + // + // Disable the interrupts + // + *(unsigned long*)(gpio->base_addr + CTRL_REG_OFFSET) &= (~0x01); + + // Enable the interrupt bit + // + *(unsigned long*)(gpio->base_addr + INTE_REG_OFFSET) |= (1 << bit); + + // Enable the edge type + // + if ( edge == POS_EDGE ) + *(unsigned long*)(gpio->base_addr + PTRIG_REG_OFFSET) |= (1 << bit); + else + *(unsigned long*)(gpio->base_addr + PTRIG_REG_OFFSET) &= (~(1 << bit)); + + // Set the function vector + // + gpio->vectors[bit].vec = func; + + int_add( 6, gpio_interrupt, gpio ); + + // Re-enable the global control bit + // + *(unsigned long*)(gpio->base_addr + CTRL_REG_OFFSET) |= 0x01; + } else { + // Port is configured as IO_OUTPUT + uart_print_str("gpio pin is not an input pin.\n"); + return; + } + + } else { + // Print the error msgs here + // + uart_print_str("gpio inst in NULL.\n"); + return; + } + +} + +void gpio_interrupt(gpio_t *gpio) +{ + int i; + unsigned long int interrupt_status; + + if ( (*(unsigned long*)(gpio->base_addr + CTRL_REG_OFFSET)) & 0x02 ) + { + // Interrupt is pending here + // + interrupt_status = *(unsigned long*)(gpio->base_addr + INTS_REG_OFFSET); + + // Prioritize from lower bits(0) to higher ones(31) + // + + for ( i=MIN_GPIO_BIT; i<=MAX_GPIO_BIT; i++ ) { + if ( (interrupt_status & (1<base_addr + INTS_REG_OFFSET) &= (~( 1 << i )); + (gpio->vectors[i].vec)(); + } + } + + *(unsigned long*)(gpio->base_addr + CTRL_REG_OFFSET) &= (~0x02); + + } +} + +void hello_east() +{ + uart_print_str("Hello from PUSH Button EAST.\n"); +} + + +void hello_west() +{ + uart_print_str("Hello from PUSH Button WEST.\n"); +} + + +void hello_south() +{ + uart_print_str("Hello from PUSH Button SOUTH.\n"); +} + + + + +#define MAX_COUNT 10 + +int main() +{ + gpio_t gpio_1; + unsigned long t0, t1, t2, t3; + unsigned long count = 0; + + tick_init(); + uart_init(); + int_init(); + int_add(2,&uart_interrupt); + + gpio_init( &gpio_1, 1, GPIO_BASE ); + + gpio_config_bit( &gpio_1, LED_0, IO_OUTPUT); + gpio_config_bit( &gpio_1, LED_1, IO_OUTPUT); + gpio_config_bit( &gpio_1, LED_2, IO_OUTPUT); + gpio_config_bit( &gpio_1, LED_3, IO_OUTPUT); + gpio_config_bit( &gpio_1, LED_4, IO_OUTPUT); + gpio_config_bit( &gpio_1, LED_5, IO_OUTPUT); + gpio_config_bit( &gpio_1, LED_6, IO_OUTPUT); + gpio_config_bit( &gpio_1, LED_7, IO_OUTPUT); + + while ( count++ < MAX_COUNT ) { + gpio_set_bit( &gpio_1, LED_7, 0 ); + gpio_set_bit( &gpio_1, LED_0, 1 ); + udelay(); + gpio_set_bit( &gpio_1, LED_0, 0 ); + gpio_set_bit( &gpio_1, LED_1, 1 ); + udelay(); + gpio_set_bit( &gpio_1, LED_1, 0 ); + gpio_set_bit( &gpio_1, LED_2, 1 ); + udelay(); + gpio_set_bit( &gpio_1, LED_2, 0 ); + gpio_set_bit( &gpio_1, LED_3, 1 ); + udelay(); + gpio_set_bit( &gpio_1, LED_3, 0 ); + gpio_set_bit( &gpio_1, LED_4, 1 ); + udelay(); + gpio_set_bit( &gpio_1, LED_4, 0 ); + gpio_set_bit( &gpio_1, LED_5, 1 ); + udelay(); + gpio_set_bit( &gpio_1, LED_5, 0 ); + gpio_set_bit( &gpio_1, LED_6, 1 ); + udelay(); + gpio_set_bit( &gpio_1, LED_6, 0 ); + gpio_set_bit( &gpio_1, LED_7, 1 ); + udelay(); + } + + gpio_set_bit( &gpio_1, LED_7, 0 ); + + report(0xdeaddead); + or32_exit(0); +} Index: rc-1.0/utils/contributions/gpio/sw/udelay.c =================================================================== --- rc-1.0/utils/contributions/gpio/sw/udelay.c (nonexistent) +++ rc-1.0/utils/contributions/gpio/sw/udelay.c (revision 109) @@ -0,0 +1,13 @@ +#include "../support/support.h" +#include "../support/board.h" + +#include "../drivers/tick.h" + +extern int tick_int; + +void udelay(void) +{ + while (!tick_int); + tick_ack(); +} + Index: rc-1.0/utils/contributions/gpio/sw/gpio.h =================================================================== --- rc-1.0/utils/contributions/gpio/sw/gpio.h (nonexistent) +++ rc-1.0/utils/contributions/gpio/sw/gpio.h (revision 109) @@ -0,0 +1,76 @@ +#ifndef __GPIO_H__ + +#define __GPIO_H__ + +#define MIN_GPIO_BIT 0 +#define MAX_GPIO_BIT 31 + +#define TOTAL_GPIO_BITS ((MAX_GPIO_BIT-MIN_GPIO_BIT+1)) + + +#define IN_REG_OFFSET 0x00 +#define OUT_REG_OFFSET 0x04 +#define OE_REG_OFFSET 0x08 +#define INTE_REG_OFFSET 0x0C +#define PTRIG_REG_OFFSET 0x10 +#define AUX_REG_OFFSET 0x14 +#define CTRL_REG_OFFSET 0x18 +#define INTS_REG_OFFSET 0x1C +#define ECLK_REG_OFFSET 0x20 +#define NEC_REG_OFFSET 0x24 + + +typedef struct vector_t_ +{ + void (*vec)(); +} vector_t; + +typedef struct gpio_t_ +{ + volatile unsigned char *base_addr; + unsigned int instance_num; + unsigned int io_config; + vector_t vectors[TOTAL_GPIO_BITS]; +} gpio_t; + +typedef enum iotype_t_ +{ + IO_OUTPUT = 0, + IO_INPUT = 1 +} iotype_t; + +typedef enum edge_t_ +{ + NEG_EDGE = 0, + POS_EDGE = 1 +} edge_t; + + +#define LED_0 0x00 +#define LED_1 0x01 +#define LED_2 0x02 +#define LED_3 0x03 +#define LED_4 0x04 +#define LED_5 0x05 +#define LED_6 0x06 +#define LED_7 0x07 + +#define DIP_0 0x08 +#define DIP_1 0x09 +#define DIP_2 0x0A +#define DIP_3 0x0B + +#define PUSH_EAST 0x0C +#define PUSH_WEST 0x0D +#define PUSH_NORTH 0x0E +#define PUSH_SOUTH 0x0F + + +void gpio_init(gpio_t *, long, unsigned long); +void gpio_config_bit(gpio_t *, unsigned long, iotype_t); +void gpio_set_bit(gpio_t *, unsigned long, unsigned long); +void gpio_get_bit(gpio_t *, unsigned long, unsigned long *); +void gpio_add_interrupt(gpio_t *, unsigned int, edge_t,void (*func)() ); +void gpio_interrupt(gpio_t *gpio); + +#endif Index: rc-1.0/utils/contributions/gpio/sw/Makefile =================================================================== --- rc-1.0/utils/contributions/gpio/sw/Makefile (nonexistent) +++ rc-1.0/utils/contributions/gpio/sw/Makefile (revision 109) @@ -0,0 +1,26 @@ +include ../support/Makefile.inc +drivers = ../drivers/libdrivers.a +cases = gpio-nocache gpio-icdc +common = ../support/libsupport.a ../support/except.o + +all: $(cases) + +gpio-nocache: gpio.o udelay.o ../support/reset-nocache.o $(common) $(drivers) + $(OR32_TOOL_PREFIX)-gcc $(GCC_OPT) $(GCC_LIB_OPTS) -T ../support/orp.ld $? -o $@.or32 + $(OR32_TOOL_PREFIX)-objcopy -O binary $@.or32 $@.bin + ../utils/bin2hex $@.bin 1 -size_word > $@$(FLASH_MEM_HEX_FILE_SUFFIX).hex + ../utils/bin2vmem $@.bin > $@.vmem + + +gpio-icdc: gpio.o udelay.o ../support/reset-icdc.o $(common) $(drivers) + $(OR32_TOOL_PREFIX)-gcc $(GCC_OPT) $(GCC_LIB_OPTS) -T ../support/orp.ld $? -o $@.or32 + $(OR32_TOOL_PREFIX)-objcopy -O binary $@.or32 $@.bin + ../utils/bin2hex $@.bin 1 -size_word > $@$(FLASH_MEM_HEX_FILE_SUFFIX).hex + ../utils/bin2vmem $@.bin > $@.vmem + + +gpio.o: gpio.c + $(OR32_TOOL_PREFIX)-gcc $(GCC_OPT) $? -c -o $@ + +udelay.o: udelay.c + $(OR32_TOOL_PREFIX)-gcc $(GCC_OPT) $? -c -o $@ Index: rc-1.0/utils/contributions/gpio/sw/old/gpio.c =================================================================== --- rc-1.0/utils/contributions/gpio/sw/old/gpio.c (nonexistent) +++ rc-1.0/utils/contributions/gpio/sw/old/gpio.c (revision 109) @@ -0,0 +1,351 @@ +#include "../support/support.h" +#include "../support/board.h" +#include "../support/uart.h" + +#include "../support/spr_defs.h" + +#include "gpio.h" + + +void uart_print_str(char *); +void uart_print_long(unsigned long); + +// Dummy or32 except vectors +void buserr_except(){} +void dpf_except(){} +void ipf_except(){} +void lpint_except(){} +void align_except(){} +void illegal_except(){} +/*void hpint_except(){ + +}*/ +void dtlbmiss_except(){} +void itlbmiss_except(){} +void range_except(){} +void syscall_except(){} +void res1_except(){} +void trap_except(){} +void res2_except(){} + + +void uart_interrupt() +{ + char lala; + unsigned char interrupt_id; + interrupt_id = REG8(UART_BASE + UART_IIR); + if ( interrupt_id & UART_IIR_RDI ) + { + lala = uart_getc(); + uart_putc(lala+1); + } +} + + +void uart_print_str(char *p) +{ + while(*p != 0) { + uart_putc(*p); + p++; + } +} + +void uart_print_long(unsigned long ul) +{ + int i; + char c; + + + uart_print_str("0x"); + for(i=0; i<8; i++) { + + c = (char) (ul>>((7-i)*4)) & 0xf; + if(c >= 0x0 && c<=0x9) + c += '0'; + else + c += 'a' - 10; + uart_putc(c); + } + +} + +void uart_print_short(unsigned long ul) +{ + int i; + char c; + char flag=0; + + + uart_print_str("0x"); + for(i=0; i<8; i++) { + + c = (char) (ul>>((7-i)*4)) & 0xf; + if(c >= 0x0 && c<=0x9) + c += '0'; + else + c += 'a' - 10; + if ((c != '0') || (i==7)) + flag=1; + if(flag) + uart_putc(c); + } + +} + +/* + * + * + * + * + * + * + * + * + * + */ + +void gpio_init(gpio_t *gpio, long instance_num, unsigned long base_addr) +{ + int i = MIN_GPIO_BIT; + + if ( gpio != NULL ) { + gpio->instance_num = instance_num; + gpio->base_addr = (unsigned char*)base_addr; + for ( ;i<=MAX_GPIO_BIT;i++) + gpio->vectors[i].vec = NULL; + return; + } else { + // Print the error msgs here + // + uart_print_str("gpio inst in NULL.\n"); + return; + } +} + +void gpio_config_bit(gpio_t *gpio, unsigned long bit, iotype_t io) +{ + if ( gpio != NULL ) { + if ( io == IO_INPUT ) { + gpio->io_config |= (1 << bit); + *(unsigned long*)(gpio->base_addr + OE_REG_OFFSET) &= (~(1 << bit)); + } else { + gpio->io_config &= (~(1 << bit)); + *(unsigned long*)(gpio->base_addr + OE_REG_OFFSET) |= (1 << bit); + } + return; + } else { + // Print the error msgs here + // + uart_print_str("gpio inst in NULL.\n"); + return; + } +} + +void gpio_set_bit(gpio_t *gpio, unsigned long bit, unsigned long val) +{ + if ( gpio != NULL ) { + if ( val != 0 ) + *(unsigned long*)(gpio->base_addr + OUT_REG_OFFSET) |= (1 << bit); + else + *(unsigned long*)(gpio->base_addr + OUT_REG_OFFSET) &= (~(1 << bit)); + return; + } else { + // Print the error msgs here + // + uart_print_str("gpio inst in NULL.\n"); + return; + } +} + +void gpio_get_bit(gpio_t *gpio, unsigned long bit, unsigned long *val) +{ + unsigned long temp; + + if ( gpio != NULL ) { + temp = *(unsigned long*)(gpio->base_addr + IN_REG_OFFSET); + *val = (temp & (1 << bit))? 1 : 0; + return; + } else { + // Print the error msgs here + // + uart_print_str("gpio inst in NULL.\n"); + return; + } +} + + +void gpio_add_interrupt(gpio_t *gpio, unsigned int bit, edge_t edge,void (*func)() ) +{ + if ( gpio != NULL ) { + if ( ( gpio->io_config &(1 << bit)) != 0 ) { // Port bit is configured as IO_INPUT + // + // Disable the interrupts + // + *(unsigned long*)(gpio->base_addr + CTRL_REG_OFFSET) &= (~0x01); + + // Enable the interrupt bit + // + *(unsigned long*)(gpio->base_addr + INTE_REG_OFFSET) |= (1 << bit); + + // Enable the edge type + // + if ( edge == POS_EDGE ) + *(unsigned long*)(gpio->base_addr + PTRIG_REG_OFFSET) |= (1 << bit); + else + *(unsigned long*)(gpio->base_addr + PTRIG_REG_OFFSET) &= (~(1 << bit)); + + // Set the function vector + // + gpio->vectors[bit].vec = func; + + int_add( 6, gpio_interrupt, gpio ); + + // Re-enable the global control bit + // + *(unsigned long*)(gpio->base_addr + CTRL_REG_OFFSET) |= 0x01; + } else { + // Port is configured as IO_OUTPUT + uart_print_str("gpio pin is not an input pin.\n"); + return; + } + + } else { + // Print the error msgs here + // + uart_print_str("gpio inst in NULL.\n"); + return; + } + +} + +void gpio_interrupt(gpio_t *gpio) +{ + int i; + unsigned long int interrupt_status; + + if ( (*(unsigned long*)(gpio->base_addr + CTRL_REG_OFFSET)) & 0x02 ) + { + // Interrupt is pending here + // + interrupt_status = *(unsigned long*)(gpio->base_addr + INTS_REG_OFFSET); + + // Prioritize from lower bits(0) to higher ones(31) + // + + for ( i=MIN_GPIO_BIT; i<=MAX_GPIO_BIT; i++ ) { + if ( (interrupt_status & (1<base_addr + INTS_REG_OFFSET) &= (~( 1 << i )); + (gpio->vectors[i].vec)(); + } + } + + *(unsigned long*)(gpio->base_addr + CTRL_REG_OFFSET) &= (~0x02); + + } +} + +void hello_east() +{ + uart_print_str("Hello from PUSH Button EAST.\n"); +} + + +void hello_west() +{ + uart_print_str("Hello from PUSH Button WEST.\n"); +} + + +void hello_south() +{ + uart_print_str("Hello from PUSH Button SOUTH.\n"); +} + + + + +#define MAX_COUNT 10 + +int main() +{ + gpio_t gpio_1; + unsigned long t0, t1, t2, t3; + unsigned long count = 0; + + uart_init(); + int_init(); + int_add(2,&uart_interrupt); + + gpio_init( &gpio_1, 1, GPIO_BASE ); + + gpio_config_bit( &gpio_1, LED_0, IO_OUTPUT); + gpio_config_bit( &gpio_1, LED_1, IO_OUTPUT); + gpio_config_bit( &gpio_1, LED_2, IO_OUTPUT); + gpio_config_bit( &gpio_1, LED_3, IO_OUTPUT); + gpio_config_bit( &gpio_1, LED_4, IO_OUTPUT); + gpio_config_bit( &gpio_1, LED_5, IO_OUTPUT); + gpio_config_bit( &gpio_1, LED_6, IO_OUTPUT); + gpio_config_bit( &gpio_1, LED_7, IO_OUTPUT); + + gpio_config_bit( &gpio_1, DIP_0, IO_INPUT); + gpio_config_bit( &gpio_1, DIP_1, IO_INPUT); + gpio_config_bit( &gpio_1, DIP_2, IO_INPUT); + gpio_config_bit( &gpio_1, DIP_3, IO_INPUT); + + uart_print_str("Demo 1 : Check for running LED patterns on board ...\n"); + + while ( count++ < MAX_COUNT ) { + gpio_set_bit( &gpio_1, LED_7, 0 ); + gpio_set_bit( &gpio_1, LED_0, 1 ); + udelay( 100000 ); + gpio_set_bit( &gpio_1, LED_0, 0 ); + gpio_set_bit( &gpio_1, LED_1, 1 ); + udelay( 100000 ); + gpio_set_bit( &gpio_1, LED_1, 0 ); + gpio_set_bit( &gpio_1, LED_2, 1 ); + udelay( 100000 ); + gpio_set_bit( &gpio_1, LED_2, 0 ); + gpio_set_bit( &gpio_1, LED_3, 1 ); + udelay( 100000 ); + gpio_set_bit( &gpio_1, LED_3, 0 ); + gpio_set_bit( &gpio_1, LED_4, 1 ); + udelay( 100000 ); + gpio_set_bit( &gpio_1, LED_4, 0 ); + gpio_set_bit( &gpio_1, LED_5, 1 ); + udelay( 100000 ); + gpio_set_bit( &gpio_1, LED_5, 0 ); + gpio_set_bit( &gpio_1, LED_6, 1 ); + udelay( 100000 ); + gpio_set_bit( &gpio_1, LED_6, 0 ); + gpio_set_bit( &gpio_1, LED_7, 1 ); + udelay( 100000 ); + } + + gpio_set_bit( &gpio_1, LED_7, 0 ); + + gpio_config_bit( &gpio_1, PUSH_EAST, IO_INPUT); + gpio_add_interrupt( &gpio_1, PUSH_EAST, POS_EDGE, hello_east ); + gpio_config_bit( &gpio_1, PUSH_WEST, IO_INPUT); + gpio_add_interrupt( &gpio_1, PUSH_WEST, POS_EDGE, hello_west ); + gpio_config_bit( &gpio_1, PUSH_SOUTH, IO_INPUT); + gpio_add_interrupt( &gpio_1, PUSH_SOUTH, POS_EDGE, hello_south ); + + uart_print_str("Demo 2 : Press the DIP switches and watch corresponding LED glow ...\n"); + + + while (1) { + gpio_get_bit( &gpio_1, DIP_0, &t0 ); + gpio_get_bit( &gpio_1, DIP_1, &t1 ); + gpio_get_bit( &gpio_1, DIP_2, &t2 ); + gpio_get_bit( &gpio_1, DIP_3, &t3 ); + // + gpio_set_bit( &gpio_1, LED_0, t0 ); + gpio_set_bit( &gpio_1, LED_1, t1 ); + gpio_set_bit( &gpio_1, LED_2, t2 ); + gpio_set_bit( &gpio_1, LED_3, t3 ); + } + + + report(0xdeaddead); + or32_exit(0); +} Index: rc-1.0/utils/contributions/gpio/sw/old/udelay.c =================================================================== --- rc-1.0/utils/contributions/gpio/sw/old/udelay.c (nonexistent) +++ rc-1.0/utils/contributions/gpio/sw/old/udelay.c (revision 109) @@ -0,0 +1,17 @@ +#include "../support/support.h" +#include "../support/board.h" + + +void udelay(unsigned long); + +void udelay(unsigned long usecs) +{ + unsigned long i; + unsigned long cycles = usecs / (IN_CLK / 1000000 ); + unsigned long mem_dummy; + volatile unsigned long* ptr = &mem_dummy; + + for ( i=0; i< cycles; i++) + *ptr = 0xABCD; +} + Index: rc-1.0/utils/contributions/gpio/sw/old/gpio.h =================================================================== --- rc-1.0/utils/contributions/gpio/sw/old/gpio.h (nonexistent) +++ rc-1.0/utils/contributions/gpio/sw/old/gpio.h (revision 109) @@ -0,0 +1,76 @@ +#ifndef __GPIO_H__ + +#define __GPIO_H__ + +#define MIN_GPIO_BIT 0 +#define MAX_GPIO_BIT 31 + +#define TOTAL_GPIO_BITS ((MAX_GPIO_BIT-MIN_GPIO_BIT+1)) + + +#define IN_REG_OFFSET 0x00 +#define OUT_REG_OFFSET 0x04 +#define OE_REG_OFFSET 0x08 +#define INTE_REG_OFFSET 0x0C +#define PTRIG_REG_OFFSET 0x10 +#define AUX_REG_OFFSET 0x14 +#define CTRL_REG_OFFSET 0x18 +#define INTS_REG_OFFSET 0x1C +#define ECLK_REG_OFFSET 0x20 +#define NEC_REG_OFFSET 0x24 + + +typedef struct vector_t_ +{ + void (*vec)(); +} vector_t; + +typedef struct gpio_t_ +{ + volatile unsigned char *base_addr; + unsigned int instance_num; + unsigned int io_config; + vector_t vectors[TOTAL_GPIO_BITS]; +} gpio_t; + +typedef enum iotype_t_ +{ + IO_OUTPUT = 0, + IO_INPUT = 1 +} iotype_t; + +typedef enum edge_t_ +{ + NEG_EDGE = 0, + POS_EDGE = 1 +} edge_t; + + +#define LED_0 0x00 +#define LED_1 0x01 +#define LED_2 0x02 +#define LED_3 0x03 +#define LED_4 0x04 +#define LED_5 0x05 +#define LED_6 0x06 +#define LED_7 0x07 + +#define DIP_0 0x08 +#define DIP_1 0x09 +#define DIP_2 0x0A +#define DIP_3 0x0B + +#define PUSH_EAST 0x0C +#define PUSH_WEST 0x0D +#define PUSH_NORTH 0x0E +#define PUSH_SOUTH 0x0F + + +void gpio_init(gpio_t *, long, unsigned long); +void gpio_config_bit(gpio_t *, unsigned long, iotype_t); +void gpio_set_bit(gpio_t *, unsigned long, unsigned long); +void gpio_get_bit(gpio_t *, unsigned long, unsigned long *); +void gpio_add_interrupt(gpio_t *, unsigned int, edge_t,void (*func)() ); +void gpio_interrupt(gpio_t *gpio); + +#endif Index: rc-1.0/utils/contributions/gpio/sw/old/Makefile =================================================================== --- rc-1.0/utils/contributions/gpio/sw/old/Makefile (nonexistent) +++ rc-1.0/utils/contributions/gpio/sw/old/Makefile (revision 109) @@ -0,0 +1,26 @@ +include ../support/Makefile.inc +cases = gpio-nocache gpio-icdc +common = ../support/libsupport.a ../support/except.o + +all: $(cases) + +gpio-nocache: gpio.o udelay.o ../support/reset-nocache.o $(common) + $(OR32_TOOL_PREFIX)-gcc $(GCC_OPT) $(GCC_LIB_OPTS) -T ../support/orp.ld $? -o $@.or32 + $(OR32_TOOL_PREFIX)-objcopy -O binary $@.or32 $@.bin + ../utils/bin2hex $@.bin 1 -size_word > $@$(FLASH_MEM_HEX_FILE_SUFFIX).hex + ../utils/bin2vmem $@.bin > $@.vmem + + +gpio-icdc: gpio.o udelay.o ../support/reset-icdc.o + $(OR32_TOOL_PREFIX)-gcc $(GCC_OPT) $(GCC_LIB_OPTS) -T ../support/orp.ld $? -o $@.or32 $(common) + $(OR32_TOOL_PREFIX)-objcopy -O binary $@.or32 $@.bin + ../utils/bin2hex $@.bin 1 -size_word > $@$(FLASH_MEM_HEX_FILE_SUFFIX).hex + ../utils/bin2vmem $@.bin > $@.vmem + + +gpio.o: gpio.c + $(OR32_TOOL_PREFIX)-gcc $(GCC_OPT) $? -c -o $@ + +udelay.o: udelay.c + $(OR32_TOOL_PREFIX)-gcc $(GCC_OPT) $? -c -o $@ + Index: rc-1.0/utils/contributions/setup/beautify.sh =================================================================== --- rc-1.0/utils/contributions/setup/beautify.sh (nonexistent) +++ rc-1.0/utils/contributions/setup/beautify.sh (revision 109) @@ -0,0 +1,45 @@ +#!/bin/bash +# Xanthopoulos Constantinos +# Some useful function for my scripts + +function cecho +{ + echo -e "\033[1m\033[33m$1\033[0m" +} + +function cnecho +{ + echo -e -n "\033[0m\033[33m$1\033[0m" +} + +function errormsg +{ + echo -e "\033[1m\033[31mError: $1\033[0m\n"; + exit 1; +} + +function execcmd +{ + # Print Message + echo -e "\033[35m$1\033[0m" + # Execute command + echo $2 + if [ $DEBUG -ne 1 ]; + then + eval $2; + fi; + # Check Execution + if [ $? -eq 0 ] + then + echo -e "\033[32mSuccessfully \"$1\"\033[0m\n"; + else + errormsg "$1"; + exit 1; + + fi +} + +if [ $DEBUG -eq 1 ] +then + cecho "Debug mode on! Nothing will actually run"; +fi Index: rc-1.0/utils/contributions/setup/TODO.txt =================================================================== --- rc-1.0/utils/contributions/setup/TODO.txt (nonexistent) +++ rc-1.0/utils/contributions/setup/TODO.txt (revision 109) @@ -0,0 +1,4 @@ +# TODO list for the setup script + + * Install ftdi drivers according to the $ENV + * Test it in cygwin and freebsd. Index: rc-1.0/utils/contributions/setup/minsoc-install.sh =================================================================== --- rc-1.0/utils/contributions/setup/minsoc-install.sh (nonexistent) +++ rc-1.0/utils/contributions/setup/minsoc-install.sh (revision 109) @@ -0,0 +1,132 @@ +#!/bin/bash +# Author: Constantinos Xanthopoulos +# This script install MinSOC tree +# under a specific directory. + +# ===== CONFIGURATIONS ===== +# ========================== + +# Where should I put the dir. minsoc? +# ex. /home/conx/Thesis/ +DIR_TO_INSTALL="" + +# This variable should be set to trunk +# or to stable. +VERSION="" + +# This variable should take one of +# the following values depending +# to your system: linux, cygwin, freebsd +ENV="" + +# !!! DO NOT EDIT BELLOW THIS LINE !!! +# =================================== + +# ===== SCRIPT ====== +# =================== + +# Debug ? +export DEBUG=0; +. beautify.sh + +# User check! +if [ `whoami` = "root" ]; +then + errormsg "You shouldn't be root for this script to run."; +fi; + +# Wizard +if [ -z ${DIR_TO_INSTALL} ] +then + cnecho "Give full path (ex. /home/foo/): "; + read DIR_TO_INSTALL; +fi + +# Directory exists? +if [ ! -d ${DIR_TO_INSTALL} ] +then + errormsg "Directory doesn't exist. Please create it"; +fi; + +cd ${DIR_TO_INSTALL} + +# Which Version? +if [ -z ${VERSION} ] +then + while [ "$VERSION" != "trunk" -a "$VERSION" != "stable" ] + do + cnecho "Select MinSOC Version [stable/trunk]: " + read VERSION; + done +fi + +if [ -z ${ENV} ] +then + while [ "$ENV" != "linux" -a "$ENV" != "cygwin" -a "$ENV" != "freebsd" ] + do + cnecho "Select build environment [linux/cygwin/freebsd]: " + read ENV; + done +fi + + + +# Checkout MinSOC +if [ "${VERSION}" = "trunk" ] +then + execcmd "Download minsoc" "svn co -q http://opencores.org/ocsvn/minsoc/minsoc/trunk/ minsoc" +else + execcmd "Download minsoc" "svn co -q http://opencores.org/ocsvn/minsoc/minsoc/tags/release-0.9/ minsoc" +fi + +cd minsoc/rtl/verilog + +execcmd "Checkout adv_jtag_bridge" "svn co -q http://opencores.org/ocsvn/adv_debug_sys/adv_debug_sys/trunk adv_debug_sys" +execcmd "Checkout ethmac" "svn co -q http://opencores.org/ocsvn/ethmac/ethmac/trunk ethmac" +execcmd "Checkout openrisc" "svn co -q http://opencores.org/ocsvn/openrisc/openrisc/trunk/or1200 or1200" +execcmd "Checkout uart" "svn co -q http://opencores.org/ocsvn/uart16550/uart16550/trunk uart16550" + +cecho "I will now start to compile everything that's needed"; + +cd ${DIR_TO_INSTALL}/minsoc/sw/utils + +echo $PWD + +execcmd "Make utils" "make" + +cd ../support + +execcmd "Make support tools" "make" + +cd ../drivers + +execcmd "Make drivers" "make" + + +cd ../uart + +execcmd "Make UART" "make" + +# adv_jtag_bridge install +cd ${DIR_TO_INSTALL}/minsoc/rtl/verilog/adv_debug_sys/Software/adv_jtag_bridge + +# FIXME: install FTDI headers for all build environments +#cecho "Installing FTDI headers! You will be asked to give root pass" + +#execcmd "Install FTDI headers" "su -c \"aptitude install libftdi-dev\""; + +if [ `grep "INCLUDE_JSP_SERVER=true" Makefile` != "" ] +then + cecho "Switching off the adv_jtag_bridge JSP_SERVER option"; + sed 's/INCLUDE_JSP_SERVER=true/INCLUDE_JSP_SERVER=false/' Makefile > TMPFILE && mv TMPFILE Makefile +fi + +if [ "${ENV}" != "cygwin" ] +then + cecho "Setting the right build environment"; + sed "s/BUILD_ENVIRONMENT=cygwin/BUILD_ENVIRONMENT=${ENV}/" Makefile > TMPFILE && mv TMPFILE Makefile +fi + +execcmd "Make adv_jtag_bridge" "make" + +cecho "Installation Finised"
rc-1.0/utils/contributions/setup/minsoc-install.sh Property changes : Added: svn:executable ## -0,0 +1 ## +* \ No newline at end of property Index: rc-1.0/utils/contributions/setup/toolchain-install.sh =================================================================== --- rc-1.0/utils/contributions/setup/toolchain-install.sh (nonexistent) +++ rc-1.0/utils/contributions/setup/toolchain-install.sh (revision 109) @@ -0,0 +1,51 @@ +#!/bin/bash +# Xanthopoulos Constantinos +# Installing OR GNU Toolchain. +# Only tested in Debian Squeeze. + + +# ===== CONFIGURATIONS ===== +# ========================== + +# Where will I put the binaries? +# ex. /opt/openrisc/bin +DIR_TO_INSTALL=""; + +# Debian's kernel architecture {32,64} +# ex. KERNEL_ARCH="32" +KERNEL_ARCH="" + +# ===== SCRIPT ====== +# =================== +export DEBUG=0; +. conxshlib.sh + +if [ `whoami` == "root" ]; +then + errormsg "You shouldn't be root for this script to run."; +fi; + +if [ ! -d $DIR_TO_INSTALL ] +then + errormsg "Directory doesn't exist. Please create it"; +fi; + +execcmd "Change permissions" "chmod 777 $DIR_TO_INSTALL"; + +cd $DIR_TO_INSTALL; + +if [ $KERNEL_ARCH == "32" ]; +then + execcmd "Download toolchain (it may take a while)" "wget ftp://ocuser:oc@opencores.org/toolchain/or32-elf-linux-x86.tar.bz2"; +elif [ $KERNEL_ARCH == "64"]; +then + execcmd "Download toolchain (it may take a while)" "wget ftp://ocuser:oc@opencores.org/toolchain/or32-elf-linux-x86_64.tar.bz2"; +else + errormsg "Not a correct architecture. Check Configurations"; +fi + +execcmd "Un-tar" "tar xf *bz2"; + +execcmd "Adding toolchain to PATH" "echo \"PATH=\\\$PATH:$DIR_TO_INSTALL/or32-elf/bin/\" >> /home/$(whoami)/.bashrc;"; + +cecho "Install completed"
rc-1.0/utils/contributions/setup/toolchain-install.sh Property changes : Added: svn:executable ## -0,0 +1 ## +* \ No newline at end of property Index: rc-1.0/utils/contributions/initialized_onchip_ram/minsoc_onchip_ram_top_altera.v =================================================================== --- rc-1.0/utils/contributions/initialized_onchip_ram/minsoc_onchip_ram_top_altera.v (nonexistent) +++ rc-1.0/utils/contributions/initialized_onchip_ram/minsoc_onchip_ram_top_altera.v (revision 109) @@ -0,0 +1,310 @@ +////////////////////////////////////////////////////////////////////// +//// //// +//// Generic Wishbone controller for //// +//// Single-Port Synchronous RAM //// +//// //// +//// This file is part of memory library available from //// +//// http://www.opencores.org/cvsweb.shtml/minsoc/ //// +//// //// +//// Description //// +//// This Wishbone controller connects to the wrapper of //// +//// the single-port synchronous memory interface. //// +//// Besides universal memory due to onchip_ram it provides a //// +//// generic way to set the depth of the memory. //// +//// //// +//// To Do: //// +//// //// +//// Author(s): //// +//// - Raul Fajardo, rfajardo@gmail.com //// +//// //// +////////////////////////////////////////////////////////////////////// +//// //// +//// Copyright (C) 2000 Authors and OPENCORES.ORG //// +//// //// +//// This source file may be used and distributed without //// +//// restriction provided that this copyright statement is not //// +//// removed from the file and that any derivative work contains //// +//// the original copyright notice and the associated disclaimer. //// +//// //// +//// This source file is free software; you can redistribute it //// +//// and/or modify it under the terms of the GNU Lesser General //// +//// Public License as published by the Free Software Foundation; //// +//// either version 2.1 of the License, or (at your option) any //// +//// later version. //// +//// //// +//// This source is distributed in the hope that it will be //// +//// useful, but WITHOUT ANY WARRANTY; without even the implied //// +//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR //// +//// PURPOSE. See the GNU Lesser General Public License for more //// +//// details. //// +//// //// +//// You should have received a copy of the GNU Lesser General //// +//// Public License along with this source; if not, download it //// +//// from http://www.gnu.org/licenses/lgpl.html //// +//// //// +////////////////////////////////////////////////////////////////////// +// +// Revision History +// +// Revision 1.1 2009/10/02 16:49 fajardo +// Not using the oe signal (output enable) from +// memories, instead multiplexing the outputs +// between the different instantiated blocks +// +// +// Revision 1.0 2009/08/18 15:15:00 fajardo +// Created interface and tested +// +`include "minsoc_defines.v" + +`define mem_init_file "uart-nocache.mif" //specific memory initalization file name, which can be intel hex(.hex) or Altera mif file + //if no initalization file used, give a name of "UNUSED" + +module minsoc_onchip_ram_top ( + wb_clk_i, wb_rst_i, + + wb_dat_i, wb_dat_o, wb_adr_i, wb_sel_i, wb_we_i, wb_cyc_i, + wb_stb_i, wb_ack_o, wb_err_o +); + +// +// Parameters +// +parameter adr_width = 13; //Memory address width, is composed by blocks of aw_int, is not allowed to be less than 12 +localparam aw_int = 11; //11 = 2048 +localparam blocks = (1<<(adr_width-aw_int)); //generated memory contains "blocks" memory blocks of 2048x32 2048 depth x32 bit data + +// +// I/O Ports +// +input wb_clk_i; +input wb_rst_i; + +// +// WB slave i/f +// +input [31:0] wb_dat_i; +output [31:0] wb_dat_o; +input [31:0] wb_adr_i; +input [3:0] wb_sel_i; +input wb_we_i; +input wb_cyc_i; +input wb_stb_i; +output wb_ack_o; +output wb_err_o; + +// +// Internal regs and wires +// +wire we; +wire [3:0] be_i; +wire [31:0] wb_dat_o; +reg ack_we; +reg ack_re; +// +// Aliases and simple assignments +// +assign wb_ack_o = ack_re | ack_we; +assign wb_err_o = wb_cyc_i & wb_stb_i & (|wb_adr_i[23:adr_width+2]); // If Access to > (8-bit leading prefix ignored) +assign we = wb_cyc_i & wb_stb_i & wb_we_i & (|wb_sel_i[3:0]); +assign be_i = (wb_cyc_i & wb_stb_i) * wb_sel_i; + +// +// Write acknowledge +// +always @ (negedge wb_clk_i or posedge wb_rst_i) +begin +if (wb_rst_i) + ack_we <= 1'b0; + else + if (wb_cyc_i & wb_stb_i & wb_we_i & ~ack_we) + ack_we <= #1 1'b1; + else + ack_we <= #1 1'b0; +end + +// +// read acknowledge +// +always @ (posedge wb_clk_i or posedge wb_rst_i) +begin + if (wb_rst_i) + ack_re <= 1'b0; + else + if (wb_cyc_i & wb_stb_i & ~wb_err_o & ~wb_we_i & ~ack_re) + ack_re <= #1 1'b1; + else + ack_re <= #1 1'b0; +end + +`ifdef ALTERA_FPGA //only for altera memory initialization + +//2^adr_width x 32bit single-port ram. +altsyncram altsyncram_component ( + .wren_a (we), + .clock0 (wb_clk_i), + .byteena_a (be_i), + .address_a (wb_adr_i[adr_width+1:2]), + .data_a (wb_dat_i), + .q_a (wb_dat_o), + .aclr0 (1'b0), + .aclr1 (1'b0), + .address_b (1'b1), + .addressstall_a (1'b0), + .addressstall_b (1'b0), + .byteena_b (1'b1), + .clock1 (1'b1), + .clocken0 (1'b1), + .clocken1 (1'b1), + .clocken2 (1'b1), + .clocken3 (1'b1), + .data_b (1'b1), + .eccstatus (), + .q_b (), + .rden_a (1'b1), + .rden_b (1'b1), + .wren_b (1'b0)); + defparam + altsyncram_component.clock_enable_input_a = "BYPASS", + altsyncram_component.clock_enable_output_a = "BYPASS", + altsyncram_component.init_file = `mem_init_file, + altsyncram_component.intended_device_family = "Stratix III", + altsyncram_component.lpm_hint = "ENABLE_RUNTIME_MOD=NO", + altsyncram_component.lpm_type = "altsyncram", + altsyncram_component.operation_mode = "SINGLE_PORT", + altsyncram_component.outdata_aclr_a = "NONE", + altsyncram_component.outdata_reg_a = "UNREGISTERED", + altsyncram_component.power_up_uninitialized = "FALSE", + altsyncram_component.read_during_write_mode_port_a = "NEW_DATA_NO_NBE_READ", + altsyncram_component.numwords_a = (1<>(j+1)); k=k+1) begin : MUX + if (j==0) begin + mux2 # + ( + .dw(32) + ) + mux_int( + .sel( wb_adr_i[aw_int+2+j] ), + .in1( int_dat_o[k*2] ), + .in2( int_dat_o[k*2+1] ), + .out( mux_out[k] ) + ); + end + else begin + mux2 # + ( + .dw(32) + ) + mux_int( + .sel( wb_adr_i[aw_int+2+j] ), + .in1( mux_out[(mux_in_nr-(mux_in_nr>>(j-1)))+k*2] ), + .in2( mux_out[(mux_in_nr-(mux_in_nr>>(j-1)))+k*2+1] ), + .out( mux_out[(mux_in_nr-(mux_in_nr>>j))+k] ) + ); + end + end + end +endgenerate + +//last output = total output +assign wb_dat_o = mux_out[mux_out_nr-1]; + +//(mux_in_nr-(mux_in_nr>>j)): +//-Given sum of 2^i | i = x -> y series can be resumed to 2^(y+1)-2^x +//so, with this expression I'm evaluating how many times the internal loop has been run + +wire [blocks-1:0] bank; + +generate +genvar i; + for (i=0; i < blocks; i=i+1) begin : MEM + + assign bank[i] = wb_adr_i[adr_width+1:aw_int+2] == i; + + //BANK0 + minsoc_onchip_ram block_ram_0 ( + .clk(wb_clk_i), + .rst(wb_rst_i), + .addr(wb_adr_i[aw_int+1:2]), + .di(wb_dat_i[7:0]), + .doq(int_dat_o[i][7:0]), + .we(we & bank[i]), + .oe(1'b1), + .ce(be_i[0]) + ); + + + minsoc_onchip_ram block_ram_1 ( + .clk(wb_clk_i), + .rst(wb_rst_i), + .addr(wb_adr_i[aw_int+1:2]), + .di(wb_dat_i[15:8]), + .doq(int_dat_o[i][15:8]), + .we(we & bank[i]), + .oe(1'b1), + .ce(be_i[1]) + ); + + minsoc_onchip_ram block_ram_2 ( + .clk(wb_clk_i), + .rst(wb_rst_i), + .addr(wb_adr_i[aw_int+1:2]), + .di(wb_dat_i[23:16]), + .doq(int_dat_o[i][23:16]), + .we(we & bank[i]), + .oe(1'b1), + .ce(be_i[2]) + ); + + minsoc_onchip_ram block_ram_3 ( + .clk(wb_clk_i), + .rst(wb_rst_i), + .addr(wb_adr_i[aw_int+1:2]), + .di(wb_dat_i[31:24]), + .doq(int_dat_o[i][31:24]), + .we(we & bank[i]), + .oe(1'b1), + .ce(be_i[3]) + ); + + end +endgenerate +`endif + +endmodule + +module mux2(sel,in1,in2,out); + +parameter dw = 32; + +input sel; +input [dw-1:0] in1, in2; +output reg [dw-1:0] out; + +always @ (sel or in1 or in2) +begin + case (sel) + 1'b0: out = in1; + 1'b1: out = in2; + endcase +end + +endmodule Index: rc-1.0/utils/contributions/initialized_onchip_ram/bin2init.py =================================================================== --- rc-1.0/utils/contributions/initialized_onchip_ram/bin2init.py (nonexistent) +++ rc-1.0/utils/contributions/initialized_onchip_ram/bin2init.py (revision 109) @@ -0,0 +1,212 @@ +""" +***************************************************************************** + * + H E A D E R I N F O R M A T I O N * + * +***************************************************************************** +Project Name : SysPy (System Python) + http://cgi.di.uoa.gr/~evlog/syspy.html + +File Name : bin2init.py + +Created by : Evangelos Logaras + + +***************************************************************************** + * + C O P Y R I G H T N O T I C E * + * +***************************************************************************** + + This library is free software; you can redistribute it and/or + modify it under the terms of the GNU Lesser General Public + License as published by the Free Software Foundation; + version 2.1 of the License, a copy of which is available from + http://www.gnu.org/licenses/old-licenses/lgpl-2.1.txt. + + This library is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + Lesser General Public License for more details. + + You should have received a copy of the GNU Lesser General Public + License along with this library; if not, write to the Free Software + Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA + + +***************************************************************************** + * + D E S C R I P T I O N * + * +***************************************************************************** + + Generates block_ram.init file from binary images. Binary images are first converted in hex files + using bin2hex.c file, provided with the ORPSoC v2 project. bin2hex executable must exist in the same folder with this script. + + Currently init file is generated for Xilinx's RAMB16_S9 BRAMs + + Usage: python bin2init.py (Python 2.6) +""" + +import commands +import sys + + +# Python's variable declarations +#---------------------------------------------------------------------------------------------------------------------------------- +y = ' ' +mem_arr = [] +block_ram_num = 4 +block0 = [] +block1 = [] +block2 = [] +block3 = [] +block_ram = [block3, block2, block1, block0] +init_arr = [] +mem_size2 = 8192 +mem_count = 0 +bram_count = -1 +init_count = -1 +hex_count = 0 +zero_pad = '' +filename = '' +#---------------------------------------------------------------------------------------------------------------------------------- + +# Exceptions' class +#---------------------------------------------------------------------------------------------------------------------------------- +class MyExceptions(Exception): + def __init__(self, value): + self.value = value + def __str__(self): + return repr(self.value) +#---------------------------------------------------------------------------------------------------------------------------------- + +# Raising exception if a *.bin file is not provided as an argument +#---------------------------------------------------------------------------------------------------------------------------------- +filename = sys.argv[len(sys.argv) - 1] + +if (filename.find(".bin") == -1): + raise MyExceptions("*.bin file required") +#---------------------------------------------------------------------------------------------------------------------------------- + +i = filename.find(".bin") + +filename = filename[:i] + +# Deleting old *.hex and *.bin files +#---------------------------------------------------------------------------------------------------------------------------------- +commands.getoutput("rm " + filename + ".hex") +commands.getoutput("rm " + filename + ".init") +#---------------------------------------------------------------------------------------------------------------------------------- + +## Calling bin2hex executable to convert *.bin file to *.hex +commands.getoutput("./bin2hex " + filename + ".bin 4 > "+ filename + ".hex") + +# Opening the *.hex and the *.init file +#---------------------------------------------------------------------------------------------------------------------------------- +hexFile = open(filename + ".hex", 'r') +initFile = open(filename + ".init", 'w') +#---------------------------------------------------------------------------------------------------------------------------------- + +# Reading the *.hex file and appending its contents to mem_arr[] +#---------------------------------------------------------------------------------------------------------------------------------- +y = ' ' +hex_count = 0 +while(y): + hex_count = hex_count + 1 + if (hex_count == 127): + mem_arr.append("00000000") + + y = hexFile.readline() + mem_arr.append(y) +#---------------------------------------------------------------------------------------------------------------------------------- + +# Reading mem_arr[] and creating the contents of BRAMs +#---------------------------------------------------------------------------------------------------------------------------------- +for i in range(len(mem_arr)): + bram_count = bram_count + 1 + if (bram_count < 32): + block_ram[0].append(mem_arr[i][6:8]) + block_ram[1].append(mem_arr[i][4:6]) + block_ram[2].append(mem_arr[i][2:4]) + block_ram[3].append(mem_arr[i][0:2]) + + elif (bram_count >= 32): + bram_count = 0 + + init_count = init_count + 1 + + if (init_count >= 64): + init_count = 0 + mem_count = mem_count + 1 + + hex_init_count = str(hex(init_count)) + hex_init_count = hex_init_count[2:] + hex_init_count = hex_init_count.upper() + if (init_count < 16): + hex_init_count = '0' + hex_init_count + + + for j in range((block_ram_num - 1), -1, -1): + if (j == (block_ram_num - 1)): + init_arr.append(";\ndefparam MEM[" + str(mem_count) + "].block_ram_" + str(j) + ".INIT_" + hex_init_count + " = 256'h") + block_ram[j].reverse() + for k in range(len(block_ram[j])): + init_arr.append(block_ram[j][k].replace("\n", '')) + else: + init_arr.append(";\ndefparam MEM[" + str(mem_count) + "].block_ram_" + str(j) + ".INIT_" + hex_init_count + " = 256'h") + block_ram[j].reverse() + for k in range(len(block_ram[j])): + init_arr.append(block_ram[j][k].replace("\n", '')) + + block_ram[0] = [] + block_ram[1] = [] + block_ram[2] = [] + block_ram[3] = [] + + block_ram[0].append(mem_arr[i][6:8]) + block_ram[1].append(mem_arr[i][4:6]) + block_ram[2].append(mem_arr[i][2:4]) + block_ram[3].append(mem_arr[i][0:2]) + + +if (bram_count != -1): + init_count = init_count + 1 + hex_init_count = str(hex(init_count)) + hex_init_count = hex_init_count[2:] + hex_init_count = hex_init_count.upper() + if (init_count < 16): + hex_init_count = '0' + hex_init_count + + if (init_count == 0): + for j in range(64 - 2 * bram_count): + zero_pad = zero_pad + '0' + else: + for j in range(64 - 2 * bram_count): + zero_pad = zero_pad + '0' + + for j in range((block_ram_num - 1), -1, -1): + init_arr.append(";\ndefparam MEM[" + str(mem_count) + "].block_ram_" + str(j) + ".INIT_" + hex_init_count + " = 256'h") + block_ram[j].reverse() + init_arr.append(zero_pad) + for k in range(len(block_ram[j])): + init_arr.append(block_ram[j][k].replace("\n", '')) + +init_arr.append(';') +#---------------------------------------------------------------------------------------------------------------------------------- + +# Writing BRAMs contetns to *.init file +#---------------------------------------------------------------------------------------------------------------------------------- +i = init_arr[0].find(";/n") + +init_arr[0] = init_arr[0][i + 2:] + +for i in range(len(init_arr)): + initFile.write(init_arr[i]) +#---------------------------------------------------------------------------------------------------------------------------------- + +# Closing the *.hex and the *.init file +#---------------------------------------------------------------------------------------------------------------------------------- +hexFile.close() +initFile.close() +#---------------------------------------------------------------------------------------------------------------------------------- Index: rc-1.0/utils/contributions/initialized_onchip_ram/minsoc_onchip_ram_top_xilinx.v =================================================================== --- rc-1.0/utils/contributions/initialized_onchip_ram/minsoc_onchip_ram_top_xilinx.v (nonexistent) +++ rc-1.0/utils/contributions/initialized_onchip_ram/minsoc_onchip_ram_top_xilinx.v (revision 109) @@ -0,0 +1,312 @@ +////////////////////////////////////////////////////////////////////// +//// //// +//// Generic Wishbone controller for //// +//// Single-Port Synchronous RAM //// +//// //// +//// This file is part of memory library available from //// +//// http://www.opencores.org/cvsweb.shtml/minsoc/ //// +//// //// +//// Description //// +//// This Wishbone controller connects to the wrapper of //// +//// the single-port synchronous memory interface. //// +//// Besides universal memory due to onchip_ram it provides a //// +//// generic way to set the depth of the memory. //// +//// //// +//// To Do: //// +//// //// +//// Author(s): //// +//// - Raul Fajardo, rfajardo@gmail.com //// +//// //// +////////////////////////////////////////////////////////////////////// +//// //// +//// Copyright (C) 2000 Authors and OPENCORES.ORG //// +//// //// +//// This source file may be used and distributed without //// +//// restriction provided that this copyright statement is not //// +//// removed from the file and that any derivative work contains //// +//// the original copyright notice and the associated disclaimer. //// +//// //// +//// This source file is free software; you can redistribute it //// +//// and/or modify it under the terms of the GNU Lesser General //// +//// Public License as published by the Free Software Foundation; //// +//// either version 2.1 of the License, or (at your option) any //// +//// later version. //// +//// //// +//// This source is distributed in the hope that it will be //// +//// useful, but WITHOUT ANY WARRANTY; without even the implied //// +//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR //// +//// PURPOSE. See the GNU Lesser General Public License for more //// +//// details. //// +//// //// +//// You should have received a copy of the GNU Lesser General //// +//// Public License along with this source; if not, download it //// +//// from http://www.gnu.org/licenses/lgpl.html //// +//// //// +////////////////////////////////////////////////////////////////////// +// +// Revision History +// +// Revision 1.1 2009/10/02 16:49 fajardo +// Not using the oe signal (output enable) from +// memories, instead multiplexing the outputs +// between the different instantiated blocks +// +// +// Revision 1.0 2009/08/18 15:15:00 fajardo +// Created interface and tested +// +`include "minsoc_defines.v" + +module minsoc_onchip_ram_top ( + wb_clk_i, wb_rst_i, + + wb_dat_i, wb_dat_o, wb_adr_i, wb_sel_i, wb_we_i, wb_cyc_i, + wb_stb_i, wb_ack_o, wb_err_o +); + +// +// Parameters +// +parameter adr_width = 13; //Memory address width, is composed by blocks of aw_int, is not allowed to be less than 12 +localparam aw_int = 11; //11 = 2048 +localparam blocks = (1<<(adr_width-aw_int)); //generated memory contains "blocks" memory blocks of 2048x32 2048 depth x32 bit data + +// +// I/O Ports +// +input wb_clk_i; +input wb_rst_i; + +// +// WB slave i/f +// +input [31:0] wb_dat_i; +output [31:0] wb_dat_o; +input [31:0] wb_adr_i; +input [3:0] wb_sel_i; +input wb_we_i; +input wb_cyc_i; +input wb_stb_i; +output wb_ack_o; +output wb_err_o; + +// +// Internal regs and wires +// +wire we; +wire [3:0] be_i; +wire [31:0] wb_dat_o; +reg ack_we; +reg ack_re; +// +// Aliases and simple assignments +// +assign wb_ack_o = ack_re | ack_we; +assign wb_err_o = wb_cyc_i & wb_stb_i & (|wb_adr_i[23:adr_width+2]); // If Access to > (8-bit leading prefix ignored) +assign we = wb_cyc_i & wb_stb_i & wb_we_i & (|wb_sel_i[3:0]); +assign be_i = (wb_cyc_i & wb_stb_i) * wb_sel_i; + +// +// Write acknowledge +// +always @ (negedge wb_clk_i or posedge wb_rst_i) +begin +if (wb_rst_i) + ack_we <= 1'b0; + else + if (wb_cyc_i & wb_stb_i & wb_we_i & ~ack_we) + ack_we <= #1 1'b1; + else + ack_we <= #1 1'b0; +end + +// +// read acknowledge +// +always @ (posedge wb_clk_i or posedge wb_rst_i) +begin + if (wb_rst_i) + ack_re <= 1'b0; + else + if (wb_cyc_i & wb_stb_i & ~wb_err_o & ~wb_we_i & ~ack_re) + ack_re <= #1 1'b1; + else + ack_re <= #1 1'b0; +end + +//Generic (multiple inputs x 1 output) MUX +localparam mux_in_nr = blocks; +localparam slices = adr_width-aw_int; +localparam mux_out_nr = blocks-1; + +wire [31:0] int_dat_o[0:mux_in_nr-1]; +wire [31:0] mux_out[0:mux_out_nr-1]; + +generate +genvar j, k; + for (j=0; j>(j+1)); k=k+1) begin : MUX + if (j==0) begin + mux21 # + ( + .dw(32) + ) + mux_int( + .sel( wb_adr_i[aw_int+2+j] ), + .in1( int_dat_o[k*2] ), + .in2( int_dat_o[k*2+1] ), + .out( mux_out[k] ) + ); + end + else begin + mux21 # + ( + .dw(32) + ) + mux_int( + .sel( wb_adr_i[aw_int+2+j] ), + .in1( mux_out[(mux_in_nr-(mux_in_nr>>(j-1)))+k*2] ), + .in2( mux_out[(mux_in_nr-(mux_in_nr>>(j-1)))+k*2+1] ), + .out( mux_out[(mux_in_nr-(mux_in_nr>>j))+k] ) + ); + end + end + end +endgenerate + +//last output = total output +assign wb_dat_o = mux_out[mux_out_nr-1]; + +//(mux_in_nr-(mux_in_nr>>j)): +//-Given sum of 2^i | i = x -> y series can be resumed to 2^(y+1)-2^x +//so, with this expression I'm evaluating how many times the internal loop has been run + +wire [blocks-1:0] bank; + +generate +genvar i; + for (i=0; i < blocks; i=i+1) begin : MEM + + assign bank[i] = wb_adr_i[adr_width+1:aw_int+2] == i; + + //BANK0 +/* minsoc_onchip_ram block_ram_0 ( + .clk(wb_clk_i), + .rst(wb_rst_i), + .addr(wb_adr_i[aw_int+1:2]), + .di(wb_dat_i[7:0]), + .doq(int_dat_o[i][7:0]), + .we(we & bank[i]), + .oe(1'b1), + .ce(be_i[0]) + ); +*/ + RAMB16_S9 block_ram_0( + .CLK(wb_clk_i), + .SSR(wb_rst_i), + .ADDR(wb_adr_i[aw_int+1:2]), + .DI(wb_dat_i[7:0]), + .DIP(1'b0), + .EN(be_i[0]), + .WE(we & bank[i]), + .DO(int_dat_o[i][7:0]), + .DOP() + ); + +/* + minsoc_onchip_ram block_ram_1 ( + .clk(wb_clk_i), + .rst(wb_rst_i), + .addr(wb_adr_i[aw_int+1:2]), + .di(wb_dat_i[15:8]), + .doq(int_dat_o[i][15:8]), + .we(we & bank[i]), + .oe(1'b1), + .ce(be_i[1]) + ); +*/ + RAMB16_S9 block_ram_1( + .CLK(wb_clk_i), + .SSR(wb_rst_i), + .ADDR(wb_adr_i[aw_int+1:2]), + .DI(wb_dat_i[15:8]), + .DIP(1'b0), + .EN(be_i[1]), + .WE(we & bank[i]), + .DO(int_dat_o[i][15:8]), + .DOP() + ); +/* + minsoc_onchip_ram block_ram_2 ( + .clk(wb_clk_i), + .rst(wb_rst_i), + .addr(wb_adr_i[aw_int+1:2]), + .di(wb_dat_i[23:16]), + .doq(int_dat_o[i][23:16]), + .we(we & bank[i]), + .oe(1'b1), + .ce(be_i[2]) + ); +*/ + RAMB16_S9 block_ram_2( + .CLK(wb_clk_i), + .SSR(wb_rst_i), + .ADDR(wb_adr_i[aw_int+1:2]), + .DI(wb_dat_i[23:16]), + .DIP(1'b0), + .EN(be_i[2]), + .WE(we & bank[i]), + .DO(int_dat_o[i][23:16]), + .DOP() + ); + +/* + minsoc_onchip_ram block_ram_3 ( + .clk(wb_clk_i), + .rst(wb_rst_i), + .addr(wb_adr_i[aw_int+1:2]), + .di(wb_dat_i[31:24]), + .doq(int_dat_o[i][31:24]), + .we(we & bank[i]), + .oe(1'b1), + .ce(be_i[3]) + ); +*/ + RAMB16_S9 block_ram_3( + .CLK(wb_clk_i), + .SSR(wb_rst_i), + .ADDR(wb_adr_i[aw_int+1:2]), + .DI(wb_dat_i[31:24]), + .DIP(1'b0), + .EN(be_i[3]), + .WE(we & bank[i]), + .DO(int_dat_o[i][31:24]), + .DOP() + ); + + end +endgenerate + +`ifdef BLOCK_RAM_INIT +`include "block_ram.init" +`endif + +endmodule + +module mux21(sel,in1,in2,out); + +parameter dw = 32; + +input sel; +input [dw-1:0] in1, in2; +output reg [dw-1:0] out; + +always @ (sel or in1 or in2) +begin + case (sel) + 1'b0: out = in1; + 1'b1: out = in2; + endcase +end + +endmodule Index: rc-1.0/utils/contributions/synthesis_makefile/guideTop.pdf =================================================================== Cannot display: file marked as a binary type. svn:mime-type = application/octet-stream Index: rc-1.0/utils/contributions/synthesis_makefile/guideTop.pdf =================================================================== --- rc-1.0/utils/contributions/synthesis_makefile/guideTop.pdf (nonexistent) +++ rc-1.0/utils/contributions/synthesis_makefile/guideTop.pdf (revision 109)
rc-1.0/utils/contributions/synthesis_makefile/guideTop.pdf Property changes : Added: svn:mime-type ## -0,0 +1 ## +application/octet-stream \ No newline at end of property Index: rc-1.0/utils/contributions/synthesis_makefile/Makefile =================================================================== --- rc-1.0/utils/contributions/synthesis_makefile/Makefile (nonexistent) +++ rc-1.0/utils/contributions/synthesis_makefile/Makefile (revision 109) @@ -0,0 +1,107 @@ +ROOT = /home/mdhicks2/Desktop/softPatch/baseSoC +MINSOC = $(ROOT)/minsoc +MINSOC_RTL = $(MINSOC)/rtl/verilog +UART_RTL = $(ROOT)/uart16550/rtl/verilog +ADV_DEBUG_ROOT = $(ROOT)/adv_debug_sys/Hardware +DEBUG_RTL = $(ADV_DEBUG_ROOT)/adv_dbg_if/rtl/verilog +XIL_DEBUG_RTL = $(ADV_DEBUG_ROOT)/xilinx_internal_jtag/rtl/verilog +OR1200_RTL = $(ROOT)/or1200/rtl/verilog + +help: + @echo " all: Synthesize and implement the SoC, then generate a bit stream" + @echo " soc: Synthesize the SoC" + @echo " translate: Convert the SoC's ngc file to an ngd file for mapping" + @echo " map: Express the SoC netlist in the target hardware" + @echo " par: Place the target hardware, then route the wires" + @echo " bitgen: Generate a programming file for the target FPGA" + @echo " clean: Delete all superfluous files generated by Xilinx tools" + @echo " distclean: Delete all generated files" + @echo " uart: Synthesize the UART" + @echo " debug: Synthesize the debug interface" + @echo " xilDebug: Synthesize the Xilinx JTAG user interface" + @echo " or1200: Synthesize the OR1200 processor" +all: minsoc_top.ngc minsoc.ngd minsoc.ncd minsoc_par.ncd minsoc.bit +soc: minsoc_top.ngc +translate: minsoc.ngd +map: minsoc.ncd +par: minsoc_par.ncd +bitgen: minsoc.bit + +distclean: + rm -f _xmsgs xst *.{ngc,ncd,ngd,bit,xst,xrpt,srp,lso,log} +clean: + rm -f _xmsgs xst *.{xst,xrpt,srp,lso,log} + +minsoc_top.ngc: $(MINSOC_RTL)/*.v buildSupport/*.xst buildSupport/*.prj #uart_top.ngc adbg_top.ngc xilinx_internal_jtag.ngc or1200_top.ngc + xst -ifn "buildSupport/minsoc_top.xst" + rm -f minsoc_top_xst.xrpt + rm -f minsoc_top.srp + rm -f minsoc_top.lso + rm -rf _xmsgs + rm -rf xst +uart: uart_top.ngc +uart_top.ngc: $(UART_RTL)/*.v buildSupport/uart_top.xst buildSupport/uart_top.prj + xst -ifn "buildSupport/uart_top.xst" + rm -f uart_top_xst.xrpt + rm -f uart_top.srp + rm -f uart_top.lso + rm -rf _xmsgs + rm -rf xst +debug: adbg_top.ngc +adbg_top.ngc: $(DEBUG_RTL)/*.v buildSupport/adbg_top.xst buildSupport/adbg_top.prj + xst -ifn "buildSupport/adbg_top.xst" + rm -f adbg_top_xst.xrpt + rm -f adbg_top.srp + rm -f adbg_top.lso + rm -rf _xmsgs + rm -rf xst +xilDebug: xilinx_internal_jtag.ngc +xilinx_internal_jtag.ngc: $(XIL_DEBUG_RTL)/*.v buildSupport/xilinx_internal_jtag.xst buildSupport/xilinx_internal_jtag.prj + xst -ifn "buildSupport/xilinx_internal_jtag.xst" + rm -f xilinx_internal_jtag_xst.xrpt + rm -f xilinx_internal_jtag.srp + rm -f xilinx_internal_jtag.lso + rm -rf _xmsgs + rm -rf xst +or1200: or1200_top.ngc +or1200_top.ngc: $(OR1200_RTL)/*.v buildSupport/or1200_top.xst buildSupport/or1200_top.prj + xst -ifn "buildSupport/or1200_top.xst" + rm -f or1200_top_xst.xrpt + rm -f or1200_top.srp + rm -f or1200_top.lso + rm -rf _xmsgs + rm -rf xst +minsoc.ngd: $(MINSOC)/backend/ml509.ucf minsoc_top.ngc + ngdbuild -p xc5vlx110t-ff1136-3 -uc $(MINSOC)/backend/ml509.ucf -aul -aut minsoc_top.ngc minsoc.ngd + rm -rf netlist.lst + rm -rf minsoc.bld + rm -rf minsoc*.xrpt + rm -rf xlnx_auto_0_xdb + rm -rf _xmsgs +minsoc.ncd : minsoc.ngd + map -bp -timing -cm speed -equivalent_register_removal on -global_opt speed -logic_opt on -mt 2 -ol high -power off -register_duplication on -retiming on -w -xe n minsoc.ngd + rm -rf minsoc.map + rm -rf minsoc.mrp + rm -rf minsoc.ngm + rm -rf minsoc.pcf + rm -rf minsoc.psr + rm -rf minsoc*.xml + rm -rf minsoc_top*.xrpt + rm -rf _xmsgs +minsoc_par.ncd: minsoc.ncd + par -mt 4 -ol high -w -xe n minsoc.ncd minsoc_par.ncd + rm -rf minsoc_par.pad + rm -rf minsoc_par.par + rm -rf minsoc_par.ptwx + rm -rf minsoc_par.unroutes + rm -rf minsoc_par.xpi + rm -rf minsoc_par_pad* + rm -rf minsoc_top*.xrpt + rm -rf _xmsgs +minsoc.bit: minsoc_par.ncd + bitgen -d -w minsoc_par.ncd minsoc.bit + rm -rf minsoc.bgn + rm -rf *.xwbt + rm -rf *.xml + rm -rf *.log + rm -rf _xmsgs Index: rc-1.0/utils/contributions/minsoc_tc_top_B3.v =================================================================== --- rc-1.0/utils/contributions/minsoc_tc_top_B3.v (nonexistent) +++ rc-1.0/utils/contributions/minsoc_tc_top_B3.v (revision 109) @@ -0,0 +1,1883 @@ +////////////////////////////////////////////////////////////////////// +//// //// +//// Xess Traffic Cop //// +//// //// +//// This file is part of the OR1K test application //// +//// http://www.opencores.org/cores/or1k/ //// +//// //// +//// Description //// +//// This block connectes the RISC and peripheral controller //// +//// cores together. //// +//// //// +//// To Do: //// +//// - nothing really //// +//// //// +//// Author(s): //// +//// - Damjan Lampret, lampret@opencores.org //// +//// //// +////////////////////////////////////////////////////////////////////// +//// //// +//// Copyright (C) 2002 OpenCores //// +//// //// +//// This source file may be used and distributed without //// +//// restriction provided that this copyright statement is not //// +//// removed from the file and that any derivative work contains //// +//// the original copyright notice and the associated disclaimer. //// +//// //// +//// This source file is free software; you can redistribute it //// +//// and/or modify it under the terms of the GNU Lesser General //// +//// Public License as published by the Free Software Foundation; //// +//// either version 2.1 of the License, or (at your option) any //// +//// later version. //// +//// //// +//// This source is distributed in the hope that it will be //// +//// useful, but WITHOUT ANY WARRANTY; without even the implied //// +//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR //// +//// PURPOSE. See the GNU Lesser General Public License for more //// +//// details. //// +//// //// +//// You should have received a copy of the GNU Lesser General //// +//// Public License along with this source; if not, download it //// +//// from http://www.opencores.org/lgpl.shtml //// +//// //// +////////////////////////////////////////////////////////////////////// +// +// CVS Revision History +// +// $Log: tc_top.v,v $ +// Revision 1.4 2004/04/05 08:44:34 lampret +// Merged branch_qmem into main tree. +// +// Revision 1.2 2002/03/29 20:57:30 lampret +// Removed unused ports wb_clki and wb_rst_i +// +// Revision 1.1.1.1 2002/03/21 16:55:44 lampret +// First import of the "new" XESS XSV environment. +// +// +// + +// synopsys translate_off +`include "timescale.v" +// synopsys translate_on + +// +// Width of address bus +// +`define TC_AW 32 + +// +// Width of data bus +// +`define TC_DW 32 + +// +// Width of byte select bus +// +`define TC_BSW 4 + +// +// Width of WB target inputs (coming from WB slave) +// +// data bus width + ack + err +// +`define TC_TIN_W `TC_DW+1+1 + +// +// Width of WB initiator inputs (coming from WB masters) +// +// cyc + stb + address bus width + +// byte select bus width + we + data bus width +// +`define TC_IIN_W 1+1+1+`TC_AW+`TC_BSW+1+`TC_DW + +// +// Traffic Cop Top +// +module minsoc_tc_top ( + wb_clk_i, + wb_rst_i, + + i0_wb_cyc_i, + i0_wb_stb_i, + i0_wb_adr_i, + i0_wb_sel_i, + i0_wb_we_i, + i0_wb_dat_i, + i0_wb_dat_o, + i0_wb_ack_o, + i0_wb_err_o, + i0_wb_cti_i, + i0_wb_bte_i, + + i1_wb_cyc_i, + i1_wb_stb_i, + i1_wb_adr_i, + i1_wb_sel_i, + i1_wb_we_i, + i1_wb_dat_i, + i1_wb_dat_o, + i1_wb_ack_o, + i1_wb_err_o, + i1_wb_cti_i, + i1_wb_bte_i, + + i2_wb_cyc_i, + i2_wb_stb_i, + i2_wb_adr_i, + i2_wb_sel_i, + i2_wb_we_i, + i2_wb_dat_i, + i2_wb_dat_o, + i2_wb_ack_o, + i2_wb_err_o, + i2_wb_cti_i, + i2_wb_bte_i, + + i3_wb_cyc_i, + i3_wb_stb_i, + i3_wb_adr_i, + i3_wb_sel_i, + i3_wb_we_i, + i3_wb_dat_i, + i3_wb_dat_o, + i3_wb_ack_o, + i3_wb_err_o, + i3_wb_cti_i, + i3_wb_bte_i, + + i4_wb_cyc_i, + i4_wb_stb_i, + i4_wb_adr_i, + i4_wb_sel_i, + i4_wb_we_i, + i4_wb_dat_i, + i4_wb_dat_o, + i4_wb_ack_o, + i4_wb_err_o, + i4_wb_cti_i, + i4_wb_bte_i, + + i5_wb_cyc_i, + i5_wb_stb_i, + i5_wb_adr_i, + i5_wb_sel_i, + i5_wb_we_i, + i5_wb_dat_i, + i5_wb_dat_o, + i5_wb_ack_o, + i5_wb_err_o, + i5_wb_cti_i, + i5_wb_bte_i, + + i6_wb_cyc_i, + i6_wb_stb_i, + i6_wb_adr_i, + i6_wb_sel_i, + i6_wb_we_i, + i6_wb_dat_i, + i6_wb_dat_o, + i6_wb_ack_o, + i6_wb_err_o, + i6_wb_cti_i, + i6_wb_bte_i, + + i7_wb_cyc_i, + i7_wb_stb_i, + i7_wb_adr_i, + i7_wb_sel_i, + i7_wb_we_i, + i7_wb_dat_i, + i7_wb_dat_o, + i7_wb_ack_o, + i7_wb_err_o, + i7_wb_cti_i, + i7_wb_bte_i, + + t0_wb_cyc_o, + t0_wb_stb_o, + t0_wb_adr_o, + t0_wb_sel_o, + t0_wb_we_o, + t0_wb_dat_o, + t0_wb_dat_i, + t0_wb_ack_i, + t0_wb_err_i, + t0_wb_cti_o, + t0_wb_bte_o, + + t1_wb_cyc_o, + t1_wb_stb_o, + t1_wb_adr_o, + t1_wb_sel_o, + t1_wb_we_o, + t1_wb_dat_o, + t1_wb_dat_i, + t1_wb_ack_i, + t1_wb_err_i, + t1_wb_cti_o, + t1_wb_bte_o, + + t2_wb_cyc_o, + t2_wb_stb_o, + t2_wb_adr_o, + t2_wb_sel_o, + t2_wb_we_o, + t2_wb_dat_o, + t2_wb_dat_i, + t2_wb_ack_i, + t2_wb_err_i, + t2_wb_cti_o, + t2_wb_bte_o, + + t3_wb_cyc_o, + t3_wb_stb_o, + t3_wb_adr_o, + t3_wb_sel_o, + t3_wb_we_o, + t3_wb_dat_o, + t3_wb_dat_i, + t3_wb_ack_i, + t3_wb_err_i, + t3_wb_cti_o, + t3_wb_bte_o, + + t4_wb_cyc_o, + t4_wb_stb_o, + t4_wb_adr_o, + t4_wb_sel_o, + t4_wb_we_o, + t4_wb_dat_o, + t4_wb_dat_i, + t4_wb_ack_i, + t4_wb_err_i, + t4_wb_cti_o, + t4_wb_bte_o, + + t5_wb_cyc_o, + t5_wb_stb_o, + t5_wb_adr_o, + t5_wb_sel_o, + t5_wb_we_o, + t5_wb_dat_o, + t5_wb_dat_i, + t5_wb_ack_i, + t5_wb_err_i, + t5_wb_cti_o, + t5_wb_bte_o, + + t6_wb_cyc_o, + t6_wb_stb_o, + t6_wb_adr_o, + t6_wb_sel_o, + t6_wb_we_o, + t6_wb_dat_o, + t6_wb_dat_i, + t6_wb_ack_i, + t6_wb_err_i, + t6_wb_cti_o, + t6_wb_bte_o, + + t7_wb_cyc_o, + t7_wb_stb_o, + t7_wb_adr_o, + t7_wb_sel_o, + t7_wb_we_o, + t7_wb_dat_o, + t7_wb_dat_i, + t7_wb_ack_i, + t7_wb_err_i, + t7_wb_cti_o, + t7_wb_bte_o, + + t8_wb_cyc_o, + t8_wb_stb_o, + t8_wb_adr_o, + t8_wb_sel_o, + t8_wb_we_o, + t8_wb_dat_o, + t8_wb_dat_i, + t8_wb_ack_i, + t8_wb_err_i, + t8_wb_cti_o, + t8_wb_bte_o + + +); + +// +// Parameters +// +parameter t0_addr_w = 4; +parameter t0_addr = 4'd8; +parameter t1_addr_w = 4; +parameter t1_addr = 4'd0; +parameter t28c_addr_w = 4; +parameter t28_addr = 4'd0; +parameter t28i_addr_w = 4; +parameter t2_addr = 4'd1; +parameter t3_addr = 4'd2; +parameter t4_addr = 4'd3; +parameter t5_addr = 4'd4; +parameter t6_addr = 4'd5; +parameter t7_addr = 4'd6; +parameter t8_addr = 4'd7; + +// +// I/O Ports +// +input wb_clk_i; +input wb_rst_i; +// +// WB slave i/f connecting initiator 0 +// +input i0_wb_cyc_i; +input i0_wb_stb_i; +input [`TC_AW-1:0] i0_wb_adr_i; +input [`TC_BSW-1:0] i0_wb_sel_i; +input i0_wb_we_i; +input [`TC_DW-1:0] i0_wb_dat_i; +output [`TC_DW-1:0] i0_wb_dat_o; +output i0_wb_ack_o; +output i0_wb_err_o; +input [2:0] i0_wb_cti_i; +input [1:0] i0_wb_bte_i; + +// +// WB slave i/f connecting initiator 1 +// +input i1_wb_cyc_i; +input i1_wb_stb_i; +input [`TC_AW-1:0] i1_wb_adr_i; +input [`TC_BSW-1:0] i1_wb_sel_i; +input i1_wb_we_i; +input [`TC_DW-1:0] i1_wb_dat_i; +output [`TC_DW-1:0] i1_wb_dat_o; +output i1_wb_ack_o; +output i1_wb_err_o; +input [2:0] i1_wb_cti_i; +input [1:0] i1_wb_bte_i; + +// +// WB slave i/f connecting initiator 2 +// +input i2_wb_cyc_i; +input i2_wb_stb_i; +input [`TC_AW-1:0] i2_wb_adr_i; +input [`TC_BSW-1:0] i2_wb_sel_i; +input i2_wb_we_i; +input [`TC_DW-1:0] i2_wb_dat_i; +output [`TC_DW-1:0] i2_wb_dat_o; +output i2_wb_ack_o; +output i2_wb_err_o; +input [2:0] i2_wb_cti_i; +input [1:0] i2_wb_bte_i; + +// +// WB slave i/f connecting initiator 3 +// +input i3_wb_cyc_i; +input i3_wb_stb_i; +input [`TC_AW-1:0] i3_wb_adr_i; +input [`TC_BSW-1:0] i3_wb_sel_i; +input i3_wb_we_i; +input [`TC_DW-1:0] i3_wb_dat_i; +output [`TC_DW-1:0] i3_wb_dat_o; +output i3_wb_ack_o; +output i3_wb_err_o; +input [2:0] i3_wb_cti_i; +input [1:0] i3_wb_bte_i; + +// +// WB slave i/f connecting initiator 4 +// +input i4_wb_cyc_i; +input i4_wb_stb_i; +input [`TC_AW-1:0] i4_wb_adr_i; +input [`TC_BSW-1:0] i4_wb_sel_i; +input i4_wb_we_i; +input [`TC_DW-1:0] i4_wb_dat_i; +output [`TC_DW-1:0] i4_wb_dat_o; +output i4_wb_ack_o; +output i4_wb_err_o; +input [2:0] i4_wb_cti_i; +input [1:0] i4_wb_bte_i; + +// +// WB slave i/f connecting initiator 5 +// +input i5_wb_cyc_i; +input i5_wb_stb_i; +input [`TC_AW-1:0] i5_wb_adr_i; +input [`TC_BSW-1:0] i5_wb_sel_i; +input i5_wb_we_i; +input [`TC_DW-1:0] i5_wb_dat_i; +output [`TC_DW-1:0] i5_wb_dat_o; +output i5_wb_ack_o; +output i5_wb_err_o; +input [2:0] i5_wb_cti_i; +input [1:0] i5_wb_bte_i; + +// +// WB slave i/f connecting initiator 6 +// +input i6_wb_cyc_i; +input i6_wb_stb_i; +input [`TC_AW-1:0] i6_wb_adr_i; +input [`TC_BSW-1:0] i6_wb_sel_i; +input i6_wb_we_i; +input [`TC_DW-1:0] i6_wb_dat_i; +output [`TC_DW-1:0] i6_wb_dat_o; +output i6_wb_ack_o; +output i6_wb_err_o; +input [2:0] i6_wb_cti_i; +input [1:0] i6_wb_bte_i; + +// +// WB slave i/f connecting initiator 7 +// +input i7_wb_cyc_i; +input i7_wb_stb_i; +input [`TC_AW-1:0] i7_wb_adr_i; +input [`TC_BSW-1:0] i7_wb_sel_i; +input i7_wb_we_i; +input [`TC_DW-1:0] i7_wb_dat_i; +output [`TC_DW-1:0] i7_wb_dat_o; +output i7_wb_ack_o; +output i7_wb_err_o; +input [2:0] i7_wb_cti_i; +input [1:0] i7_wb_bte_i; + +// +// WB master i/f connecting target 0 +// +output t0_wb_cyc_o; +output t0_wb_stb_o; +output [`TC_AW-1:0] t0_wb_adr_o; +output [`TC_BSW-1:0] t0_wb_sel_o; +output t0_wb_we_o; +output [`TC_DW-1:0] t0_wb_dat_o; +input [`TC_DW-1:0] t0_wb_dat_i; +input t0_wb_ack_i; +input t0_wb_err_i; +output [2:0] t0_wb_cti_o; +output [1:0] t0_wb_bte_o; + +// +// WB master i/f connecting target 1 +// +output t1_wb_cyc_o; +output t1_wb_stb_o; +output [`TC_AW-1:0] t1_wb_adr_o; +output [`TC_BSW-1:0] t1_wb_sel_o; +output t1_wb_we_o; +output [`TC_DW-1:0] t1_wb_dat_o; +input [`TC_DW-1:0] t1_wb_dat_i; +input t1_wb_ack_i; +input t1_wb_err_i; +output [2:0] t1_wb_cti_o; +output [1:0] t1_wb_bte_o; + +// +// WB master i/f connecting target 2 +// +output t2_wb_cyc_o; +output t2_wb_stb_o; +output [`TC_AW-1:0] t2_wb_adr_o; +output [`TC_BSW-1:0] t2_wb_sel_o; +output t2_wb_we_o; +output [`TC_DW-1:0] t2_wb_dat_o; +input [`TC_DW-1:0] t2_wb_dat_i; +input t2_wb_ack_i; +input t2_wb_err_i; +output [2:0] t2_wb_cti_o; +output [1:0] t2_wb_bte_o; + +// +// WB master i/f connecting target 3 +// +output t3_wb_cyc_o; +output t3_wb_stb_o; +output [`TC_AW-1:0] t3_wb_adr_o; +output [`TC_BSW-1:0] t3_wb_sel_o; +output t3_wb_we_o; +output [`TC_DW-1:0] t3_wb_dat_o; +input [`TC_DW-1:0] t3_wb_dat_i; +input t3_wb_ack_i; +input t3_wb_err_i; +output [2:0] t3_wb_cti_o; +output [1:0] t3_wb_bte_o; + +// +// WB master i/f connecting target 4 +// +output t4_wb_cyc_o; +output t4_wb_stb_o; +output [`TC_AW-1:0] t4_wb_adr_o; +output [`TC_BSW-1:0] t4_wb_sel_o; +output t4_wb_we_o; +output [`TC_DW-1:0] t4_wb_dat_o; +input [`TC_DW-1:0] t4_wb_dat_i; +input t4_wb_ack_i; +input t4_wb_err_i; +output [2:0] t4_wb_cti_o; +output [1:0] t4_wb_bte_o; + +// +// WB master i/f connecting target 5 +// +output t5_wb_cyc_o; +output t5_wb_stb_o; +output [`TC_AW-1:0] t5_wb_adr_o; +output [`TC_BSW-1:0] t5_wb_sel_o; +output t5_wb_we_o; +output [`TC_DW-1:0] t5_wb_dat_o; +input [`TC_DW-1:0] t5_wb_dat_i; +input t5_wb_ack_i; +input t5_wb_err_i; +output [2:0] t5_wb_cti_o; +output [1:0] t5_wb_bte_o; + +// +// WB master i/f connecting target 6 +// +output t6_wb_cyc_o; +output t6_wb_stb_o; +output [`TC_AW-1:0] t6_wb_adr_o; +output [`TC_BSW-1:0] t6_wb_sel_o; +output t6_wb_we_o; +output [`TC_DW-1:0] t6_wb_dat_o; +input [`TC_DW-1:0] t6_wb_dat_i; +input t6_wb_ack_i; +input t6_wb_err_i; +output [2:0] t6_wb_cti_o; +output [1:0] t6_wb_bte_o; + +// +// WB master i/f connecting target 7 +// +output t7_wb_cyc_o; +output t7_wb_stb_o; +output [`TC_AW-1:0] t7_wb_adr_o; +output [`TC_BSW-1:0] t7_wb_sel_o; +output t7_wb_we_o; +output [`TC_DW-1:0] t7_wb_dat_o; +input [`TC_DW-1:0] t7_wb_dat_i; +input t7_wb_ack_i; +input t7_wb_err_i; +output [2:0] t7_wb_cti_o; +output [1:0] t7_wb_bte_o; + +// +// WB master i/f connecting target 8 +// +output t8_wb_cyc_o; +output t8_wb_stb_o; +output [`TC_AW-1:0] t8_wb_adr_o; +output [`TC_BSW-1:0] t8_wb_sel_o; +output t8_wb_we_o; +output [`TC_DW-1:0] t8_wb_dat_o; +input [`TC_DW-1:0] t8_wb_dat_i; +input t8_wb_ack_i; +input t8_wb_err_i; +output [2:0] t8_wb_cti_o; +output [1:0] t8_wb_bte_o; + + +// +// Internal wires & registers +// + +// +// Outputs for initiators from both mi_to_st blocks +// +wire [`TC_DW-1:0] xi0_wb_dat_o; +wire xi0_wb_ack_o; +wire xi0_wb_err_o; +wire [`TC_DW-1:0] xi1_wb_dat_o; +wire xi1_wb_ack_o; +wire xi1_wb_err_o; +wire [`TC_DW-1:0] xi2_wb_dat_o; +wire xi2_wb_ack_o; +wire xi2_wb_err_o; +wire [`TC_DW-1:0] xi3_wb_dat_o; +wire xi3_wb_ack_o; +wire xi3_wb_err_o; +wire [`TC_DW-1:0] xi4_wb_dat_o; +wire xi4_wb_ack_o; +wire xi4_wb_err_o; +wire [`TC_DW-1:0] xi5_wb_dat_o; +wire xi5_wb_ack_o; +wire xi5_wb_err_o; +wire [`TC_DW-1:0] xi6_wb_dat_o; +wire xi6_wb_ack_o; +wire xi6_wb_err_o; +wire [`TC_DW-1:0] xi7_wb_dat_o; +wire xi7_wb_ack_o; +wire xi7_wb_err_o; +wire [`TC_DW-1:0] yi0_wb_dat_o; +wire yi0_wb_ack_o; +wire yi0_wb_err_o; +wire [`TC_DW-1:0] yi1_wb_dat_o; +wire yi1_wb_ack_o; +wire yi1_wb_err_o; +wire [`TC_DW-1:0] yi2_wb_dat_o; +wire yi2_wb_ack_o; +wire yi2_wb_err_o; +wire [`TC_DW-1:0] yi3_wb_dat_o; +wire yi3_wb_ack_o; +wire yi3_wb_err_o; +wire [`TC_DW-1:0] yi4_wb_dat_o; +wire yi4_wb_ack_o; +wire yi4_wb_err_o; +wire [`TC_DW-1:0] yi5_wb_dat_o; +wire yi5_wb_ack_o; +wire yi5_wb_err_o; +wire [`TC_DW-1:0] yi6_wb_dat_o; +wire yi6_wb_ack_o; +wire yi6_wb_err_o; +wire [`TC_DW-1:0] yi7_wb_dat_o; +wire yi7_wb_ack_o; +wire yi7_wb_err_o; + +// +// Intermediate signals connecting peripheral channel's +// mi_to_st and si_to_mt blocks. +// +wire z_wb_cyc_i; +wire z_wb_stb_i; +wire [`TC_AW-1:0] z_wb_adr_i; +wire [`TC_BSW-1:0] z_wb_sel_i; +wire z_wb_we_i; +wire [`TC_DW-1:0] z_wb_dat_i; +wire [`TC_DW-1:0] z_wb_dat_t; +wire z_wb_ack_t; +wire z_wb_err_t; +wire [2:0] z_wb_cti_i; +wire [1:0] z_wb_bte_i; + +// +// Outputs for initiators are ORed from both mi_to_st blocks +// +assign i0_wb_dat_o = xi0_wb_dat_o | yi0_wb_dat_o; +assign i0_wb_ack_o = xi0_wb_ack_o | yi0_wb_ack_o; +assign i0_wb_err_o = xi0_wb_err_o | yi0_wb_err_o; +assign i1_wb_dat_o = xi1_wb_dat_o | yi1_wb_dat_o; +assign i1_wb_ack_o = xi1_wb_ack_o | yi1_wb_ack_o; +assign i1_wb_err_o = xi1_wb_err_o | yi1_wb_err_o; +assign i2_wb_dat_o = xi2_wb_dat_o | yi2_wb_dat_o; +assign i2_wb_ack_o = xi2_wb_ack_o | yi2_wb_ack_o; +assign i2_wb_err_o = xi2_wb_err_o | yi2_wb_err_o; +assign i3_wb_dat_o = xi3_wb_dat_o | yi3_wb_dat_o; +assign i3_wb_ack_o = xi3_wb_ack_o | yi3_wb_ack_o; +assign i3_wb_err_o = xi3_wb_err_o | yi3_wb_err_o; +assign i4_wb_dat_o = xi4_wb_dat_o | yi4_wb_dat_o; +assign i4_wb_ack_o = xi4_wb_ack_o | yi4_wb_ack_o; +assign i4_wb_err_o = xi4_wb_err_o | yi4_wb_err_o; +assign i5_wb_dat_o = xi5_wb_dat_o | yi5_wb_dat_o; +assign i5_wb_ack_o = xi5_wb_ack_o | yi5_wb_ack_o; +assign i5_wb_err_o = xi5_wb_err_o | yi5_wb_err_o; +assign i6_wb_dat_o = xi6_wb_dat_o | yi6_wb_dat_o; +assign i6_wb_ack_o = xi6_wb_ack_o | yi6_wb_ack_o; +assign i6_wb_err_o = xi6_wb_err_o | yi6_wb_err_o; +assign i7_wb_dat_o = xi7_wb_dat_o | yi7_wb_dat_o; +assign i7_wb_ack_o = xi7_wb_ack_o | yi7_wb_ack_o; +assign i7_wb_err_o = xi7_wb_err_o | yi7_wb_err_o; + +// +// From initiators to target 0 +// +tc_mi_to_st #(t0_addr_w, t0_addr, + 0, t0_addr_w, t0_addr) t0_ch( + .wb_clk_i(wb_clk_i), + .wb_rst_i(wb_rst_i), + .i0_wb_cyc_i(i0_wb_cyc_i), + .i0_wb_stb_i(i0_wb_stb_i), + .i0_wb_adr_i(i0_wb_adr_i), + .i0_wb_sel_i(i0_wb_sel_i), + .i0_wb_we_i(i0_wb_we_i), + .i0_wb_dat_i(i0_wb_dat_i), + .i0_wb_dat_o(xi0_wb_dat_o), + .i0_wb_ack_o(xi0_wb_ack_o), + .i0_wb_err_o(xi0_wb_err_o), + .i0_wb_cti_i(i0_wb_cti_i), + .i0_wb_bte_i(i0_wb_bte_i), + + .i1_wb_cyc_i(i1_wb_cyc_i), + .i1_wb_stb_i(i1_wb_stb_i), + .i1_wb_adr_i(i1_wb_adr_i), + .i1_wb_sel_i(i1_wb_sel_i), + .i1_wb_we_i(i1_wb_we_i), + .i1_wb_dat_i(i1_wb_dat_i), + .i1_wb_dat_o(xi1_wb_dat_o), + .i1_wb_ack_o(xi1_wb_ack_o), + .i1_wb_err_o(xi1_wb_err_o), + .i1_wb_cti_i(i1_wb_cti_i), + .i1_wb_bte_i(i1_wb_bte_i), + + .i2_wb_cyc_i(i2_wb_cyc_i), + .i2_wb_stb_i(i2_wb_stb_i), + .i2_wb_adr_i(i2_wb_adr_i), + .i2_wb_sel_i(i2_wb_sel_i), + .i2_wb_we_i(i2_wb_we_i), + .i2_wb_dat_i(i2_wb_dat_i), + .i2_wb_dat_o(xi2_wb_dat_o), + .i2_wb_ack_o(xi2_wb_ack_o), + .i2_wb_err_o(xi2_wb_err_o), + .i2_wb_cti_i(i2_wb_cti_i), + .i2_wb_bte_i(i2_wb_bte_i), + + .i3_wb_cyc_i(i3_wb_cyc_i), + .i3_wb_stb_i(i3_wb_stb_i), + .i3_wb_adr_i(i3_wb_adr_i), + .i3_wb_sel_i(i3_wb_sel_i), + .i3_wb_we_i(i3_wb_we_i), + .i3_wb_dat_i(i3_wb_dat_i), + .i3_wb_dat_o(xi3_wb_dat_o), + .i3_wb_ack_o(xi3_wb_ack_o), + .i3_wb_err_o(xi3_wb_err_o), + .i3_wb_cti_i(i3_wb_cti_i), + .i3_wb_bte_i(i3_wb_bte_i), + + .i4_wb_cyc_i(i4_wb_cyc_i), + .i4_wb_stb_i(i4_wb_stb_i), + .i4_wb_adr_i(i4_wb_adr_i), + .i4_wb_sel_i(i4_wb_sel_i), + .i4_wb_we_i(i4_wb_we_i), + .i4_wb_dat_i(i4_wb_dat_i), + .i4_wb_dat_o(xi4_wb_dat_o), + .i4_wb_ack_o(xi4_wb_ack_o), + .i4_wb_err_o(xi4_wb_err_o), + .i4_wb_cti_i(i4_wb_cti_i), + .i4_wb_bte_i(i4_wb_bte_i), + + .i5_wb_cyc_i(i5_wb_cyc_i), + .i5_wb_stb_i(i5_wb_stb_i), + .i5_wb_adr_i(i5_wb_adr_i), + .i5_wb_sel_i(i5_wb_sel_i), + .i5_wb_we_i(i5_wb_we_i), + .i5_wb_dat_i(i5_wb_dat_i), + .i5_wb_dat_o(xi5_wb_dat_o), + .i5_wb_ack_o(xi5_wb_ack_o), + .i5_wb_err_o(xi5_wb_err_o), + .i5_wb_cti_i(i5_wb_cti_i), + .i5_wb_bte_i(i5_wb_bte_i), + + .i6_wb_cyc_i(i6_wb_cyc_i), + .i6_wb_stb_i(i6_wb_stb_i), + .i6_wb_adr_i(i6_wb_adr_i), + .i6_wb_sel_i(i6_wb_sel_i), + .i6_wb_we_i(i6_wb_we_i), + .i6_wb_dat_i(i6_wb_dat_i), + .i6_wb_dat_o(xi6_wb_dat_o), + .i6_wb_ack_o(xi6_wb_ack_o), + .i6_wb_err_o(xi6_wb_err_o), + .i6_wb_cti_i(i6_wb_cti_i), + .i6_wb_bte_i(i6_wb_bte_i), + + .i7_wb_cyc_i(i7_wb_cyc_i), + .i7_wb_stb_i(i7_wb_stb_i), + .i7_wb_adr_i(i7_wb_adr_i), + .i7_wb_sel_i(i7_wb_sel_i), + .i7_wb_we_i(i7_wb_we_i), + .i7_wb_dat_i(i7_wb_dat_i), + .i7_wb_dat_o(xi7_wb_dat_o), + .i7_wb_ack_o(xi7_wb_ack_o), + .i7_wb_err_o(xi7_wb_err_o), + .i7_wb_cti_i(i7_wb_cti_i), + .i7_wb_bte_i(i7_wb_bte_i), + + + .t0_wb_cyc_o(t0_wb_cyc_o), + .t0_wb_stb_o(t0_wb_stb_o), + .t0_wb_adr_o(t0_wb_adr_o), + .t0_wb_sel_o(t0_wb_sel_o), + .t0_wb_we_o(t0_wb_we_o), + .t0_wb_dat_o(t0_wb_dat_o), + .t0_wb_dat_i(t0_wb_dat_i), + .t0_wb_ack_i(t0_wb_ack_i), + .t0_wb_err_i(t0_wb_err_i), + .t0_wb_cti_o(t0_wb_cti_o), + .t0_wb_bte_o(t0_wb_bte_o) + +); + +// +// From initiators to targets 1-8 (upper part) +// +tc_mi_to_st #(t1_addr_w, t1_addr, + 1, t28c_addr_w, t28_addr) t18_ch_upper( + .wb_clk_i(wb_clk_i), + .wb_rst_i(wb_rst_i), + .i0_wb_cyc_i(i0_wb_cyc_i), + .i0_wb_stb_i(i0_wb_stb_i), + .i0_wb_adr_i(i0_wb_adr_i), + .i0_wb_sel_i(i0_wb_sel_i), + .i0_wb_we_i(i0_wb_we_i), + .i0_wb_dat_i(i0_wb_dat_i), + .i0_wb_dat_o(yi0_wb_dat_o), + .i0_wb_ack_o(yi0_wb_ack_o), + .i0_wb_err_o(yi0_wb_err_o), + .i0_wb_cti_i(i0_wb_cti_i), + .i0_wb_bte_i(i0_wb_bte_i), + + .i1_wb_cyc_i(i1_wb_cyc_i), + .i1_wb_stb_i(i1_wb_stb_i), + .i1_wb_adr_i(i1_wb_adr_i), + .i1_wb_sel_i(i1_wb_sel_i), + .i1_wb_we_i(i1_wb_we_i), + .i1_wb_dat_i(i1_wb_dat_i), + .i1_wb_dat_o(yi1_wb_dat_o), + .i1_wb_ack_o(yi1_wb_ack_o), + .i1_wb_err_o(yi1_wb_err_o), + .i1_wb_cti_i(i1_wb_cti_i), + .i1_wb_bte_i(i1_wb_bte_i), + + .i2_wb_cyc_i(i2_wb_cyc_i), + .i2_wb_stb_i(i2_wb_stb_i), + .i2_wb_adr_i(i2_wb_adr_i), + .i2_wb_sel_i(i2_wb_sel_i), + .i2_wb_we_i(i2_wb_we_i), + .i2_wb_dat_i(i2_wb_dat_i), + .i2_wb_dat_o(yi2_wb_dat_o), + .i2_wb_ack_o(yi2_wb_ack_o), + .i2_wb_err_o(yi2_wb_err_o), + .i2_wb_cti_i(i2_wb_cti_i), + .i2_wb_bte_i(i2_wb_bte_i), + + .i3_wb_cyc_i(i3_wb_cyc_i), + .i3_wb_stb_i(i3_wb_stb_i), + .i3_wb_adr_i(i3_wb_adr_i), + .i3_wb_sel_i(i3_wb_sel_i), + .i3_wb_we_i(i3_wb_we_i), + .i3_wb_dat_i(i3_wb_dat_i), + .i3_wb_dat_o(yi3_wb_dat_o), + .i3_wb_ack_o(yi3_wb_ack_o), + .i3_wb_err_o(yi3_wb_err_o), + .i3_wb_cti_i(i3_wb_cti_i), + .i3_wb_bte_i(i3_wb_bte_i), + + .i4_wb_cyc_i(i4_wb_cyc_i), + .i4_wb_stb_i(i4_wb_stb_i), + .i4_wb_adr_i(i4_wb_adr_i), + .i4_wb_sel_i(i4_wb_sel_i), + .i4_wb_we_i(i4_wb_we_i), + .i4_wb_dat_i(i4_wb_dat_i), + .i4_wb_dat_o(yi4_wb_dat_o), + .i4_wb_ack_o(yi4_wb_ack_o), + .i4_wb_err_o(yi4_wb_err_o), + .i4_wb_cti_i(i4_wb_cti_i), + .i4_wb_bte_i(i4_wb_bte_i), + + .i5_wb_cyc_i(i5_wb_cyc_i), + .i5_wb_stb_i(i5_wb_stb_i), + .i5_wb_adr_i(i5_wb_adr_i), + .i5_wb_sel_i(i5_wb_sel_i), + .i5_wb_we_i(i5_wb_we_i), + .i5_wb_dat_i(i5_wb_dat_i), + .i5_wb_dat_o(yi5_wb_dat_o), + .i5_wb_ack_o(yi5_wb_ack_o), + .i5_wb_err_o(yi5_wb_err_o), + .i5_wb_cti_i(i5_wb_cti_i), + .i5_wb_bte_i(i5_wb_bte_i), + + .i6_wb_cyc_i(i6_wb_cyc_i), + .i6_wb_stb_i(i6_wb_stb_i), + .i6_wb_adr_i(i6_wb_adr_i), + .i6_wb_sel_i(i6_wb_sel_i), + .i6_wb_we_i(i6_wb_we_i), + .i6_wb_dat_i(i6_wb_dat_i), + .i6_wb_dat_o(yi6_wb_dat_o), + .i6_wb_ack_o(yi6_wb_ack_o), + .i6_wb_err_o(yi6_wb_err_o), + .i6_wb_cti_i(i6_wb_cti_i), + .i6_wb_bte_i(i6_wb_bte_i), + + .i7_wb_cyc_i(i7_wb_cyc_i), + .i7_wb_stb_i(i7_wb_stb_i), + .i7_wb_adr_i(i7_wb_adr_i), + .i7_wb_sel_i(i7_wb_sel_i), + .i7_wb_we_i(i7_wb_we_i), + .i7_wb_dat_i(i7_wb_dat_i), + .i7_wb_dat_o(yi7_wb_dat_o), + .i7_wb_ack_o(yi7_wb_ack_o), + .i7_wb_err_o(yi7_wb_err_o), + .i7_wb_cti_i(i7_wb_cti_i), + .i7_wb_bte_i(i7_wb_bte_i), + + + .t0_wb_cyc_o(z_wb_cyc_i), + .t0_wb_stb_o(z_wb_stb_i), + .t0_wb_adr_o(z_wb_adr_i), + .t0_wb_sel_o(z_wb_sel_i), + .t0_wb_we_o(z_wb_we_i), + .t0_wb_dat_o(z_wb_dat_i), + .t0_wb_dat_i(z_wb_dat_t), + .t0_wb_ack_i(z_wb_ack_t), + .t0_wb_err_i(z_wb_err_t), + .t0_wb_cti_o(z_wb_cti_i), + .t0_wb_bte_o(z_wb_bte_i) + +); + +// +// From initiators to targets 1-8 (lower part) +// +tc_si_to_mt #(t1_addr_w, t1_addr, t28i_addr_w, t2_addr, t3_addr, + t4_addr, t5_addr, t6_addr, t7_addr, t8_addr) t18_ch_lower( + + + .i0_wb_cyc_i(z_wb_cyc_i), + .i0_wb_stb_i(z_wb_stb_i), + .i0_wb_adr_i(z_wb_adr_i), + .i0_wb_sel_i(z_wb_sel_i), + .i0_wb_we_i(z_wb_we_i), + .i0_wb_dat_i(z_wb_dat_i), + .i0_wb_dat_o(z_wb_dat_t), + .i0_wb_ack_o(z_wb_ack_t), + .i0_wb_err_o(z_wb_err_t), + .i0_wb_cti_i(z_wb_cti_i), + .i0_wb_bte_i(z_wb_bte_i), + + .t0_wb_cyc_o(t1_wb_cyc_o), + .t0_wb_stb_o(t1_wb_stb_o), + .t0_wb_adr_o(t1_wb_adr_o), + .t0_wb_sel_o(t1_wb_sel_o), + .t0_wb_we_o(t1_wb_we_o), + .t0_wb_dat_o(t1_wb_dat_o), + .t0_wb_dat_i(t1_wb_dat_i), + .t0_wb_ack_i(t1_wb_ack_i), + .t0_wb_err_i(t1_wb_err_i), + .t0_wb_cti_o(t1_wb_cti_o), + .t0_wb_bte_o(t1_wb_bte_o), + + .t1_wb_cyc_o(t2_wb_cyc_o), + .t1_wb_stb_o(t2_wb_stb_o), + .t1_wb_adr_o(t2_wb_adr_o), + .t1_wb_sel_o(t2_wb_sel_o), + .t1_wb_we_o(t2_wb_we_o), + .t1_wb_dat_o(t2_wb_dat_o), + .t1_wb_dat_i(t2_wb_dat_i), + .t1_wb_ack_i(t2_wb_ack_i), + .t1_wb_err_i(t2_wb_err_i), + .t1_wb_cti_o(t2_wb_cti_o), + .t1_wb_bte_o(t2_wb_bte_o), + + .t2_wb_cyc_o(t3_wb_cyc_o), + .t2_wb_stb_o(t3_wb_stb_o), + .t2_wb_adr_o(t3_wb_adr_o), + .t2_wb_sel_o(t3_wb_sel_o), + .t2_wb_we_o(t3_wb_we_o), + .t2_wb_dat_o(t3_wb_dat_o), + .t2_wb_dat_i(t3_wb_dat_i), + .t2_wb_ack_i(t3_wb_ack_i), + .t2_wb_err_i(t3_wb_err_i), + .t2_wb_cti_o(t3_wb_cti_o), + .t2_wb_bte_o(t3_wb_bte_o), + + .t3_wb_cyc_o(t4_wb_cyc_o), + .t3_wb_stb_o(t4_wb_stb_o), + .t3_wb_adr_o(t4_wb_adr_o), + .t3_wb_sel_o(t4_wb_sel_o), + .t3_wb_we_o(t4_wb_we_o), + .t3_wb_dat_o(t4_wb_dat_o), + .t3_wb_dat_i(t4_wb_dat_i), + .t3_wb_ack_i(t4_wb_ack_i), + .t3_wb_err_i(t4_wb_err_i), + .t3_wb_cti_o(t4_wb_cti_o), + .t3_wb_bte_o(t4_wb_bte_o), + + .t4_wb_cyc_o(t5_wb_cyc_o), + .t4_wb_stb_o(t5_wb_stb_o), + .t4_wb_adr_o(t5_wb_adr_o), + .t4_wb_sel_o(t5_wb_sel_o), + .t4_wb_we_o(t5_wb_we_o), + .t4_wb_dat_o(t5_wb_dat_o), + .t4_wb_dat_i(t5_wb_dat_i), + .t4_wb_ack_i(t5_wb_ack_i), + .t4_wb_err_i(t5_wb_err_i), + .t4_wb_cti_o(t5_wb_cti_o), + .t4_wb_bte_o(t5_wb_bte_o), + + .t5_wb_cyc_o(t6_wb_cyc_o), + .t5_wb_stb_o(t6_wb_stb_o), + .t5_wb_adr_o(t6_wb_adr_o), + .t5_wb_sel_o(t6_wb_sel_o), + .t5_wb_we_o(t6_wb_we_o), + .t5_wb_dat_o(t6_wb_dat_o), + .t5_wb_dat_i(t6_wb_dat_i), + .t5_wb_ack_i(t6_wb_ack_i), + .t5_wb_err_i(t6_wb_err_i), + .t5_wb_cti_o(t6_wb_cti_o), + .t5_wb_bte_o(t6_wb_bte_o), + + .t6_wb_cyc_o(t7_wb_cyc_o), + .t6_wb_stb_o(t7_wb_stb_o), + .t6_wb_adr_o(t7_wb_adr_o), + .t6_wb_sel_o(t7_wb_sel_o), + .t6_wb_we_o(t7_wb_we_o), + .t6_wb_dat_o(t7_wb_dat_o), + .t6_wb_dat_i(t7_wb_dat_i), + .t6_wb_ack_i(t7_wb_ack_i), + .t6_wb_err_i(t7_wb_err_i), + .t6_wb_cti_o(t7_wb_cti_o), + .t6_wb_bte_o(t7_wb_bte_o), + + .t7_wb_cyc_o(t8_wb_cyc_o), + .t7_wb_stb_o(t8_wb_stb_o), + .t7_wb_adr_o(t8_wb_adr_o), + .t7_wb_sel_o(t8_wb_sel_o), + .t7_wb_we_o(t8_wb_we_o), + .t7_wb_dat_o(t8_wb_dat_o), + .t7_wb_dat_i(t8_wb_dat_i), + .t7_wb_ack_i(t8_wb_ack_i), + .t7_wb_err_i(t8_wb_err_i), + .t7_wb_cti_o(t8_wb_cti_o), + .t7_wb_bte_o(t8_wb_bte_o), + + +); + +endmodule + +// +// Multiple initiator to single target +// +module tc_mi_to_st ( + wb_clk_i, + wb_rst_i, + i0_wb_cyc_i, + i0_wb_stb_i, + i0_wb_adr_i, + i0_wb_sel_i, + i0_wb_we_i, + i0_wb_dat_i, + i0_wb_dat_o, + i0_wb_ack_o, + i0_wb_err_o, + i0_wb_cti_i, + i0_wb_bte_i, + + i1_wb_cyc_i, + i1_wb_stb_i, + i1_wb_adr_i, + i1_wb_sel_i, + i1_wb_we_i, + i1_wb_dat_i, + i1_wb_dat_o, + i1_wb_ack_o, + i1_wb_err_o, + i1_wb_cti_i, + i1_wb_bte_i, + + i2_wb_cyc_i, + i2_wb_stb_i, + i2_wb_adr_i, + i2_wb_sel_i, + i2_wb_we_i, + i2_wb_dat_i, + i2_wb_dat_o, + i2_wb_ack_o, + i2_wb_err_o, + i2_wb_cti_i, + i2_wb_bte_i, + + i3_wb_cyc_i, + i3_wb_stb_i, + i3_wb_adr_i, + i3_wb_sel_i, + i3_wb_we_i, + i3_wb_dat_i, + i3_wb_dat_o, + i3_wb_ack_o, + i3_wb_err_o, + i3_wb_cti_i, + i3_wb_bte_i, + + i4_wb_cyc_i, + i4_wb_stb_i, + i4_wb_adr_i, + i4_wb_sel_i, + i4_wb_we_i, + i4_wb_dat_i, + i4_wb_dat_o, + i4_wb_ack_o, + i4_wb_err_o, + i4_wb_cti_i, + i4_wb_bte_i, + + i5_wb_cyc_i, + i5_wb_stb_i, + i5_wb_adr_i, + i5_wb_sel_i, + i5_wb_we_i, + i5_wb_dat_i, + i5_wb_dat_o, + i5_wb_ack_o, + i5_wb_err_o, + i5_wb_cti_i, + i5_wb_bte_i, + + i6_wb_cyc_i, + i6_wb_stb_i, + i6_wb_adr_i, + i6_wb_sel_i, + i6_wb_we_i, + i6_wb_dat_i, + i6_wb_dat_o, + i6_wb_ack_o, + i6_wb_err_o, + i6_wb_cti_i, + i6_wb_bte_i, + + i7_wb_cyc_i, + i7_wb_stb_i, + i7_wb_adr_i, + i7_wb_sel_i, + i7_wb_we_i, + i7_wb_dat_i, + i7_wb_dat_o, + i7_wb_ack_o, + i7_wb_err_o, + i7_wb_cti_i, + i7_wb_bte_i, + + + t0_wb_cyc_o, + t0_wb_stb_o, + t0_wb_adr_o, + t0_wb_sel_o, + t0_wb_we_o, + t0_wb_dat_o, + t0_wb_dat_i, + t0_wb_ack_i, + t0_wb_err_i, + t0_wb_cti_o, + t0_wb_bte_o + +); + +// +// Parameters +// +parameter t0_addr_w = 2; +parameter t0_addr = 2'b00; +parameter multitarg = 1'b0; +parameter t17_addr_w = 2; +parameter t17_addr = 2'b00; + +// +// I/O Ports +// +input wb_clk_i; +input wb_rst_i; +// +// WB slave i/f connecting initiator 0 +// +input i0_wb_cyc_i; +input i0_wb_stb_i; +input [`TC_AW-1:0] i0_wb_adr_i; +input [`TC_BSW-1:0] i0_wb_sel_i; +input i0_wb_we_i; +input [`TC_DW-1:0] i0_wb_dat_i; +output [`TC_DW-1:0] i0_wb_dat_o; +output i0_wb_ack_o; +output i0_wb_err_o; +input [2:0] i0_wb_cti_i; +input [1:0] i0_wb_bte_i; + +// +// WB slave i/f connecting initiator 1 +// +input i1_wb_cyc_i; +input i1_wb_stb_i; +input [`TC_AW-1:0] i1_wb_adr_i; +input [`TC_BSW-1:0] i1_wb_sel_i; +input i1_wb_we_i; +input [`TC_DW-1:0] i1_wb_dat_i; +output [`TC_DW-1:0] i1_wb_dat_o; +output i1_wb_ack_o; +output i1_wb_err_o; +input [2:0] i1_wb_cti_i; +input [1:0] i1_wb_bte_i; + +// +// WB slave i/f connecting initiator 2 +// +input i2_wb_cyc_i; +input i2_wb_stb_i; +input [`TC_AW-1:0] i2_wb_adr_i; +input [`TC_BSW-1:0] i2_wb_sel_i; +input i2_wb_we_i; +input [`TC_DW-1:0] i2_wb_dat_i; +output [`TC_DW-1:0] i2_wb_dat_o; +output i2_wb_ack_o; +output i2_wb_err_o; +input [2:0] i2_wb_cti_i; +input [1:0] i2_wb_bte_i; + +// +// WB slave i/f connecting initiator 3 +// +input i3_wb_cyc_i; +input i3_wb_stb_i; +input [`TC_AW-1:0] i3_wb_adr_i; +input [`TC_BSW-1:0] i3_wb_sel_i; +input i3_wb_we_i; +input [`TC_DW-1:0] i3_wb_dat_i; +output [`TC_DW-1:0] i3_wb_dat_o; +output i3_wb_ack_o; +output i3_wb_err_o; +input [2:0] i3_wb_cti_i; +input [1:0] i3_wb_bte_i; + +// +// WB slave i/f connecting initiator 4 +// +input i4_wb_cyc_i; +input i4_wb_stb_i; +input [`TC_AW-1:0] i4_wb_adr_i; +input [`TC_BSW-1:0] i4_wb_sel_i; +input i4_wb_we_i; +input [`TC_DW-1:0] i4_wb_dat_i; +output [`TC_DW-1:0] i4_wb_dat_o; +output i4_wb_ack_o; +output i4_wb_err_o; +input [2:0] i4_wb_cti_i; +input [1:0] i4_wb_bte_i; + +// +// WB slave i/f connecting initiator 5 +// +input i5_wb_cyc_i; +input i5_wb_stb_i; +input [`TC_AW-1:0] i5_wb_adr_i; +input [`TC_BSW-1:0] i5_wb_sel_i; +input i5_wb_we_i; +input [`TC_DW-1:0] i5_wb_dat_i; +output [`TC_DW-1:0] i5_wb_dat_o; +output i5_wb_ack_o; +output i5_wb_err_o; +input [2:0] i5_wb_cti_i; +input [1:0] i5_wb_bte_i; + +// +// WB slave i/f connecting initiator 6 +// +input i6_wb_cyc_i; +input i6_wb_stb_i; +input [`TC_AW-1:0] i6_wb_adr_i; +input [`TC_BSW-1:0] i6_wb_sel_i; +input i6_wb_we_i; +input [`TC_DW-1:0] i6_wb_dat_i; +output [`TC_DW-1:0] i6_wb_dat_o; +output i6_wb_ack_o; +output i6_wb_err_o; +input [2:0] i6_wb_cti_i; +input [1:0] i6_wb_bte_i; + +// +// WB slave i/f connecting initiator 7 +// +input i7_wb_cyc_i; +input i7_wb_stb_i; +input [`TC_AW-1:0] i7_wb_adr_i; +input [`TC_BSW-1:0] i7_wb_sel_i; +input i7_wb_we_i; +input [`TC_DW-1:0] i7_wb_dat_i; +output [`TC_DW-1:0] i7_wb_dat_o; +output i7_wb_ack_o; +output i7_wb_err_o; +input [2:0] i7_wb_cti_i; +input [1:0] i7_wb_bte_i; + + +// +// WB master i/f connecting target +// +output t0_wb_cyc_o; +output t0_wb_stb_o; +output [`TC_AW-1:0] t0_wb_adr_o; +output [`TC_BSW-1:0] t0_wb_sel_o; +output t0_wb_we_o; +output [`TC_DW-1:0] t0_wb_dat_o; +input [`TC_DW-1:0] t0_wb_dat_i; +input t0_wb_ack_i; +input t0_wb_err_i; +output [2:0] t0_wb_cti_o; +output [1:0] t0_wb_bte_o; + +// +// Internal wires & registers +// +wire [`TC_IIN_W-1:0] i0_in, i1_in, + i2_in, i3_in, + i4_in, i5_in, + i6_in, i7_in; +wire [`TC_TIN_W-1:0] i0_out, i1_out, + i2_out, i3_out, + i4_out, i5_out, + i6_out, i7_out; +wire [`TC_IIN_W-1:0] t0_out; +wire [`TC_TIN_W-1:0] t0_in; +wire [7:0] req_i; +wire [2:0] req_won; +reg req_cont; +reg [2:0] req_r; +// +// Group WB initiator 0 i/f inputs and outputs +// +assign i0_in = {i0_wb_cyc_i, i0_wb_stb_i, i0_wb_adr_i, + i0_wb_sel_i, i0_wb_we_i, i0_wb_dat_i, i0_wb_cti_i, i0_wb_bte_i}; +assign {i0_wb_dat_o, i0_wb_ack_o, i0_wb_err_o} = i0_out; + +// +// Group WB initiator 1 i/f inputs and outputs +// +assign i1_in = {i1_wb_cyc_i, i1_wb_stb_i, i1_wb_adr_i, + i1_wb_sel_i, i1_wb_we_i, i1_wb_dat_i, i1_wb_cti_i, i1_wb_bte_i}; +assign {i1_wb_dat_o, i1_wb_ack_o, i1_wb_err_o} = i1_out; + +// +// Group WB initiator 2 i/f inputs and outputs +// +assign i2_in = {i2_wb_cyc_i, i2_wb_stb_i, i2_wb_adr_i, + i2_wb_sel_i, i2_wb_we_i, i2_wb_dat_i, i2_wb_cti_i, i2_wb_bte_i}; +assign {i2_wb_dat_o, i2_wb_ack_o, i2_wb_err_o} = i2_out; + +// +// Group WB initiator 3 i/f inputs and outputs +// +assign i3_in = {i3_wb_cyc_i, i3_wb_stb_i, i3_wb_adr_i, + i3_wb_sel_i, i3_wb_we_i, i3_wb_dat_i, i3_wb_cti_i, i3_wb_bte_i}; +assign {i3_wb_dat_o, i3_wb_ack_o, i3_wb_err_o} = i3_out; + +// +// Group WB initiator 4 i/f inputs and outputs +// +assign i4_in = {i4_wb_cyc_i, i4_wb_stb_i, i4_wb_adr_i, + i4_wb_sel_i, i4_wb_we_i, i4_wb_dat_i, i4_wb_cti_i, i4_wb_bte_i}; +assign {i4_wb_dat_o, i4_wb_ack_o, i4_wb_err_o} = i4_out; + +// +// Group WB initiator 5 i/f inputs and outputs +// +assign i5_in = {i5_wb_cyc_i, i5_wb_stb_i, i5_wb_adr_i, + i5_wb_sel_i, i5_wb_we_i, i5_wb_dat_i, i5_wb_cti_i, i5_wb_bte_i}; +assign {i5_wb_dat_o, i5_wb_ack_o, i5_wb_err_o} = i5_out; + +// +// Group WB initiator 6 i/f inputs and outputs +// +assign i6_in = {i6_wb_cyc_i, i6_wb_stb_i, i6_wb_adr_i, + i6_wb_sel_i, i6_wb_we_i, i6_wb_dat_i, i6_wb_cti_i, i6_wb_bte_i}; +assign {i6_wb_dat_o, i6_wb_ack_o, i6_wb_err_o} = i6_out; + +// +// Group WB initiator 7 i/f inputs and outputs +// +assign i7_in = {i7_wb_cyc_i, i7_wb_stb_i, i7_wb_adr_i, + i7_wb_sel_i, i7_wb_we_i, i7_wb_dat_i, i7_wb_cti_i, i7_wb_bte_i}; +assign {i7_wb_dat_o, i7_wb_ack_o, i7_wb_err_o} = i7_out; + + +// +// Group WB target 0 i/f inputs and outputs +// +assign {t0_wb_cyc_o, t0_wb_stb_o, t0_wb_adr_o, + t0_wb_sel_o, t0_wb_we_o, t0_wb_dat_o, t0_wb_cti_o, t0_wb_bte_o} = t0_out; +assign t0_in = {t0_wb_dat_i, t0_wb_ack_i, t0_wb_err_i}; + +// +// Assign to WB initiator i/f outputs +// +// Either inputs from the target are assigned or zeros. +// +assign i0_out = (req_won == 3'd0) ? t0_in : {`TC_TIN_W{1'b0}}; +assign i1_out = (req_won == 3'd1) ? t0_in : {`TC_TIN_W{1'b0}}; +assign i2_out = (req_won == 3'd2) ? t0_in : {`TC_TIN_W{1'b0}}; +assign i3_out = (req_won == 3'd3) ? t0_in : {`TC_TIN_W{1'b0}}; +assign i4_out = (req_won == 3'd4) ? t0_in : {`TC_TIN_W{1'b0}}; +assign i5_out = (req_won == 3'd5) ? t0_in : {`TC_TIN_W{1'b0}}; +assign i6_out = (req_won == 3'd6) ? t0_in : {`TC_TIN_W{1'b0}}; +assign i7_out = (req_won == 3'd7) ? t0_in : {`TC_TIN_W{1'b0}}; + +// +// Assign to WB target i/f outputs +// +// Assign inputs from initiator to target outputs according to +// which initiator has won. If there is no request for the target, +// assign zeros. +// +assign t0_out = (req_won == 3'd0) ? i0_in : + (req_won == 3'd1) ? i1_in : + (req_won == 3'd2) ? i2_in : + (req_won == 3'd3) ? i3_in : + (req_won == 3'd4) ? i4_in : + (req_won == 3'd5) ? i5_in : + (req_won == 3'd6) ? i6_in : + (req_won == 3'd7) ? i7_in : {`TC_IIN_W{1'b0}}; + +// +// Determine if an initiator has address of the target. +// +assign req_i[0] = i0_wb_cyc_i & + ((i0_wb_adr_i[`TC_AW-1:`TC_AW-t0_addr_w] == t0_addr) | + multitarg & (i0_wb_adr_i[`TC_AW-1:`TC_AW-t17_addr_w] == t17_addr)); +assign req_i[1] = i1_wb_cyc_i & + ((i1_wb_adr_i[`TC_AW-1:`TC_AW-t0_addr_w] == t0_addr) | + multitarg & (i1_wb_adr_i[`TC_AW-1:`TC_AW-t17_addr_w] == t17_addr)); +assign req_i[2] = i2_wb_cyc_i & + ((i2_wb_adr_i[`TC_AW-1:`TC_AW-t0_addr_w] == t0_addr) | + multitarg & (i2_wb_adr_i[`TC_AW-1:`TC_AW-t17_addr_w] == t17_addr)); +assign req_i[3] = i3_wb_cyc_i & + ((i3_wb_adr_i[`TC_AW-1:`TC_AW-t0_addr_w] == t0_addr) | + multitarg & (i3_wb_adr_i[`TC_AW-1:`TC_AW-t17_addr_w] == t17_addr)); +assign req_i[4] = i4_wb_cyc_i & + ((i4_wb_adr_i[`TC_AW-1:`TC_AW-t0_addr_w] == t0_addr) | + multitarg & (i4_wb_adr_i[`TC_AW-1:`TC_AW-t17_addr_w] == t17_addr)); +assign req_i[5] = i5_wb_cyc_i & + ((i5_wb_adr_i[`TC_AW-1:`TC_AW-t0_addr_w] == t0_addr) | + multitarg & (i5_wb_adr_i[`TC_AW-1:`TC_AW-t17_addr_w] == t17_addr)); +assign req_i[6] = i6_wb_cyc_i & + ((i6_wb_adr_i[`TC_AW-1:`TC_AW-t0_addr_w] == t0_addr) | + multitarg & (i6_wb_adr_i[`TC_AW-1:`TC_AW-t17_addr_w] == t17_addr)); +assign req_i[7] = i7_wb_cyc_i & + ((i7_wb_adr_i[`TC_AW-1:`TC_AW-t0_addr_w] == t0_addr) | + multitarg & (i7_wb_adr_i[`TC_AW-1:`TC_AW-t17_addr_w] == t17_addr)); + +// +// Determine who gets current access to the target. +// +// If current initiator still asserts request, do nothing +// (keep current initiator). +// Otherwise check each initiator's request, starting from initiator 0 +// (highest priority). +// If there is no requests from initiators, park initiator 0. +// +assign req_won = req_cont ? req_r : + req_i[0] ? 3'd0 : + req_i[1] ? 3'd1 : + req_i[2] ? 3'd2 : + req_i[3] ? 3'd3 : + req_i[4] ? 3'd4 : + req_i[5] ? 3'd5 : + req_i[6] ? 3'd6 : + req_i[7] ? 3'd7 : 3'd0; + +// +// Check if current initiator still wants access to the target and if +// it does, assert req_cont. +// +always @(req_r or req_i) + case (req_r) // synopsys parallel_case + 3'd0: req_cont = req_i[0]; + 3'd1: req_cont = req_i[1]; + 3'd2: req_cont = req_i[2]; + 3'd3: req_cont = req_i[3]; + 3'd4: req_cont = req_i[4]; + 3'd5: req_cont = req_i[5]; + 3'd6: req_cont = req_i[6]; + 3'd7: req_cont = req_i[7]; + endcase + +// +// Register who has current access to the target. +// +always @(posedge wb_clk_i or posedge wb_rst_i) + if (wb_rst_i) + req_r <= #1 3'd0; + else + req_r <= #1 req_won; + +endmodule + +// +// Single initiator to multiple targets +// +module tc_si_to_mt ( + + i0_wb_cyc_i, + i0_wb_stb_i, + i0_wb_adr_i, + i0_wb_sel_i, + i0_wb_we_i, + i0_wb_dat_i, + i0_wb_dat_o, + i0_wb_ack_o, + i0_wb_err_o, + i0_wb_cti_i, + i0_wb_bte_i, + + t0_wb_cyc_o, + t0_wb_stb_o, + t0_wb_adr_o, + t0_wb_sel_o, + t0_wb_we_o, + t0_wb_dat_o, + t0_wb_dat_i, + t0_wb_ack_i, + t0_wb_err_i, + t0_wb_cti_o, + t0_wb_bte_o, + + t1_wb_cyc_o, + t1_wb_stb_o, + t1_wb_adr_o, + t1_wb_sel_o, + t1_wb_we_o, + t1_wb_dat_o, + t1_wb_dat_i, + t1_wb_ack_i, + t1_wb_err_i, + t1_wb_cti_o, + t1_wb_bte_o, + + t2_wb_cyc_o, + t2_wb_stb_o, + t2_wb_adr_o, + t2_wb_sel_o, + t2_wb_we_o, + t2_wb_dat_o, + t2_wb_dat_i, + t2_wb_ack_i, + t2_wb_err_i, + t2_wb_cti_o, + t2_wb_bte_o, + + t3_wb_cyc_o, + t3_wb_stb_o, + t3_wb_adr_o, + t3_wb_sel_o, + t3_wb_we_o, + t3_wb_dat_o, + t3_wb_dat_i, + t3_wb_ack_i, + t3_wb_err_i, + t3_wb_cti_o, + t3_wb_bte_o, + + t4_wb_cyc_o, + t4_wb_stb_o, + t4_wb_adr_o, + t4_wb_sel_o, + t4_wb_we_o, + t4_wb_dat_o, + t4_wb_dat_i, + t4_wb_ack_i, + t4_wb_err_i, + t4_wb_cti_o, + t4_wb_bte_o, + + t5_wb_cyc_o, + t5_wb_stb_o, + t5_wb_adr_o, + t5_wb_sel_o, + t5_wb_we_o, + t5_wb_dat_o, + t5_wb_dat_i, + t5_wb_ack_i, + t5_wb_err_i, + t5_wb_cti_o, + t5_wb_bte_o, + + t6_wb_cyc_o, + t6_wb_stb_o, + t6_wb_adr_o, + t6_wb_sel_o, + t6_wb_we_o, + t6_wb_dat_o, + t6_wb_dat_i, + t6_wb_ack_i, + t6_wb_err_i, + t6_wb_cti_o, + t6_wb_bte_o, + + t7_wb_cyc_o, + t7_wb_stb_o, + t7_wb_adr_o, + t7_wb_sel_o, + t7_wb_we_o, + t7_wb_dat_o, + t7_wb_dat_i, + t7_wb_ack_i, + t7_wb_err_i, + t7_wb_cti_o, + t7_wb_bte_o + + +); + +// +// Parameters +// +parameter t0_addr_w = 3; +parameter t0_addr = 3'd0; +parameter t17_addr_w = 3; +parameter t1_addr = 3'd1; +parameter t2_addr = 3'd2; +parameter t3_addr = 3'd3; +parameter t4_addr = 3'd4; +parameter t5_addr = 3'd5; +parameter t6_addr = 3'd6; +parameter t7_addr = 3'd7; + +// +// I/O Ports +// + +// +// WB slave i/f connecting initiator 0 +// +input i0_wb_cyc_i; +input i0_wb_stb_i; +input [`TC_AW-1:0] i0_wb_adr_i; +input [`TC_BSW-1:0] i0_wb_sel_i; +input i0_wb_we_i; +input [`TC_DW-1:0] i0_wb_dat_i; +output [`TC_DW-1:0] i0_wb_dat_o; +output i0_wb_ack_o; +output i0_wb_err_o; +input [2:0] i0_wb_cti_i; +input [1:0] i0_wb_bte_i; +// +// WB master i/f connecting target 0 +// +output t0_wb_cyc_o; +output t0_wb_stb_o; +output [`TC_AW-1:0] t0_wb_adr_o; +output [`TC_BSW-1:0] t0_wb_sel_o; +output t0_wb_we_o; +output [`TC_DW-1:0] t0_wb_dat_o; +input [`TC_DW-1:0] t0_wb_dat_i; +input t0_wb_ack_i; +input t0_wb_err_i; +output [2:0] t0_wb_cti_o; +output [1:0] t0_wb_bte_o; + +// +// WB master i/f connecting target 1 +// +output t1_wb_cyc_o; +output t1_wb_stb_o; +output [`TC_AW-1:0] t1_wb_adr_o; +output [`TC_BSW-1:0] t1_wb_sel_o; +output t1_wb_we_o; +output [`TC_DW-1:0] t1_wb_dat_o; +input [`TC_DW-1:0] t1_wb_dat_i; +input t1_wb_ack_i; +input t1_wb_err_i; +output [2:0] t1_wb_cti_o; +output [1:0] t1_wb_bte_o; + +// +// WB master i/f connecting target 2 +// +output t2_wb_cyc_o; +output t2_wb_stb_o; +output [`TC_AW-1:0] t2_wb_adr_o; +output [`TC_BSW-1:0] t2_wb_sel_o; +output t2_wb_we_o; +output [`TC_DW-1:0] t2_wb_dat_o; +input [`TC_DW-1:0] t2_wb_dat_i; +input t2_wb_ack_i; +input t2_wb_err_i; +output [2:0] t2_wb_cti_o; +output [1:0] t2_wb_bte_o; + +// +// WB master i/f connecting target 3 +// +output t3_wb_cyc_o; +output t3_wb_stb_o; +output [`TC_AW-1:0] t3_wb_adr_o; +output [`TC_BSW-1:0] t3_wb_sel_o; +output t3_wb_we_o; +output [`TC_DW-1:0] t3_wb_dat_o; +input [`TC_DW-1:0] t3_wb_dat_i; +input t3_wb_ack_i; +input t3_wb_err_i; +output [2:0] t3_wb_cti_o; +output [1:0] t3_wb_bte_o; + +// +// WB master i/f connecting target 4 +// +output t4_wb_cyc_o; +output t4_wb_stb_o; +output [`TC_AW-1:0] t4_wb_adr_o; +output [`TC_BSW-1:0] t4_wb_sel_o; +output t4_wb_we_o; +output [`TC_DW-1:0] t4_wb_dat_o; +input [`TC_DW-1:0] t4_wb_dat_i; +input t4_wb_ack_i; +input t4_wb_err_i; +output [2:0] t4_wb_cti_o; +output [1:0] t4_wb_bte_o; + +// +// WB master i/f connecting target 5 +// +output t5_wb_cyc_o; +output t5_wb_stb_o; +output [`TC_AW-1:0] t5_wb_adr_o; +output [`TC_BSW-1:0] t5_wb_sel_o; +output t5_wb_we_o; +output [`TC_DW-1:0] t5_wb_dat_o; +input [`TC_DW-1:0] t5_wb_dat_i; +input t5_wb_ack_i; +input t5_wb_err_i; +output [2:0] t5_wb_cti_o; +output [1:0] t5_wb_bte_o; + +// +// WB master i/f connecting target 6 +// +output t6_wb_cyc_o; +output t6_wb_stb_o; +output [`TC_AW-1:0] t6_wb_adr_o; +output [`TC_BSW-1:0] t6_wb_sel_o; +output t6_wb_we_o; +output [`TC_DW-1:0] t6_wb_dat_o; +input [`TC_DW-1:0] t6_wb_dat_i; +input t6_wb_ack_i; +input t6_wb_err_i; +output [2:0] t6_wb_cti_o; +output [1:0] t6_wb_bte_o; + +// +// WB master i/f connecting target 7 +// +output t7_wb_cyc_o; +output t7_wb_stb_o; +output [`TC_AW-1:0] t7_wb_adr_o; +output [`TC_BSW-1:0] t7_wb_sel_o; +output t7_wb_we_o; +output [`TC_DW-1:0] t7_wb_dat_o; +input [`TC_DW-1:0] t7_wb_dat_i; +input t7_wb_ack_i; +input t7_wb_err_i; +output [2:0] t7_wb_cti_o; +output [1:0] t7_wb_bte_o; + + +// +// Internal wires & registers +// +wire [`TC_IIN_W-1:0] i0_in; +wire [`TC_TIN_W-1:0] i0_out; +wire [`TC_IIN_W-1:0] t0_out, t1_out, + t2_out, t3_out, + t4_out, t5_out, + t6_out, t7_out; +wire [`TC_TIN_W-1:0] t0_in, t1_in, + t2_in, t3_in, + t4_in, t5_in, + t6_in, t7_in; +wire [7:0] req_t; + +// +// Group WB initiator 0 i/f inputs and outputs +// +assign i0_in = {i0_wb_cyc_i, i0_wb_stb_i, i0_wb_adr_i, + i0_wb_sel_i, i0_wb_we_i, i0_wb_dat_i, i0_wb_cti_i, i0_wb_bte_i}; +assign {i0_wb_dat_o, i0_wb_ack_o, i0_wb_err_o} = i0_out; +// +// Group WB target 0 i/f inputs and outputs +// +assign {t0_wb_cyc_o, t0_wb_stb_o, t0_wb_adr_o, +t0_wb_sel_o, t0_wb_we_o, t0_wb_dat_o, t0_wb_cti_o, t0_wb_bte_o} = t0_out; +assign t0_in = {t0_wb_dat_i, t0_wb_ack_i, t0_wb_err_i}; + +// +// Group WB target 1 i/f inputs and outputs +// +assign {t1_wb_cyc_o, t1_wb_stb_o, t1_wb_adr_o, +t1_wb_sel_o, t1_wb_we_o, t1_wb_dat_o, t1_wb_cti_o, t1_wb_bte_o} = t1_out; +assign t1_in = {t1_wb_dat_i, t1_wb_ack_i, t1_wb_err_i}; + +// +// Group WB target 2 i/f inputs and outputs +// +assign {t2_wb_cyc_o, t2_wb_stb_o, t2_wb_adr_o, +t2_wb_sel_o, t2_wb_we_o, t2_wb_dat_o, t2_wb_cti_o, t2_wb_bte_o} = t2_out; +assign t2_in = {t2_wb_dat_i, t2_wb_ack_i, t2_wb_err_i}; + +// +// Group WB target 3 i/f inputs and outputs +// +assign {t3_wb_cyc_o, t3_wb_stb_o, t3_wb_adr_o, +t3_wb_sel_o, t3_wb_we_o, t3_wb_dat_o, t3_wb_cti_o, t3_wb_bte_o} = t3_out; +assign t3_in = {t3_wb_dat_i, t3_wb_ack_i, t3_wb_err_i}; + +// +// Group WB target 4 i/f inputs and outputs +// +assign {t4_wb_cyc_o, t4_wb_stb_o, t4_wb_adr_o, +t4_wb_sel_o, t4_wb_we_o, t4_wb_dat_o, t4_wb_cti_o, t4_wb_bte_o} = t4_out; +assign t4_in = {t4_wb_dat_i, t4_wb_ack_i, t4_wb_err_i}; + +// +// Group WB target 5 i/f inputs and outputs +// +assign {t5_wb_cyc_o, t5_wb_stb_o, t5_wb_adr_o, +t5_wb_sel_o, t5_wb_we_o, t5_wb_dat_o, t5_wb_cti_o, t5_wb_bte_o} = t5_out; +assign t5_in = {t5_wb_dat_i, t5_wb_ack_i, t5_wb_err_i}; + +// +// Group WB target 6 i/f inputs and outputs +// +assign {t6_wb_cyc_o, t6_wb_stb_o, t6_wb_adr_o, +t6_wb_sel_o, t6_wb_we_o, t6_wb_dat_o, t6_wb_cti_o, t6_wb_bte_o} = t6_out; +assign t6_in = {t6_wb_dat_i, t6_wb_ack_i, t6_wb_err_i}; + +// +// Group WB target 7 i/f inputs and outputs +// +assign {t7_wb_cyc_o, t7_wb_stb_o, t7_wb_adr_o, +t7_wb_sel_o, t7_wb_we_o, t7_wb_dat_o, t7_wb_cti_o, t7_wb_bte_o} = t7_out; +assign t7_in = {t7_wb_dat_i, t7_wb_ack_i, t7_wb_err_i}; + +// +// Assign to WB target i/f outputs +// +// Either inputs from the initiator are assigned or zeros. +// +assign t0_out = req_t[0] ? i0_in : {`TC_IIN_W{1'b0}}; +assign t1_out = req_t[1] ? i0_in : {`TC_IIN_W{1'b0}}; +assign t2_out = req_t[2] ? i0_in : {`TC_IIN_W{1'b0}}; +assign t3_out = req_t[3] ? i0_in : {`TC_IIN_W{1'b0}}; +assign t4_out = req_t[4] ? i0_in : {`TC_IIN_W{1'b0}}; +assign t5_out = req_t[5] ? i0_in : {`TC_IIN_W{1'b0}}; +assign t6_out = req_t[6] ? i0_in : {`TC_IIN_W{1'b0}}; +assign t7_out = req_t[7] ? i0_in : {`TC_IIN_W{1'b0}}; + +// +// Assign to WB initiator i/f outputs +// +// Assign inputs from target to initiator outputs according to +// which target is accessed. If there is no request for a target, +// assign zeros. +// +assign i0_out = req_t[0] ? t0_in : + req_t[1] ? t1_in : + req_t[2] ? t2_in : + req_t[3] ? t3_in : + req_t[4] ? t4_in : + req_t[5] ? t5_in : + req_t[6] ? t6_in : + req_t[7] ? t7_in : {`TC_TIN_W{1'b0}}; + +// +// Determine which target is being accessed. +// +assign req_t[0] = i0_wb_cyc_i & (i0_wb_adr_i[`TC_AW-1:`TC_AW-t0_addr_w] == t0_addr); +assign req_t[1] = i0_wb_cyc_i & (i0_wb_adr_i[`TC_AW-1:`TC_AW-t17_addr_w] == t1_addr); +assign req_t[2] = i0_wb_cyc_i & (i0_wb_adr_i[`TC_AW-1:`TC_AW-t17_addr_w] == t2_addr); +assign req_t[3] = i0_wb_cyc_i & (i0_wb_adr_i[`TC_AW-1:`TC_AW-t17_addr_w] == t3_addr); +assign req_t[4] = i0_wb_cyc_i & (i0_wb_adr_i[`TC_AW-1:`TC_AW-t17_addr_w] == t4_addr); +assign req_t[5] = i0_wb_cyc_i & (i0_wb_adr_i[`TC_AW-1:`TC_AW-t17_addr_w] == t5_addr); +assign req_t[6] = i0_wb_cyc_i & (i0_wb_adr_i[`TC_AW-1:`TC_AW-t17_addr_w] == t6_addr); +assign req_t[7] = i0_wb_cyc_i & (i0_wb_adr_i[`TC_AW-1:`TC_AW-t17_addr_w] == t7_addr); + +endmodule Index: rc-1.0/utils/contributions/eth_transf_linux/eth1_mac_recv.c =================================================================== --- rc-1.0/utils/contributions/eth_transf_linux/eth1_mac_recv.c (nonexistent) +++ rc-1.0/utils/contributions/eth_transf_linux/eth1_mac_recv.c (revision 109) @@ -0,0 +1,118 @@ +#include + +#include + +//packet socket +#include +#include +#include + +//protocol +#include + +//netdevice stuff +#include +#include + +//file open stuff +#include +#include +#include + +//arp stuff +//#include + +#define MAC_ADDR_LEN 6 +typedef unsigned char MacAddress[MAC_ADDR_LEN]; + +int main() +{ + int socket_id, new_sock, iRet = -1; + int addrlen, bytesread, nfound =0; + + int i = 0; + + MacAddress localMac = {0x00, 0x00, 0xC0, 0x41, 0x36, 0xD3}; +// MacAddress localMac = {0xD3, 0x36, 0x41, 0xC0, 0x00, 0x00}; + + char buf[256]; + + struct sockaddr_ll my_addr; + + struct ifreq ethreq; + + int if_index; + + //create packet socket from type sock_dgram where headers are automatically thrown out + if ( ( socket_id = socket(PF_PACKET, SOCK_DGRAM, htons(ETH_P_ALL) ) ) < 0 ) + { + perror("socket"); + exit(1); + } + else + { + printf("Socket has been created: socket_number %d\n", socket_id); + } + + + //GET ethreq for if "eth1" + strncpy(ethreq.ifr_name,"eth1",IFNAMSIZ); + ioctl(socket_id, SIOCGIFFLAGS, ðreq); + //SET promisc mode for if ethreq +// ethreq.ifr_flags |= IFF_PROMISC; +// ioctl(socket_id, SIOCSIFFLAGS, ðreq); + //request index + ioctl(socket_id, SIOCGIFINDEX, ðreq); + + if_index = ethreq.ifr_ifindex; + + printf("This is the index of the interface: %d\n", if_index ); + + memset(&my_addr, '0', sizeof(my_addr) ); + + my_addr.sll_family = AF_PACKET; + my_addr.sll_protocol = htons(ETH_P_ALL); //defaults to socket protocol + my_addr.sll_ifindex = if_index; +// my_addr.sll_hatype = htons(ARPHRD_ETHER); +// my_addr.sll_pkttype = PACKET_OTHERHOST; + my_addr.sll_halen = 6; + memcpy( &(my_addr.sll_addr), localMac, MAC_ADDR_LEN ); + + //request hw_addres + ioctl(socket_id, SIOCGIFHWADDR, ðreq); + + printf("This is the address of my card: %d\n", my_addr.sll_addr[5] ); + + //bind to interface goten from ioctl SIOCGIFHWADDR directive (otherwise all packets are recved) + if ( bind( socket_id, (struct sockaddr *) &my_addr, sizeof(my_addr) ) ) + { + perror("bind"); + exit(1); + } + + struct sockaddr_ll from; + int fromlen; + + fromlen = sizeof(from); + + for (;;) + { + iRet = recvfrom(socket_id, buf, 256, 0, &from, &fromlen); + if ( iRet == -1 ) + { + perror("recvfrom"); + exit(1); + } + else + { + printf("Received %d bytes of data.\n", iRet); + printf("This is the received data:\n"); + for ( i = 0; i < iRet; i++) + printf("Byte %d: %X\n", i, (int)buf[i]); + printf("End of transmission!\n"); + } + } + + return 0; +} + Index: rc-1.0/utils/contributions/eth_transf_linux/eth1_mac_snd.c =================================================================== --- rc-1.0/utils/contributions/eth_transf_linux/eth1_mac_snd.c (nonexistent) +++ rc-1.0/utils/contributions/eth_transf_linux/eth1_mac_snd.c (revision 109) @@ -0,0 +1,139 @@ +#include + +#include + +//packet socket +#include +#include +#include + +//protocol +#include + +//netdevice stuff +#include +#include + +//file open stuff +#include +#include +#include + +//arp stuff +//#include + +#define MAC_ADDR_LEN 6 +typedef unsigned char MacAddress[MAC_ADDR_LEN]; + +int main() +{ + int socket_id, new_sock, iRet = -1; + int addrlen, bytesread, nfound =0; + + int i = 0; + + MacAddress localMac = {0x00, 0x00, 0xC0, 0x41, 0x36, 0xD3}; + MacAddress extMac = {0x55, 0x47, 0x34, 0x22, 0x88, 0x92}; +// MacAddress extMac = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00}; + + char buf[256]; + + struct sockaddr_ll my_addr; + + struct ifreq ethreq; + + int if_index; + + if ( ( socket_id = socket(PF_PACKET, SOCK_DGRAM, htons(ETH_P_ALL) ) ) < 0 ) + { + perror("socket"); + exit(1); + } + else + { + printf("Socket has been created: socket_number %d\n", socket_id); + } + + + //GET ethreq for if "eth1" + strncpy(ethreq.ifr_name,"eth1",IFNAMSIZ); + ioctl(socket_id, SIOCGIFFLAGS, ðreq); + //SET promisc mode for if ethreq +// ethreq.ifr_flags |= IFF_PROMISC; +// ioctl(socket_id, SIOCSIFFLAGS, ðreq); + //request index + ioctl(socket_id, SIOCGIFINDEX, ðreq); + if_index = ethreq.ifr_ifindex; + + printf("This is the index of the interface: %d\n", if_index ); + + memset(&my_addr, '0', sizeof(my_addr) ); + + my_addr.sll_family = AF_PACKET; + my_addr.sll_protocol = htons(ETH_P_ALL); //defaults to socket protocol + my_addr.sll_ifindex = if_index; +// my_addr.sll_hatype = htons(ARPHRD_ETHER); +// my_addr.sll_pkttype = PACKET_OTHERHOST; + my_addr.sll_halen = 6; + memcpy( &(my_addr.sll_addr), localMac, MAC_ADDR_LEN ); + + //request hw_addres + ioctl(socket_id, SIOCGIFHWADDR, ðreq); + + printf("This is the address of my card: %d\n", my_addr.sll_addr[5] ); + + if ( bind( socket_id, (struct sockaddr *) &my_addr, sizeof(my_addr) ) ) + { + perror("bind"); + exit(1); + } + + struct sockaddr_ll addr_to; + int addr_toLen; + + addr_toLen = sizeof(addr_to); + + memset(&addr_to, '0', sizeof(addr_to) ); + + addr_to.sll_family = AF_PACKET; + addr_to.sll_ifindex = if_index; + addr_to.sll_halen = 6; + memcpy( &(addr_to.sll_addr), extMac, MAC_ADDR_LEN ); + + for (i=0; i<256 ; i++ ) + buf[i] = 0; + + //first 2 bytes are gathered with length and are ignored + buf[0] = 0xAA; + buf[1] = 0xAA; + //now it gets to fpga: send opcode 0xBA8 + buf[2] = 0xBA; + buf[3] = 0x87; + //opcode sent + buf[4] = 0xAA; + buf[5] = 0xAA; + buf[6] = 0xAA; + buf[7] = 0xAA; + buf[8] = 0xAA; + buf[9] = 0xAA; + buf[10] = 0xAA; + buf[11] = 0xAA; + +// for (;;) +// { + iRet = sendto(socket_id, buf, 46, 0, (struct sockaddr *) &addr_to, addr_toLen); + if ( iRet == -1 ) + { + perror("sendto"); + exit(1); + } + else + { +// printf("%s\n", buf); + printf("Data sent!\nExiting...\n"); + } +// } + + return 0; +} + Index: rc-1.0/utils/cable_parallel.c =================================================================== --- rc-1.0/utils/cable_parallel.c (nonexistent) +++ rc-1.0/utils/cable_parallel.c (revision 109) @@ -0,0 +1,219 @@ +/* cable_parallel.c - Parallel cable drivers (XPC3 and XESS) for the Advanced JTAG Bridge + Copyright (C) 2001 Marko Mlinar, markom@opencores.org + Copyright (C) 2004 Gyrgy Jeney, nog@sdf.lonestar.org + + + This program is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 2 of the License, or + (at your option) any later version. + + This program is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program; if not, write to the Free Software + Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. */ + + + +#include +#include + +#include +#include +#include +#include +#include +#include + +#include "cable_common.h" +#include "errcodes.h" + + +// Common functions used by both cable types +static int cable_parallel_out(uint8_t value); +static int cable_parallel_inout(uint8_t value, uint8_t *inval); + + +int fd; + + + +///////////////////////////////////////////////////////////////////////////////// +/*-------------------------------------[ Parallel port specific functions ]---*/ +/////////////////////////////////////////////////////////////////////////////// + +int cable_parallel_init() +{ +/* + //#ifndef WIN32 + if (ioperm(base, 3, 1)) { + fprintf(stderr, "Couldn't get the port at %x\n", base); + perror("Root privileges are required.\n"); + return APP_ERR_INIT_FAILED; + } + printf("Connected to parallel port at %x\n", base); + printf("Dropping root privileges.\n"); + setreuid(getuid(), getuid()); + //#endif +*/ + int mode = IEEE1284_MODE_COMPAT; + fd = open("/dev/parport0", O_RDWR | O_NONBLOCK); + if (fd == -1) + { + perror("Not able to acquire the device desriptor\n"); + return APP_ERR_INIT_FAILED; + } + if (ioctl(fd, PPCLAIM) == -1) + { + perror("Fail to claim the interface for itself.\n"); + return APP_ERR_INIT_FAILED; + } + if (ioctl(fd, PPSETMODE, &mode) == -1) + { + perror("Setting compatibility mode failed.\n"); + return APP_ERR_INIT_FAILED; + } + + return APP_ERR_NONE; +} + + +int cable_parallel_opt(int c, char *str) +{ + switch(c) { + case 'p': +// if(!sscanf(str, "%x", &base)) { +// fprintf(stderr, "p parameter must have a hex number as parameter\n"); + return APP_ERR_BAD_PARAM; +// } + break; + default: + fprintf(stderr, "Unknown parameter '%c'\n", c); + return APP_ERR_BAD_PARAM; + } + return APP_ERR_NONE; +} + +/*-----------------------------------------[ Physical board wait function ]---*/ +void cable_parallel_phys_wait() +{ + /* Multiple users have reported poor performance of parallel cables, + * which has been traced to usleep() sleeping much longer than + * microseconds. The same users have reported error-free functionality + * and an order of magnitude improvement in upload speed. + * If you get strange data errors while running, add this sleep back + * in, or perhaps a busy-wait delay. + */ + /* usleep(10); */ +} + +/*----------------------------------------------[ xpc3 specific functions ]---*/ +int cable_xpc3_out(uint8_t value) +{ + uint8_t out = 0; + + /* First convert the bits in value byte to the ones that the cable wants */ + if(value & TCLK_BIT) + out |= 0x02; /* D1 pin 3 */ + if(value & TRST_BIT) + out |= 0x10; /* Not used */ + if(value & TDI_BIT) + out |= 0x01; /* D0 pin 2 */ + if(value & TMS_BIT) + out |= 0x04; /* D2 pin 4 */ + + return cable_parallel_out(out); +} + +int cable_xpc3_inout(uint8_t value, uint8_t *inval) +{ + uint8_t in; + int retval; + uint8_t out = 0; + + /* First convert the bits in value byte to the ones that the cable wants */ + if(value & TCLK_BIT) + out |= 0x02; /* D1 pin 3 */ + if(value & TRST_BIT) + out |= 0x10; /* Not used */ + if(value & TDI_BIT) + out |= 0x01; /* D0 pin 2 */ + if(value & TMS_BIT) + out |= 0x04; /* D2 pin 4 */ + + retval = cable_parallel_inout(out, &in); + + if(in & 0x10) /* S6 pin 13 */ + *inval = 1; + else + *inval = 0; + + return retval; +} + +/*----------------------------------------------[ xess specific functions ]---*/ +int cable_xess_out(uint8_t value) +{ + uint8_t out = 0; + + /* First convert the bits in value byte to the ones that the cable wants */ + if(value & TCLK_BIT) + out |= 0x04; /* D2 pin 4 */ + if(value & TRST_BIT) + out |= 0x08; /* D3 pin 5 */ + if(value & TDI_BIT) + out |= 0x10; /* D4 pin 6 */ + if(value & TMS_BIT) + out |= 0x20; /* D3 pin 5 */ + + return cable_parallel_out(out); +} + +uint8_t cable_xess_inout(uint8_t value, uint8_t *inval) +{ + uint8_t in; + int retval; + uint8_t out = 0; + + /* First convert the bits in value byte to the ones that the cable wants */ + if(value & TCLK_BIT) + out |= 0x04; /* D2 pin 4 */ + if(value & TRST_BIT) + out |= 0x08; /* D3 pin 5 */ + if(value & TDI_BIT) + out |= 0x10; /* D4 pin 6 */ + if(value & TMS_BIT) + out |= 0x20; /* D3 pin 5 */ + + retval = cable_parallel_inout(out, &in); + + if(in & 0x20) /* S5 pin 12*/ + *inval = 1; + else + *inval = 0; + + return retval; +} + + +/*----------------------------------------------[ common helper functions ]---*/ +// 'static' for internal access only + +static int cable_parallel_out(uint8_t value) +{ + ioctl(fd, PPWDATA, &value); + + return APP_ERR_NONE; +} + +static int cable_parallel_inout(uint8_t value, uint8_t *inval) +{ + ioctl(fd, PPRSTATUS, inval); + ioctl(fd, PPWDATA, &value); + + return APP_ERR_NONE; +}
rc-1.0/utils/cable_parallel.c Property changes : Added: svn:executable ## -0,0 +1 ## +* \ No newline at end of property Index: rc-1.0/utils/minsoc_wb_32_8_bridge.v =================================================================== --- rc-1.0/utils/minsoc_wb_32_8_bridge.v (nonexistent) +++ rc-1.0/utils/minsoc_wb_32_8_bridge.v (revision 109) @@ -0,0 +1,52 @@ + +module minsoc_wb_32_8_bridge( + wb_32_sel_i, + wb_32_dat_i, wb_32_dat_o, wb_32_adr_i, + + wb_8_dat_i, wb_8_dat_o, wb_8_adr_i +); + +input [3:0] wb_32_sel_i; + +input [31:0] wb_32_dat_i; +output reg [31:0] wb_32_dat_o; +input [31:0] wb_32_adr_i; + +output reg [7:0] wb_8_dat_i; +input [7:0] wb_8_dat_o; +output [31:0] wb_8_adr_i; + +reg [1:0] wb_8_adr; + +// put output to the correct byte in 32 bits using select line +always @(wb_32_sel_i or wb_8_dat_o) + case (wb_32_sel_i) + 4'b0001: wb_32_dat_o <= #1 {24'b0, wb_8_dat_o}; + 4'b0010: wb_32_dat_o <= #1 {16'b0, wb_8_dat_o , 8'b0}; + 4'b0100: wb_32_dat_o <= #1 {8'b0, wb_8_dat_o , 16'b0}; + 4'b1000: wb_32_dat_o <= #1 {wb_8_dat_o , 24'b0}; + 4'b1111: wb_32_dat_o <= #1 {24'b0, wb_8_dat_o}; + default: wb_32_dat_o <= #1 0; + endcase // case(wb_sel_i) + +always @(wb_32_sel_i or wb_32_dat_i) +begin + case (wb_32_sel_i) + 4'b0001 : wb_8_dat_i = wb_32_dat_i[7:0]; + 4'b0010 : wb_8_dat_i = wb_32_dat_i[15:8]; + 4'b0100 : wb_8_dat_i = wb_32_dat_i[23:16]; + 4'b1000 : wb_8_dat_i = wb_32_dat_i[31:24]; + default : wb_8_dat_i = wb_32_dat_i[7:0]; + endcase // case(wb_sel_i) + case (wb_32_sel_i) + 4'b0001 : wb_8_adr = 2'h3; + 4'b0010 : wb_8_adr = 2'h2; + 4'b0100 : wb_8_adr = 2'h1; + 4'b1000 : wb_8_adr = 2'h0; + default : wb_8_adr = 2'h0; + endcase // case(wb_sel_i) +end + +assign wb_8_adr_i = { wb_32_adr_i[31:2] , wb_8_adr }; + +endmodule Index: rc-1.0/backend/spartan3a_dsp_kit/configure =================================================================== --- rc-1.0/backend/spartan3a_dsp_kit/configure (nonexistent) +++ rc-1.0/backend/spartan3a_dsp_kit/configure (revision 109) @@ -0,0 +1,99 @@ +#!/bin/bash + +#new boards have to udpate this +BOARD=spartan3a_dsp_kit #this has to have the name of the directory this file is in +DEVICE_PART='xc3sd1800a-4-fg676' +CONSTRAINT_FILE='spartan3a_dsp_kit.ucf' +#~new boards update + +#system workings +MINSOC_DIR=`pwd`/../.. +BACKEND_DIR=$MINSOC_DIR/backend +SYN_DIR=$MINSOC_DIR/syn +SYNSRC_DIR=$MINSOC_DIR/prj/xilinx +SYNSUPPORT_DIR=$SYN_DIR/buildSupport +MAKEFILE_DIR=$SYN_DIR/xilinx + +SYN_FILES=(ethmac.xst uart_top.xst adbg_top.xst or1200_top.xst minsoc_top.xst) +MAKEFILE=Makefile + +FIND_PART='DEVICE_PART' +FIND_CONSTRAINT='CONSTRAINT_FILE' + +BOARD_DIR=$BACKEND_DIR/$BOARD +BOARD_FILES=(board.h orp.ld minsoc_defines.v minsoc_bench_defines.v gcc-opt.mk $CONSTRAINT_FILE) + +in_minsoc=`pwd | grep minsoc/backend/${BOARD}$` +if [ -z $in_minsoc ] +then + echo "" + echo " !!!WARNING!!!" + echo "This script cannot be run if not in a board directory inside minsoc/backend," + echo "because it relies on the directory structure of the minsoc system." + echo "" + echo "Possibly your minsoc directory is named differently, minsoc_trunk for example." + echo "Its name must be minsoc only." + echo "" + exit 1 +fi + +echo "" +echo "This script sets up the SoC for simulations and synthesis." +echo "" +echo "In order to do so, SoC board's specific files for firmware compilation, " +echo "testbench generation and synthesis are configured." +echo "Firmware and testbench looks for board specific files under $BACKEND_DIR." +echo "Synthesis work under $SYN_DIR." +echo "" +echo "" + +echo "Generating project files for simulation and synthesis..." +make -C $MINSOC_DIR/prj +echo "Generation complete." +echo "__________________________________________________________________________" +echo "" + +if [ $CONSTRAINT_FILE == 'NONE' ] +then + echo "Skipping synthesis preparation. Standard implementation can only be simulated." +else + echo "Device part for files under $SYNSRC_DIR will be patched and stored " + echo "temporarily." + echo "Afterwards, they are copied to $SYNSUPPORT_DIR." + echo "__________________________________________________________________________" + echo "" + for file in "${SYN_FILES[@]}" + do + echo "Updating synthesis file, $file..." + echo "Copying $file to synthesis directory..." + echo "" + sed "s/$FIND_PART/$DEVICE_PART/g" $SYNSRC_DIR/$file > TMPFILE + sed "s/$FIND_CONSTRAINT/$CONSTRAINT_FILE/g" TMPFILE > TMPFILE2 && mv TMPFILE2 $SYNSUPPORT_DIR/$file + rm TMPFILE + done + + echo "Updating Makefile file under $MAKEFILE_DIR..." + echo "Copying Makefile to synthesis directory, $SYN_DIR..." + echo "" + sed "s/$FIND_PART/$DEVICE_PART/g" $MAKEFILE_DIR/$MAKEFILE > TMPFILE + sed "s/$FIND_CONSTRAINT/$CONSTRAINT_FILE/g" TMPFILE > TMPFILE2 && mv TMPFILE2 $SYN_DIR/$MAKEFILE + rm TMPFILE + cp $MAKEFILE_DIR/setup.bat $SYN_DIR/setup.bat +fi +echo "" +echo "" + + +echo "Copying board specific SoC files from $BOARD_DIR to $BACKEND_DIR directory." +echo "__________________________________________________________________________" +echo "" +for file in "${BOARD_FILES[@]}" +do + if [ $file != NONE ] + then + echo "Copying $file, to backend directory..." + cp $BOARD_DIR/$file $BACKEND_DIR + fi +done +echo "" +echo ""
rc-1.0/backend/spartan3a_dsp_kit/configure Property changes : Added: svn:executable ## -0,0 +1 ## +* \ No newline at end of property Index: rc-1.0/backend/spartan3a_dsp_kit/minsoc_defines.v =================================================================== --- rc-1.0/backend/spartan3a_dsp_kit/minsoc_defines.v (nonexistent) +++ rc-1.0/backend/spartan3a_dsp_kit/minsoc_defines.v (revision 109) @@ -0,0 +1,150 @@ +// +// Define FPGA manufacturer +// +//`define GENERIC_FPGA +//`define ALTERA_FPGA +`define XILINX_FPGA + +// +// Define Xilinx FPGA family +// +`ifdef XILINX_FPGA +//`define SPARTAN2 +//`define SPARTAN3 +//`define SPARTAN3E +`define SPARTAN3A +//`define VIRTEX +//`define VIRTEX2 +//`define VIRTEX4 +//`define VIRTEX5 + +// +// Define Altera FPGA family +// +`elsif ALTERA_FPGA +//`define ARRIA_GX +//`define ARRIA_II_GX +//`define CYCLONE_I +//`define CYCLONE_II +`define CYCLONE_III +//`define CYCLONE_III_LS +//`define CYCLONE_IV_E +//`define CYCLONE_IV_GS +//`define MAX_II +//`define MAX_V +//`define MAX3000A +//`define MAX7000AE +//`define MAX7000B +//`define MAX7000S +//`define STRATIX +//`define STRATIX_II +//`define STRATIX_II_GX +//`define STRATIX_III +`endif + +// +// Memory +// +`define MEMORY_ADR_WIDTH 15 //MEMORY_ADR_WIDTH IS NOT ALLOWED TO BE LESS THAN 12, + //memory is composed by blocks of address width 11 + //Address width of memory -> select memory depth, + //2 powers MEMORY_ADR_WIDTH defines the memory depth + //the memory data width is 32 bit, + //memory amount in Bytes = 4*memory depth + +// +// Memory type (uncomment something if ASIC or generic memory) +// +//`define GENERIC_MEMORY +//`define AVANT_ATP +//`define VIRAGE_SSP +//`define VIRTUALSILICON_SSP + + +// +// TAP selection +// +//`define GENERIC_TAP +`define FPGA_TAP + +// +// Clock Division selection +// +//`define NO_CLOCK_DIVISION +//`define GENERIC_CLOCK_DIVISION +`define FPGA_CLOCK_DIVISION // For Altera ALTPLL, only CYCLONE_III family has been tested. + +// +// Define division +// +`define CLOCK_DIVISOR 5 //in case of GENERIC_CLOCK_DIVISION the real value will be rounded + //down to an even value in FPGA case, check minsoc_clock_manager + //for allowed divisors. + //DO NOT USE CLOCK_DIVISOR = 1 COMMENT THE CLOCK DIVISION SELECTION + //INSTEAD. + +// +// Reset polarity +// +//`define NEGATIVE_RESET //rstn +`define POSITIVE_RESET //rst + +// +// Start-up circuit (only necessary later to load firmware automatically from SPI memory) +// +//`define START_UP + +// +// Connected modules +// +`define UART +`define ETHERNET + +// +// Ethernet reset +// +//`define ETH_RESET 1'b0 +`define ETH_RESET 1'b1 + +// +// Interrupts +// +`define APP_INT_RES1 1:0 +`define APP_INT_UART 2 +`define APP_INT_RES2 3 +`define APP_INT_ETH 4 +`define APP_INT_PS2 5 +`define APP_INT_RES3 19:6 + +// +// Address map +// +`define APP_ADDR_DEC_W 8 +`define APP_ADDR_SRAM `APP_ADDR_DEC_W'h00 +`define APP_ADDR_FLASH `APP_ADDR_DEC_W'h04 +`define APP_ADDR_DECP_W 4 +`define APP_ADDR_PERIP `APP_ADDR_DECP_W'h9 +`define APP_ADDR_SPI `APP_ADDR_DEC_W'h97 +`define APP_ADDR_ETH `APP_ADDR_DEC_W'h92 +`define APP_ADDR_AUDIO `APP_ADDR_DEC_W'h9d +`define APP_ADDR_UART `APP_ADDR_DEC_W'h90 +`define APP_ADDR_PS2 `APP_ADDR_DEC_W'h94 +`define APP_ADDR_RES1 `APP_ADDR_DEC_W'h9e +`define APP_ADDR_RES2 `APP_ADDR_DEC_W'h9f + +// +// Set-up GENERIC_TAP, GENERIC_MEMORY if GENERIC_FPGA was chosen +// and GENERIC_CLOCK_DIVISION if NO_CLOCK_DIVISION was not set +// +`ifdef GENERIC_FPGA + `undef FPGA_TAP + `undef FPGA_CLOCK_DIVISION + `undef XILINX_FPGA + `undef SPARTAN3A + + `define GENERIC_TAP + `define GENERIC_MEMORY + `ifndef NO_CLOCK_DIVISION + `define GENERIC_CLOCK_DIVISION + `endif +`endif Index: rc-1.0/backend/spartan3a_dsp_kit/gcc-opt.mk =================================================================== --- rc-1.0/backend/spartan3a_dsp_kit/gcc-opt.mk (nonexistent) +++ rc-1.0/backend/spartan3a_dsp_kit/gcc-opt.mk (revision 109) @@ -0,0 +1 @@ +GCC_OPT=-mhard-mul -mhard-div -nostdlib Index: rc-1.0/backend/spartan3a_dsp_kit/minsoc_bench_defines.v =================================================================== --- rc-1.0/backend/spartan3a_dsp_kit/minsoc_bench_defines.v (nonexistent) +++ rc-1.0/backend/spartan3a_dsp_kit/minsoc_bench_defines.v (revision 109) @@ -0,0 +1,26 @@ +//set RTL for simulation, override FPGA specific definitions (JTAG TAP, MEMORY and CLOCK DIVIDER) +`define GENERIC_FPGA +`define MEMORY_MODEL //simulation uses a memory model enabling INITIALIZE_MEMORY_MODEL. If you comment this, START_UP might be interesting. +`define NO_CLOCK_DIVISION //if commented out, generic clock division is implemented (odd divisors are rounded down) +//~set RTL for simulation, override FPGA specific definitions (JTAG TAP, MEMORY and CLOCK DIVIDER) + +`define FREQ_NUM_FOR_NS 1000000000 + +`define FREQ 25000000 +`define CLK_PERIOD (`FREQ_NUM_FOR_NS/`FREQ) + +`define ETH_PHY_FREQ 25000000 +`define ETH_PHY_PERIOD (`FREQ_NUM_FOR_NS/`ETH_PHY_FREQ) //40ns + +`define UART_BAUDRATE 115200 + +`define VPI_DEBUG + +//`define VCD_OUTPUT + +//`define START_UP //pass firmware over spi to or1k_startup + +`define INITIALIZE_MEMORY_MODEL //instantaneously initialize memory model with firmware + //only use with the memory model. + //If you use the original memory (`define MEMORY_MODEL + //commented out), comment this too.
rc-1.0/backend/spartan3a_dsp_kit/minsoc_bench_defines.v Property changes : Added: svn:executable ## -0,0 +1 ## +* \ No newline at end of property Index: rc-1.0/backend/spartan3a_dsp_kit/spartan3a_dsp_kit.ucf =================================================================== --- rc-1.0/backend/spartan3a_dsp_kit/spartan3a_dsp_kit.ucf (nonexistent) +++ rc-1.0/backend/spartan3a_dsp_kit/spartan3a_dsp_kit.ucf (revision 109) @@ -0,0 +1,72 @@ +########################### +## +## Global signals +## +net "clk" loc = "f13"; #125MHz clock +net "reset" loc = "j17"; #SW5 +########################### + +########################### +## +## JTAG +## +#net "jtag_tms" loc = "aa23"; #SAM D0 +#net "jtag_tdi" loc = "u20"; #SAM D2 +#net "jtag_tdo" loc = "aa25"; #SAM D4 +#net "jtag_tck" loc = "u18" | CLOCK_DEDICATED_ROUTE = FALSE; #SAM D6 +#net "jtag_gnd" loc = "y23"; #SAM D8 +#net "jtag_vref" loc = "t20"; #SAM D10 +########################### + +############################# +## +## SPI Flash External Memory +## +#NET "spi_flash_mosi" LOC = "ab15"; +#NET "spi_flash_miso" LOC = "af24"; +#NET "spi_flash_sclk" LOC = "ae24"; +#NET "spi_flash_ss(1)" LOC = "ac25"; +#NET "spi_flash_ss(0)" LOC = "aa7"; +########################### + +########################### +## +## UART +## +net "uart_stx" loc = "p22"; +net "uart_srx" loc = "n21"; +########################### + +########################### +## +## ETH +## +NET "eth_txd(3)" LOC = "b1"; +NET "eth_txd(2)" LOC = "b2"; +NET "eth_txd(1)" LOC = "j9"; +NET "eth_txd(0)" LOC = "j8"; + +NET "eth_tx_en" LOC = "d3"; +NET "eth_tx_clk" LOC = "p2"; +NET "eth_tx_er" LOC = "e4"; + +NET "eth_rxd(3)" LOC = "d2"; +NET "eth_rxd(2)" LOC = "g5"; +NET "eth_rxd(1)" LOC = "g2"; +NET "eth_rxd(0)" LOC = "c2"; + +NET "eth_rx_er" LOC = "j3"; +NET "eth_rx_dv" LOC = "d1"; + +NET "eth_rx_clk" LOC = "p1"; + +NET "eth_mdio" LOC = "f5" | PULLUP; +NET "eth_crs" LOC = "g1"; +NET "eth_col" LOC = "y3"; +NET "eth_mdc" LOC = "f4"; + +NET "eth_trste" LOC = "g4"; + +NET "eth_fds_mdint" LOC = "j1"; +########################### +
rc-1.0/backend/spartan3a_dsp_kit/spartan3a_dsp_kit.ucf Property changes : Added: svn:executable ## -0,0 +1 ## +* \ No newline at end of property Index: rc-1.0/backend/spartan3a_dsp_kit/board.h =================================================================== --- rc-1.0/backend/spartan3a_dsp_kit/board.h (nonexistent) +++ rc-1.0/backend/spartan3a_dsp_kit/board.h (revision 109) @@ -0,0 +1,40 @@ +#ifndef _BOARD_H_ +#define _BOARD_H_ + +#define MC_ENABLED 0 + +#define IC_ENABLE 0 +#define IC_SIZE 8192 +#define DC_ENABLE 0 +#define DC_SIZE 8192 + + +#define IN_CLK 25000000 + + +#define STACK_SIZE 0x01000 + +#define UART_BAUD_RATE 115200 + +#define UART_BASE 0x90000000 +#define UART_IRQ 2 +#define ETH_BASE 0x92000000 +#define ETH_IRQ 4 +#define I2C_BASE 0x9D000000 +#define I2C_IRQ 3 +#define CAN_BASE 0x94000000 +#define CAN_IRQ 5 + +#define MC_BASE_ADDR 0x60000000 +#define SPI_BASE 0xa0000000 + +#define ETH_DATA_BASE 0xa8000000 /* Address for ETH_DATA */ + +#define ETH_MACADDR0 0x00 +#define ETH_MACADDR1 0x12 +#define ETH_MACADDR2 0x34 +#define ETH_MACADDR3 0x56 +#define ETH_MACADDR4 0x78 +#define ETH_MACADDR5 0x9a + +#endif
rc-1.0/backend/spartan3a_dsp_kit/board.h Property changes : Added: svn:executable ## -0,0 +1 ## +* \ No newline at end of property Index: rc-1.0/backend/spartan3a_dsp_kit/orp.ld =================================================================== --- rc-1.0/backend/spartan3a_dsp_kit/orp.ld (nonexistent) +++ rc-1.0/backend/spartan3a_dsp_kit/orp.ld (revision 109) @@ -0,0 +1,60 @@ +MEMORY + { + reset : ORIGIN = 0x00000000, LENGTH = 0x00000200 + vectors : ORIGIN = 0x00000200, LENGTH = 0x00001000 + ram : ORIGIN = 0x00001200, LENGTH = 0x0001EE00 /*0x20000 total*/ + } + +SECTIONS +{ + .reset : + { + *(.reset) + } > reset + + + + .vectors : + { + _vec_start = .; + *(.vectors) + _vec_end = .; + } > vectors + + .text : + { + *(.text) + } > ram + + .rodata : + { + *(.rodata) + *(.rodata.*) + } > ram + + .icm : + { + _icm_start = .; + *(.icm) + _icm_end = .; + } > ram + + .data : + { + _dst_beg = .; + *(.data) + _dst_end = .; + } > ram + + .bss : + { + *(.bss) + } > ram + + .stack (NOLOAD) : + { + *(.stack) + _src_addr = .; + } > ram + +}
rc-1.0/backend/spartan3a_dsp_kit/orp.ld Property changes : Added: svn:executable ## -0,0 +1 ## +* \ No newline at end of property Index: rc-1.0/backend/std/configure =================================================================== --- rc-1.0/backend/std/configure (nonexistent) +++ rc-1.0/backend/std/configure (revision 109) @@ -0,0 +1,99 @@ +#!/bin/bash + +#new boards have to udpate this +BOARD=std #this has to have the name of the directory this file is in +DEVICE_PART='NONE' +CONSTRAINT_FILE='NONE' +#~new boards update + +#system workings +MINSOC_DIR=`pwd`/../.. +BACKEND_DIR=$MINSOC_DIR/backend +SYN_DIR=$MINSOC_DIR/syn +SYNSRC_DIR=$MINSOC_DIR/prj/xilinx +SYNSUPPORT_DIR=$SYN_DIR/buildSupport +MAKEFILE_DIR=$SYN_DIR/xilinx + +SYN_FILES=(ethmac.xst uart_top.xst adbg_top.xst or1200_top.xst minsoc_top.xst) +MAKEFILE=Makefile + +FIND_PART='DEVICE_PART' +FIND_CONSTRAINT='CONSTRAINT_FILE' + +BOARD_DIR=$BACKEND_DIR/$BOARD +BOARD_FILES=(board.h orp.ld minsoc_defines.v minsoc_bench_defines.v gcc-opt.mk $CONSTRAINT_FILE) + +in_minsoc=`pwd | grep minsoc/backend/${BOARD}$` +if [ -z $in_minsoc ] +then + echo "" + echo " !!!WARNING!!!" + echo "This script cannot be run if not in a board directory inside minsoc/backend," + echo "because it relies on the directory structure of the minsoc system." + echo "" + echo "Possibly your minsoc directory is named differently, minsoc_trunk for example." + echo "Its name must be minsoc only." + echo "" + exit 1 +fi + +echo "" +echo "This script sets up the SoC for simulations and synthesis." +echo "" +echo "In order to do so, SoC board's specific files for firmware compilation, " +echo "testbench generation and synthesis are configured." +echo "Firmware and testbench looks for board specific files under $BACKEND_DIR." +echo "Synthesis work under $SYN_DIR." +echo "" +echo "" + +echo "Generating project files for simulation and synthesis..." +make -C $MINSOC_DIR/prj +echo "Generation complete." +echo "__________________________________________________________________________" +echo "" + +if [ $CONSTRAINT_FILE == 'NONE' ] +then + echo "Skipping synthesis preparation. Standard implementation can only be simulated." +else + echo "Device part for files under $SYNSRC_DIR will be patched and stored " + echo "temporarily." + echo "Afterwards, they are copied to $SYNSUPPORT_DIR." + echo "__________________________________________________________________________" + echo "" + for file in "${SYN_FILES[@]}" + do + echo "Updating synthesis file, $file..." + echo "Copying $file to synthesis directory..." + echo "" + sed "s/$FIND_PART/$DEVICE_PART/g" $SYNSRC_DIR/$file > TMPFILE + sed "s/$FIND_CONSTRAINT/$CONSTRAINT_FILE/g" TMPFILE > TMPFILE2 && mv TMPFILE2 $SYNSUPPORT_DIR/$file + rm TMPFILE + done + + echo "Updating Makefile file under $MAKEFILE_DIR..." + echo "Copying Makefile to synthesis directory, $SYN_DIR..." + echo "" + sed "s/$FIND_PART/$DEVICE_PART/g" $MAKEFILE_DIR/$MAKEFILE > TMPFILE + sed "s/$FIND_CONSTRAINT/$CONSTRAINT_FILE/g" TMPFILE > TMPFILE2 && mv TMPFILE2 $SYN_DIR/$MAKEFILE + rm TMPFILE + cp $MAKEFILE_DIR/setup.bat $SYN_DIR/setup.bat +fi +echo "" +echo "" + + +echo "Copying board specific SoC files from $BOARD_DIR to $BACKEND_DIR directory." +echo "__________________________________________________________________________" +echo "" +for file in "${BOARD_FILES[@]}" +do + if [ $file != NONE ] + then + echo "Copying $file, to backend directory..." + cp $BOARD_DIR/$file $BACKEND_DIR + fi +done +echo "" +echo ""
rc-1.0/backend/std/configure Property changes : Added: svn:executable ## -0,0 +1 ## +* \ No newline at end of property Index: rc-1.0/backend/std/gcc-opt.mk =================================================================== --- rc-1.0/backend/std/gcc-opt.mk (nonexistent) +++ rc-1.0/backend/std/gcc-opt.mk (revision 109) @@ -0,0 +1 @@ +GCC_OPT=-mhard-mul -mhard-div -nostdlib Index: rc-1.0/backend/std/minsoc_bench_defines.v =================================================================== --- rc-1.0/backend/std/minsoc_bench_defines.v (nonexistent) +++ rc-1.0/backend/std/minsoc_bench_defines.v (revision 109) @@ -0,0 +1,26 @@ +//set RTL for simulation, override FPGA specific definitions (JTAG TAP, MEMORY and CLOCK DIVIDER) +`define GENERIC_FPGA +`define MEMORY_MODEL //simulation uses a memory model enabling INITIALIZE_MEMORY_MODEL. If you comment this, START_UP might be interesting. +`define NO_CLOCK_DIVISION //if commented out, generic clock division is implemented (odd divisors are rounded down) +//~set RTL for simulation, override FPGA specific definitions (JTAG TAP, MEMORY and CLOCK DIVIDER) + +`define FREQ_NUM_FOR_NS 1000000000 + +`define FREQ 25000000 +`define CLK_PERIOD (`FREQ_NUM_FOR_NS/`FREQ) + +`define ETH_PHY_FREQ 25000000 +`define ETH_PHY_PERIOD (`FREQ_NUM_FOR_NS/`ETH_PHY_FREQ) //40ns + +`define UART_BAUDRATE 115200 + +`define VPI_DEBUG + +//`define VCD_OUTPUT + +//`define START_UP //pass firmware over spi to or1k_startup + +`define INITIALIZE_MEMORY_MODEL //instantaneously initialize memory model with firmware + //only use with the memory model. + //If you use the original memory (`define MEMORY_MODEL + //commented out), comment this too.
rc-1.0/backend/std/minsoc_bench_defines.v Property changes : Added: svn:executable ## -0,0 +1 ## +* \ No newline at end of property Index: rc-1.0/backend/std/minsoc_defines.v =================================================================== --- rc-1.0/backend/std/minsoc_defines.v (nonexistent) +++ rc-1.0/backend/std/minsoc_defines.v (revision 109) @@ -0,0 +1,148 @@ +// +// Define FPGA manufacturer +// +`define GENERIC_FPGA +//`define ALTERA_FPGA +//`define XILINX_FPGA + +// +// Define Xilinx FPGA family +// +`ifdef XILINX_FPGA +//`define SPARTAN2 +//`define SPARTAN3 +//`define SPARTAN3E +`define SPARTAN3A +//`define VIRTEX +//`define VIRTEX2 +//`define VIRTEX4 +//`define VIRTEX5 + +// +// Define Altera FPGA family +// +`elsif ALTERA_FPGA +//`define ARRIA_GX +//`define ARRIA_II_GX +//`define CYCLONE_I +//`define CYCLONE_II +`define CYCLONE_III +//`define CYCLONE_III_LS +//`define CYCLONE_IV_E +//`define CYCLONE_IV_GS +//`define MAX_II +//`define MAX_V +//`define MAX3000A +//`define MAX7000AE +//`define MAX7000B +//`define MAX7000S +//`define STRATIX +//`define STRATIX_II +//`define STRATIX_II_GX +//`define STRATIX_III +`endif + +// +// Memory +// +`define MEMORY_ADR_WIDTH 13 //MEMORY_ADR_WIDTH IS NOT ALLOWED TO BE LESS THAN 12, + //memory is composed by blocks of address width 11 + //Address width of memory -> select memory depth, + //2 powers MEMORY_ADR_WIDTH defines the memory depth + //the memory data width is 32 bit, + //memory amount in Bytes = 4*memory depth + +// +// Memory type (uncomment something if ASIC or generic memory) +// +//`define GENERIC_MEMORY +//`define AVANT_ATP +//`define VIRAGE_SSP +//`define VIRTUALSILICON_SSP + + +// +// TAP selection +// +//`define GENERIC_TAP +`define FPGA_TAP + +// +// Clock Division selection +// +//`define NO_CLOCK_DIVISION +//`define GENERIC_CLOCK_DIVISION +`define FPGA_CLOCK_DIVISION // For Altera ALTPLL, only CYCLONE_III family has been tested. + +// +// Define division +// +`define CLOCK_DIVISOR 5 //in case of GENERIC_CLOCK_DIVISION the real value will be rounded + //down to an even value in FPGA case, check minsoc_clock_manager + //for allowed divisors. + //DO NOT USE CLOCK_DIVISOR = 1 COMMENT THE CLOCK DIVISION SELECTION + //INSTEAD. + +// +// Reset polarity +// +`define NEGATIVE_RESET //rstn +//`define POSITIVE_RESET //rst + +// +// Start-up circuit (only necessary later to load firmware automatically from SPI memory) +// +//`define START_UP + +// +// Connected modules +// +`define UART +`define ETHERNET + +// +// Ethernet reset +// +`define ETH_RESET 1'b0 +//`define ETH_RESET 1'b1 + +// +// Interrupts +// +`define APP_INT_RES1 1:0 +`define APP_INT_UART 2 +`define APP_INT_RES2 3 +`define APP_INT_ETH 4 +`define APP_INT_PS2 5 +`define APP_INT_RES3 19:6 + +// +// Address map +// +`define APP_ADDR_DEC_W 8 +`define APP_ADDR_SRAM `APP_ADDR_DEC_W'h00 +`define APP_ADDR_FLASH `APP_ADDR_DEC_W'h04 +`define APP_ADDR_DECP_W 4 +`define APP_ADDR_PERIP `APP_ADDR_DECP_W'h9 +`define APP_ADDR_SPI `APP_ADDR_DEC_W'h97 +`define APP_ADDR_ETH `APP_ADDR_DEC_W'h92 +`define APP_ADDR_AUDIO `APP_ADDR_DEC_W'h9d +`define APP_ADDR_UART `APP_ADDR_DEC_W'h90 +`define APP_ADDR_PS2 `APP_ADDR_DEC_W'h94 +`define APP_ADDR_RES1 `APP_ADDR_DEC_W'h9e +`define APP_ADDR_RES2 `APP_ADDR_DEC_W'h9f + +// +// Set-up GENERIC_TAP, GENERIC_MEMORY if GENERIC_FPGA was chosen +// and GENERIC_CLOCK_DIVISION if NO_CLOCK_DIVISION was not set +// +`ifdef GENERIC_FPGA + `undef FPGA_TAP + `undef FPGA_CLOCK_DIVISION + + `define GENERIC_TAP + `define GENERIC_MEMORY + `ifndef NO_CLOCK_DIVISION + `define GENERIC_CLOCK_DIVISION + `endif +`endif
rc-1.0/backend/std/minsoc_defines.v Property changes : Added: svn:executable ## -0,0 +1 ## +* \ No newline at end of property Index: rc-1.0/backend/std/board.h =================================================================== --- rc-1.0/backend/std/board.h (nonexistent) +++ rc-1.0/backend/std/board.h (revision 109) @@ -0,0 +1,40 @@ +#ifndef _BOARD_H_ +#define _BOARD_H_ + +#define MC_ENABLED 0 + +#define IC_ENABLE 0 +#define IC_SIZE 8192 +#define DC_ENABLE 0 +#define DC_SIZE 8192 + + +#define IN_CLK 25000000 + + +#define STACK_SIZE 0x01000 + +#define UART_BAUD_RATE 115200 + +#define UART_BASE 0x90000000 +#define UART_IRQ 2 +#define ETH_BASE 0x92000000 +#define ETH_IRQ 4 +#define I2C_BASE 0x9D000000 +#define I2C_IRQ 3 +#define CAN_BASE 0x94000000 +#define CAN_IRQ 5 + +#define MC_BASE_ADDR 0x60000000 +#define SPI_BASE 0xa0000000 + +#define ETH_DATA_BASE 0xa8000000 /* Address for ETH_DATA */ + +#define ETH_MACADDR0 0x00 +#define ETH_MACADDR1 0x12 +#define ETH_MACADDR2 0x34 +#define ETH_MACADDR3 0x56 +#define ETH_MACADDR4 0x78 +#define ETH_MACADDR5 0x9a + +#endif
rc-1.0/backend/std/board.h Property changes : Added: svn:executable ## -0,0 +1 ## +* \ No newline at end of property Index: rc-1.0/backend/std/orp.ld =================================================================== --- rc-1.0/backend/std/orp.ld (nonexistent) +++ rc-1.0/backend/std/orp.ld (revision 109) @@ -0,0 +1,60 @@ +MEMORY + { + reset : ORIGIN = 0x00000000, LENGTH = 0x00000200 + vectors : ORIGIN = 0x00000200, LENGTH = 0x00001000 + ram : ORIGIN = 0x00001200, LENGTH = 0x00006E00 /*0x8000 total*/ + } + +SECTIONS +{ + .reset : + { + *(.reset) + } > reset + + + + .vectors : + { + _vec_start = .; + *(.vectors) + _vec_end = .; + } > vectors + + .text : + { + *(.text) + } > ram + + .rodata : + { + *(.rodata) + *(.rodata.*) + } > ram + + .icm : + { + _icm_start = .; + *(.icm) + _icm_end = .; + } > ram + + .data : + { + _dst_beg = .; + *(.data) + _dst_end = .; + } > ram + + .bss : + { + *(.bss) + } > ram + + .stack (NOLOAD) : + { + *(.stack) + _src_addr = .; + } > ram + +}
rc-1.0/backend/std/orp.ld Property changes : Added: svn:executable ## -0,0 +1 ## +* \ No newline at end of property Index: rc-1.0/backend/altera_3c25_board/configure =================================================================== --- rc-1.0/backend/altera_3c25_board/configure (nonexistent) +++ rc-1.0/backend/altera_3c25_board/configure (revision 109) @@ -0,0 +1,108 @@ +#!/bin/bash + +#new boards have to udpate this +BOARD=altera_3c25_board #this has to have the name of the directory this file is in +DEVICE_PART=EP3C25Q240C8 +CONSTRAINT_FILE='altera_3c25_board.ucf' +FAMILY_PART="Cyclone III" +#~new boards update + +#system workings +MINSOC_DIR=`pwd`/../.. +BACKEND_DIR=$MINSOC_DIR/backend +SYN_DIR=$MINSOC_DIR/syn +SYNSRC_DIR=$MINSOC_DIR/prj/altera +SYNSUPPORT_DIR=$SYN_DIR/buildSupport +MAKEFILE_DIR=$SYN_DIR/altera + +PROJECT_FILE=minsoc_top.qsf + +SYN_FILES=(adbg_top.prj jtag_top.prj or1200_top.prj uart_top.prj minsoc_top.prj altera_virtual_jtag.prj) +MAKEFILE=Makefile + +FIND_PART='DEVICE_PART' +FIND_FAMILY='FAMILY_PART' +FIND_VERSION='SW_VERSION' +FIND_CONSTRAINT='CONSTRAINT_FILE' + +BOARD_DIR=$BACKEND_DIR/$BOARD +BOARD_FILES=(board.h orp.ld minsoc_defines.v minsoc_bench_defines.v gcc-opt.mk $CONSTRAINT_FILE) + +in_minsoc=`pwd | grep minsoc/backend/${BOARD}$` +if [ -z $in_minsoc ] +then + echo "" + echo " !!!WARNING!!!" + echo "This script cannot be run if not in a board directory inside minsoc/backend," + echo "because it relies on the directory structure of the minsoc system." + echo "" + echo "Possibly your minsoc directory is named differently, minsoc_trunk for example." + echo "Its name must be minsoc only." + echo "" + exit 1 +fi + +echo "" +echo "This script sets up the SoC for simulations and synthesis." +echo "" +echo "In order to do so, SoC board's specific files for firmware compilation, " +echo "testbench generation and synthesis are configured." +echo "Firmware and testbench looks for board specific files under $BACKEND_DIR." +echo "Synthesis work under $SYN_DIR." +echo "" +echo "" + +echo "Generating project files for simulation and synthesis..." +make -C $MINSOC_DIR/prj +echo "Generation complete." +echo "__________________________________________________________________________" +echo "" + +if [ $CONSTRAINT_FILE == 'NONE' ] +then + echo "Skipping synthesis preparation. Standard implementation can only be simulated." +else + echo "Device part and family for files under $SYNSRC_DIR will patched and stored " + echo "temporarily." + echo "Afterwards, they are copied to $SYNSUPPORT_DIR." + echo "__________________________________________________________________________" + echo "" + sed "s/$FIND_PART/$DEVICE_PART/g" $MAKEFILE_DIR/$PROJECT_FILE > TMPFILE + sed "s/$FIND_FAMILY/$FAMILY_PART/g" TMPFILE > TMPFILE2 + #sed "s/$FIND_VERSION/$SW_VERSION/g" TMPFILE> TMPFILE + echo "Adding settings from constraint file..." + cat $CONSTRAINT_FILE >> TMPFILE2 + + echo "Generating quartus settings from prj files in $SYNSRC_DIR" + for file in "${SYN_FILES[@]}" + do + echo "Adding settings from file $file..." + cat $SYNSRC_DIR/$file >> TMPFILE2 + done + mv TMPFILE2 $SYNSUPPORT_DIR/$PROJECT_FILE + rm TMPFILE + echo "" + echo "Generated quartus settings file in $SYNSUPPORT_DIR/$PROJECT_FILE" + echo "" + + echo "Copying Makefile from $MAKEFILE_DIR to synthesis directory, $SYN_DIR..." + cp $MAKEFILE_DIR/$MAKEFILE $SYN_DIR/$MAKEFILE + cp $MAKEFILE_DIR/setup.bat $SYN_DIR/setup.bat + echo "" + + echo "Copying board specific SoC files from $BOARD_DIR to $BACKEND_DIR directory." + echo "__________________________________________________________________________" + echo "" + for file in "${BOARD_FILES[@]}" + do + if [ $file != NONE ] + then + echo "Copying $file, to backend directory..." + cp $BOARD_DIR/$file $BACKEND_DIR + fi + done + echo "" + echo "Configuration done." + echo "For synthesis help go to $SYN_DIR and type \"make\"." +fi +
rc-1.0/backend/altera_3c25_board/configure Property changes : Added: svn:executable ## -0,0 +1 ## +* \ No newline at end of property Index: rc-1.0/backend/altera_3c25_board/minsoc_defines.v =================================================================== --- rc-1.0/backend/altera_3c25_board/minsoc_defines.v (nonexistent) +++ rc-1.0/backend/altera_3c25_board/minsoc_defines.v (revision 109) @@ -0,0 +1,150 @@ +// +// Define FPGA manufacturer +// +//`define GENERIC_FPGA +`define ALTERA_FPGA +//`define XILINX_FPGA + +// +// Define Xilinx FPGA family +// +`ifdef XILINX_FPGA +//`define SPARTAN2 +//`define SPARTAN3 +//`define SPARTAN3E +`define SPARTAN3A +//`define VIRTEX +//`define VIRTEX2 +//`define VIRTEX4 +//`define VIRTEX5 + +// +// Define Altera FPGA family +// +`elsif ALTERA_FPGA +//`define ARRIA_GX +//`define ARRIA_II_GX +//`define CYCLONE_I +//`define CYCLONE_II +`define CYCLONE_III +//`define CYCLONE_III_LS +//`define CYCLONE_IV_E +//`define CYCLONE_IV_GS +//`define MAX_II +//`define MAX_V +//`define MAX3000A +//`define MAX7000AE +//`define MAX7000B +//`define MAX7000S +//`define STRATIX +//`define STRATIX_II +//`define STRATIX_II_GX +//`define STRATIX_III +`endif + +// +// Memory +// +`define MEMORY_ADR_WIDTH 13 //MEMORY_ADR_WIDTH IS NOT ALLOWED TO BE LESS THAN 12, + //memory is composed by blocks of address width 11 + //Address width of memory -> select memory depth, + //2 powers MEMORY_ADR_WIDTH defines the memory depth + //the memory data width is 32 bit, + //memory amount in Bytes = 4*memory depth + +// +// Memory type (uncomment something if ASIC or generic memory) +// +//`define GENERIC_MEMORY +//`define AVANT_ATP +//`define VIRAGE_SSP +//`define VIRTUALSILICON_SSP + + +// +// TAP selection +// +//`define GENERIC_TAP +`define FPGA_TAP + +// +// Clock Division selection +// +//`define NO_CLOCK_DIVISION +//`define GENERIC_CLOCK_DIVISION +`define FPGA_CLOCK_DIVISION // For Altera ALTPLL, only CYCLONE_III family has been tested. + +// +// Define division +// +`define CLOCK_DIVISOR 2 //in case of GENERIC_CLOCK_DIVISION the real value will be rounded + //down to an even value in FPGA case, check minsoc_clock_manager + //for allowed divisors. + //DO NOT USE CLOCK_DIVISOR = 1 COMMENT THE CLOCK DIVISION SELECTION + //INSTEAD. + +// +// Reset polarity +// +`define NEGATIVE_RESET //rstn +//`define POSITIVE_RESET //rst + +// +// Start-up circuit (only necessary later to load firmware automatically from SPI memory) +// +//`define START_UP + +// +// Connected modules +// +`define UART +//`define ETHERNET + +// +// Ethernet reset +// +//`define ETH_RESET 1'b0 +`define ETH_RESET 1'b1 + +// +// Interrupts +// +`define APP_INT_RES1 1:0 +`define APP_INT_UART 2 +`define APP_INT_RES2 3 +`define APP_INT_ETH 4 +`define APP_INT_PS2 5 +`define APP_INT_RES3 19:6 + +// +// Address map +// +`define APP_ADDR_DEC_W 8 +`define APP_ADDR_SRAM `APP_ADDR_DEC_W'h00 +`define APP_ADDR_FLASH `APP_ADDR_DEC_W'h04 +`define APP_ADDR_DECP_W 4 +`define APP_ADDR_PERIP `APP_ADDR_DECP_W'h9 +`define APP_ADDR_SPI `APP_ADDR_DEC_W'h97 +`define APP_ADDR_ETH `APP_ADDR_DEC_W'h92 +`define APP_ADDR_AUDIO `APP_ADDR_DEC_W'h9d +`define APP_ADDR_UART `APP_ADDR_DEC_W'h90 +`define APP_ADDR_PS2 `APP_ADDR_DEC_W'h94 +`define APP_ADDR_RES1 `APP_ADDR_DEC_W'h9e +`define APP_ADDR_RES2 `APP_ADDR_DEC_W'h9f + +// +// Set-up GENERIC_TAP, GENERIC_MEMORY if GENERIC_FPGA was chosen +// and GENERIC_CLOCK_DIVISION if NO_CLOCK_DIVISION was not set +// +`ifdef GENERIC_FPGA + `undef FPGA_TAP + `undef FPGA_CLOCK_DIVISION + `undef ALTERA_FPGA + `undef CYCLONE_III + + `define GENERIC_TAP + `define GENERIC_MEMORY + `ifndef NO_CLOCK_DIVISION + `define GENERIC_CLOCK_DIVISION + `endif +`endif Index: rc-1.0/backend/altera_3c25_board/gcc-opt.mk =================================================================== --- rc-1.0/backend/altera_3c25_board/gcc-opt.mk (nonexistent) +++ rc-1.0/backend/altera_3c25_board/gcc-opt.mk (revision 109) @@ -0,0 +1 @@ +GCC_OPT=-mhard-mul -mhard-div -nostdlib Index: rc-1.0/backend/altera_3c25_board/altera_3c25_board.ucf =================================================================== --- rc-1.0/backend/altera_3c25_board/altera_3c25_board.ucf (nonexistent) +++ rc-1.0/backend/altera_3c25_board/altera_3c25_board.ucf (revision 109) @@ -0,0 +1,16 @@ +# Altera 3c25 board based pinout and definitions. +# This file uses quartus qsf file format for compose final config file. + +# RS232 Port +set_location_assignment PIN_12 -to uart_srx +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to uart_srx +set_location_assignment PIN_14 -to uart_stx +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to uart_stx + +# 50 Mhz Pin +set_location_assignment PIN_152 -to clk +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to clk + +# Reset pin. +set_location_assignment PIN_200 -to reset +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to reset Index: rc-1.0/backend/altera_3c25_board/minsoc_bench_defines.v =================================================================== --- rc-1.0/backend/altera_3c25_board/minsoc_bench_defines.v (nonexistent) +++ rc-1.0/backend/altera_3c25_board/minsoc_bench_defines.v (revision 109) @@ -0,0 +1,26 @@ +//set RTL for simulation, override FPGA specific definitions (JTAG TAP, MEMORY and CLOCK DIVIDER) +`define GENERIC_FPGA +`define MEMORY_MODEL //simulation uses a memory model enabling INITIALIZE_MEMORY_MODEL. If you comment this, START_UP might be interesting. +`define NO_CLOCK_DIVISION //if commented out, generic clock division is implemented (odd divisors are rounded down) +//~set RTL for simulation, override FPGA specific definitions (JTAG TAP, MEMORY and CLOCK DIVIDER) + +`define FREQ_NUM_FOR_NS 1000000000 + +`define FREQ 25000000 +`define CLK_PERIOD (`FREQ_NUM_FOR_NS/`FREQ) + +`define ETH_PHY_FREQ 25000000 +`define ETH_PHY_PERIOD (`FREQ_NUM_FOR_NS/`ETH_PHY_FREQ) //40ns + +`define UART_BAUDRATE 115200 + +`define VPI_DEBUG + +//`define VCD_OUTPUT + +//`define START_UP //pass firmware over spi to or1k_startup + +`define INITIALIZE_MEMORY_MODEL //instantaneously initialize memory model with firmware + //only use with the memory model. + //If you use the original memory (`define MEMORY_MODEL + //commented out), comment this too.
rc-1.0/backend/altera_3c25_board/minsoc_bench_defines.v Property changes : Added: svn:executable ## -0,0 +1 ## +* \ No newline at end of property Index: rc-1.0/backend/altera_3c25_board/board.h =================================================================== --- rc-1.0/backend/altera_3c25_board/board.h (nonexistent) +++ rc-1.0/backend/altera_3c25_board/board.h (revision 109) @@ -0,0 +1,40 @@ +#ifndef _BOARD_H_ +#define _BOARD_H_ + +#define MC_ENABLED 0 + +#define IC_ENABLE 0 +#define IC_SIZE 8192 +#define DC_ENABLE 0 +#define DC_SIZE 8192 + + +#define IN_CLK 25000000 + + +#define STACK_SIZE 0x01000 + +#define UART_BAUD_RATE 115200 + +#define UART_BASE 0x90000000 +#define UART_IRQ 2 +#define ETH_BASE 0x92000000 +#define ETH_IRQ 4 +#define I2C_BASE 0x9D000000 +#define I2C_IRQ 3 +#define CAN_BASE 0x94000000 +#define CAN_IRQ 5 + +#define MC_BASE_ADDR 0x60000000 +#define SPI_BASE 0xa0000000 + +#define ETH_DATA_BASE 0xa8000000 /* Address for ETH_DATA */ + +#define ETH_MACADDR0 0x00 +#define ETH_MACADDR1 0x12 +#define ETH_MACADDR2 0x34 +#define ETH_MACADDR3 0x56 +#define ETH_MACADDR4 0x78 +#define ETH_MACADDR5 0x9a + +#endif
rc-1.0/backend/altera_3c25_board/board.h Property changes : Added: svn:executable ## -0,0 +1 ## +* \ No newline at end of property Index: rc-1.0/backend/altera_3c25_board/orp.ld =================================================================== --- rc-1.0/backend/altera_3c25_board/orp.ld (nonexistent) +++ rc-1.0/backend/altera_3c25_board/orp.ld (revision 109) @@ -0,0 +1,60 @@ +MEMORY + { + reset : ORIGIN = 0x00000000, LENGTH = 0x00000200 + vectors : ORIGIN = 0x00000200, LENGTH = 0x00001000 + ram : ORIGIN = 0x00001200, LENGTH = 0x0001EE00 /*0x20000 total*/ + } + +SECTIONS +{ + .reset : + { + *(.reset) + } > reset + + + + .vectors : + { + _vec_start = .; + *(.vectors) + _vec_end = .; + } > vectors + + .text : + { + *(.text) + } > ram + + .rodata : + { + *(.rodata) + *(.rodata.*) + } > ram + + .icm : + { + _icm_start = .; + *(.icm) + _icm_end = .; + } > ram + + .data : + { + _dst_beg = .; + *(.data) + _dst_end = .; + } > ram + + .bss : + { + *(.bss) + } > ram + + .stack (NOLOAD) : + { + *(.stack) + _src_addr = .; + } > ram + +}
rc-1.0/backend/altera_3c25_board/orp.ld Property changes : Added: svn:executable ## -0,0 +1 ## +* \ No newline at end of property Index: rc-1.0/backend/spartan3e_starter_kit/configure =================================================================== --- rc-1.0/backend/spartan3e_starter_kit/configure (nonexistent) +++ rc-1.0/backend/spartan3e_starter_kit/configure (revision 109) @@ -0,0 +1,117 @@ +#!/bin/bash + +#NON STANDARD SCRIPT, USE ANOTHER AS TEMPLATE, NON STANDARD PART IS MARKED AS COMMENT + +#new boards have to udpate this +BOARD=spartan3e_starter_kit #this has to have the name of the directory this file is in +DEVICE_PART='xc3s500e-4-fg320' +CONSTRAINT_FILE='spartan3e_starter_kit.ucf' +#~new boards update + +#system workings +MINSOC_DIR=`pwd`/../.. +BACKEND_DIR=$MINSOC_DIR/backend +SYN_DIR=$MINSOC_DIR/syn +SYNSRC_DIR=$MINSOC_DIR/prj/xilinx +SYNSUPPORT_DIR=$SYN_DIR/buildSupport +MAKEFILE_DIR=$SYN_DIR/xilinx + +SYN_FILES=(ethmac.xst uart_top.xst adbg_top.xst or1200_top.xst minsoc_top.xst) +MAKEFILE=Makefile + +FIND_PART='DEVICE_PART' +FIND_CONSTRAINT='CONSTRAINT_FILE' + +BOARD_DIR=$BACKEND_DIR/$BOARD +BOARD_FILES=(board.h orp.ld minsoc_defines.v minsoc_bench_defines.v gcc-opt.mk $CONSTRAINT_FILE) + +in_minsoc=`pwd | grep minsoc/backend/${BOARD}$` +if [ -z $in_minsoc ] +then + echo "" + echo " !!!WARNING!!!" + echo "This script cannot be run if not in a board directory inside minsoc/backend," + echo "because it relies on the directory structure of the minsoc system." + echo "" + echo "Possibly your minsoc directory is named differently, minsoc_trunk for example." + echo "Its name must be minsoc only." + echo "" + exit 1 +fi + +#NON STANDARD SCRIPT PART +echo "THIS SCRIPT HAS A NON-STANDARD BEGINNING." +echo "__________________________________________________________________________" +echo "Spartan3E Starter Kit requires another configuration for or1200_r3." +echo "or1200_r1 should work fine, roll back this for minsoc release-1.0." + +echo "" +echo "Copying or1200_defines.v, to or1200 implementation directory..." +echo "(minsoc/rtl/verilog/or1200/rtl/verilog)" +echo "__________________________________________________________________________" +cp $BOARD_DIR/or1200_defines.v $MINSOC_DIR/rtl/verilog/or1200/rtl/verilog +echo "" +echo "REGULAR SCRIPT STARTS NOW" +echo "__________________________________________________________________________" +#~NON STANDARD SCRIPT PART + +echo "" +echo "This script sets up the SoC for simulations and synthesis." +echo "" +echo "In order to do so, SoC board's specific files for firmware compilation, " +echo "testbench generation and synthesis are configured." +echo "Firmware and testbench looks for board specific files under $BACKEND_DIR." +echo "Synthesis work under $SYN_DIR." +echo "" +echo "" + +echo "Generating project files for simulation and synthesis..." +make -C $MINSOC_DIR/prj +echo "Generation complete." +echo "__________________________________________________________________________" +echo "" + +if [ $CONSTRAINT_FILE == 'NONE' ] +then + echo "Skipping synthesis preparation. Standard implementation can only be simulated." +else + echo "Device part for files under $SYNSRC_DIR will be patched and stored " + echo "temporarily." + echo "Afterwards, they are copied to $SYNSUPPORT_DIR." + echo "__________________________________________________________________________" + echo "" + for file in "${SYN_FILES[@]}" + do + echo "Updating synthesis file, $file..." + echo "Copying $file to synthesis directory..." + echo "" + sed "s/$FIND_PART/$DEVICE_PART/g" $SYNSRC_DIR/$file > TMPFILE + sed "s/$FIND_CONSTRAINT/$CONSTRAINT_FILE/g" TMPFILE > TMPFILE2 && mv TMPFILE2 $SYNSUPPORT_DIR/$file + rm TMPFILE + done + + echo "Updating Makefile file under $MAKEFILE_DIR..." + echo "Copying Makefile to synthesis directory, $SYN_DIR..." + echo "" + sed "s/$FIND_PART/$DEVICE_PART/g" $MAKEFILE_DIR/$MAKEFILE > TMPFILE + sed "s/$FIND_CONSTRAINT/$CONSTRAINT_FILE/g" TMPFILE > TMPFILE2 && mv TMPFILE2 $SYN_DIR/$MAKEFILE + rm TMPFILE + cp $MAKEFILE_DIR/setup.bat $SYN_DIR/setup.bat +fi +echo "" +echo "" + + +echo "Copying board specific SoC files from $BOARD_DIR to $BACKEND_DIR directory." +echo "__________________________________________________________________________" +echo "" +for file in "${BOARD_FILES[@]}" +do + if [ $file != NONE ] + then + echo "Copying $file, to backend directory..." + cp $BOARD_DIR/$file $BACKEND_DIR + fi +done +echo "" +echo ""
rc-1.0/backend/spartan3e_starter_kit/configure Property changes : Added: svn:executable ## -0,0 +1 ## +* \ No newline at end of property Index: rc-1.0/backend/spartan3e_starter_kit/or1200_defines.v =================================================================== --- rc-1.0/backend/spartan3e_starter_kit/or1200_defines.v (nonexistent) +++ rc-1.0/backend/spartan3e_starter_kit/or1200_defines.v (revision 109) @@ -0,0 +1,1823 @@ +////////////////////////////////////////////////////////////////////// +//// //// +//// OR1200's definitions //// +//// //// +//// This file is part of the OpenRISC 1200 project //// +//// http://opencores.org/project,or1k //// +//// //// +//// Description //// +//// Defines for the OR1200 core //// +//// //// +//// To Do: //// +//// - add parameters that are missing //// +//// //// +//// Author(s): //// +//// - Damjan Lampret, lampret@opencores.org //// +//// //// +////////////////////////////////////////////////////////////////////// +//// //// +//// Copyright (C) 2000 Authors and OPENCORES.ORG //// +//// //// +//// This source file may be used and distributed without //// +//// restriction provided that this copyright statement is not //// +//// removed from the file and that any derivative work contains //// +//// the original copyright notice and the associated disclaimer. //// +//// //// +//// This source file is free software; you can redistribute it //// +//// and/or modify it under the terms of the GNU Lesser General //// +//// Public License as published by the Free Software Foundation; //// +//// either version 2.1 of the License, or (at your option) any //// +//// later version. //// +//// //// +//// This source is distributed in the hope that it will be //// +//// useful, but WITHOUT ANY WARRANTY; without even the implied //// +//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR //// +//// PURPOSE. See the GNU Lesser General Public License for more //// +//// details. //// +//// //// +//// You should have received a copy of the GNU Lesser General //// +//// Public License along with this source; if not, download it //// +//// from http://www.opencores.org/lgpl.shtml //// +//// //// +////////////////////////////////////////////////////////////////////// +// +// $Log: or1200_defines.v,v $ +// Revision 2.0 2010/06/30 11:00:00 ORSoC +// Minor update: +// Defines added, bugs fixed. + +// +// Dump VCD +// +//`define OR1200_VCD_DUMP + +// +// Generate debug messages during simulation +// +//`define OR1200_VERBOSE + +// `define OR1200_ASIC +//////////////////////////////////////////////////////// +// +// Typical configuration for an ASIC +// +`ifdef OR1200_ASIC + +// +// Target ASIC memories +// +//`define OR1200_ARTISAN_SSP +//`define OR1200_ARTISAN_SDP +//`define OR1200_ARTISAN_STP +`define OR1200_VIRTUALSILICON_SSP +//`define OR1200_VIRTUALSILICON_STP_T1 +//`define OR1200_VIRTUALSILICON_STP_T2 + +// +// Do not implement Data cache +// +//`define OR1200_NO_DC + +// +// Do not implement Insn cache +// +//`define OR1200_NO_IC + +// +// Do not implement Data MMU +// +//`define OR1200_NO_DMMU + +// +// Do not implement Insn MMU +// +//`define OR1200_NO_IMMU + +// +// Select between ASIC optimized and generic multiplier +// +//`define OR1200_ASIC_MULTP2_32X32 +`define OR1200_GENERIC_MULTP2_32X32 + +// +// Size/type of insn/data cache if implemented +// +// `define OR1200_IC_1W_512B +// `define OR1200_IC_1W_4KB +`define OR1200_IC_1W_8KB +// `define OR1200_DC_1W_4KB +`define OR1200_DC_1W_8KB + +`else + + +///////////////////////////////////////////////////////// +// +// Typical configuration for an FPGA +// + +// +// Target FPGA memories +// +//`define OR1200_ALTERA_LPM +//`define OR1200_XILINX_RAMB16 +//`define OR1200_XILINX_RAMB4 +//`define OR1200_XILINX_RAM32X1D +//`define OR1200_USE_RAM16X1D_FOR_RAM32X1D +// Generic models should infer RAM blocks at synthesis time (not only effects +// single port ram.) +`define OR1200_GENERIC + +// +// Do not implement Data cache +// +`define OR1200_NO_DC + +// +// Do not implement Insn cache +// +`define OR1200_NO_IC + +// +// Do not implement Data MMU +// +`define OR1200_NO_DMMU + +// +// Do not implement Insn MMU +// +`define OR1200_NO_IMMU + +// +// Select between ASIC and generic multiplier +// +// (Generic seems to trigger a bug in the Cadence Ncsim simulator) +// +//`define OR1200_ASIC_MULTP2_32X32 +`define OR1200_GENERIC_MULTP2_32X32 + +// +// Size/type of insn/data cache if implemented +// (consider available FPGA memory resources) +// +//`define OR1200_IC_1W_512B +//`define OR1200_IC_1W_4KB +`define OR1200_IC_1W_8KB +//`define OR1200_IC_1W_16KB +//`define OR1200_IC_1W_32KB +//`define OR1200_DC_1W_4KB +`define OR1200_DC_1W_8KB +//`define OR1200_DC_1W_16KB +//`define OR1200_DC_1W_32KB + +`endif + + +////////////////////////////////////////////////////////// +// +// Do not change below unless you know what you are doing +// + +// +// Reset active low +// +//`define OR1200_RST_ACT_LOW + +// +// Enable RAM BIST +// +// At the moment this only works for Virtual Silicon +// single port RAMs. For other RAMs it has not effect. +// Special wrapper for VS RAMs needs to be provided +// with scan flops to facilitate bist scan. +// +//`define OR1200_BIST + +// +// Register OR1200 WISHBONE outputs +// (must be defined/enabled) +// +`define OR1200_REGISTERED_OUTPUTS + +// +// Register OR1200 WISHBONE inputs +// +// (must be undefined/disabled) +// +//`define OR1200_REGISTERED_INPUTS + +// +// Disable bursts if they are not supported by the +// memory subsystem (only affect cache line fill) +// +//`define OR1200_NO_BURSTS +// + +// +// WISHBONE retry counter range +// +// 2^value range for retry counter. Retry counter +// is activated whenever *wb_rty_i is asserted and +// until retry counter expires, corresponding +// WISHBONE interface is deactivated. +// +// To disable retry counters and *wb_rty_i all together, +// undefine this macro. +// +//`define OR1200_WB_RETRY 7 + +// +// WISHBONE Consecutive Address Burst +// +// This was used prior to WISHBONE B3 specification +// to identify bursts. It is no longer needed but +// remains enabled for compatibility with old designs. +// +// To remove *wb_cab_o ports undefine this macro. +// +//`define OR1200_WB_CAB + +// +// WISHBONE B3 compatible interface +// +// This follows the WISHBONE B3 specification. +// It is not enabled by default because most +// designs still don't use WB b3. +// +// To enable *wb_cti_o/*wb_bte_o ports, +// define this macro. +// +`define OR1200_WB_B3 + +// +// LOG all WISHBONE accesses +// +`define OR1200_LOG_WB_ACCESS + +// +// Enable additional synthesis directives if using +// _Synopsys_ synthesis tool +// +//`define OR1200_ADDITIONAL_SYNOPSYS_DIRECTIVES + +// +// Enables default statement in some case blocks +// and disables Synopsys synthesis directive full_case +// +// By default it is enabled. When disabled it +// can increase clock frequency. +// +`define OR1200_CASE_DEFAULT + +// +// Operand width / register file address width +// +// (DO NOT CHANGE) +// +`define OR1200_OPERAND_WIDTH 32 +`define OR1200_REGFILE_ADDR_WIDTH 5 + +// +// l.add/l.addi/l.and and optional l.addc/l.addic +// also set (compare) flag when result of their +// operation equals zero +// +// At the time of writing this, default or32 +// C/C++ compiler doesn't generate code that +// would benefit from this optimization. +// +// By default this optimization is disabled to +// save area. +// +//`define OR1200_ADDITIONAL_FLAG_MODIFIERS + +// +// Implement l.addc/l.addic instructions +// +// By default implementation of l.addc/l.addic +// instructions is enabled in case you need them. +// If you don't use them, then disable implementation +// to save area. +// +`define OR1200_IMPL_ADDC + +// +// Implement l.sub instruction +// +// By default implementation of l.sub instructions +// is enabled to be compliant with the simulator. +// If you don't use carry bit, then disable +// implementation to save area. +// +`define OR1200_IMPL_SUB + +// +// Implement carry bit SR[CY] +// +// +// By default implementation of SR[CY] is enabled +// to be compliant with the simulator. However SR[CY] +// is explicitly only used by l.addc/l.addic/l.sub +// instructions and if these three insns are not +// implemented there is not much point having SR[CY]. +// +`define OR1200_IMPL_CY + +// +// Implement carry bit SR[OV] +// +// Compiler doesn't use this, but other code may like +// to. +// +`define OR1200_IMPL_OV + +// +// Implement carry bit SR[OVE] +// +// Overflow interrupt indicator. When enabled, SR[OV] flag +// does not remain asserted after exception. +// +`define OR1200_IMPL_OVE + + +// +// Implement rotate in the ALU +// +// At the time of writing this, or32 +// C/C++ compiler doesn't generate rotate +// instructions. However or32 assembler +// can assemble code that uses rotate insn. +// This means that rotate instructions +// must be used manually inserted. +// +// By default implementation of rotate +// is disabled to save area and increase +// clock frequency. +// +//`define OR1200_IMPL_ALU_ROTATE + +// +// Type of ALU compare to implement +// +// Try to find which synthesizes with +// most efficient logic use or highest speed. +// +//`define OR1200_IMPL_ALU_COMP1 +//`define OR1200_IMPL_ALU_COMP2 +`define OR1200_IMPL_ALU_COMP3 + +// +// Implement Find First/Last '1' +// +`define OR1200_IMPL_ALU_FFL1 + +// +// Implement l.cust5 ALU instruction +// +//`define OR1200_IMPL_ALU_CUST5 + +// +// Implement l.extXs and l.extXz instructions +// +`define OR1200_IMPL_ALU_EXT + +// +// Implement multiplier +// +// By default multiplier is implemented +// +`define OR1200_MULT_IMPLEMENTED + +// +// Implement multiply-and-accumulate +// +// By default MAC is implemented. To +// implement MAC, multiplier (non-serial) needs to be +// implemented. +// +//`define OR1200_MAC_IMPLEMENTED + +// +// Implement optional l.div/l.divu instructions +// +// By default divide instructions are not implemented +// to save area. +// +// +`define OR1200_DIV_IMPLEMENTED + +// +// Serial multiplier. +// +//`define OR1200_MULT_SERIAL + +// +// Serial divider. +// Uncomment to use a serial divider, otherwise will +// be a generic parallel implementation. +// +`define OR1200_DIV_SERIAL + +// +// Implement HW Single Precision FPU +// +//`define OR1200_FPU_IMPLEMENTED + +// +// Clock ratio RISC clock versus WB clock +// +// If you plan to run WB:RISC clock fixed to 1:1, disable +// both defines +// +// For WB:RISC 1:2 or 1:1, enable OR1200_CLKDIV_2_SUPPORTED +// and use clmode to set ratio +// +// For WB:RISC 1:4, 1:2 or 1:1, enable both defines and use +// clmode to set ratio +// +//`define OR1200_CLKDIV_2_SUPPORTED +//`define OR1200_CLKDIV_4_SUPPORTED + +// +// Type of register file RAM +// +// Memory macro w/ two ports (see or1200_tpram_32x32.v) +//`define OR1200_RFRAM_TWOPORT +// +// Memory macro dual port (see or1200_dpram.v) +`define OR1200_RFRAM_DUALPORT + +// +// Generic (flip-flop based) register file (see or1200_rfram_generic.v) +//`define OR1200_RFRAM_GENERIC +// Generic register file supports - 16 registers +`ifdef OR1200_RFRAM_GENERIC +// `define OR1200_RFRAM_16REG +`endif + +// +// Type of mem2reg aligner to implement. +// +// Once OR1200_IMPL_MEM2REG2 yielded faster +// circuit, however with today tools it will +// most probably give you slower circuit. +// +`define OR1200_IMPL_MEM2REG1 +//`define OR1200_IMPL_MEM2REG2 + +// +// Reset value and event +// +`ifdef OR1200_RST_ACT_LOW + `define OR1200_RST_VALUE (1'b0) + `define OR1200_RST_EVENT negedge +`else + `define OR1200_RST_VALUE (1'b1) + `define OR1200_RST_EVENT posedge +`endif + +// +// ALUOPs +// +`define OR1200_ALUOP_WIDTH 5 +`define OR1200_ALUOP_NOP 5'b0_0100 +/* LS-nibble encodings correspond to bits [3:0] of instruction */ +`define OR1200_ALUOP_ADD 5'b0_0000 // 0 +`define OR1200_ALUOP_ADDC 5'b0_0001 // 1 +`define OR1200_ALUOP_SUB 5'b0_0010 // 2 +`define OR1200_ALUOP_AND 5'b0_0011 // 3 +`define OR1200_ALUOP_OR 5'b0_0100 // 4 +`define OR1200_ALUOP_XOR 5'b0_0101 // 5 +`define OR1200_ALUOP_MUL 5'b0_0110 // 6 +`define OR1200_ALUOP_RESERVED 5'b0_0111 // 7 +`define OR1200_ALUOP_SHROT 5'b0_1000 // 8 +`define OR1200_ALUOP_DIV 5'b0_1001 // 9 +`define OR1200_ALUOP_DIVU 5'b0_1010 // a +`define OR1200_ALUOP_MULU 5'b0_1011 // b +`define OR1200_ALUOP_EXTHB 5'b0_1100 // c +`define OR1200_ALUOP_EXTW 5'b0_1101 // d +`define OR1200_ALUOP_CMOV 5'b0_1110 // e +`define OR1200_ALUOP_FFL1 5'b0_1111 // f + +/* Values sent to ALU from decode unit - not defined by ISA */ +`define OR1200_ALUOP_COMP 5'b1_0000 // Comparison +`define OR1200_ALUOP_MOVHI 5'b1_0001 // Move-high +`define OR1200_ALUOP_CUST5 5'b1_0010 // l.cust5 + +// ALU instructions second opcode field +`define OR1200_ALUOP2_POS 9:6 +`define OR1200_ALUOP2_WIDTH 4 + +// +// MACOPs +// +`define OR1200_MACOP_WIDTH 3 +`define OR1200_MACOP_NOP 3'b000 +`define OR1200_MACOP_MAC 3'b001 +`define OR1200_MACOP_MSB 3'b010 + +// +// Shift/rotate ops +// +`define OR1200_SHROTOP_WIDTH 4 +`define OR1200_SHROTOP_NOP 4'd0 +`define OR1200_SHROTOP_SLL 4'd0 +`define OR1200_SHROTOP_SRL 4'd1 +`define OR1200_SHROTOP_SRA 4'd2 +`define OR1200_SHROTOP_ROR 4'd3 + +// +// Zero/Sign Extend ops +// +`define OR1200_EXTHBOP_WIDTH 4 +`define OR1200_EXTHBOP_BS 4'h1 +`define OR1200_EXTHBOP_HS 4'h0 +`define OR1200_EXTHBOP_BZ 4'h3 +`define OR1200_EXTHBOP_HZ 4'h2 +`define OR1200_EXTWOP_WIDTH 4 +`define OR1200_EXTWOP_WS 4'h0 +`define OR1200_EXTWOP_WZ 4'h1 + +// Execution cycles per instruction +`define OR1200_MULTICYCLE_WIDTH 3 +`define OR1200_ONE_CYCLE 3'd0 +`define OR1200_TWO_CYCLES 3'd1 + +// Execution control which will "wait on" a module to finish +`define OR1200_WAIT_ON_WIDTH 2 +`define OR1200_WAIT_ON_NOTHING `OR1200_WAIT_ON_WIDTH'd0 +`define OR1200_WAIT_ON_MULTMAC `OR1200_WAIT_ON_WIDTH'd1 +`define OR1200_WAIT_ON_FPU `OR1200_WAIT_ON_WIDTH'd2 +`define OR1200_WAIT_ON_MTSPR `OR1200_WAIT_ON_WIDTH'd3 + + +// Operand MUX selects +`define OR1200_SEL_WIDTH 2 +`define OR1200_SEL_RF 2'd0 +`define OR1200_SEL_IMM 2'd1 +`define OR1200_SEL_EX_FORW 2'd2 +`define OR1200_SEL_WB_FORW 2'd3 + +// +// BRANCHOPs +// +`define OR1200_BRANCHOP_WIDTH 3 +`define OR1200_BRANCHOP_NOP 3'd0 +`define OR1200_BRANCHOP_J 3'd1 +`define OR1200_BRANCHOP_JR 3'd2 +`define OR1200_BRANCHOP_BAL 3'd3 +`define OR1200_BRANCHOP_BF 3'd4 +`define OR1200_BRANCHOP_BNF 3'd5 +`define OR1200_BRANCHOP_RFE 3'd6 + +// +// LSUOPs +// +// Bit 0: sign extend +// Bits 1-2: 00 doubleword, 01 byte, 10 halfword, 11 singleword +// Bit 3: 0 load, 1 store +`define OR1200_LSUOP_WIDTH 4 +`define OR1200_LSUOP_NOP 4'b0000 +`define OR1200_LSUOP_LBZ 4'b0010 +`define OR1200_LSUOP_LBS 4'b0011 +`define OR1200_LSUOP_LHZ 4'b0100 +`define OR1200_LSUOP_LHS 4'b0101 +`define OR1200_LSUOP_LWZ 4'b0110 +`define OR1200_LSUOP_LWS 4'b0111 +`define OR1200_LSUOP_LD 4'b0001 +`define OR1200_LSUOP_SD 4'b1000 +`define OR1200_LSUOP_SB 4'b1010 +`define OR1200_LSUOP_SH 4'b1100 +`define OR1200_LSUOP_SW 4'b1110 + +// Number of bits of load/store EA precalculated in ID stage +// for balancing ID and EX stages. +// +// Valid range: 2,3,...,30,31 +`define OR1200_LSUEA_PRECALC 2 + +// FETCHOPs +`define OR1200_FETCHOP_WIDTH 1 +`define OR1200_FETCHOP_NOP 1'b0 +`define OR1200_FETCHOP_LW 1'b1 + +// +// Register File Write-Back OPs +// +// Bit 0: register file write enable +// Bits 3-1: write-back mux selects +// +`define OR1200_RFWBOP_WIDTH 4 +`define OR1200_RFWBOP_NOP 4'b0000 +`define OR1200_RFWBOP_ALU 3'b000 +`define OR1200_RFWBOP_LSU 3'b001 +`define OR1200_RFWBOP_SPRS 3'b010 +`define OR1200_RFWBOP_LR 3'b011 +`define OR1200_RFWBOP_FPU 3'b100 + +// Compare instructions +`define OR1200_COP_SFEQ 3'b000 +`define OR1200_COP_SFNE 3'b001 +`define OR1200_COP_SFGT 3'b010 +`define OR1200_COP_SFGE 3'b011 +`define OR1200_COP_SFLT 3'b100 +`define OR1200_COP_SFLE 3'b101 +`define OR1200_COP_X 3'b111 +`define OR1200_SIGNED_COMPARE 'd3 +`define OR1200_COMPOP_WIDTH 4 + +// +// FP OPs +// +// MSbit indicates FPU operation valid +// +`define OR1200_FPUOP_WIDTH 8 +// FPU unit from Usselman takes 5 cycles from decode, so 4 ex. cycles +`define OR1200_FPUOP_CYCLES 3'd4 +// FP instruction is double precision if bit 4 is set. We're a 32-bit +// implementation thus do not support double precision FP +`define OR1200_FPUOP_DOUBLE_BIT 4 +`define OR1200_FPUOP_ADD 8'b0000_0000 +`define OR1200_FPUOP_SUB 8'b0000_0001 +`define OR1200_FPUOP_MUL 8'b0000_0010 +`define OR1200_FPUOP_DIV 8'b0000_0011 +`define OR1200_FPUOP_ITOF 8'b0000_0100 +`define OR1200_FPUOP_FTOI 8'b0000_0101 +`define OR1200_FPUOP_REM 8'b0000_0110 +`define OR1200_FPUOP_RESERVED 8'b0000_0111 +// FP Compare instructions +`define OR1200_FPCOP_SFEQ 8'b0000_1000 +`define OR1200_FPCOP_SFNE 8'b0000_1001 +`define OR1200_FPCOP_SFGT 8'b0000_1010 +`define OR1200_FPCOP_SFGE 8'b0000_1011 +`define OR1200_FPCOP_SFLT 8'b0000_1100 +`define OR1200_FPCOP_SFLE 8'b0000_1101 + +// +// TAGs for instruction bus +// +`define OR1200_ITAG_IDLE 4'h0 // idle bus +`define OR1200_ITAG_NI 4'h1 // normal insn +`define OR1200_ITAG_BE 4'hb // Bus error exception +`define OR1200_ITAG_PE 4'hc // Page fault exception +`define OR1200_ITAG_TE 4'hd // TLB miss exception + +// +// TAGs for data bus +// +`define OR1200_DTAG_IDLE 4'h0 // idle bus +`define OR1200_DTAG_ND 4'h1 // normal data +`define OR1200_DTAG_AE 4'ha // Alignment exception +`define OR1200_DTAG_BE 4'hb // Bus error exception +`define OR1200_DTAG_PE 4'hc // Page fault exception +`define OR1200_DTAG_TE 4'hd // TLB miss exception + + +////////////////////////////////////////////// +// +// ORBIS32 ISA specifics +// + +// SHROT_OP position in machine word +`define OR1200_SHROTOP_POS 7:6 + +// +// Instruction opcode groups (basic) +// +`define OR1200_OR32_J 6'b000000 +`define OR1200_OR32_JAL 6'b000001 +`define OR1200_OR32_BNF 6'b000011 +`define OR1200_OR32_BF 6'b000100 +`define OR1200_OR32_NOP 6'b000101 +`define OR1200_OR32_MOVHI 6'b000110 +`define OR1200_OR32_MACRC 6'b000110 +`define OR1200_OR32_XSYNC 6'b001000 +`define OR1200_OR32_RFE 6'b001001 +/* */ +`define OR1200_OR32_JR 6'b010001 +`define OR1200_OR32_JALR 6'b010010 +`define OR1200_OR32_MACI 6'b010011 +/* */ +`define OR1200_OR32_LWZ 6'b100001 +`define OR1200_OR32_LBZ 6'b100011 +`define OR1200_OR32_LBS 6'b100100 +`define OR1200_OR32_LHZ 6'b100101 +`define OR1200_OR32_LHS 6'b100110 +`define OR1200_OR32_ADDI 6'b100111 +`define OR1200_OR32_ADDIC 6'b101000 +`define OR1200_OR32_ANDI 6'b101001 +`define OR1200_OR32_ORI 6'b101010 +`define OR1200_OR32_XORI 6'b101011 +`define OR1200_OR32_MULI 6'b101100 +`define OR1200_OR32_MFSPR 6'b101101 +`define OR1200_OR32_SH_ROTI 6'b101110 +`define OR1200_OR32_SFXXI 6'b101111 +/* */ +`define OR1200_OR32_MTSPR 6'b110000 +`define OR1200_OR32_MACMSB 6'b110001 +`define OR1200_OR32_FLOAT 6'b110010 +/* */ +`define OR1200_OR32_SW 6'b110101 +`define OR1200_OR32_SB 6'b110110 +`define OR1200_OR32_SH 6'b110111 +`define OR1200_OR32_ALU 6'b111000 +`define OR1200_OR32_SFXX 6'b111001 +`define OR1200_OR32_CUST5 6'b111100 + +///////////////////////////////////////////////////// +// +// Exceptions +// + +// +// Exception vectors per OR1K architecture: +// 0xPPPPP100 - reset +// 0xPPPPP200 - bus error +// ... etc +// where P represents exception prefix. +// +// Exception vectors can be customized as per +// the following formula: +// 0xPPPPPNVV - exception N +// +// P represents exception prefix +// N represents exception N +// VV represents length of the individual vector space, +// usually it is 8 bits wide and starts with all bits zero +// + +// +// PPPPP and VV parts +// +// Sum of these two defines needs to be 28 +// +`define OR1200_EXCEPT_EPH0_P 20'h00000 +`define OR1200_EXCEPT_EPH1_P 20'hF0000 +`define OR1200_EXCEPT_V 8'h00 + +// +// N part width +// +`define OR1200_EXCEPT_WIDTH 4 + +// +// Definition of exception vectors +// +// To avoid implementation of a certain exception, +// simply comment out corresponding line +// +`define OR1200_EXCEPT_UNUSED `OR1200_EXCEPT_WIDTH'hf +`define OR1200_EXCEPT_TRAP `OR1200_EXCEPT_WIDTH'he +`define OR1200_EXCEPT_FLOAT `OR1200_EXCEPT_WIDTH'hd +`define OR1200_EXCEPT_SYSCALL `OR1200_EXCEPT_WIDTH'hc +`define OR1200_EXCEPT_RANGE `OR1200_EXCEPT_WIDTH'hb +`define OR1200_EXCEPT_ITLBMISS `OR1200_EXCEPT_WIDTH'ha +`define OR1200_EXCEPT_DTLBMISS `OR1200_EXCEPT_WIDTH'h9 +`define OR1200_EXCEPT_INT `OR1200_EXCEPT_WIDTH'h8 +`define OR1200_EXCEPT_ILLEGAL `OR1200_EXCEPT_WIDTH'h7 +`define OR1200_EXCEPT_ALIGN `OR1200_EXCEPT_WIDTH'h6 +`define OR1200_EXCEPT_TICK `OR1200_EXCEPT_WIDTH'h5 +`define OR1200_EXCEPT_IPF `OR1200_EXCEPT_WIDTH'h4 +`define OR1200_EXCEPT_DPF `OR1200_EXCEPT_WIDTH'h3 +`define OR1200_EXCEPT_BUSERR `OR1200_EXCEPT_WIDTH'h2 +`define OR1200_EXCEPT_RESET `OR1200_EXCEPT_WIDTH'h1 +`define OR1200_EXCEPT_NONE `OR1200_EXCEPT_WIDTH'h0 + + +///////////////////////////////////////////////////// +// +// SPR groups +// + +// Bits that define the group +`define OR1200_SPR_GROUP_BITS 15:11 + +// Width of the group bits +`define OR1200_SPR_GROUP_WIDTH 5 + +// Bits that define offset inside the group +`define OR1200_SPR_OFS_BITS 10:0 + +// List of groups +`define OR1200_SPR_GROUP_SYS 5'd00 +`define OR1200_SPR_GROUP_DMMU 5'd01 +`define OR1200_SPR_GROUP_IMMU 5'd02 +`define OR1200_SPR_GROUP_DC 5'd03 +`define OR1200_SPR_GROUP_IC 5'd04 +`define OR1200_SPR_GROUP_MAC 5'd05 +`define OR1200_SPR_GROUP_DU 5'd06 +`define OR1200_SPR_GROUP_PM 5'd08 +`define OR1200_SPR_GROUP_PIC 5'd09 +`define OR1200_SPR_GROUP_TT 5'd10 +`define OR1200_SPR_GROUP_FPU 5'd11 + +///////////////////////////////////////////////////// +// +// System group +// + +// +// System registers +// +`define OR1200_SPR_CFGR 7'd0 +`define OR1200_SPR_RF 6'd32 // 1024 >> 5 +`define OR1200_SPR_NPC 11'd16 +`define OR1200_SPR_SR 11'd17 +`define OR1200_SPR_PPC 11'd18 +`define OR1200_SPR_FPCSR 11'd20 +`define OR1200_SPR_EPCR 11'd32 +`define OR1200_SPR_EEAR 11'd48 +`define OR1200_SPR_ESR 11'd64 + +// +// SR bits +// +`define OR1200_SR_WIDTH 17 +`define OR1200_SR_SM 0 +`define OR1200_SR_TEE 1 +`define OR1200_SR_IEE 2 +`define OR1200_SR_DCE 3 +`define OR1200_SR_ICE 4 +`define OR1200_SR_DME 5 +`define OR1200_SR_IME 6 +`define OR1200_SR_LEE 7 +`define OR1200_SR_CE 8 +`define OR1200_SR_F 9 +`define OR1200_SR_CY 10 // Optional +`define OR1200_SR_OV 11 // Optional +`define OR1200_SR_OVE 12 // Optional +`define OR1200_SR_DSX 13 // Unused +`define OR1200_SR_EPH 14 +`define OR1200_SR_FO 15 +`define OR1200_SR_TED 16 +`define OR1200_SR_CID 31:28 // Unimplemented + +// +// Bits that define offset inside the group +// +`define OR1200_SPROFS_BITS 10:0 + +// +// Default Exception Prefix +// +// 1'b0 - OR1200_EXCEPT_EPH0_P (0x0000_0000) +// 1'b1 - OR1200_EXCEPT_EPH1_P (0xF000_0000) +// +`define OR1200_SR_EPH_DEF 1'b0 + + +// +// FPCSR bits +// +`define OR1200_FPCSR_WIDTH 12 +`define OR1200_FPCSR_FPEE 0 +`define OR1200_FPCSR_RM 2:1 +`define OR1200_FPCSR_OVF 3 +`define OR1200_FPCSR_UNF 4 +`define OR1200_FPCSR_SNF 5 +`define OR1200_FPCSR_QNF 6 +`define OR1200_FPCSR_ZF 7 +`define OR1200_FPCSR_IXF 8 +`define OR1200_FPCSR_IVF 9 +`define OR1200_FPCSR_INF 10 +`define OR1200_FPCSR_DZF 11 +`define OR1200_FPCSR_RES 31:12 + +///////////////////////////////////////////////////// +// +// Power Management (PM) +// + +// Define it if you want PM implemented +//`define OR1200_PM_IMPLEMENTED + +// Bit positions inside PMR (don't change) +`define OR1200_PM_PMR_SDF 3:0 +`define OR1200_PM_PMR_DME 4 +`define OR1200_PM_PMR_SME 5 +`define OR1200_PM_PMR_DCGE 6 +`define OR1200_PM_PMR_UNUSED 31:7 + +// PMR offset inside PM group of registers +`define OR1200_PM_OFS_PMR 11'b0 + +// PM group +`define OR1200_SPRGRP_PM 5'd8 + +// Define if PMR can be read/written at any address inside PM group +`define OR1200_PM_PARTIAL_DECODING + +// Define if reading PMR is allowed +`define OR1200_PM_READREGS + +// Define if unused PMR bits should be zero +`define OR1200_PM_UNUSED_ZERO + + +///////////////////////////////////////////////////// +// +// Debug Unit (DU) +// + +// Define it if you want DU implemented +`define OR1200_DU_IMPLEMENTED + +// +// Define if you want HW Breakpoints +// (if HW breakpoints are not implemented +// only default software trapping is +// possible with l.trap insn - this is +// however already enough for use +// with or32 gdb) +// +//`define OR1200_DU_HWBKPTS + +// Number of DVR/DCR pairs if HW breakpoints enabled +// Comment / uncomment DU_DVRn / DU_DCRn pairs bellow according to this number ! +// DU_DVR0..DU_DVR7 should be uncommented for 8 DU_DVRDCR_PAIRS +`define OR1200_DU_DVRDCR_PAIRS 8 + +// Define if you want trace buffer +// (for now only available for Xilinx Virtex FPGAs) +//`define OR1200_DU_TB_IMPLEMENTED + + +// +// Address offsets of DU registers inside DU group +// +// To not implement a register, doq not define its address +// +`ifdef OR1200_DU_HWBKPTS +`define OR1200_DU_DVR0 11'd0 +`define OR1200_DU_DVR1 11'd1 +`define OR1200_DU_DVR2 11'd2 +`define OR1200_DU_DVR3 11'd3 +`define OR1200_DU_DVR4 11'd4 +`define OR1200_DU_DVR5 11'd5 +`define OR1200_DU_DVR6 11'd6 +`define OR1200_DU_DVR7 11'd7 +`define OR1200_DU_DCR0 11'd8 +`define OR1200_DU_DCR1 11'd9 +`define OR1200_DU_DCR2 11'd10 +`define OR1200_DU_DCR3 11'd11 +`define OR1200_DU_DCR4 11'd12 +`define OR1200_DU_DCR5 11'd13 +`define OR1200_DU_DCR6 11'd14 +`define OR1200_DU_DCR7 11'd15 +`endif +`define OR1200_DU_DMR1 11'd16 +`ifdef OR1200_DU_HWBKPTS +`define OR1200_DU_DMR2 11'd17 +`define OR1200_DU_DWCR0 11'd18 +`define OR1200_DU_DWCR1 11'd19 +`endif +`define OR1200_DU_DSR 11'd20 +`define OR1200_DU_DRR 11'd21 +`ifdef OR1200_DU_TB_IMPLEMENTED +`define OR1200_DU_TBADR 11'h0ff +`define OR1200_DU_TBIA 11'h1?? +`define OR1200_DU_TBIM 11'h2?? +`define OR1200_DU_TBAR 11'h3?? +`define OR1200_DU_TBTS 11'h4?? +`endif + +// Position of offset bits inside SPR address +`define OR1200_DUOFS_BITS 10:0 + +// DCR bits +`define OR1200_DU_DCR_DP 0 +`define OR1200_DU_DCR_CC 3:1 +`define OR1200_DU_DCR_SC 4 +`define OR1200_DU_DCR_CT 7:5 + +// DMR1 bits +`define OR1200_DU_DMR1_CW0 1:0 +`define OR1200_DU_DMR1_CW1 3:2 +`define OR1200_DU_DMR1_CW2 5:4 +`define OR1200_DU_DMR1_CW3 7:6 +`define OR1200_DU_DMR1_CW4 9:8 +`define OR1200_DU_DMR1_CW5 11:10 +`define OR1200_DU_DMR1_CW6 13:12 +`define OR1200_DU_DMR1_CW7 15:14 +`define OR1200_DU_DMR1_CW8 17:16 +`define OR1200_DU_DMR1_CW9 19:18 +`define OR1200_DU_DMR1_CW10 21:20 +`define OR1200_DU_DMR1_ST 22 +`define OR1200_DU_DMR1_BT 23 +`define OR1200_DU_DMR1_DXFW 24 +`define OR1200_DU_DMR1_ETE 25 + +// DMR2 bits +`define OR1200_DU_DMR2_WCE0 0 +`define OR1200_DU_DMR2_WCE1 1 +`define OR1200_DU_DMR2_AWTC 12:2 +`define OR1200_DU_DMR2_WGB 23:13 + +// DWCR bits +`define OR1200_DU_DWCR_COUNT 15:0 +`define OR1200_DU_DWCR_MATCH 31:16 + +// DSR bits +`define OR1200_DU_DSR_WIDTH 14 +`define OR1200_DU_DSR_RSTE 0 +`define OR1200_DU_DSR_BUSEE 1 +`define OR1200_DU_DSR_DPFE 2 +`define OR1200_DU_DSR_IPFE 3 +`define OR1200_DU_DSR_TTE 4 +`define OR1200_DU_DSR_AE 5 +`define OR1200_DU_DSR_IIE 6 +`define OR1200_DU_DSR_IE 7 +`define OR1200_DU_DSR_DME 8 +`define OR1200_DU_DSR_IME 9 +`define OR1200_DU_DSR_RE 10 +`define OR1200_DU_DSR_SCE 11 +`define OR1200_DU_DSR_FPE 12 +`define OR1200_DU_DSR_TE 13 + +// DRR bits +`define OR1200_DU_DRR_RSTE 0 +`define OR1200_DU_DRR_BUSEE 1 +`define OR1200_DU_DRR_DPFE 2 +`define OR1200_DU_DRR_IPFE 3 +`define OR1200_DU_DRR_TTE 4 +`define OR1200_DU_DRR_AE 5 +`define OR1200_DU_DRR_IIE 6 +`define OR1200_DU_DRR_IE 7 +`define OR1200_DU_DRR_DME 8 +`define OR1200_DU_DRR_IME 9 +`define OR1200_DU_DRR_RE 10 +`define OR1200_DU_DRR_SCE 11 +`define OR1200_DU_DRR_FPE 12 +`define OR1200_DU_DRR_TE 13 + +// Define if reading DU regs is allowed +`define OR1200_DU_READREGS + +// Define if unused DU registers bits should be zero +`define OR1200_DU_UNUSED_ZERO + +// Define if IF/LSU status is not needed by devel i/f +`define OR1200_DU_STATUS_UNIMPLEMENTED + +///////////////////////////////////////////////////// +// +// Programmable Interrupt Controller (PIC) +// + +// Define it if you want PIC implemented +`define OR1200_PIC_IMPLEMENTED + +// Define number of interrupt inputs (2-31) +`define OR1200_PIC_INTS 20 + +// Address offsets of PIC registers inside PIC group +`define OR1200_PIC_OFS_PICMR 2'd0 +`define OR1200_PIC_OFS_PICSR 2'd2 + +// Position of offset bits inside SPR address +`define OR1200_PICOFS_BITS 1:0 + +// Define if you want these PIC registers to be implemented +`define OR1200_PIC_PICMR +`define OR1200_PIC_PICSR + +// Define if reading PIC registers is allowed +`define OR1200_PIC_READREGS + +// Define if unused PIC register bits should be zero +`define OR1200_PIC_UNUSED_ZERO + + +///////////////////////////////////////////////////// +// +// Tick Timer (TT) +// + +// Define it if you want TT implemented +`define OR1200_TT_IMPLEMENTED + +// Address offsets of TT registers inside TT group +`define OR1200_TT_OFS_TTMR 1'd0 +`define OR1200_TT_OFS_TTCR 1'd1 + +// Position of offset bits inside SPR group +`define OR1200_TTOFS_BITS 0 + +// Define if you want these TT registers to be implemented +`define OR1200_TT_TTMR +`define OR1200_TT_TTCR + +// TTMR bits +`define OR1200_TT_TTMR_TP 27:0 +`define OR1200_TT_TTMR_IP 28 +`define OR1200_TT_TTMR_IE 29 +`define OR1200_TT_TTMR_M 31:30 + +// Define if reading TT registers is allowed +`define OR1200_TT_READREGS + + +////////////////////////////////////////////// +// +// MAC +// +`define OR1200_MAC_ADDR 0 // MACLO 0xxxxxxxx1, MACHI 0xxxxxxxx0 +`define OR1200_MAC_SPR_WE // Define if MACLO/MACHI are SPR writable + +// +// Shift {MACHI,MACLO} into destination register when executing l.macrc +// +// According to architecture manual there is no shift, so default value is 0. +// However the implementation has deviated in this from the arch manual and had +// hard coded shift by 28 bits which is a useful optimization for MP3 decoding +// (if using libmad fixed point library). Shifts are no longer default setup, +// but if you need to remain backward compatible, define your shift bits, which +// were normally +// dest_GPR = {MACHI,MACLO}[59:28] +`define OR1200_MAC_SHIFTBY 0 // 0 = According to arch manual, 28 = obsolete backward compatibility + + +////////////////////////////////////////////// +// +// Data MMU (DMMU) +// + +// +// Address that selects between TLB TR and MR +// +`define OR1200_DTLB_TM_ADDR 7 + +// +// DTLBMR fields +// +`define OR1200_DTLBMR_V_BITS 0 +`define OR1200_DTLBMR_CID_BITS 4:1 +`define OR1200_DTLBMR_RES_BITS 11:5 +`define OR1200_DTLBMR_VPN_BITS 31:13 + +// +// DTLBTR fields +// +`define OR1200_DTLBTR_CC_BITS 0 +`define OR1200_DTLBTR_CI_BITS 1 +`define OR1200_DTLBTR_WBC_BITS 2 +`define OR1200_DTLBTR_WOM_BITS 3 +`define OR1200_DTLBTR_A_BITS 4 +`define OR1200_DTLBTR_D_BITS 5 +`define OR1200_DTLBTR_URE_BITS 6 +`define OR1200_DTLBTR_UWE_BITS 7 +`define OR1200_DTLBTR_SRE_BITS 8 +`define OR1200_DTLBTR_SWE_BITS 9 +`define OR1200_DTLBTR_RES_BITS 11:10 +`define OR1200_DTLBTR_PPN_BITS 31:13 + +// +// DTLB configuration +// +`define OR1200_DMMU_PS 13 // 13 for 8KB page size +`define OR1200_DTLB_INDXW 6 // 6 for 64 entry DTLB 7 for 128 entries +`define OR1200_DTLB_INDXL `OR1200_DMMU_PS // 13 13 +`define OR1200_DTLB_INDXH `OR1200_DMMU_PS+`OR1200_DTLB_INDXW-1 // 18 19 +`define OR1200_DTLB_INDX `OR1200_DTLB_INDXH:`OR1200_DTLB_INDXL // 18:13 19:13 +`define OR1200_DTLB_TAGW 32-`OR1200_DTLB_INDXW-`OR1200_DMMU_PS // 13 12 +`define OR1200_DTLB_TAGL `OR1200_DTLB_INDXH+1 // 19 20 +`define OR1200_DTLB_TAG 31:`OR1200_DTLB_TAGL // 31:19 31:20 +`define OR1200_DTLBMRW `OR1200_DTLB_TAGW+1 // +1 because of V bit +`define OR1200_DTLBTRW 32-`OR1200_DMMU_PS+5 // +5 because of protection bits and CI + +// +// Cache inhibit while DMMU is not enabled/implemented +// +// cache inhibited 0GB-4GB 1'b1 +// cache inhibited 0GB-2GB !dcpu_adr_i[31] +// cache inhibited 0GB-1GB 2GB-3GB !dcpu_adr_i[30] +// cache inhibited 1GB-2GB 3GB-4GB dcpu_adr_i[30] +// cache inhibited 2GB-4GB (default) dcpu_adr_i[31] +// cached 0GB-4GB 1'b0 +// +`define OR1200_DMMU_CI dcpu_adr_i[31] + + +////////////////////////////////////////////// +// +// Insn MMU (IMMU) +// + +// +// Address that selects between TLB TR and MR +// +`define OR1200_ITLB_TM_ADDR 7 + +// +// ITLBMR fields +// +`define OR1200_ITLBMR_V_BITS 0 +`define OR1200_ITLBMR_CID_BITS 4:1 +`define OR1200_ITLBMR_RES_BITS 11:5 +`define OR1200_ITLBMR_VPN_BITS 31:13 + +// +// ITLBTR fields +// +`define OR1200_ITLBTR_CC_BITS 0 +`define OR1200_ITLBTR_CI_BITS 1 +`define OR1200_ITLBTR_WBC_BITS 2 +`define OR1200_ITLBTR_WOM_BITS 3 +`define OR1200_ITLBTR_A_BITS 4 +`define OR1200_ITLBTR_D_BITS 5 +`define OR1200_ITLBTR_SXE_BITS 6 +`define OR1200_ITLBTR_UXE_BITS 7 +`define OR1200_ITLBTR_RES_BITS 11:8 +`define OR1200_ITLBTR_PPN_BITS 31:13 + +// +// ITLB configuration +// +`define OR1200_IMMU_PS 13 // 13 for 8KB page size +`define OR1200_ITLB_INDXW 6 // 6 for 64 entry ITLB 7 for 128 entries +`define OR1200_ITLB_INDXL `OR1200_IMMU_PS // 13 13 +`define OR1200_ITLB_INDXH `OR1200_IMMU_PS+`OR1200_ITLB_INDXW-1 // 18 19 +`define OR1200_ITLB_INDX `OR1200_ITLB_INDXH:`OR1200_ITLB_INDXL // 18:13 19:13 +`define OR1200_ITLB_TAGW 32-`OR1200_ITLB_INDXW-`OR1200_IMMU_PS // 13 12 +`define OR1200_ITLB_TAGL `OR1200_ITLB_INDXH+1 // 19 20 +`define OR1200_ITLB_TAG 31:`OR1200_ITLB_TAGL // 31:19 31:20 +`define OR1200_ITLBMRW `OR1200_ITLB_TAGW+1 // +1 because of V bit +`define OR1200_ITLBTRW 32-`OR1200_IMMU_PS+3 // +3 because of protection bits and CI + +// +// Cache inhibit while IMMU is not enabled/implemented +// Note: all combinations that use icpu_adr_i cause async loop +// +// cache inhibited 0GB-4GB 1'b1 +// cache inhibited 0GB-2GB !icpu_adr_i[31] +// cache inhibited 0GB-1GB 2GB-3GB !icpu_adr_i[30] +// cache inhibited 1GB-2GB 3GB-4GB icpu_adr_i[30] +// cache inhibited 2GB-4GB (default) icpu_adr_i[31] +// cached 0GB-4GB 1'b0 +// +`define OR1200_IMMU_CI 1'b0 + + +///////////////////////////////////////////////// +// +// Insn cache (IC) +// + +// 4 for 16 byte line, 5 for 32 byte lines. +`ifdef OR1200_IC_1W_32KB + `define OR1200_ICLS 5 +`else + `define OR1200_ICLS 4 +`endif + +// +// IC configurations +// +`ifdef OR1200_IC_1W_512B +`define OR1200_ICSIZE 9 // 512 +`define OR1200_ICINDX `OR1200_ICSIZE-2 // 7 +`define OR1200_ICINDXH `OR1200_ICSIZE-1 // 8 +`define OR1200_ICTAGL `OR1200_ICINDXH+1 // 9 +`define OR1200_ICTAG `OR1200_ICSIZE-`OR1200_ICLS // 5 +`define OR1200_ICTAG_W 24 +`endif +`ifdef OR1200_IC_1W_4KB +`define OR1200_ICSIZE 12 // 4096 +`define OR1200_ICINDX `OR1200_ICSIZE-2 // 10 +`define OR1200_ICINDXH `OR1200_ICSIZE-1 // 11 +`define OR1200_ICTAGL `OR1200_ICINDXH+1 // 12 +`define OR1200_ICTAG `OR1200_ICSIZE-`OR1200_ICLS // 8 +`define OR1200_ICTAG_W 21 +`endif +`ifdef OR1200_IC_1W_8KB +`define OR1200_ICSIZE 13 // 8192 +`define OR1200_ICINDX `OR1200_ICSIZE-2 // 11 +`define OR1200_ICINDXH `OR1200_ICSIZE-1 // 12 +`define OR1200_ICTAGL `OR1200_ICINDXH+1 // 13 +`define OR1200_ICTAG `OR1200_ICSIZE-`OR1200_ICLS // 9 +`define OR1200_ICTAG_W 20 +`endif +`ifdef OR1200_IC_1W_16KB +`define OR1200_ICSIZE 14 // 16384 +`define OR1200_ICINDX `OR1200_ICSIZE-2 // 12 +`define OR1200_ICINDXH `OR1200_ICSIZE-1 // 13 +`define OR1200_ICTAGL `OR1200_ICINDXH+1 // 14 +`define OR1200_ICTAG `OR1200_ICSIZE-`OR1200_ICLS // 10 +`define OR1200_ICTAG_W 19 +`endif +`ifdef OR1200_IC_1W_32KB +`define OR1200_ICSIZE 15 // 32768 +`define OR1200_ICINDX `OR1200_ICSIZE-2 // 13 +`define OR1200_ICINDXH `OR1200_ICSIZE-1 // 14 +`define OR1200_ICTAGL `OR1200_ICINDXH+1 // 14 +`define OR1200_ICTAG `OR1200_ICSIZE-`OR1200_ICLS // 10 +`define OR1200_ICTAG_W 18 +`endif + + +///////////////////////////////////////////////// +// +// Data cache (DC) +// + +// 4 for 16 bytes, 5 for 32 bytes +`ifdef OR1200_DC_1W_32KB + `define OR1200_DCLS 5 +`else + `define OR1200_DCLS 4 +`endif + +// Define to enable default behavior of cache as write through +// Turning this off enabled write back statergy +// +`define OR1200_DC_WRITETHROUGH + +// Define to enable stores from the stack not doing writethrough. +// EXPERIMENTAL +//`define OR1200_DC_NOSTACKWRITETHROUGH + +// Data cache SPR definitions +`define OR1200_SPRGRP_DC_ADR_WIDTH 3 +// Data cache group SPR addresses +`define OR1200_SPRGRP_DC_DCCR 3'd0 // Not implemented +`define OR1200_SPRGRP_DC_DCBPR 3'd1 // Not implemented +`define OR1200_SPRGRP_DC_DCBFR 3'd2 +`define OR1200_SPRGRP_DC_DCBIR 3'd3 +`define OR1200_SPRGRP_DC_DCBWR 3'd4 // Not implemented +`define OR1200_SPRGRP_DC_DCBLR 3'd5 // Not implemented + +// +// DC configurations +// +`ifdef OR1200_DC_1W_4KB +`define OR1200_DCSIZE 12 // 4096 +`define OR1200_DCINDX `OR1200_DCSIZE-2 // 10 +`define OR1200_DCINDXH `OR1200_DCSIZE-1 // 11 +`define OR1200_DCTAGL `OR1200_DCINDXH+1 // 12 +`define OR1200_DCTAG `OR1200_DCSIZE-`OR1200_DCLS // 8 +`define OR1200_DCTAG_W 21 +`endif +`ifdef OR1200_DC_1W_8KB +`define OR1200_DCSIZE 13 // 8192 +`define OR1200_DCINDX `OR1200_DCSIZE-2 // 11 +`define OR1200_DCINDXH `OR1200_DCSIZE-1 // 12 +`define OR1200_DCTAGL `OR1200_DCINDXH+1 // 13 +`define OR1200_DCTAG `OR1200_DCSIZE-`OR1200_DCLS // 9 +`define OR1200_DCTAG_W 20 +`endif +`ifdef OR1200_DC_1W_16KB +`define OR1200_DCSIZE 14 // 16384 +`define OR1200_DCINDX `OR1200_DCSIZE-2 // 12 +`define OR1200_DCINDXH `OR1200_DCSIZE-1 // 13 +`define OR1200_DCTAGL `OR1200_DCINDXH+1 // 14 +`define OR1200_DCTAG `OR1200_DCSIZE-`OR1200_DCLS // 10 +`define OR1200_DCTAG_W 19 +`endif +`ifdef OR1200_DC_1W_32KB +`define OR1200_DCSIZE 15 // 32768 +`define OR1200_DCINDX `OR1200_DCSIZE-2 // 13 +`define OR1200_DCINDXH `OR1200_DCSIZE-1 // 14 +`define OR1200_DCTAGL `OR1200_DCINDXH+1 // 15 +`define OR1200_DCTAG `OR1200_DCSIZE-`OR1200_DCLS // 10 +`define OR1200_DCTAG_W 18 +`endif + + +///////////////////////////////////////////////// +// +// Store buffer (SB) +// + +// +// Store buffer +// +// It will improve performance by "caching" CPU stores +// using store buffer. This is most important for function +// prologues because DC can only work in write though mode +// and all stores would have to complete external WB writes +// to memory. +// Store buffer is between DC and data BIU. +// All stores will be stored into store buffer and immediately +// completed by the CPU, even though actual external writes +// will be performed later. As a consequence store buffer masks +// all data bus errors related to stores (data bus errors +// related to loads are delivered normally). +// All pending CPU loads will wait until store buffer is empty to +// ensure strict memory model. Right now this is necessary because +// we don't make destinction between cached and cache inhibited +// address space, so we simply empty store buffer until loads +// can begin. +// +// It makes design a bit bigger, depending what is the number of +// entries in SB FIFO. Number of entries can be changed further +// down. +// +//`define OR1200_SB_IMPLEMENTED + +// +// Number of store buffer entries +// +// Verified number of entries are 4 and 8 entries +// (2 and 3 for OR1200_SB_LOG). OR1200_SB_ENTRIES must +// always match 2**OR1200_SB_LOG. +// To disable store buffer, undefine +// OR1200_SB_IMPLEMENTED. +// +`define OR1200_SB_LOG 2 // 2 or 3 +`define OR1200_SB_ENTRIES 4 // 4 or 8 + + +///////////////////////////////////////////////// +// +// Quick Embedded Memory (QMEM) +// + +// +// Quick Embedded Memory +// +// Instantiation of dedicated insn/data memory (RAM or ROM). +// Insn fetch has effective throughput 1insn / clock cycle. +// Data load takes two clock cycles / access, data store +// takes 1 clock cycle / access (if there is no insn fetch)). +// Memory instantiation is shared between insn and data, +// meaning if insn fetch are performed, data load/store +// performance will be lower. +// +// Main reason for QMEM is to put some time critical functions +// into this memory and to have predictable and fast access +// to these functions. (soft fpu, context switch, exception +// handlers, stack, etc) +// +// It makes design a bit bigger and slower. QMEM sits behind +// IMMU/DMMU so all addresses are physical (so the MMUs can be +// used with QMEM and QMEM is seen by the CPU just like any other +// memory in the system). IC/DC are sitting behind QMEM so the +// whole design timing might be worse with QMEM implemented. +// +//`define OR1200_QMEM_IMPLEMENTED + +// +// Base address and mask of QMEM +// +// Base address defines first address of QMEM. Mask defines +// QMEM range in address space. Actual size of QMEM is however +// determined with instantiated RAM/ROM. However bigger +// mask will reserve more address space for QMEM, but also +// make design faster, while more tight mask will take +// less address space but also make design slower. If +// instantiated RAM/ROM is smaller than space reserved with +// the mask, instatiated RAM/ROM will also be shadowed +// at higher addresses in reserved space. +// +`define OR1200_QMEM_IADDR 32'h0080_0000 +`define OR1200_QMEM_IMASK 32'hfff0_0000 // Max QMEM size 1MB +`define OR1200_QMEM_DADDR 32'h0080_0000 +`define OR1200_QMEM_DMASK 32'hfff0_0000 // Max QMEM size 1MB + +// +// QMEM interface byte-select capability +// +// To enable qmem_sel* ports, define this macro. +// +//`define OR1200_QMEM_BSEL + +// +// QMEM interface acknowledge +// +// To enable qmem_ack port, define this macro. +// +//`define OR1200_QMEM_ACK + +///////////////////////////////////////////////////// +// +// VR, UPR and Configuration Registers +// +// +// VR, UPR and configuration registers are optional. If +// implemented, operating system can automatically figure +// out how to use the processor because it knows +// what units are available in the processor and how they +// are configured. +// +// This section must be last in or1200_defines.v file so +// that all units are already configured and thus +// configuration registers are properly set. +// + +// Define if you want configuration registers implemented +`define OR1200_CFGR_IMPLEMENTED + +// Define if you want full address decode inside SYS group +`define OR1200_SYS_FULL_DECODE + +// Offsets of VR, UPR and CFGR registers +`define OR1200_SPRGRP_SYS_VR 4'h0 +`define OR1200_SPRGRP_SYS_UPR 4'h1 +`define OR1200_SPRGRP_SYS_CPUCFGR 4'h2 +`define OR1200_SPRGRP_SYS_DMMUCFGR 4'h3 +`define OR1200_SPRGRP_SYS_IMMUCFGR 4'h4 +`define OR1200_SPRGRP_SYS_DCCFGR 4'h5 +`define OR1200_SPRGRP_SYS_ICCFGR 4'h6 +`define OR1200_SPRGRP_SYS_DCFGR 4'h7 + +// VR fields +`define OR1200_VR_REV_BITS 5:0 +`define OR1200_VR_RES1_BITS 15:6 +`define OR1200_VR_CFG_BITS 23:16 +`define OR1200_VR_VER_BITS 31:24 + +// VR values +`define OR1200_VR_REV 6'h08 +`define OR1200_VR_RES1 10'h000 +`define OR1200_VR_CFG 8'h00 +`define OR1200_VR_VER 8'h12 + +// UPR fields +`define OR1200_UPR_UP_BITS 0 +`define OR1200_UPR_DCP_BITS 1 +`define OR1200_UPR_ICP_BITS 2 +`define OR1200_UPR_DMP_BITS 3 +`define OR1200_UPR_IMP_BITS 4 +`define OR1200_UPR_MP_BITS 5 +`define OR1200_UPR_DUP_BITS 6 +`define OR1200_UPR_PCUP_BITS 7 +`define OR1200_UPR_PMP_BITS 8 +`define OR1200_UPR_PICP_BITS 9 +`define OR1200_UPR_TTP_BITS 10 +`define OR1200_UPR_FPP_BITS 11 +`define OR1200_UPR_RES1_BITS 23:12 +`define OR1200_UPR_CUP_BITS 31:24 + +// UPR values +`define OR1200_UPR_UP 1'b1 +`ifdef OR1200_NO_DC +`define OR1200_UPR_DCP 1'b0 +`else +`define OR1200_UPR_DCP 1'b1 +`endif +`ifdef OR1200_NO_IC +`define OR1200_UPR_ICP 1'b0 +`else +`define OR1200_UPR_ICP 1'b1 +`endif +`ifdef OR1200_NO_DMMU +`define OR1200_UPR_DMP 1'b0 +`else +`define OR1200_UPR_DMP 1'b1 +`endif +`ifdef OR1200_NO_IMMU +`define OR1200_UPR_IMP 1'b0 +`else +`define OR1200_UPR_IMP 1'b1 +`endif +`ifdef OR1200_MAC_IMPLEMENTED +`define OR1200_UPR_MP 1'b1 +`else +`define OR1200_UPR_MP 1'b0 +`endif +`ifdef OR1200_DU_IMPLEMENTED +`define OR1200_UPR_DUP 1'b1 +`else +`define OR1200_UPR_DUP 1'b0 +`endif +`define OR1200_UPR_PCUP 1'b0 // Performance counters not present +`ifdef OR1200_PM_IMPLEMENTED +`define OR1200_UPR_PMP 1'b1 +`else +`define OR1200_UPR_PMP 1'b0 +`endif +`ifdef OR1200_PIC_IMPLEMENTED +`define OR1200_UPR_PICP 1'b1 +`else +`define OR1200_UPR_PICP 1'b0 +`endif +`ifdef OR1200_TT_IMPLEMENTED +`define OR1200_UPR_TTP 1'b1 +`else +`define OR1200_UPR_TTP 1'b0 +`endif +`ifdef OR1200_FPU_IMPLEMENTED +`define OR1200_UPR_FPP 1'b1 +`else +`define OR1200_UPR_FPP 1'b0 +`endif +`define OR1200_UPR_RES1 12'h000 +`define OR1200_UPR_CUP 8'h00 + +// CPUCFGR fields +`define OR1200_CPUCFGR_NSGF_BITS 3:0 +`define OR1200_CPUCFGR_HGF_BITS 4 +`define OR1200_CPUCFGR_OB32S_BITS 5 +`define OR1200_CPUCFGR_OB64S_BITS 6 +`define OR1200_CPUCFGR_OF32S_BITS 7 +`define OR1200_CPUCFGR_OF64S_BITS 8 +`define OR1200_CPUCFGR_OV64S_BITS 9 +`define OR1200_CPUCFGR_RES1_BITS 31:10 + +// CPUCFGR values +`define OR1200_CPUCFGR_NSGF 4'h0 +`ifdef OR1200_RFRAM_16REG + `define OR1200_CPUCFGR_HGF 1'b1 +`else + `define OR1200_CPUCFGR_HGF 1'b0 +`endif +`define OR1200_CPUCFGR_OB32S 1'b1 +`define OR1200_CPUCFGR_OB64S 1'b0 +`ifdef OR1200_FPU_IMPLEMENTED + `define OR1200_CPUCFGR_OF32S 1'b1 +`else + `define OR1200_CPUCFGR_OF32S 1'b0 +`endif + +`define OR1200_CPUCFGR_OF64S 1'b0 +`define OR1200_CPUCFGR_OV64S 1'b0 +`define OR1200_CPUCFGR_RES1 22'h000000 + +// DMMUCFGR fields +`define OR1200_DMMUCFGR_NTW_BITS 1:0 +`define OR1200_DMMUCFGR_NTS_BITS 4:2 +`define OR1200_DMMUCFGR_NAE_BITS 7:5 +`define OR1200_DMMUCFGR_CRI_BITS 8 +`define OR1200_DMMUCFGR_PRI_BITS 9 +`define OR1200_DMMUCFGR_TEIRI_BITS 10 +`define OR1200_DMMUCFGR_HTR_BITS 11 +`define OR1200_DMMUCFGR_RES1_BITS 31:12 + +// DMMUCFGR values +`ifdef OR1200_NO_DMMU +`define OR1200_DMMUCFGR_NTW 2'h0 // Irrelevant +`define OR1200_DMMUCFGR_NTS 3'h0 // Irrelevant +`define OR1200_DMMUCFGR_NAE 3'h0 // Irrelevant +`define OR1200_DMMUCFGR_CRI 1'b0 // Irrelevant +`define OR1200_DMMUCFGR_PRI 1'b0 // Irrelevant +`define OR1200_DMMUCFGR_TEIRI 1'b0 // Irrelevant +`define OR1200_DMMUCFGR_HTR 1'b0 // Irrelevant +`define OR1200_DMMUCFGR_RES1 20'h00000 +`else +`define OR1200_DMMUCFGR_NTW 2'h0 // 1 TLB way +`define OR1200_DMMUCFGR_NTS 3'h`OR1200_DTLB_INDXW // Num TLB sets +`define OR1200_DMMUCFGR_NAE 3'h0 // No ATB entries +`define OR1200_DMMUCFGR_CRI 1'b0 // No control register +`define OR1200_DMMUCFGR_PRI 1'b0 // No protection reg +`define OR1200_DMMUCFGR_TEIRI 1'b0 // TLB entry inv reg NOT impl. +`define OR1200_DMMUCFGR_HTR 1'b0 // No HW TLB reload +`define OR1200_DMMUCFGR_RES1 20'h00000 +`endif + +// IMMUCFGR fields +`define OR1200_IMMUCFGR_NTW_BITS 1:0 +`define OR1200_IMMUCFGR_NTS_BITS 4:2 +`define OR1200_IMMUCFGR_NAE_BITS 7:5 +`define OR1200_IMMUCFGR_CRI_BITS 8 +`define OR1200_IMMUCFGR_PRI_BITS 9 +`define OR1200_IMMUCFGR_TEIRI_BITS 10 +`define OR1200_IMMUCFGR_HTR_BITS 11 +`define OR1200_IMMUCFGR_RES1_BITS 31:12 + +// IMMUCFGR values +`ifdef OR1200_NO_IMMU +`define OR1200_IMMUCFGR_NTW 2'h0 // Irrelevant +`define OR1200_IMMUCFGR_NTS 3'h0 // Irrelevant +`define OR1200_IMMUCFGR_NAE 3'h0 // Irrelevant +`define OR1200_IMMUCFGR_CRI 1'b0 // Irrelevant +`define OR1200_IMMUCFGR_PRI 1'b0 // Irrelevant +`define OR1200_IMMUCFGR_TEIRI 1'b0 // Irrelevant +`define OR1200_IMMUCFGR_HTR 1'b0 // Irrelevant +`define OR1200_IMMUCFGR_RES1 20'h00000 +`else +`define OR1200_IMMUCFGR_NTW 2'h0 // 1 TLB way +`define OR1200_IMMUCFGR_NTS 3'h`OR1200_ITLB_INDXW // Num TLB sets +`define OR1200_IMMUCFGR_NAE 3'h0 // No ATB entry +`define OR1200_IMMUCFGR_CRI 1'b0 // No control reg +`define OR1200_IMMUCFGR_PRI 1'b0 // No protection reg +`define OR1200_IMMUCFGR_TEIRI 1'b0 // TLB entry inv reg NOT impl +`define OR1200_IMMUCFGR_HTR 1'b0 // No HW TLB reload +`define OR1200_IMMUCFGR_RES1 20'h00000 +`endif + +// DCCFGR fields +`define OR1200_DCCFGR_NCW_BITS 2:0 +`define OR1200_DCCFGR_NCS_BITS 6:3 +`define OR1200_DCCFGR_CBS_BITS 7 +`define OR1200_DCCFGR_CWS_BITS 8 +`define OR1200_DCCFGR_CCRI_BITS 9 +`define OR1200_DCCFGR_CBIRI_BITS 10 +`define OR1200_DCCFGR_CBPRI_BITS 11 +`define OR1200_DCCFGR_CBLRI_BITS 12 +`define OR1200_DCCFGR_CBFRI_BITS 13 +`define OR1200_DCCFGR_CBWBRI_BITS 14 +`define OR1200_DCCFGR_RES1_BITS 31:15 + +// DCCFGR values +`ifdef OR1200_NO_DC +`define OR1200_DCCFGR_NCW 3'h0 // Irrelevant +`define OR1200_DCCFGR_NCS 4'h0 // Irrelevant +`define OR1200_DCCFGR_CBS 1'b0 // Irrelevant +`define OR1200_DCCFGR_CWS 1'b0 // Irrelevant +`define OR1200_DCCFGR_CCRI 1'b0 // Irrelevant +`define OR1200_DCCFGR_CBIRI 1'b0 // Irrelevant +`define OR1200_DCCFGR_CBPRI 1'b0 // Irrelevant +`define OR1200_DCCFGR_CBLRI 1'b0 // Irrelevant +`define OR1200_DCCFGR_CBFRI 1'b0 // Irrelevant +`define OR1200_DCCFGR_CBWBRI 1'b0 // Irrelevant +`define OR1200_DCCFGR_RES1 17'h00000 +`else +`define OR1200_DCCFGR_NCW 3'h0 // 1 cache way +`define OR1200_DCCFGR_NCS (`OR1200_DCTAG) // Num cache sets +`define OR1200_DCCFGR_CBS `OR1200_DCLS==4 ? 1'b0 : 1'b1 // 16 byte cache block +`ifdef OR1200_DC_WRITETHROUGH + `define OR1200_DCCFGR_CWS 1'b0 // Write-through strategy +`else + `define OR1200_DCCFGR_CWS 1'b1 // Write-back strategy +`endif +`define OR1200_DCCFGR_CCRI 1'b1 // Cache control reg impl. +`define OR1200_DCCFGR_CBIRI 1'b1 // Cache block inv reg impl. +`define OR1200_DCCFGR_CBPRI 1'b0 // Cache block prefetch reg not impl. +`define OR1200_DCCFGR_CBLRI 1'b0 // Cache block lock reg not impl. +`define OR1200_DCCFGR_CBFRI 1'b1 // Cache block flush reg impl. +`ifdef OR1200_DC_WRITETHROUGH + `define OR1200_DCCFGR_CBWBRI 1'b0 // Cache block WB reg not impl. +`else + `define OR1200_DCCFGR_CBWBRI 1'b1 // Cache block WB reg impl. +`endif +`define OR1200_DCCFGR_RES1 17'h00000 +`endif + +// ICCFGR fields +`define OR1200_ICCFGR_NCW_BITS 2:0 +`define OR1200_ICCFGR_NCS_BITS 6:3 +`define OR1200_ICCFGR_CBS_BITS 7 +`define OR1200_ICCFGR_CWS_BITS 8 +`define OR1200_ICCFGR_CCRI_BITS 9 +`define OR1200_ICCFGR_CBIRI_BITS 10 +`define OR1200_ICCFGR_CBPRI_BITS 11 +`define OR1200_ICCFGR_CBLRI_BITS 12 +`define OR1200_ICCFGR_CBFRI_BITS 13 +`define OR1200_ICCFGR_CBWBRI_BITS 14 +`define OR1200_ICCFGR_RES1_BITS 31:15 + +// ICCFGR values +`ifdef OR1200_NO_IC +`define OR1200_ICCFGR_NCW 3'h0 // Irrelevant +`define OR1200_ICCFGR_NCS 4'h0 // Irrelevant +`define OR1200_ICCFGR_CBS 1'b0 // Irrelevant +`define OR1200_ICCFGR_CWS 1'b0 // Irrelevant +`define OR1200_ICCFGR_CCRI 1'b0 // Irrelevant +`define OR1200_ICCFGR_CBIRI 1'b0 // Irrelevant +`define OR1200_ICCFGR_CBPRI 1'b0 // Irrelevant +`define OR1200_ICCFGR_CBLRI 1'b0 // Irrelevant +`define OR1200_ICCFGR_CBFRI 1'b0 // Irrelevant +`define OR1200_ICCFGR_CBWBRI 1'b0 // Irrelevant +`define OR1200_ICCFGR_RES1 17'h00000 +`else +`define OR1200_ICCFGR_NCW 3'h0 // 1 cache way +`define OR1200_ICCFGR_NCS (`OR1200_ICTAG) // Num cache sets +`define OR1200_ICCFGR_CBS `OR1200_ICLS==4 ? 1'b0: 1'b1 // 16 byte cache block +`define OR1200_ICCFGR_CWS 1'b0 // Irrelevant +`define OR1200_ICCFGR_CCRI 1'b1 // Cache control reg impl. +`define OR1200_ICCFGR_CBIRI 1'b1 // Cache block inv reg impl. +`define OR1200_ICCFGR_CBPRI 1'b0 // Cache block prefetch reg not impl. +`define OR1200_ICCFGR_CBLRI 1'b0 // Cache block lock reg not impl. +`define OR1200_ICCFGR_CBFRI 1'b1 // Cache block flush reg impl. +`define OR1200_ICCFGR_CBWBRI 1'b0 // Irrelevant +`define OR1200_ICCFGR_RES1 17'h00000 +`endif + +// DCFGR fields +`define OR1200_DCFGR_NDP_BITS 3:0 +`define OR1200_DCFGR_WPCI_BITS 4 +`define OR1200_DCFGR_RES1_BITS 31:5 + +// DCFGR values +`ifdef OR1200_DU_HWBKPTS +`define OR1200_DCFGR_NDP 4'h`OR1200_DU_DVRDCR_PAIRS // # of DVR/DCR pairs +`ifdef OR1200_DU_DWCR0 +`define OR1200_DCFGR_WPCI 1'b1 +`else +`define OR1200_DCFGR_WPCI 1'b0 // WP counters not impl. +`endif +`else +`define OR1200_DCFGR_NDP 4'h0 // Zero DVR/DCR pairs +`define OR1200_DCFGR_WPCI 1'b0 // WP counters not impl. +`endif +`define OR1200_DCFGR_RES1 27'd0 + +/////////////////////////////////////////////////////////////////////////////// +// Boot Address Selection // +// // +// Allows a definable boot address, potentially different to the usual reset // +// vector to allow for power-on code to be run, if desired. // +// // +// OR1200_BOOT_ADR should be the 32-bit address of the boot location // +// OR1200_BOOT_PCREG_DEFAULT should be ((OR1200_BOOT_ADR-4)>>2) // +// // +// For default reset behavior uncomment the settings under the "Boot 0x100" // +// comment below. // +// // +/////////////////////////////////////////////////////////////////////////////// +// Boot from 0xf0000100 +//`define OR1200_BOOT_PCREG_DEFAULT 30'h3c00003f +//`define OR1200_BOOT_ADR 32'hf0000100 +// Boot from 0x100 + `define OR1200_BOOT_PCREG_DEFAULT 30'h0000003f + `define OR1200_BOOT_ADR 32'h00000100 Index: rc-1.0/backend/spartan3e_starter_kit/minsoc_defines.v =================================================================== --- rc-1.0/backend/spartan3e_starter_kit/minsoc_defines.v (nonexistent) +++ rc-1.0/backend/spartan3e_starter_kit/minsoc_defines.v (revision 109) @@ -0,0 +1,150 @@ +// +// Define FPGA manufacturer +// +//`define GENERIC_FPGA +//`define ALTERA_FPGA +`define XILINX_FPGA + +// +// Define Xilinx FPGA family +// +`ifdef XILINX_FPGA +//`define SPARTAN2 +//`define SPARTAN3 +`define SPARTAN3E +//`define SPARTAN3A +//`define VIRTEX +//`define VIRTEX2 +//`define VIRTEX4 +//`define VIRTEX5 + +// +// Define Altera FPGA family +// +`elsif ALTERA_FPGA +//`define ARRIA_GX +//`define ARRIA_II_GX +//`define CYCLONE_I +//`define CYCLONE_II +`define CYCLONE_III +//`define CYCLONE_III_LS +//`define CYCLONE_IV_E +//`define CYCLONE_IV_GS +//`define MAX_II +//`define MAX_V +//`define MAX3000A +//`define MAX7000AE +//`define MAX7000B +//`define MAX7000S +//`define STRATIX +//`define STRATIX_II +//`define STRATIX_II_GX +//`define STRATIX_III +`endif + +// +// Memory +// +`define MEMORY_ADR_WIDTH 13 //MEMORY_ADR_WIDTH IS NOT ALLOWED TO BE LESS THAN 12, + //memory is composed by blocks of address width 11 + //Address width of memory -> select memory depth, + //2 powers MEMORY_ADR_WIDTH defines the memory depth + //the memory data width is 32 bit, + //memory amount in Bytes = 4*memory depth + +// +// Memory type (uncomment something if ASIC or generic memory) +// +//`define GENERIC_MEMORY +//`define AVANT_ATP +//`define VIRAGE_SSP +//`define VIRTUALSILICON_SSP + + +// +// TAP selection +// +//`define GENERIC_TAP +`define FPGA_TAP + +// +// Clock Division selection +// +//`define NO_CLOCK_DIVISION +//`define GENERIC_CLOCK_DIVISION +`define FPGA_CLOCK_DIVISION // For Altera ALTPLL, only CYCLONE_III family has been tested. + +// +// Define division +// +`define CLOCK_DIVISOR 2 //in case of GENERIC_CLOCK_DIVISION the real value will be rounded + //down to an even value in FPGA case, check minsoc_clock_manager + //for allowed divisors. + //DO NOT USE CLOCK_DIVISOR = 1 COMMENT THE CLOCK DIVISION SELECTION + //INSTEAD. + +// +// Reset polarity +// +//`define NEGATIVE_RESET //rstn +`define POSITIVE_RESET //rst + +// +// Start-up circuit (only necessary later to load firmware automatically from SPI memory) +// +//`define START_UP + +// +// Connected modules +// +`define UART +//`define ETHERNET + +// +// Ethernet reset +// +`define ETH_RESET 1'b0 +//`define ETH_RESET 1'b1 + +// +// Interrupts +// +`define APP_INT_RES1 1:0 +`define APP_INT_UART 2 +`define APP_INT_RES2 3 +`define APP_INT_ETH 4 +`define APP_INT_PS2 5 +`define APP_INT_RES3 19:6 + +// +// Address map +// +`define APP_ADDR_DEC_W 8 +`define APP_ADDR_SRAM `APP_ADDR_DEC_W'h00 +`define APP_ADDR_FLASH `APP_ADDR_DEC_W'h04 +`define APP_ADDR_DECP_W 4 +`define APP_ADDR_PERIP `APP_ADDR_DECP_W'h9 +`define APP_ADDR_SPI `APP_ADDR_DEC_W'h97 +`define APP_ADDR_ETH `APP_ADDR_DEC_W'h92 +`define APP_ADDR_AUDIO `APP_ADDR_DEC_W'h9d +`define APP_ADDR_UART `APP_ADDR_DEC_W'h90 +`define APP_ADDR_PS2 `APP_ADDR_DEC_W'h94 +`define APP_ADDR_RES1 `APP_ADDR_DEC_W'h9e +`define APP_ADDR_RES2 `APP_ADDR_DEC_W'h9f + +// +// Set-up GENERIC_TAP, GENERIC_MEMORY if GENERIC_FPGA was chosen +// and GENERIC_CLOCK_DIVISION if NO_CLOCK_DIVISION was not set +// +`ifdef GENERIC_FPGA + `undef FPGA_TAP + `undef FPGA_CLOCK_DIVISION + `undef XILINX_FPGA + `undef SPARTAN3E + + `define GENERIC_TAP + `define GENERIC_MEMORY + `ifndef NO_CLOCK_DIVISION + `define GENERIC_CLOCK_DIVISION + `endif +`endif
rc-1.0/backend/spartan3e_starter_kit/minsoc_defines.v Property changes : Added: svn:executable ## -0,0 +1 ## +* \ No newline at end of property Index: rc-1.0/backend/spartan3e_starter_kit/gcc-opt.mk =================================================================== --- rc-1.0/backend/spartan3e_starter_kit/gcc-opt.mk (nonexistent) +++ rc-1.0/backend/spartan3e_starter_kit/gcc-opt.mk (revision 109) @@ -0,0 +1 @@ +GCC_OPT=-mhard-mul -mhard-div -nostdlib Index: rc-1.0/backend/spartan3e_starter_kit/minsoc_bench_defines.v =================================================================== --- rc-1.0/backend/spartan3e_starter_kit/minsoc_bench_defines.v (nonexistent) +++ rc-1.0/backend/spartan3e_starter_kit/minsoc_bench_defines.v (revision 109) @@ -0,0 +1,26 @@ +//set RTL for simulation, override FPGA specific definitions (JTAG TAP, MEMORY and CLOCK DIVIDER) +`define GENERIC_FPGA +`define MEMORY_MODEL //simulation uses a memory model enabling INITIALIZE_MEMORY_MODEL. If you comment this, START_UP might be interesting. +`define NO_CLOCK_DIVISION //if commented out, generic clock division is implemented (odd divisors are rounded down) +//~set RTL for simulation, override FPGA specific definitions (JTAG TAP, MEMORY and CLOCK DIVIDER) + +`define FREQ_NUM_FOR_NS 1000000000 + +`define FREQ 25000000 +`define CLK_PERIOD (`FREQ_NUM_FOR_NS/`FREQ) + +`define ETH_PHY_FREQ 25000000 +`define ETH_PHY_PERIOD (`FREQ_NUM_FOR_NS/`ETH_PHY_FREQ) //40ns + +`define UART_BAUDRATE 115200 + +`define VPI_DEBUG + +//`define VCD_OUTPUT + +//`define START_UP //pass firmware over spi to or1k_startup + +`define INITIALIZE_MEMORY_MODEL //instantaneously initialize memory model with firmware + //only use with the memory model. + //If you use the original memory (`define MEMORY_MODEL + //commented out), comment this too.
rc-1.0/backend/spartan3e_starter_kit/minsoc_bench_defines.v Property changes : Added: svn:executable ## -0,0 +1 ## +* \ No newline at end of property Index: rc-1.0/backend/spartan3e_starter_kit/spartan3e_starter_kit.ucf =================================================================== --- rc-1.0/backend/spartan3e_starter_kit/spartan3e_starter_kit.ucf (nonexistent) +++ rc-1.0/backend/spartan3e_starter_kit/spartan3e_starter_kit.ucf (revision 109) @@ -0,0 +1,64 @@ +# +# Soldered 50MHz clock. +# +NET "clk" LOC = "C9"; + +# +# Use button "south" as reset. +# +NET "reset" LOC = "K17" | PULLDOWN ; + +# +# UART serial port (RS232 DCE) - connector DB9 female. +# +NET "uart_srx" LOC = "R7"; +NET "uart_stx" LOC = "M14" | DRIVE = 8 | SLEW = SLOW ; + +########################### +## +## ETH +## +#NET "eth_txd(3)" LOC = "t5"; +#NET "eth_txd(2)" LOC = "r5"; +#NET "eth_txd(1)" LOC = "t15"; +#NET "eth_txd(0)" LOC = "r11"; +# +#NET "eth_tx_en" LOC = "p15"; +#NET "eth_tx_clk" LOC = "t7" | CLOCK_DEDICATED_ROUTE = FALSE; +#NET "eth_tx_er" LOC = "r6"; +# +#NET "eth_rxd(3)" LOC = "v14"; +#NET "eth_rxd(2)" LOC = "u11"; +#NET "eth_rxd(1)" LOC = "t11"; +#NET "eth_rxd(0)" LOC = "v8"; +# +#NET "eth_rx_er" LOC = "u14"; +#NET "eth_rx_dv" LOC = "v2"; +# +#NET "eth_rx_clk" LOC = "v3" | CLOCK_DEDICATED_ROUTE = FALSE; +# +#NET "eth_mdio" LOC = "u5" | PULLUP; +#NET "eth_crs" LOC = "u13"; +#NET "eth_col" LOC = "u6"; +#NET "eth_mdc" LOC = "p9"; +# +#NET "eth_trste" LOC = "p13"; #put it to a non connected FPGA pin (starter kit schematic BANK3) +# +#NET "eth_fds_mdint" LOC = "r13" | PULLUP; #put it to a non connected FPGA pin (starter kit schematic BANK3)(pullup not to generate interrupts) +########################### + +# +# JTAG signals - on J4 6-pin accessory header. +# + +#NET "jtag_tms" LOC = "D7" | PULLDOWN ; +#NET "jtag_tdi" LOC = "C7" | PULLDOWN ; +#NET "jtag_tdo" LOC = "F8" | SLEW = FAST | DRIVE = 8 ; +#NET "jtag_tck" LOC = "E8" | PULLDOWN ; + +#net "jtag_gnd" loc = "k2"; #put it to a non connected FPGA pin (starter kit schematic BANK3) +#net "jtag_vref" loc = "k7"; #put it to a non connected FPGA pin (starter kit schematic BANK3) + +# +# End of file. +#
rc-1.0/backend/spartan3e_starter_kit/spartan3e_starter_kit.ucf Property changes : Added: svn:executable ## -0,0 +1 ## +* \ No newline at end of property Index: rc-1.0/backend/spartan3e_starter_kit/board.h =================================================================== --- rc-1.0/backend/spartan3e_starter_kit/board.h (nonexistent) +++ rc-1.0/backend/spartan3e_starter_kit/board.h (revision 109) @@ -0,0 +1,40 @@ +#ifndef _BOARD_H_ +#define _BOARD_H_ + +#define MC_ENABLED 0 + +#define IC_ENABLE 0 +#define IC_SIZE 8192 +#define DC_ENABLE 0 +#define DC_SIZE 8192 + + +#define IN_CLK 25000000 + + +#define STACK_SIZE 0x01000 + +#define UART_BAUD_RATE 115200 + +#define UART_BASE 0x90000000 +#define UART_IRQ 2 +#define ETH_BASE 0x92000000 +#define ETH_IRQ 4 +#define I2C_BASE 0x9D000000 +#define I2C_IRQ 3 +#define CAN_BASE 0x94000000 +#define CAN_IRQ 5 + +#define MC_BASE_ADDR 0x60000000 +#define SPI_BASE 0xa0000000 + +#define ETH_DATA_BASE 0xa8000000 /* Address for ETH_DATA */ + +#define ETH_MACADDR0 0x00 +#define ETH_MACADDR1 0x12 +#define ETH_MACADDR2 0x34 +#define ETH_MACADDR3 0x56 +#define ETH_MACADDR4 0x78 +#define ETH_MACADDR5 0x9a + +#endif
rc-1.0/backend/spartan3e_starter_kit/board.h Property changes : Added: svn:executable ## -0,0 +1 ## +* \ No newline at end of property Index: rc-1.0/backend/spartan3e_starter_kit/orp.ld =================================================================== --- rc-1.0/backend/spartan3e_starter_kit/orp.ld (nonexistent) +++ rc-1.0/backend/spartan3e_starter_kit/orp.ld (revision 109) @@ -0,0 +1,60 @@ +MEMORY + { + reset : ORIGIN = 0x00000000, LENGTH = 0x00000200 + vectors : ORIGIN = 0x00000200, LENGTH = 0x00001000 + ram : ORIGIN = 0x00001200, LENGTH = 0x00006E00 /*0x8000 total*/ + } + +SECTIONS +{ + .reset : + { + *(.reset) + } > reset + + + + .vectors : + { + _vec_start = .; + *(.vectors) + _vec_end = .; + } > vectors + + .text : + { + *(.text) + } > ram + + .rodata : + { + *(.rodata) + *(.rodata.*) + } > ram + + .icm : + { + _icm_start = .; + *(.icm) + _icm_end = .; + } > ram + + .data : + { + _dst_beg = .; + *(.data) + _dst_end = .; + } > ram + + .bss : + { + *(.bss) + } > ram + + .stack (NOLOAD) : + { + *(.stack) + _src_addr = .; + } > ram + +}
rc-1.0/backend/spartan3e_starter_kit/orp.ld Property changes : Added: svn:executable ## -0,0 +1 ## +* \ No newline at end of property Index: rc-1.0/backend/spartan3e_starter_kit_eth/configure =================================================================== --- rc-1.0/backend/spartan3e_starter_kit_eth/configure (nonexistent) +++ rc-1.0/backend/spartan3e_starter_kit_eth/configure (revision 109) @@ -0,0 +1,118 @@ +#!/bin/bash + +#NON STANDARD SCRIPT, USE ANOTHER AS TEMPLATE, NON STANDARD PART IS MARKED AS COMMENT + +#new boards have to udpate this +BOARD=spartan3e_starter_kit_eth #this has to have the name of the directory this file is in +DEVICE_PART='xc3s500e-4-fg320' +CONSTRAINT_FILE='spartan3e_starter_kit_eth.ucf' +#~new boards update + +#system workings +MINSOC_DIR=`pwd`/../.. +BACKEND_DIR=$MINSOC_DIR/backend +SYN_DIR=$MINSOC_DIR/syn +SYNSRC_DIR=$MINSOC_DIR/prj/xilinx +SYNSUPPORT_DIR=$SYN_DIR/buildSupport +MAKEFILE_DIR=$SYN_DIR/xilinx + +SYN_FILES=(ethmac.xst uart_top.xst adbg_top.xst or1200_top.xst minsoc_top.xst) +MAKEFILE=Makefile + +FIND_PART='DEVICE_PART' +FIND_CONSTRAINT='CONSTRAINT_FILE' + +BOARD_DIR=$BACKEND_DIR/$BOARD +BOARD_FILES=(board.h orp.ld minsoc_defines.v minsoc_bench_defines.v gcc-opt.mk $CONSTRAINT_FILE) + +in_minsoc=`pwd | grep minsoc/backend/${BOARD}$` +if [ -z $in_minsoc ] +then + echo "" + echo " !!!WARNING!!!" + echo "This script cannot be run if not in a board directory inside minsoc/backend," + echo "because it relies on the directory structure of the minsoc system." + echo "" + echo "Possibly your minsoc directory is named differently, minsoc_trunk for example." + echo "Its name must be minsoc only." + echo "" + exit 1 +fi + +#NON STANDARD SCRIPT PART +echo "THIS SCRIPT HAS A NON-STANDARD BEGINNING." +echo "__________________________________________________________________________" +echo "Ethernet on Spartan3E Starter Kit requires another configuration for or1200." +echo "For minsoc release-1.0 or1200_r1 will be used." +echo "This will need or1200_defines.v of or1200_r1 with same configuration." + +echo "" +echo "Copying or1200_defines.v, to or1200 implementation directory..." +echo "(minsoc/rtl/verilog/or1200/rtl/verilog)" +echo "__________________________________________________________________________" +cp $BOARD_DIR/or1200_defines.v $MINSOC_DIR/rtl/verilog/or1200/rtl/verilog +echo "" +echo "REGULAR SCRIPT STARTS NOW" +echo "__________________________________________________________________________" +#~NON STANDARD SCRIPT PART + +echo "" +echo "This script sets up the SoC for simulations and synthesis." +echo "" +echo "In order to do so, SoC board's specific files for firmware compilation, " +echo "testbench generation and synthesis are configured." +echo "Firmware and testbench looks for board specific files under $BACKEND_DIR." +echo "Synthesis work under $SYN_DIR." +echo "" +echo "" + +echo "Generating project files for simulation and synthesis..." +make -C $MINSOC_DIR/prj +echo "Generation complete." +echo "__________________________________________________________________________" +echo "" + +if [ $CONSTRAINT_FILE == 'NONE' ] +then + echo "Skipping synthesis preparation. Standard implementation can only be simulated." +else + echo "Device part for files under $SYNSRC_DIR will be patched and stored " + echo "temporarily." + echo "Afterwards, they are copied to $SYNSUPPORT_DIR." + echo "__________________________________________________________________________" + echo "" + for file in "${SYN_FILES[@]}" + do + echo "Updating synthesis file, $file..." + echo "Copying $file to synthesis directory..." + echo "" + sed "s/$FIND_PART/$DEVICE_PART/g" $SYNSRC_DIR/$file > TMPFILE + sed "s/$FIND_CONSTRAINT/$CONSTRAINT_FILE/g" TMPFILE > TMPFILE2 && mv TMPFILE2 $SYNSUPPORT_DIR/$file + rm TMPFILE + done + + echo "Updating Makefile file under $MAKEFILE_DIR..." + echo "Copying Makefile to synthesis directory, $SYN_DIR..." + echo "" + sed "s/$FIND_PART/$DEVICE_PART/g" $MAKEFILE_DIR/$MAKEFILE > TMPFILE + sed "s/$FIND_CONSTRAINT/$CONSTRAINT_FILE/g" TMPFILE > TMPFILE2 && mv TMPFILE2 $SYN_DIR/$MAKEFILE + rm TMPFILE + cp $MAKEFILE_DIR/setup.bat $SYN_DIR/setup.bat +fi +echo "" +echo "" + + +echo "Copying board specific SoC files from $BOARD_DIR to $BACKEND_DIR directory." +echo "__________________________________________________________________________" +echo "" +for file in "${BOARD_FILES[@]}" +do + if [ $file != NONE ] + then + echo "Copying $file, to backend directory..." + cp $BOARD_DIR/$file $BACKEND_DIR + fi +done +echo "" +echo ""
rc-1.0/backend/spartan3e_starter_kit_eth/configure Property changes : Added: svn:executable ## -0,0 +1 ## +* \ No newline at end of property Index: rc-1.0/backend/spartan3e_starter_kit_eth/or1200_defines.v =================================================================== --- rc-1.0/backend/spartan3e_starter_kit_eth/or1200_defines.v (nonexistent) +++ rc-1.0/backend/spartan3e_starter_kit_eth/or1200_defines.v (revision 109) @@ -0,0 +1,1823 @@ +////////////////////////////////////////////////////////////////////// +//// //// +//// OR1200's definitions //// +//// //// +//// This file is part of the OpenRISC 1200 project //// +//// http://opencores.org/project,or1k //// +//// //// +//// Description //// +//// Defines for the OR1200 core //// +//// //// +//// To Do: //// +//// - add parameters that are missing //// +//// //// +//// Author(s): //// +//// - Damjan Lampret, lampret@opencores.org //// +//// //// +////////////////////////////////////////////////////////////////////// +//// //// +//// Copyright (C) 2000 Authors and OPENCORES.ORG //// +//// //// +//// This source file may be used and distributed without //// +//// restriction provided that this copyright statement is not //// +//// removed from the file and that any derivative work contains //// +//// the original copyright notice and the associated disclaimer. //// +//// //// +//// This source file is free software; you can redistribute it //// +//// and/or modify it under the terms of the GNU Lesser General //// +//// Public License as published by the Free Software Foundation; //// +//// either version 2.1 of the License, or (at your option) any //// +//// later version. //// +//// //// +//// This source is distributed in the hope that it will be //// +//// useful, but WITHOUT ANY WARRANTY; without even the implied //// +//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR //// +//// PURPOSE. See the GNU Lesser General Public License for more //// +//// details. //// +//// //// +//// You should have received a copy of the GNU Lesser General //// +//// Public License along with this source; if not, download it //// +//// from http://www.opencores.org/lgpl.shtml //// +//// //// +////////////////////////////////////////////////////////////////////// +// +// $Log: or1200_defines.v,v $ +// Revision 2.0 2010/06/30 11:00:00 ORSoC +// Minor update: +// Defines added, bugs fixed. + +// +// Dump VCD +// +//`define OR1200_VCD_DUMP + +// +// Generate debug messages during simulation +// +//`define OR1200_VERBOSE + +// `define OR1200_ASIC +//////////////////////////////////////////////////////// +// +// Typical configuration for an ASIC +// +`ifdef OR1200_ASIC + +// +// Target ASIC memories +// +//`define OR1200_ARTISAN_SSP +//`define OR1200_ARTISAN_SDP +//`define OR1200_ARTISAN_STP +`define OR1200_VIRTUALSILICON_SSP +//`define OR1200_VIRTUALSILICON_STP_T1 +//`define OR1200_VIRTUALSILICON_STP_T2 + +// +// Do not implement Data cache +// +//`define OR1200_NO_DC + +// +// Do not implement Insn cache +// +//`define OR1200_NO_IC + +// +// Do not implement Data MMU +// +//`define OR1200_NO_DMMU + +// +// Do not implement Insn MMU +// +//`define OR1200_NO_IMMU + +// +// Select between ASIC optimized and generic multiplier +// +//`define OR1200_ASIC_MULTP2_32X32 +`define OR1200_GENERIC_MULTP2_32X32 + +// +// Size/type of insn/data cache if implemented +// +// `define OR1200_IC_1W_512B +// `define OR1200_IC_1W_4KB +`define OR1200_IC_1W_8KB +// `define OR1200_DC_1W_4KB +`define OR1200_DC_1W_8KB + +`else + + +///////////////////////////////////////////////////////// +// +// Typical configuration for an FPGA +// + +// +// Target FPGA memories +// +//`define OR1200_ALTERA_LPM +//`define OR1200_XILINX_RAMB16 +//`define OR1200_XILINX_RAMB4 +//`define OR1200_XILINX_RAM32X1D +//`define OR1200_USE_RAM16X1D_FOR_RAM32X1D +// Generic models should infer RAM blocks at synthesis time (not only effects +// single port ram.) +`define OR1200_GENERIC + +// +// Do not implement Data cache +// +`define OR1200_NO_DC + +// +// Do not implement Insn cache +// +`define OR1200_NO_IC + +// +// Do not implement Data MMU +// +`define OR1200_NO_DMMU + +// +// Do not implement Insn MMU +// +`define OR1200_NO_IMMU + +// +// Select between ASIC and generic multiplier +// +// (Generic seems to trigger a bug in the Cadence Ncsim simulator) +// +//`define OR1200_ASIC_MULTP2_32X32 +`define OR1200_GENERIC_MULTP2_32X32 + +// +// Size/type of insn/data cache if implemented +// (consider available FPGA memory resources) +// +//`define OR1200_IC_1W_512B +//`define OR1200_IC_1W_4KB +`define OR1200_IC_1W_8KB +//`define OR1200_IC_1W_16KB +//`define OR1200_IC_1W_32KB +//`define OR1200_DC_1W_4KB +`define OR1200_DC_1W_8KB +//`define OR1200_DC_1W_16KB +//`define OR1200_DC_1W_32KB + +`endif + + +////////////////////////////////////////////////////////// +// +// Do not change below unless you know what you are doing +// + +// +// Reset active low +// +//`define OR1200_RST_ACT_LOW + +// +// Enable RAM BIST +// +// At the moment this only works for Virtual Silicon +// single port RAMs. For other RAMs it has not effect. +// Special wrapper for VS RAMs needs to be provided +// with scan flops to facilitate bist scan. +// +//`define OR1200_BIST + +// +// Register OR1200 WISHBONE outputs +// (must be defined/enabled) +// +`define OR1200_REGISTERED_OUTPUTS + +// +// Register OR1200 WISHBONE inputs +// +// (must be undefined/disabled) +// +//`define OR1200_REGISTERED_INPUTS + +// +// Disable bursts if they are not supported by the +// memory subsystem (only affect cache line fill) +// +//`define OR1200_NO_BURSTS +// + +// +// WISHBONE retry counter range +// +// 2^value range for retry counter. Retry counter +// is activated whenever *wb_rty_i is asserted and +// until retry counter expires, corresponding +// WISHBONE interface is deactivated. +// +// To disable retry counters and *wb_rty_i all together, +// undefine this macro. +// +//`define OR1200_WB_RETRY 7 + +// +// WISHBONE Consecutive Address Burst +// +// This was used prior to WISHBONE B3 specification +// to identify bursts. It is no longer needed but +// remains enabled for compatibility with old designs. +// +// To remove *wb_cab_o ports undefine this macro. +// +//`define OR1200_WB_CAB + +// +// WISHBONE B3 compatible interface +// +// This follows the WISHBONE B3 specification. +// It is not enabled by default because most +// designs still don't use WB b3. +// +// To enable *wb_cti_o/*wb_bte_o ports, +// define this macro. +// +`define OR1200_WB_B3 + +// +// LOG all WISHBONE accesses +// +`define OR1200_LOG_WB_ACCESS + +// +// Enable additional synthesis directives if using +// _Synopsys_ synthesis tool +// +//`define OR1200_ADDITIONAL_SYNOPSYS_DIRECTIVES + +// +// Enables default statement in some case blocks +// and disables Synopsys synthesis directive full_case +// +// By default it is enabled. When disabled it +// can increase clock frequency. +// +`define OR1200_CASE_DEFAULT + +// +// Operand width / register file address width +// +// (DO NOT CHANGE) +// +`define OR1200_OPERAND_WIDTH 32 +`define OR1200_REGFILE_ADDR_WIDTH 5 + +// +// l.add/l.addi/l.and and optional l.addc/l.addic +// also set (compare) flag when result of their +// operation equals zero +// +// At the time of writing this, default or32 +// C/C++ compiler doesn't generate code that +// would benefit from this optimization. +// +// By default this optimization is disabled to +// save area. +// +//`define OR1200_ADDITIONAL_FLAG_MODIFIERS + +// +// Implement l.addc/l.addic instructions +// +// By default implementation of l.addc/l.addic +// instructions is enabled in case you need them. +// If you don't use them, then disable implementation +// to save area. +// +`define OR1200_IMPL_ADDC + +// +// Implement l.sub instruction +// +// By default implementation of l.sub instructions +// is enabled to be compliant with the simulator. +// If you don't use carry bit, then disable +// implementation to save area. +// +`define OR1200_IMPL_SUB + +// +// Implement carry bit SR[CY] +// +// +// By default implementation of SR[CY] is enabled +// to be compliant with the simulator. However SR[CY] +// is explicitly only used by l.addc/l.addic/l.sub +// instructions and if these three insns are not +// implemented there is not much point having SR[CY]. +// +`define OR1200_IMPL_CY + +// +// Implement carry bit SR[OV] +// +// Compiler doesn't use this, but other code may like +// to. +// +`define OR1200_IMPL_OV + +// +// Implement carry bit SR[OVE] +// +// Overflow interrupt indicator. When enabled, SR[OV] flag +// does not remain asserted after exception. +// +`define OR1200_IMPL_OVE + + +// +// Implement rotate in the ALU +// +// At the time of writing this, or32 +// C/C++ compiler doesn't generate rotate +// instructions. However or32 assembler +// can assemble code that uses rotate insn. +// This means that rotate instructions +// must be used manually inserted. +// +// By default implementation of rotate +// is disabled to save area and increase +// clock frequency. +// +//`define OR1200_IMPL_ALU_ROTATE + +// +// Type of ALU compare to implement +// +// Try to find which synthesizes with +// most efficient logic use or highest speed. +// +//`define OR1200_IMPL_ALU_COMP1 +//`define OR1200_IMPL_ALU_COMP2 +`define OR1200_IMPL_ALU_COMP3 + +// +// Implement Find First/Last '1' +// +`define OR1200_IMPL_ALU_FFL1 + +// +// Implement l.cust5 ALU instruction +// +//`define OR1200_IMPL_ALU_CUST5 + +// +// Implement l.extXs and l.extXz instructions +// +`define OR1200_IMPL_ALU_EXT + +// +// Implement multiplier +// +// By default multiplier is implemented +// +`define OR1200_MULT_IMPLEMENTED + +// +// Implement multiply-and-accumulate +// +// By default MAC is implemented. To +// implement MAC, multiplier (non-serial) needs to be +// implemented. +// +//`define OR1200_MAC_IMPLEMENTED + +// +// Implement optional l.div/l.divu instructions +// +// By default divide instructions are not implemented +// to save area. +// +// +//`define OR1200_DIV_IMPLEMENTED + +// +// Serial multiplier. +// +//`define OR1200_MULT_SERIAL + +// +// Serial divider. +// Uncomment to use a serial divider, otherwise will +// be a generic parallel implementation. +// +`define OR1200_DIV_SERIAL + +// +// Implement HW Single Precision FPU +// +//`define OR1200_FPU_IMPLEMENTED + +// +// Clock ratio RISC clock versus WB clock +// +// If you plan to run WB:RISC clock fixed to 1:1, disable +// both defines +// +// For WB:RISC 1:2 or 1:1, enable OR1200_CLKDIV_2_SUPPORTED +// and use clmode to set ratio +// +// For WB:RISC 1:4, 1:2 or 1:1, enable both defines and use +// clmode to set ratio +// +//`define OR1200_CLKDIV_2_SUPPORTED +//`define OR1200_CLKDIV_4_SUPPORTED + +// +// Type of register file RAM +// +// Memory macro w/ two ports (see or1200_tpram_32x32.v) +//`define OR1200_RFRAM_TWOPORT +// +// Memory macro dual port (see or1200_dpram.v) +`define OR1200_RFRAM_DUALPORT + +// +// Generic (flip-flop based) register file (see or1200_rfram_generic.v) +//`define OR1200_RFRAM_GENERIC +// Generic register file supports - 16 registers +`ifdef OR1200_RFRAM_GENERIC +// `define OR1200_RFRAM_16REG +`endif + +// +// Type of mem2reg aligner to implement. +// +// Once OR1200_IMPL_MEM2REG2 yielded faster +// circuit, however with today tools it will +// most probably give you slower circuit. +// +`define OR1200_IMPL_MEM2REG1 +//`define OR1200_IMPL_MEM2REG2 + +// +// Reset value and event +// +`ifdef OR1200_RST_ACT_LOW + `define OR1200_RST_VALUE (1'b0) + `define OR1200_RST_EVENT negedge +`else + `define OR1200_RST_VALUE (1'b1) + `define OR1200_RST_EVENT posedge +`endif + +// +// ALUOPs +// +`define OR1200_ALUOP_WIDTH 5 +`define OR1200_ALUOP_NOP 5'b0_0100 +/* LS-nibble encodings correspond to bits [3:0] of instruction */ +`define OR1200_ALUOP_ADD 5'b0_0000 // 0 +`define OR1200_ALUOP_ADDC 5'b0_0001 // 1 +`define OR1200_ALUOP_SUB 5'b0_0010 // 2 +`define OR1200_ALUOP_AND 5'b0_0011 // 3 +`define OR1200_ALUOP_OR 5'b0_0100 // 4 +`define OR1200_ALUOP_XOR 5'b0_0101 // 5 +`define OR1200_ALUOP_MUL 5'b0_0110 // 6 +`define OR1200_ALUOP_RESERVED 5'b0_0111 // 7 +`define OR1200_ALUOP_SHROT 5'b0_1000 // 8 +`define OR1200_ALUOP_DIV 5'b0_1001 // 9 +`define OR1200_ALUOP_DIVU 5'b0_1010 // a +`define OR1200_ALUOP_MULU 5'b0_1011 // b +`define OR1200_ALUOP_EXTHB 5'b0_1100 // c +`define OR1200_ALUOP_EXTW 5'b0_1101 // d +`define OR1200_ALUOP_CMOV 5'b0_1110 // e +`define OR1200_ALUOP_FFL1 5'b0_1111 // f + +/* Values sent to ALU from decode unit - not defined by ISA */ +`define OR1200_ALUOP_COMP 5'b1_0000 // Comparison +`define OR1200_ALUOP_MOVHI 5'b1_0001 // Move-high +`define OR1200_ALUOP_CUST5 5'b1_0010 // l.cust5 + +// ALU instructions second opcode field +`define OR1200_ALUOP2_POS 9:6 +`define OR1200_ALUOP2_WIDTH 4 + +// +// MACOPs +// +`define OR1200_MACOP_WIDTH 3 +`define OR1200_MACOP_NOP 3'b000 +`define OR1200_MACOP_MAC 3'b001 +`define OR1200_MACOP_MSB 3'b010 + +// +// Shift/rotate ops +// +`define OR1200_SHROTOP_WIDTH 4 +`define OR1200_SHROTOP_NOP 4'd0 +`define OR1200_SHROTOP_SLL 4'd0 +`define OR1200_SHROTOP_SRL 4'd1 +`define OR1200_SHROTOP_SRA 4'd2 +`define OR1200_SHROTOP_ROR 4'd3 + +// +// Zero/Sign Extend ops +// +`define OR1200_EXTHBOP_WIDTH 4 +`define OR1200_EXTHBOP_BS 4'h1 +`define OR1200_EXTHBOP_HS 4'h0 +`define OR1200_EXTHBOP_BZ 4'h3 +`define OR1200_EXTHBOP_HZ 4'h2 +`define OR1200_EXTWOP_WIDTH 4 +`define OR1200_EXTWOP_WS 4'h0 +`define OR1200_EXTWOP_WZ 4'h1 + +// Execution cycles per instruction +`define OR1200_MULTICYCLE_WIDTH 3 +`define OR1200_ONE_CYCLE 3'd0 +`define OR1200_TWO_CYCLES 3'd1 + +// Execution control which will "wait on" a module to finish +`define OR1200_WAIT_ON_WIDTH 2 +`define OR1200_WAIT_ON_NOTHING `OR1200_WAIT_ON_WIDTH'd0 +`define OR1200_WAIT_ON_MULTMAC `OR1200_WAIT_ON_WIDTH'd1 +`define OR1200_WAIT_ON_FPU `OR1200_WAIT_ON_WIDTH'd2 +`define OR1200_WAIT_ON_MTSPR `OR1200_WAIT_ON_WIDTH'd3 + + +// Operand MUX selects +`define OR1200_SEL_WIDTH 2 +`define OR1200_SEL_RF 2'd0 +`define OR1200_SEL_IMM 2'd1 +`define OR1200_SEL_EX_FORW 2'd2 +`define OR1200_SEL_WB_FORW 2'd3 + +// +// BRANCHOPs +// +`define OR1200_BRANCHOP_WIDTH 3 +`define OR1200_BRANCHOP_NOP 3'd0 +`define OR1200_BRANCHOP_J 3'd1 +`define OR1200_BRANCHOP_JR 3'd2 +`define OR1200_BRANCHOP_BAL 3'd3 +`define OR1200_BRANCHOP_BF 3'd4 +`define OR1200_BRANCHOP_BNF 3'd5 +`define OR1200_BRANCHOP_RFE 3'd6 + +// +// LSUOPs +// +// Bit 0: sign extend +// Bits 1-2: 00 doubleword, 01 byte, 10 halfword, 11 singleword +// Bit 3: 0 load, 1 store +`define OR1200_LSUOP_WIDTH 4 +`define OR1200_LSUOP_NOP 4'b0000 +`define OR1200_LSUOP_LBZ 4'b0010 +`define OR1200_LSUOP_LBS 4'b0011 +`define OR1200_LSUOP_LHZ 4'b0100 +`define OR1200_LSUOP_LHS 4'b0101 +`define OR1200_LSUOP_LWZ 4'b0110 +`define OR1200_LSUOP_LWS 4'b0111 +`define OR1200_LSUOP_LD 4'b0001 +`define OR1200_LSUOP_SD 4'b1000 +`define OR1200_LSUOP_SB 4'b1010 +`define OR1200_LSUOP_SH 4'b1100 +`define OR1200_LSUOP_SW 4'b1110 + +// Number of bits of load/store EA precalculated in ID stage +// for balancing ID and EX stages. +// +// Valid range: 2,3,...,30,31 +`define OR1200_LSUEA_PRECALC 2 + +// FETCHOPs +`define OR1200_FETCHOP_WIDTH 1 +`define OR1200_FETCHOP_NOP 1'b0 +`define OR1200_FETCHOP_LW 1'b1 + +// +// Register File Write-Back OPs +// +// Bit 0: register file write enable +// Bits 3-1: write-back mux selects +// +`define OR1200_RFWBOP_WIDTH 4 +`define OR1200_RFWBOP_NOP 4'b0000 +`define OR1200_RFWBOP_ALU 3'b000 +`define OR1200_RFWBOP_LSU 3'b001 +`define OR1200_RFWBOP_SPRS 3'b010 +`define OR1200_RFWBOP_LR 3'b011 +`define OR1200_RFWBOP_FPU 3'b100 + +// Compare instructions +`define OR1200_COP_SFEQ 3'b000 +`define OR1200_COP_SFNE 3'b001 +`define OR1200_COP_SFGT 3'b010 +`define OR1200_COP_SFGE 3'b011 +`define OR1200_COP_SFLT 3'b100 +`define OR1200_COP_SFLE 3'b101 +`define OR1200_COP_X 3'b111 +`define OR1200_SIGNED_COMPARE 'd3 +`define OR1200_COMPOP_WIDTH 4 + +// +// FP OPs +// +// MSbit indicates FPU operation valid +// +`define OR1200_FPUOP_WIDTH 8 +// FPU unit from Usselman takes 5 cycles from decode, so 4 ex. cycles +`define OR1200_FPUOP_CYCLES 3'd4 +// FP instruction is double precision if bit 4 is set. We're a 32-bit +// implementation thus do not support double precision FP +`define OR1200_FPUOP_DOUBLE_BIT 4 +`define OR1200_FPUOP_ADD 8'b0000_0000 +`define OR1200_FPUOP_SUB 8'b0000_0001 +`define OR1200_FPUOP_MUL 8'b0000_0010 +`define OR1200_FPUOP_DIV 8'b0000_0011 +`define OR1200_FPUOP_ITOF 8'b0000_0100 +`define OR1200_FPUOP_FTOI 8'b0000_0101 +`define OR1200_FPUOP_REM 8'b0000_0110 +`define OR1200_FPUOP_RESERVED 8'b0000_0111 +// FP Compare instructions +`define OR1200_FPCOP_SFEQ 8'b0000_1000 +`define OR1200_FPCOP_SFNE 8'b0000_1001 +`define OR1200_FPCOP_SFGT 8'b0000_1010 +`define OR1200_FPCOP_SFGE 8'b0000_1011 +`define OR1200_FPCOP_SFLT 8'b0000_1100 +`define OR1200_FPCOP_SFLE 8'b0000_1101 + +// +// TAGs for instruction bus +// +`define OR1200_ITAG_IDLE 4'h0 // idle bus +`define OR1200_ITAG_NI 4'h1 // normal insn +`define OR1200_ITAG_BE 4'hb // Bus error exception +`define OR1200_ITAG_PE 4'hc // Page fault exception +`define OR1200_ITAG_TE 4'hd // TLB miss exception + +// +// TAGs for data bus +// +`define OR1200_DTAG_IDLE 4'h0 // idle bus +`define OR1200_DTAG_ND 4'h1 // normal data +`define OR1200_DTAG_AE 4'ha // Alignment exception +`define OR1200_DTAG_BE 4'hb // Bus error exception +`define OR1200_DTAG_PE 4'hc // Page fault exception +`define OR1200_DTAG_TE 4'hd // TLB miss exception + + +////////////////////////////////////////////// +// +// ORBIS32 ISA specifics +// + +// SHROT_OP position in machine word +`define OR1200_SHROTOP_POS 7:6 + +// +// Instruction opcode groups (basic) +// +`define OR1200_OR32_J 6'b000000 +`define OR1200_OR32_JAL 6'b000001 +`define OR1200_OR32_BNF 6'b000011 +`define OR1200_OR32_BF 6'b000100 +`define OR1200_OR32_NOP 6'b000101 +`define OR1200_OR32_MOVHI 6'b000110 +`define OR1200_OR32_MACRC 6'b000110 +`define OR1200_OR32_XSYNC 6'b001000 +`define OR1200_OR32_RFE 6'b001001 +/* */ +`define OR1200_OR32_JR 6'b010001 +`define OR1200_OR32_JALR 6'b010010 +`define OR1200_OR32_MACI 6'b010011 +/* */ +`define OR1200_OR32_LWZ 6'b100001 +`define OR1200_OR32_LBZ 6'b100011 +`define OR1200_OR32_LBS 6'b100100 +`define OR1200_OR32_LHZ 6'b100101 +`define OR1200_OR32_LHS 6'b100110 +`define OR1200_OR32_ADDI 6'b100111 +`define OR1200_OR32_ADDIC 6'b101000 +`define OR1200_OR32_ANDI 6'b101001 +`define OR1200_OR32_ORI 6'b101010 +`define OR1200_OR32_XORI 6'b101011 +`define OR1200_OR32_MULI 6'b101100 +`define OR1200_OR32_MFSPR 6'b101101 +`define OR1200_OR32_SH_ROTI 6'b101110 +`define OR1200_OR32_SFXXI 6'b101111 +/* */ +`define OR1200_OR32_MTSPR 6'b110000 +`define OR1200_OR32_MACMSB 6'b110001 +`define OR1200_OR32_FLOAT 6'b110010 +/* */ +`define OR1200_OR32_SW 6'b110101 +`define OR1200_OR32_SB 6'b110110 +`define OR1200_OR32_SH 6'b110111 +`define OR1200_OR32_ALU 6'b111000 +`define OR1200_OR32_SFXX 6'b111001 +`define OR1200_OR32_CUST5 6'b111100 + +///////////////////////////////////////////////////// +// +// Exceptions +// + +// +// Exception vectors per OR1K architecture: +// 0xPPPPP100 - reset +// 0xPPPPP200 - bus error +// ... etc +// where P represents exception prefix. +// +// Exception vectors can be customized as per +// the following formula: +// 0xPPPPPNVV - exception N +// +// P represents exception prefix +// N represents exception N +// VV represents length of the individual vector space, +// usually it is 8 bits wide and starts with all bits zero +// + +// +// PPPPP and VV parts +// +// Sum of these two defines needs to be 28 +// +`define OR1200_EXCEPT_EPH0_P 20'h00000 +`define OR1200_EXCEPT_EPH1_P 20'hF0000 +`define OR1200_EXCEPT_V 8'h00 + +// +// N part width +// +`define OR1200_EXCEPT_WIDTH 4 + +// +// Definition of exception vectors +// +// To avoid implementation of a certain exception, +// simply comment out corresponding line +// +`define OR1200_EXCEPT_UNUSED `OR1200_EXCEPT_WIDTH'hf +`define OR1200_EXCEPT_TRAP `OR1200_EXCEPT_WIDTH'he +`define OR1200_EXCEPT_FLOAT `OR1200_EXCEPT_WIDTH'hd +`define OR1200_EXCEPT_SYSCALL `OR1200_EXCEPT_WIDTH'hc +`define OR1200_EXCEPT_RANGE `OR1200_EXCEPT_WIDTH'hb +`define OR1200_EXCEPT_ITLBMISS `OR1200_EXCEPT_WIDTH'ha +`define OR1200_EXCEPT_DTLBMISS `OR1200_EXCEPT_WIDTH'h9 +`define OR1200_EXCEPT_INT `OR1200_EXCEPT_WIDTH'h8 +`define OR1200_EXCEPT_ILLEGAL `OR1200_EXCEPT_WIDTH'h7 +`define OR1200_EXCEPT_ALIGN `OR1200_EXCEPT_WIDTH'h6 +`define OR1200_EXCEPT_TICK `OR1200_EXCEPT_WIDTH'h5 +`define OR1200_EXCEPT_IPF `OR1200_EXCEPT_WIDTH'h4 +`define OR1200_EXCEPT_DPF `OR1200_EXCEPT_WIDTH'h3 +`define OR1200_EXCEPT_BUSERR `OR1200_EXCEPT_WIDTH'h2 +`define OR1200_EXCEPT_RESET `OR1200_EXCEPT_WIDTH'h1 +`define OR1200_EXCEPT_NONE `OR1200_EXCEPT_WIDTH'h0 + + +///////////////////////////////////////////////////// +// +// SPR groups +// + +// Bits that define the group +`define OR1200_SPR_GROUP_BITS 15:11 + +// Width of the group bits +`define OR1200_SPR_GROUP_WIDTH 5 + +// Bits that define offset inside the group +`define OR1200_SPR_OFS_BITS 10:0 + +// List of groups +`define OR1200_SPR_GROUP_SYS 5'd00 +`define OR1200_SPR_GROUP_DMMU 5'd01 +`define OR1200_SPR_GROUP_IMMU 5'd02 +`define OR1200_SPR_GROUP_DC 5'd03 +`define OR1200_SPR_GROUP_IC 5'd04 +`define OR1200_SPR_GROUP_MAC 5'd05 +`define OR1200_SPR_GROUP_DU 5'd06 +`define OR1200_SPR_GROUP_PM 5'd08 +`define OR1200_SPR_GROUP_PIC 5'd09 +`define OR1200_SPR_GROUP_TT 5'd10 +`define OR1200_SPR_GROUP_FPU 5'd11 + +///////////////////////////////////////////////////// +// +// System group +// + +// +// System registers +// +`define OR1200_SPR_CFGR 7'd0 +`define OR1200_SPR_RF 6'd32 // 1024 >> 5 +`define OR1200_SPR_NPC 11'd16 +`define OR1200_SPR_SR 11'd17 +`define OR1200_SPR_PPC 11'd18 +`define OR1200_SPR_FPCSR 11'd20 +`define OR1200_SPR_EPCR 11'd32 +`define OR1200_SPR_EEAR 11'd48 +`define OR1200_SPR_ESR 11'd64 + +// +// SR bits +// +`define OR1200_SR_WIDTH 17 +`define OR1200_SR_SM 0 +`define OR1200_SR_TEE 1 +`define OR1200_SR_IEE 2 +`define OR1200_SR_DCE 3 +`define OR1200_SR_ICE 4 +`define OR1200_SR_DME 5 +`define OR1200_SR_IME 6 +`define OR1200_SR_LEE 7 +`define OR1200_SR_CE 8 +`define OR1200_SR_F 9 +`define OR1200_SR_CY 10 // Optional +`define OR1200_SR_OV 11 // Optional +`define OR1200_SR_OVE 12 // Optional +`define OR1200_SR_DSX 13 // Unused +`define OR1200_SR_EPH 14 +`define OR1200_SR_FO 15 +`define OR1200_SR_TED 16 +`define OR1200_SR_CID 31:28 // Unimplemented + +// +// Bits that define offset inside the group +// +`define OR1200_SPROFS_BITS 10:0 + +// +// Default Exception Prefix +// +// 1'b0 - OR1200_EXCEPT_EPH0_P (0x0000_0000) +// 1'b1 - OR1200_EXCEPT_EPH1_P (0xF000_0000) +// +`define OR1200_SR_EPH_DEF 1'b0 + + +// +// FPCSR bits +// +`define OR1200_FPCSR_WIDTH 12 +`define OR1200_FPCSR_FPEE 0 +`define OR1200_FPCSR_RM 2:1 +`define OR1200_FPCSR_OVF 3 +`define OR1200_FPCSR_UNF 4 +`define OR1200_FPCSR_SNF 5 +`define OR1200_FPCSR_QNF 6 +`define OR1200_FPCSR_ZF 7 +`define OR1200_FPCSR_IXF 8 +`define OR1200_FPCSR_IVF 9 +`define OR1200_FPCSR_INF 10 +`define OR1200_FPCSR_DZF 11 +`define OR1200_FPCSR_RES 31:12 + +///////////////////////////////////////////////////// +// +// Power Management (PM) +// + +// Define it if you want PM implemented +//`define OR1200_PM_IMPLEMENTED + +// Bit positions inside PMR (don't change) +`define OR1200_PM_PMR_SDF 3:0 +`define OR1200_PM_PMR_DME 4 +`define OR1200_PM_PMR_SME 5 +`define OR1200_PM_PMR_DCGE 6 +`define OR1200_PM_PMR_UNUSED 31:7 + +// PMR offset inside PM group of registers +`define OR1200_PM_OFS_PMR 11'b0 + +// PM group +`define OR1200_SPRGRP_PM 5'd8 + +// Define if PMR can be read/written at any address inside PM group +`define OR1200_PM_PARTIAL_DECODING + +// Define if reading PMR is allowed +`define OR1200_PM_READREGS + +// Define if unused PMR bits should be zero +`define OR1200_PM_UNUSED_ZERO + + +///////////////////////////////////////////////////// +// +// Debug Unit (DU) +// + +// Define it if you want DU implemented +`define OR1200_DU_IMPLEMENTED + +// +// Define if you want HW Breakpoints +// (if HW breakpoints are not implemented +// only default software trapping is +// possible with l.trap insn - this is +// however already enough for use +// with or32 gdb) +// +//`define OR1200_DU_HWBKPTS + +// Number of DVR/DCR pairs if HW breakpoints enabled +// Comment / uncomment DU_DVRn / DU_DCRn pairs bellow according to this number ! +// DU_DVR0..DU_DVR7 should be uncommented for 8 DU_DVRDCR_PAIRS +`define OR1200_DU_DVRDCR_PAIRS 8 + +// Define if you want trace buffer +// (for now only available for Xilinx Virtex FPGAs) +//`define OR1200_DU_TB_IMPLEMENTED + + +// +// Address offsets of DU registers inside DU group +// +// To not implement a register, doq not define its address +// +`ifdef OR1200_DU_HWBKPTS +`define OR1200_DU_DVR0 11'd0 +`define OR1200_DU_DVR1 11'd1 +`define OR1200_DU_DVR2 11'd2 +`define OR1200_DU_DVR3 11'd3 +`define OR1200_DU_DVR4 11'd4 +`define OR1200_DU_DVR5 11'd5 +`define OR1200_DU_DVR6 11'd6 +`define OR1200_DU_DVR7 11'd7 +`define OR1200_DU_DCR0 11'd8 +`define OR1200_DU_DCR1 11'd9 +`define OR1200_DU_DCR2 11'd10 +`define OR1200_DU_DCR3 11'd11 +`define OR1200_DU_DCR4 11'd12 +`define OR1200_DU_DCR5 11'd13 +`define OR1200_DU_DCR6 11'd14 +`define OR1200_DU_DCR7 11'd15 +`endif +`define OR1200_DU_DMR1 11'd16 +`ifdef OR1200_DU_HWBKPTS +`define OR1200_DU_DMR2 11'd17 +`define OR1200_DU_DWCR0 11'd18 +`define OR1200_DU_DWCR1 11'd19 +`endif +`define OR1200_DU_DSR 11'd20 +`define OR1200_DU_DRR 11'd21 +`ifdef OR1200_DU_TB_IMPLEMENTED +`define OR1200_DU_TBADR 11'h0ff +`define OR1200_DU_TBIA 11'h1?? +`define OR1200_DU_TBIM 11'h2?? +`define OR1200_DU_TBAR 11'h3?? +`define OR1200_DU_TBTS 11'h4?? +`endif + +// Position of offset bits inside SPR address +`define OR1200_DUOFS_BITS 10:0 + +// DCR bits +`define OR1200_DU_DCR_DP 0 +`define OR1200_DU_DCR_CC 3:1 +`define OR1200_DU_DCR_SC 4 +`define OR1200_DU_DCR_CT 7:5 + +// DMR1 bits +`define OR1200_DU_DMR1_CW0 1:0 +`define OR1200_DU_DMR1_CW1 3:2 +`define OR1200_DU_DMR1_CW2 5:4 +`define OR1200_DU_DMR1_CW3 7:6 +`define OR1200_DU_DMR1_CW4 9:8 +`define OR1200_DU_DMR1_CW5 11:10 +`define OR1200_DU_DMR1_CW6 13:12 +`define OR1200_DU_DMR1_CW7 15:14 +`define OR1200_DU_DMR1_CW8 17:16 +`define OR1200_DU_DMR1_CW9 19:18 +`define OR1200_DU_DMR1_CW10 21:20 +`define OR1200_DU_DMR1_ST 22 +`define OR1200_DU_DMR1_BT 23 +`define OR1200_DU_DMR1_DXFW 24 +`define OR1200_DU_DMR1_ETE 25 + +// DMR2 bits +`define OR1200_DU_DMR2_WCE0 0 +`define OR1200_DU_DMR2_WCE1 1 +`define OR1200_DU_DMR2_AWTC 12:2 +`define OR1200_DU_DMR2_WGB 23:13 + +// DWCR bits +`define OR1200_DU_DWCR_COUNT 15:0 +`define OR1200_DU_DWCR_MATCH 31:16 + +// DSR bits +`define OR1200_DU_DSR_WIDTH 14 +`define OR1200_DU_DSR_RSTE 0 +`define OR1200_DU_DSR_BUSEE 1 +`define OR1200_DU_DSR_DPFE 2 +`define OR1200_DU_DSR_IPFE 3 +`define OR1200_DU_DSR_TTE 4 +`define OR1200_DU_DSR_AE 5 +`define OR1200_DU_DSR_IIE 6 +`define OR1200_DU_DSR_IE 7 +`define OR1200_DU_DSR_DME 8 +`define OR1200_DU_DSR_IME 9 +`define OR1200_DU_DSR_RE 10 +`define OR1200_DU_DSR_SCE 11 +`define OR1200_DU_DSR_FPE 12 +`define OR1200_DU_DSR_TE 13 + +// DRR bits +`define OR1200_DU_DRR_RSTE 0 +`define OR1200_DU_DRR_BUSEE 1 +`define OR1200_DU_DRR_DPFE 2 +`define OR1200_DU_DRR_IPFE 3 +`define OR1200_DU_DRR_TTE 4 +`define OR1200_DU_DRR_AE 5 +`define OR1200_DU_DRR_IIE 6 +`define OR1200_DU_DRR_IE 7 +`define OR1200_DU_DRR_DME 8 +`define OR1200_DU_DRR_IME 9 +`define OR1200_DU_DRR_RE 10 +`define OR1200_DU_DRR_SCE 11 +`define OR1200_DU_DRR_FPE 12 +`define OR1200_DU_DRR_TE 13 + +// Define if reading DU regs is allowed +`define OR1200_DU_READREGS + +// Define if unused DU registers bits should be zero +`define OR1200_DU_UNUSED_ZERO + +// Define if IF/LSU status is not needed by devel i/f +`define OR1200_DU_STATUS_UNIMPLEMENTED + +///////////////////////////////////////////////////// +// +// Programmable Interrupt Controller (PIC) +// + +// Define it if you want PIC implemented +`define OR1200_PIC_IMPLEMENTED + +// Define number of interrupt inputs (2-31) +`define OR1200_PIC_INTS 20 + +// Address offsets of PIC registers inside PIC group +`define OR1200_PIC_OFS_PICMR 2'd0 +`define OR1200_PIC_OFS_PICSR 2'd2 + +// Position of offset bits inside SPR address +`define OR1200_PICOFS_BITS 1:0 + +// Define if you want these PIC registers to be implemented +`define OR1200_PIC_PICMR +`define OR1200_PIC_PICSR + +// Define if reading PIC registers is allowed +`define OR1200_PIC_READREGS + +// Define if unused PIC register bits should be zero +`define OR1200_PIC_UNUSED_ZERO + + +///////////////////////////////////////////////////// +// +// Tick Timer (TT) +// + +// Define it if you want TT implemented +`define OR1200_TT_IMPLEMENTED + +// Address offsets of TT registers inside TT group +`define OR1200_TT_OFS_TTMR 1'd0 +`define OR1200_TT_OFS_TTCR 1'd1 + +// Position of offset bits inside SPR group +`define OR1200_TTOFS_BITS 0 + +// Define if you want these TT registers to be implemented +`define OR1200_TT_TTMR +`define OR1200_TT_TTCR + +// TTMR bits +`define OR1200_TT_TTMR_TP 27:0 +`define OR1200_TT_TTMR_IP 28 +`define OR1200_TT_TTMR_IE 29 +`define OR1200_TT_TTMR_M 31:30 + +// Define if reading TT registers is allowed +`define OR1200_TT_READREGS + + +////////////////////////////////////////////// +// +// MAC +// +`define OR1200_MAC_ADDR 0 // MACLO 0xxxxxxxx1, MACHI 0xxxxxxxx0 +`define OR1200_MAC_SPR_WE // Define if MACLO/MACHI are SPR writable + +// +// Shift {MACHI,MACLO} into destination register when executing l.macrc +// +// According to architecture manual there is no shift, so default value is 0. +// However the implementation has deviated in this from the arch manual and had +// hard coded shift by 28 bits which is a useful optimization for MP3 decoding +// (if using libmad fixed point library). Shifts are no longer default setup, +// but if you need to remain backward compatible, define your shift bits, which +// were normally +// dest_GPR = {MACHI,MACLO}[59:28] +`define OR1200_MAC_SHIFTBY 0 // 0 = According to arch manual, 28 = obsolete backward compatibility + + +////////////////////////////////////////////// +// +// Data MMU (DMMU) +// + +// +// Address that selects between TLB TR and MR +// +`define OR1200_DTLB_TM_ADDR 7 + +// +// DTLBMR fields +// +`define OR1200_DTLBMR_V_BITS 0 +`define OR1200_DTLBMR_CID_BITS 4:1 +`define OR1200_DTLBMR_RES_BITS 11:5 +`define OR1200_DTLBMR_VPN_BITS 31:13 + +// +// DTLBTR fields +// +`define OR1200_DTLBTR_CC_BITS 0 +`define OR1200_DTLBTR_CI_BITS 1 +`define OR1200_DTLBTR_WBC_BITS 2 +`define OR1200_DTLBTR_WOM_BITS 3 +`define OR1200_DTLBTR_A_BITS 4 +`define OR1200_DTLBTR_D_BITS 5 +`define OR1200_DTLBTR_URE_BITS 6 +`define OR1200_DTLBTR_UWE_BITS 7 +`define OR1200_DTLBTR_SRE_BITS 8 +`define OR1200_DTLBTR_SWE_BITS 9 +`define OR1200_DTLBTR_RES_BITS 11:10 +`define OR1200_DTLBTR_PPN_BITS 31:13 + +// +// DTLB configuration +// +`define OR1200_DMMU_PS 13 // 13 for 8KB page size +`define OR1200_DTLB_INDXW 6 // 6 for 64 entry DTLB 7 for 128 entries +`define OR1200_DTLB_INDXL `OR1200_DMMU_PS // 13 13 +`define OR1200_DTLB_INDXH `OR1200_DMMU_PS+`OR1200_DTLB_INDXW-1 // 18 19 +`define OR1200_DTLB_INDX `OR1200_DTLB_INDXH:`OR1200_DTLB_INDXL // 18:13 19:13 +`define OR1200_DTLB_TAGW 32-`OR1200_DTLB_INDXW-`OR1200_DMMU_PS // 13 12 +`define OR1200_DTLB_TAGL `OR1200_DTLB_INDXH+1 // 19 20 +`define OR1200_DTLB_TAG 31:`OR1200_DTLB_TAGL // 31:19 31:20 +`define OR1200_DTLBMRW `OR1200_DTLB_TAGW+1 // +1 because of V bit +`define OR1200_DTLBTRW 32-`OR1200_DMMU_PS+5 // +5 because of protection bits and CI + +// +// Cache inhibit while DMMU is not enabled/implemented +// +// cache inhibited 0GB-4GB 1'b1 +// cache inhibited 0GB-2GB !dcpu_adr_i[31] +// cache inhibited 0GB-1GB 2GB-3GB !dcpu_adr_i[30] +// cache inhibited 1GB-2GB 3GB-4GB dcpu_adr_i[30] +// cache inhibited 2GB-4GB (default) dcpu_adr_i[31] +// cached 0GB-4GB 1'b0 +// +`define OR1200_DMMU_CI dcpu_adr_i[31] + + +////////////////////////////////////////////// +// +// Insn MMU (IMMU) +// + +// +// Address that selects between TLB TR and MR +// +`define OR1200_ITLB_TM_ADDR 7 + +// +// ITLBMR fields +// +`define OR1200_ITLBMR_V_BITS 0 +`define OR1200_ITLBMR_CID_BITS 4:1 +`define OR1200_ITLBMR_RES_BITS 11:5 +`define OR1200_ITLBMR_VPN_BITS 31:13 + +// +// ITLBTR fields +// +`define OR1200_ITLBTR_CC_BITS 0 +`define OR1200_ITLBTR_CI_BITS 1 +`define OR1200_ITLBTR_WBC_BITS 2 +`define OR1200_ITLBTR_WOM_BITS 3 +`define OR1200_ITLBTR_A_BITS 4 +`define OR1200_ITLBTR_D_BITS 5 +`define OR1200_ITLBTR_SXE_BITS 6 +`define OR1200_ITLBTR_UXE_BITS 7 +`define OR1200_ITLBTR_RES_BITS 11:8 +`define OR1200_ITLBTR_PPN_BITS 31:13 + +// +// ITLB configuration +// +`define OR1200_IMMU_PS 13 // 13 for 8KB page size +`define OR1200_ITLB_INDXW 6 // 6 for 64 entry ITLB 7 for 128 entries +`define OR1200_ITLB_INDXL `OR1200_IMMU_PS // 13 13 +`define OR1200_ITLB_INDXH `OR1200_IMMU_PS+`OR1200_ITLB_INDXW-1 // 18 19 +`define OR1200_ITLB_INDX `OR1200_ITLB_INDXH:`OR1200_ITLB_INDXL // 18:13 19:13 +`define OR1200_ITLB_TAGW 32-`OR1200_ITLB_INDXW-`OR1200_IMMU_PS // 13 12 +`define OR1200_ITLB_TAGL `OR1200_ITLB_INDXH+1 // 19 20 +`define OR1200_ITLB_TAG 31:`OR1200_ITLB_TAGL // 31:19 31:20 +`define OR1200_ITLBMRW `OR1200_ITLB_TAGW+1 // +1 because of V bit +`define OR1200_ITLBTRW 32-`OR1200_IMMU_PS+3 // +3 because of protection bits and CI + +// +// Cache inhibit while IMMU is not enabled/implemented +// Note: all combinations that use icpu_adr_i cause async loop +// +// cache inhibited 0GB-4GB 1'b1 +// cache inhibited 0GB-2GB !icpu_adr_i[31] +// cache inhibited 0GB-1GB 2GB-3GB !icpu_adr_i[30] +// cache inhibited 1GB-2GB 3GB-4GB icpu_adr_i[30] +// cache inhibited 2GB-4GB (default) icpu_adr_i[31] +// cached 0GB-4GB 1'b0 +// +`define OR1200_IMMU_CI 1'b0 + + +///////////////////////////////////////////////// +// +// Insn cache (IC) +// + +// 4 for 16 byte line, 5 for 32 byte lines. +`ifdef OR1200_IC_1W_32KB + `define OR1200_ICLS 5 +`else + `define OR1200_ICLS 4 +`endif + +// +// IC configurations +// +`ifdef OR1200_IC_1W_512B +`define OR1200_ICSIZE 9 // 512 +`define OR1200_ICINDX `OR1200_ICSIZE-2 // 7 +`define OR1200_ICINDXH `OR1200_ICSIZE-1 // 8 +`define OR1200_ICTAGL `OR1200_ICINDXH+1 // 9 +`define OR1200_ICTAG `OR1200_ICSIZE-`OR1200_ICLS // 5 +`define OR1200_ICTAG_W 24 +`endif +`ifdef OR1200_IC_1W_4KB +`define OR1200_ICSIZE 12 // 4096 +`define OR1200_ICINDX `OR1200_ICSIZE-2 // 10 +`define OR1200_ICINDXH `OR1200_ICSIZE-1 // 11 +`define OR1200_ICTAGL `OR1200_ICINDXH+1 // 12 +`define OR1200_ICTAG `OR1200_ICSIZE-`OR1200_ICLS // 8 +`define OR1200_ICTAG_W 21 +`endif +`ifdef OR1200_IC_1W_8KB +`define OR1200_ICSIZE 13 // 8192 +`define OR1200_ICINDX `OR1200_ICSIZE-2 // 11 +`define OR1200_ICINDXH `OR1200_ICSIZE-1 // 12 +`define OR1200_ICTAGL `OR1200_ICINDXH+1 // 13 +`define OR1200_ICTAG `OR1200_ICSIZE-`OR1200_ICLS // 9 +`define OR1200_ICTAG_W 20 +`endif +`ifdef OR1200_IC_1W_16KB +`define OR1200_ICSIZE 14 // 16384 +`define OR1200_ICINDX `OR1200_ICSIZE-2 // 12 +`define OR1200_ICINDXH `OR1200_ICSIZE-1 // 13 +`define OR1200_ICTAGL `OR1200_ICINDXH+1 // 14 +`define OR1200_ICTAG `OR1200_ICSIZE-`OR1200_ICLS // 10 +`define OR1200_ICTAG_W 19 +`endif +`ifdef OR1200_IC_1W_32KB +`define OR1200_ICSIZE 15 // 32768 +`define OR1200_ICINDX `OR1200_ICSIZE-2 // 13 +`define OR1200_ICINDXH `OR1200_ICSIZE-1 // 14 +`define OR1200_ICTAGL `OR1200_ICINDXH+1 // 14 +`define OR1200_ICTAG `OR1200_ICSIZE-`OR1200_ICLS // 10 +`define OR1200_ICTAG_W 18 +`endif + + +///////////////////////////////////////////////// +// +// Data cache (DC) +// + +// 4 for 16 bytes, 5 for 32 bytes +`ifdef OR1200_DC_1W_32KB + `define OR1200_DCLS 5 +`else + `define OR1200_DCLS 4 +`endif + +// Define to enable default behavior of cache as write through +// Turning this off enabled write back statergy +// +`define OR1200_DC_WRITETHROUGH + +// Define to enable stores from the stack not doing writethrough. +// EXPERIMENTAL +//`define OR1200_DC_NOSTACKWRITETHROUGH + +// Data cache SPR definitions +`define OR1200_SPRGRP_DC_ADR_WIDTH 3 +// Data cache group SPR addresses +`define OR1200_SPRGRP_DC_DCCR 3'd0 // Not implemented +`define OR1200_SPRGRP_DC_DCBPR 3'd1 // Not implemented +`define OR1200_SPRGRP_DC_DCBFR 3'd2 +`define OR1200_SPRGRP_DC_DCBIR 3'd3 +`define OR1200_SPRGRP_DC_DCBWR 3'd4 // Not implemented +`define OR1200_SPRGRP_DC_DCBLR 3'd5 // Not implemented + +// +// DC configurations +// +`ifdef OR1200_DC_1W_4KB +`define OR1200_DCSIZE 12 // 4096 +`define OR1200_DCINDX `OR1200_DCSIZE-2 // 10 +`define OR1200_DCINDXH `OR1200_DCSIZE-1 // 11 +`define OR1200_DCTAGL `OR1200_DCINDXH+1 // 12 +`define OR1200_DCTAG `OR1200_DCSIZE-`OR1200_DCLS // 8 +`define OR1200_DCTAG_W 21 +`endif +`ifdef OR1200_DC_1W_8KB +`define OR1200_DCSIZE 13 // 8192 +`define OR1200_DCINDX `OR1200_DCSIZE-2 // 11 +`define OR1200_DCINDXH `OR1200_DCSIZE-1 // 12 +`define OR1200_DCTAGL `OR1200_DCINDXH+1 // 13 +`define OR1200_DCTAG `OR1200_DCSIZE-`OR1200_DCLS // 9 +`define OR1200_DCTAG_W 20 +`endif +`ifdef OR1200_DC_1W_16KB +`define OR1200_DCSIZE 14 // 16384 +`define OR1200_DCINDX `OR1200_DCSIZE-2 // 12 +`define OR1200_DCINDXH `OR1200_DCSIZE-1 // 13 +`define OR1200_DCTAGL `OR1200_DCINDXH+1 // 14 +`define OR1200_DCTAG `OR1200_DCSIZE-`OR1200_DCLS // 10 +`define OR1200_DCTAG_W 19 +`endif +`ifdef OR1200_DC_1W_32KB +`define OR1200_DCSIZE 15 // 32768 +`define OR1200_DCINDX `OR1200_DCSIZE-2 // 13 +`define OR1200_DCINDXH `OR1200_DCSIZE-1 // 14 +`define OR1200_DCTAGL `OR1200_DCINDXH+1 // 15 +`define OR1200_DCTAG `OR1200_DCSIZE-`OR1200_DCLS // 10 +`define OR1200_DCTAG_W 18 +`endif + + +///////////////////////////////////////////////// +// +// Store buffer (SB) +// + +// +// Store buffer +// +// It will improve performance by "caching" CPU stores +// using store buffer. This is most important for function +// prologues because DC can only work in write though mode +// and all stores would have to complete external WB writes +// to memory. +// Store buffer is between DC and data BIU. +// All stores will be stored into store buffer and immediately +// completed by the CPU, even though actual external writes +// will be performed later. As a consequence store buffer masks +// all data bus errors related to stores (data bus errors +// related to loads are delivered normally). +// All pending CPU loads will wait until store buffer is empty to +// ensure strict memory model. Right now this is necessary because +// we don't make destinction between cached and cache inhibited +// address space, so we simply empty store buffer until loads +// can begin. +// +// It makes design a bit bigger, depending what is the number of +// entries in SB FIFO. Number of entries can be changed further +// down. +// +//`define OR1200_SB_IMPLEMENTED + +// +// Number of store buffer entries +// +// Verified number of entries are 4 and 8 entries +// (2 and 3 for OR1200_SB_LOG). OR1200_SB_ENTRIES must +// always match 2**OR1200_SB_LOG. +// To disable store buffer, undefine +// OR1200_SB_IMPLEMENTED. +// +`define OR1200_SB_LOG 2 // 2 or 3 +`define OR1200_SB_ENTRIES 4 // 4 or 8 + + +///////////////////////////////////////////////// +// +// Quick Embedded Memory (QMEM) +// + +// +// Quick Embedded Memory +// +// Instantiation of dedicated insn/data memory (RAM or ROM). +// Insn fetch has effective throughput 1insn / clock cycle. +// Data load takes two clock cycles / access, data store +// takes 1 clock cycle / access (if there is no insn fetch)). +// Memory instantiation is shared between insn and data, +// meaning if insn fetch are performed, data load/store +// performance will be lower. +// +// Main reason for QMEM is to put some time critical functions +// into this memory and to have predictable and fast access +// to these functions. (soft fpu, context switch, exception +// handlers, stack, etc) +// +// It makes design a bit bigger and slower. QMEM sits behind +// IMMU/DMMU so all addresses are physical (so the MMUs can be +// used with QMEM and QMEM is seen by the CPU just like any other +// memory in the system). IC/DC are sitting behind QMEM so the +// whole design timing might be worse with QMEM implemented. +// +//`define OR1200_QMEM_IMPLEMENTED + +// +// Base address and mask of QMEM +// +// Base address defines first address of QMEM. Mask defines +// QMEM range in address space. Actual size of QMEM is however +// determined with instantiated RAM/ROM. However bigger +// mask will reserve more address space for QMEM, but also +// make design faster, while more tight mask will take +// less address space but also make design slower. If +// instantiated RAM/ROM is smaller than space reserved with +// the mask, instatiated RAM/ROM will also be shadowed +// at higher addresses in reserved space. +// +`define OR1200_QMEM_IADDR 32'h0080_0000 +`define OR1200_QMEM_IMASK 32'hfff0_0000 // Max QMEM size 1MB +`define OR1200_QMEM_DADDR 32'h0080_0000 +`define OR1200_QMEM_DMASK 32'hfff0_0000 // Max QMEM size 1MB + +// +// QMEM interface byte-select capability +// +// To enable qmem_sel* ports, define this macro. +// +//`define OR1200_QMEM_BSEL + +// +// QMEM interface acknowledge +// +// To enable qmem_ack port, define this macro. +// +//`define OR1200_QMEM_ACK + +///////////////////////////////////////////////////// +// +// VR, UPR and Configuration Registers +// +// +// VR, UPR and configuration registers are optional. If +// implemented, operating system can automatically figure +// out how to use the processor because it knows +// what units are available in the processor and how they +// are configured. +// +// This section must be last in or1200_defines.v file so +// that all units are already configured and thus +// configuration registers are properly set. +// + +// Define if you want configuration registers implemented +//`define OR1200_CFGR_IMPLEMENTED + +// Define if you want full address decode inside SYS group +`define OR1200_SYS_FULL_DECODE + +// Offsets of VR, UPR and CFGR registers +`define OR1200_SPRGRP_SYS_VR 4'h0 +`define OR1200_SPRGRP_SYS_UPR 4'h1 +`define OR1200_SPRGRP_SYS_CPUCFGR 4'h2 +`define OR1200_SPRGRP_SYS_DMMUCFGR 4'h3 +`define OR1200_SPRGRP_SYS_IMMUCFGR 4'h4 +`define OR1200_SPRGRP_SYS_DCCFGR 4'h5 +`define OR1200_SPRGRP_SYS_ICCFGR 4'h6 +`define OR1200_SPRGRP_SYS_DCFGR 4'h7 + +// VR fields +`define OR1200_VR_REV_BITS 5:0 +`define OR1200_VR_RES1_BITS 15:6 +`define OR1200_VR_CFG_BITS 23:16 +`define OR1200_VR_VER_BITS 31:24 + +// VR values +`define OR1200_VR_REV 6'h08 +`define OR1200_VR_RES1 10'h000 +`define OR1200_VR_CFG 8'h00 +`define OR1200_VR_VER 8'h12 + +// UPR fields +`define OR1200_UPR_UP_BITS 0 +`define OR1200_UPR_DCP_BITS 1 +`define OR1200_UPR_ICP_BITS 2 +`define OR1200_UPR_DMP_BITS 3 +`define OR1200_UPR_IMP_BITS 4 +`define OR1200_UPR_MP_BITS 5 +`define OR1200_UPR_DUP_BITS 6 +`define OR1200_UPR_PCUP_BITS 7 +`define OR1200_UPR_PMP_BITS 8 +`define OR1200_UPR_PICP_BITS 9 +`define OR1200_UPR_TTP_BITS 10 +`define OR1200_UPR_FPP_BITS 11 +`define OR1200_UPR_RES1_BITS 23:12 +`define OR1200_UPR_CUP_BITS 31:24 + +// UPR values +`define OR1200_UPR_UP 1'b1 +`ifdef OR1200_NO_DC +`define OR1200_UPR_DCP 1'b0 +`else +`define OR1200_UPR_DCP 1'b1 +`endif +`ifdef OR1200_NO_IC +`define OR1200_UPR_ICP 1'b0 +`else +`define OR1200_UPR_ICP 1'b1 +`endif +`ifdef OR1200_NO_DMMU +`define OR1200_UPR_DMP 1'b0 +`else +`define OR1200_UPR_DMP 1'b1 +`endif +`ifdef OR1200_NO_IMMU +`define OR1200_UPR_IMP 1'b0 +`else +`define OR1200_UPR_IMP 1'b1 +`endif +`ifdef OR1200_MAC_IMPLEMENTED +`define OR1200_UPR_MP 1'b1 +`else +`define OR1200_UPR_MP 1'b0 +`endif +`ifdef OR1200_DU_IMPLEMENTED +`define OR1200_UPR_DUP 1'b1 +`else +`define OR1200_UPR_DUP 1'b0 +`endif +`define OR1200_UPR_PCUP 1'b0 // Performance counters not present +`ifdef OR1200_PM_IMPLEMENTED +`define OR1200_UPR_PMP 1'b1 +`else +`define OR1200_UPR_PMP 1'b0 +`endif +`ifdef OR1200_PIC_IMPLEMENTED +`define OR1200_UPR_PICP 1'b1 +`else +`define OR1200_UPR_PICP 1'b0 +`endif +`ifdef OR1200_TT_IMPLEMENTED +`define OR1200_UPR_TTP 1'b1 +`else +`define OR1200_UPR_TTP 1'b0 +`endif +`ifdef OR1200_FPU_IMPLEMENTED +`define OR1200_UPR_FPP 1'b1 +`else +`define OR1200_UPR_FPP 1'b0 +`endif +`define OR1200_UPR_RES1 12'h000 +`define OR1200_UPR_CUP 8'h00 + +// CPUCFGR fields +`define OR1200_CPUCFGR_NSGF_BITS 3:0 +`define OR1200_CPUCFGR_HGF_BITS 4 +`define OR1200_CPUCFGR_OB32S_BITS 5 +`define OR1200_CPUCFGR_OB64S_BITS 6 +`define OR1200_CPUCFGR_OF32S_BITS 7 +`define OR1200_CPUCFGR_OF64S_BITS 8 +`define OR1200_CPUCFGR_OV64S_BITS 9 +`define OR1200_CPUCFGR_RES1_BITS 31:10 + +// CPUCFGR values +`define OR1200_CPUCFGR_NSGF 4'h0 +`ifdef OR1200_RFRAM_16REG + `define OR1200_CPUCFGR_HGF 1'b1 +`else + `define OR1200_CPUCFGR_HGF 1'b0 +`endif +`define OR1200_CPUCFGR_OB32S 1'b1 +`define OR1200_CPUCFGR_OB64S 1'b0 +`ifdef OR1200_FPU_IMPLEMENTED + `define OR1200_CPUCFGR_OF32S 1'b1 +`else + `define OR1200_CPUCFGR_OF32S 1'b0 +`endif + +`define OR1200_CPUCFGR_OF64S 1'b0 +`define OR1200_CPUCFGR_OV64S 1'b0 +`define OR1200_CPUCFGR_RES1 22'h000000 + +// DMMUCFGR fields +`define OR1200_DMMUCFGR_NTW_BITS 1:0 +`define OR1200_DMMUCFGR_NTS_BITS 4:2 +`define OR1200_DMMUCFGR_NAE_BITS 7:5 +`define OR1200_DMMUCFGR_CRI_BITS 8 +`define OR1200_DMMUCFGR_PRI_BITS 9 +`define OR1200_DMMUCFGR_TEIRI_BITS 10 +`define OR1200_DMMUCFGR_HTR_BITS 11 +`define OR1200_DMMUCFGR_RES1_BITS 31:12 + +// DMMUCFGR values +`ifdef OR1200_NO_DMMU +`define OR1200_DMMUCFGR_NTW 2'h0 // Irrelevant +`define OR1200_DMMUCFGR_NTS 3'h0 // Irrelevant +`define OR1200_DMMUCFGR_NAE 3'h0 // Irrelevant +`define OR1200_DMMUCFGR_CRI 1'b0 // Irrelevant +`define OR1200_DMMUCFGR_PRI 1'b0 // Irrelevant +`define OR1200_DMMUCFGR_TEIRI 1'b0 // Irrelevant +`define OR1200_DMMUCFGR_HTR 1'b0 // Irrelevant +`define OR1200_DMMUCFGR_RES1 20'h00000 +`else +`define OR1200_DMMUCFGR_NTW 2'h0 // 1 TLB way +`define OR1200_DMMUCFGR_NTS 3'h`OR1200_DTLB_INDXW // Num TLB sets +`define OR1200_DMMUCFGR_NAE 3'h0 // No ATB entries +`define OR1200_DMMUCFGR_CRI 1'b0 // No control register +`define OR1200_DMMUCFGR_PRI 1'b0 // No protection reg +`define OR1200_DMMUCFGR_TEIRI 1'b0 // TLB entry inv reg NOT impl. +`define OR1200_DMMUCFGR_HTR 1'b0 // No HW TLB reload +`define OR1200_DMMUCFGR_RES1 20'h00000 +`endif + +// IMMUCFGR fields +`define OR1200_IMMUCFGR_NTW_BITS 1:0 +`define OR1200_IMMUCFGR_NTS_BITS 4:2 +`define OR1200_IMMUCFGR_NAE_BITS 7:5 +`define OR1200_IMMUCFGR_CRI_BITS 8 +`define OR1200_IMMUCFGR_PRI_BITS 9 +`define OR1200_IMMUCFGR_TEIRI_BITS 10 +`define OR1200_IMMUCFGR_HTR_BITS 11 +`define OR1200_IMMUCFGR_RES1_BITS 31:12 + +// IMMUCFGR values +`ifdef OR1200_NO_IMMU +`define OR1200_IMMUCFGR_NTW 2'h0 // Irrelevant +`define OR1200_IMMUCFGR_NTS 3'h0 // Irrelevant +`define OR1200_IMMUCFGR_NAE 3'h0 // Irrelevant +`define OR1200_IMMUCFGR_CRI 1'b0 // Irrelevant +`define OR1200_IMMUCFGR_PRI 1'b0 // Irrelevant +`define OR1200_IMMUCFGR_TEIRI 1'b0 // Irrelevant +`define OR1200_IMMUCFGR_HTR 1'b0 // Irrelevant +`define OR1200_IMMUCFGR_RES1 20'h00000 +`else +`define OR1200_IMMUCFGR_NTW 2'h0 // 1 TLB way +`define OR1200_IMMUCFGR_NTS 3'h`OR1200_ITLB_INDXW // Num TLB sets +`define OR1200_IMMUCFGR_NAE 3'h0 // No ATB entry +`define OR1200_IMMUCFGR_CRI 1'b0 // No control reg +`define OR1200_IMMUCFGR_PRI 1'b0 // No protection reg +`define OR1200_IMMUCFGR_TEIRI 1'b0 // TLB entry inv reg NOT impl +`define OR1200_IMMUCFGR_HTR 1'b0 // No HW TLB reload +`define OR1200_IMMUCFGR_RES1 20'h00000 +`endif + +// DCCFGR fields +`define OR1200_DCCFGR_NCW_BITS 2:0 +`define OR1200_DCCFGR_NCS_BITS 6:3 +`define OR1200_DCCFGR_CBS_BITS 7 +`define OR1200_DCCFGR_CWS_BITS 8 +`define OR1200_DCCFGR_CCRI_BITS 9 +`define OR1200_DCCFGR_CBIRI_BITS 10 +`define OR1200_DCCFGR_CBPRI_BITS 11 +`define OR1200_DCCFGR_CBLRI_BITS 12 +`define OR1200_DCCFGR_CBFRI_BITS 13 +`define OR1200_DCCFGR_CBWBRI_BITS 14 +`define OR1200_DCCFGR_RES1_BITS 31:15 + +// DCCFGR values +`ifdef OR1200_NO_DC +`define OR1200_DCCFGR_NCW 3'h0 // Irrelevant +`define OR1200_DCCFGR_NCS 4'h0 // Irrelevant +`define OR1200_DCCFGR_CBS 1'b0 // Irrelevant +`define OR1200_DCCFGR_CWS 1'b0 // Irrelevant +`define OR1200_DCCFGR_CCRI 1'b0 // Irrelevant +`define OR1200_DCCFGR_CBIRI 1'b0 // Irrelevant +`define OR1200_DCCFGR_CBPRI 1'b0 // Irrelevant +`define OR1200_DCCFGR_CBLRI 1'b0 // Irrelevant +`define OR1200_DCCFGR_CBFRI 1'b0 // Irrelevant +`define OR1200_DCCFGR_CBWBRI 1'b0 // Irrelevant +`define OR1200_DCCFGR_RES1 17'h00000 +`else +`define OR1200_DCCFGR_NCW 3'h0 // 1 cache way +`define OR1200_DCCFGR_NCS (`OR1200_DCTAG) // Num cache sets +`define OR1200_DCCFGR_CBS `OR1200_DCLS==4 ? 1'b0 : 1'b1 // 16 byte cache block +`ifdef OR1200_DC_WRITETHROUGH + `define OR1200_DCCFGR_CWS 1'b0 // Write-through strategy +`else + `define OR1200_DCCFGR_CWS 1'b1 // Write-back strategy +`endif +`define OR1200_DCCFGR_CCRI 1'b1 // Cache control reg impl. +`define OR1200_DCCFGR_CBIRI 1'b1 // Cache block inv reg impl. +`define OR1200_DCCFGR_CBPRI 1'b0 // Cache block prefetch reg not impl. +`define OR1200_DCCFGR_CBLRI 1'b0 // Cache block lock reg not impl. +`define OR1200_DCCFGR_CBFRI 1'b1 // Cache block flush reg impl. +`ifdef OR1200_DC_WRITETHROUGH + `define OR1200_DCCFGR_CBWBRI 1'b0 // Cache block WB reg not impl. +`else + `define OR1200_DCCFGR_CBWBRI 1'b1 // Cache block WB reg impl. +`endif +`define OR1200_DCCFGR_RES1 17'h00000 +`endif + +// ICCFGR fields +`define OR1200_ICCFGR_NCW_BITS 2:0 +`define OR1200_ICCFGR_NCS_BITS 6:3 +`define OR1200_ICCFGR_CBS_BITS 7 +`define OR1200_ICCFGR_CWS_BITS 8 +`define OR1200_ICCFGR_CCRI_BITS 9 +`define OR1200_ICCFGR_CBIRI_BITS 10 +`define OR1200_ICCFGR_CBPRI_BITS 11 +`define OR1200_ICCFGR_CBLRI_BITS 12 +`define OR1200_ICCFGR_CBFRI_BITS 13 +`define OR1200_ICCFGR_CBWBRI_BITS 14 +`define OR1200_ICCFGR_RES1_BITS 31:15 + +// ICCFGR values +`ifdef OR1200_NO_IC +`define OR1200_ICCFGR_NCW 3'h0 // Irrelevant +`define OR1200_ICCFGR_NCS 4'h0 // Irrelevant +`define OR1200_ICCFGR_CBS 1'b0 // Irrelevant +`define OR1200_ICCFGR_CWS 1'b0 // Irrelevant +`define OR1200_ICCFGR_CCRI 1'b0 // Irrelevant +`define OR1200_ICCFGR_CBIRI 1'b0 // Irrelevant +`define OR1200_ICCFGR_CBPRI 1'b0 // Irrelevant +`define OR1200_ICCFGR_CBLRI 1'b0 // Irrelevant +`define OR1200_ICCFGR_CBFRI 1'b0 // Irrelevant +`define OR1200_ICCFGR_CBWBRI 1'b0 // Irrelevant +`define OR1200_ICCFGR_RES1 17'h00000 +`else +`define OR1200_ICCFGR_NCW 3'h0 // 1 cache way +`define OR1200_ICCFGR_NCS (`OR1200_ICTAG) // Num cache sets +`define OR1200_ICCFGR_CBS `OR1200_ICLS==4 ? 1'b0: 1'b1 // 16 byte cache block +`define OR1200_ICCFGR_CWS 1'b0 // Irrelevant +`define OR1200_ICCFGR_CCRI 1'b1 // Cache control reg impl. +`define OR1200_ICCFGR_CBIRI 1'b1 // Cache block inv reg impl. +`define OR1200_ICCFGR_CBPRI 1'b0 // Cache block prefetch reg not impl. +`define OR1200_ICCFGR_CBLRI 1'b0 // Cache block lock reg not impl. +`define OR1200_ICCFGR_CBFRI 1'b1 // Cache block flush reg impl. +`define OR1200_ICCFGR_CBWBRI 1'b0 // Irrelevant +`define OR1200_ICCFGR_RES1 17'h00000 +`endif + +// DCFGR fields +`define OR1200_DCFGR_NDP_BITS 3:0 +`define OR1200_DCFGR_WPCI_BITS 4 +`define OR1200_DCFGR_RES1_BITS 31:5 + +// DCFGR values +`ifdef OR1200_DU_HWBKPTS +`define OR1200_DCFGR_NDP 4'h`OR1200_DU_DVRDCR_PAIRS // # of DVR/DCR pairs +`ifdef OR1200_DU_DWCR0 +`define OR1200_DCFGR_WPCI 1'b1 +`else +`define OR1200_DCFGR_WPCI 1'b0 // WP counters not impl. +`endif +`else +`define OR1200_DCFGR_NDP 4'h0 // Zero DVR/DCR pairs +`define OR1200_DCFGR_WPCI 1'b0 // WP counters not impl. +`endif +`define OR1200_DCFGR_RES1 27'd0 + +/////////////////////////////////////////////////////////////////////////////// +// Boot Address Selection // +// // +// Allows a definable boot address, potentially different to the usual reset // +// vector to allow for power-on code to be run, if desired. // +// // +// OR1200_BOOT_ADR should be the 32-bit address of the boot location // +// OR1200_BOOT_PCREG_DEFAULT should be ((OR1200_BOOT_ADR-4)>>2) // +// // +// For default reset behavior uncomment the settings under the "Boot 0x100" // +// comment below. // +// // +/////////////////////////////////////////////////////////////////////////////// +// Boot from 0xf0000100 +//`define OR1200_BOOT_PCREG_DEFAULT 30'h3c00003f +//`define OR1200_BOOT_ADR 32'hf0000100 +// Boot from 0x100 + `define OR1200_BOOT_PCREG_DEFAULT 30'h0000003f + `define OR1200_BOOT_ADR 32'h00000100 Index: rc-1.0/backend/spartan3e_starter_kit_eth/minsoc_defines.v =================================================================== --- rc-1.0/backend/spartan3e_starter_kit_eth/minsoc_defines.v (nonexistent) +++ rc-1.0/backend/spartan3e_starter_kit_eth/minsoc_defines.v (revision 109) @@ -0,0 +1,150 @@ +// +// Define FPGA manufacturer +// +//`define GENERIC_FPGA +//`define ALTERA_FPGA +`define XILINX_FPGA + +// +// Define Xilinx FPGA family +// +`ifdef XILINX_FPGA +//`define SPARTAN2 +//`define SPARTAN3 +`define SPARTAN3E +//`define SPARTAN3A +//`define VIRTEX +//`define VIRTEX2 +//`define VIRTEX4 +//`define VIRTEX5 + +// +// Define Altera FPGA family +// +`elsif ALTERA_FPGA +//`define ARRIA_GX +//`define ARRIA_II_GX +//`define CYCLONE_I +//`define CYCLONE_II +`define CYCLONE_III +//`define CYCLONE_III_LS +//`define CYCLONE_IV_E +//`define CYCLONE_IV_GS +//`define MAX_II +//`define MAX_V +//`define MAX3000A +//`define MAX7000AE +//`define MAX7000B +//`define MAX7000S +//`define STRATIX +//`define STRATIX_II +//`define STRATIX_II_GX +//`define STRATIX_III +`endif + +// +// Memory +// +`define MEMORY_ADR_WIDTH 12 //MEMORY_ADR_WIDTH IS NOT ALLOWED TO BE LESS THAN 12, + //memory is composed by blocks of address width 11 + //Address width of memory -> select memory depth, + //2 powers MEMORY_ADR_WIDTH defines the memory depth + //the memory data width is 32 bit, + //memory amount in Bytes = 4*memory depth + +// +// Memory type (uncomment something if ASIC or generic memory) +// +//`define GENERIC_MEMORY +//`define AVANT_ATP +//`define VIRAGE_SSP +//`define VIRTUALSILICON_SSP + + +// +// TAP selection +// +//`define GENERIC_TAP +`define FPGA_TAP + +// +// Clock Division selection +// +//`define NO_CLOCK_DIVISION +//`define GENERIC_CLOCK_DIVISION +`define FPGA_CLOCK_DIVISION // For Altera ALTPLL, only CYCLONE_III family has been tested. + +// +// Define division +// +`define CLOCK_DIVISOR 5 //in case of GENERIC_CLOCK_DIVISION the real value will be rounded + //down to an even value in FPGA case, check minsoc_clock_manager + //for allowed divisors. + //DO NOT USE CLOCK_DIVISOR = 1 COMMENT THE CLOCK DIVISION SELECTION + //INSTEAD. + +// +// Reset polarity +// +//`define NEGATIVE_RESET //rstn +`define POSITIVE_RESET //rst + +// +// Start-up circuit (only necessary later to load firmware automatically from SPI memory) +// +//`define START_UP + +// +// Connected modules +// +`define UART +`define ETHERNET + +// +// Ethernet reset +// +`define ETH_RESET 1'b0 +//`define ETH_RESET 1'b1 + +// +// Interrupts +// +`define APP_INT_RES1 1:0 +`define APP_INT_UART 2 +`define APP_INT_RES2 3 +`define APP_INT_ETH 4 +`define APP_INT_PS2 5 +`define APP_INT_RES3 19:6 + +// +// Address map +// +`define APP_ADDR_DEC_W 8 +`define APP_ADDR_SRAM `APP_ADDR_DEC_W'h00 +`define APP_ADDR_FLASH `APP_ADDR_DEC_W'h04 +`define APP_ADDR_DECP_W 4 +`define APP_ADDR_PERIP `APP_ADDR_DECP_W'h9 +`define APP_ADDR_SPI `APP_ADDR_DEC_W'h97 +`define APP_ADDR_ETH `APP_ADDR_DEC_W'h92 +`define APP_ADDR_AUDIO `APP_ADDR_DEC_W'h9d +`define APP_ADDR_UART `APP_ADDR_DEC_W'h90 +`define APP_ADDR_PS2 `APP_ADDR_DEC_W'h94 +`define APP_ADDR_RES1 `APP_ADDR_DEC_W'h9e +`define APP_ADDR_RES2 `APP_ADDR_DEC_W'h9f + +// +// Set-up GENERIC_TAP, GENERIC_MEMORY if GENERIC_FPGA was chosen +// and GENERIC_CLOCK_DIVISION if NO_CLOCK_DIVISION was not set +// +`ifdef GENERIC_FPGA + `undef FPGA_TAP + `undef FPGA_CLOCK_DIVISION + `undef XILINX_FPGA + `undef SPARTAN3E + + `define GENERIC_TAP + `define GENERIC_MEMORY + `ifndef NO_CLOCK_DIVISION + `define GENERIC_CLOCK_DIVISION + `endif +`endif
rc-1.0/backend/spartan3e_starter_kit_eth/minsoc_defines.v Property changes : Added: svn:executable ## -0,0 +1 ## +* \ No newline at end of property Index: rc-1.0/backend/spartan3e_starter_kit_eth/gcc-opt.mk =================================================================== --- rc-1.0/backend/spartan3e_starter_kit_eth/gcc-opt.mk (nonexistent) +++ rc-1.0/backend/spartan3e_starter_kit_eth/gcc-opt.mk (revision 109) @@ -0,0 +1 @@ +GCC_OPT=-mhard-mul -msoft-div -nostdlib Index: rc-1.0/backend/spartan3e_starter_kit_eth/minsoc_bench_defines.v =================================================================== --- rc-1.0/backend/spartan3e_starter_kit_eth/minsoc_bench_defines.v (nonexistent) +++ rc-1.0/backend/spartan3e_starter_kit_eth/minsoc_bench_defines.v (revision 109) @@ -0,0 +1,26 @@ +//set RTL for simulation, override FPGA specific definitions (JTAG TAP, MEMORY and CLOCK DIVIDER) +`define GENERIC_FPGA +`define MEMORY_MODEL //simulation uses a memory model enabling INITIALIZE_MEMORY_MODEL. If you comment this, START_UP might be interesting. +`define NO_CLOCK_DIVISION //if commented out, generic clock division is implemented (odd divisors are rounded down) +//~set RTL for simulation, override FPGA specific definitions (JTAG TAP, MEMORY and CLOCK DIVIDER) + +`define FREQ_NUM_FOR_NS 1000000000 + +`define FREQ 10000000 +`define CLK_PERIOD (`FREQ_NUM_FOR_NS/`FREQ) + +`define ETH_PHY_FREQ 25000000 +`define ETH_PHY_PERIOD (`FREQ_NUM_FOR_NS/`ETH_PHY_FREQ) //40ns + +`define UART_BAUDRATE 19200 + +`define VPI_DEBUG + +//`define VCD_OUTPUT + +//`define START_UP //pass firmware over spi to or1k_startup + +`define INITIALIZE_MEMORY_MODEL //instantaneously initialize memory model with firmware + //only use with the memory model. + //If you use the original memory (`define MEMORY_MODEL + //commented out), comment this too.
rc-1.0/backend/spartan3e_starter_kit_eth/minsoc_bench_defines.v Property changes : Added: svn:executable ## -0,0 +1 ## +* \ No newline at end of property Index: rc-1.0/backend/spartan3e_starter_kit_eth/spartan3e_starter_kit_eth.ucf =================================================================== --- rc-1.0/backend/spartan3e_starter_kit_eth/spartan3e_starter_kit_eth.ucf (nonexistent) +++ rc-1.0/backend/spartan3e_starter_kit_eth/spartan3e_starter_kit_eth.ucf (revision 109) @@ -0,0 +1,64 @@ +# +# Soldered 50MHz clock. +# +NET "clk" LOC = "C9"; + +# +# Use button "south" as reset. +# +NET "reset" LOC = "K17" | PULLDOWN ; + +# +# UART serial port (RS232 DCE) - connector DB9 female. +# +NET "uart_srx" LOC = "R7"; +NET "uart_stx" LOC = "M14" | DRIVE = 8 | SLEW = SLOW ; + +########################### +## +## ETH +## +NET "eth_txd(3)" LOC = "t5"; +NET "eth_txd(2)" LOC = "r5"; +NET "eth_txd(1)" LOC = "t15"; +NET "eth_txd(0)" LOC = "r11"; + +NET "eth_tx_en" LOC = "p15"; +NET "eth_tx_clk" LOC = "t7" | CLOCK_DEDICATED_ROUTE = FALSE; +NET "eth_tx_er" LOC = "r6"; + +NET "eth_rxd(3)" LOC = "v14"; +NET "eth_rxd(2)" LOC = "u11"; +NET "eth_rxd(1)" LOC = "t11"; +NET "eth_rxd(0)" LOC = "v8"; + +NET "eth_rx_er" LOC = "u14"; +NET "eth_rx_dv" LOC = "v2"; + +NET "eth_rx_clk" LOC = "v3" | CLOCK_DEDICATED_ROUTE = FALSE; + +NET "eth_mdio" LOC = "u5" | PULLUP; +NET "eth_crs" LOC = "u13"; +NET "eth_col" LOC = "u6"; +NET "eth_mdc" LOC = "p9"; + +NET "eth_trste" LOC = "p13"; #put it to a non connected FPGA pin (starter kit schematic BANK3) + +NET "eth_fds_mdint" LOC = "r13" | PULLUP; #put it to a non connected FPGA pin (starter kit schematic BANK3)(pullup not to generate interrupts) +########################### + +# +# JTAG signals - on J4 6-pin accessory header. +# + +#NET "jtag_tms" LOC = "D7" | PULLDOWN ; +#NET "jtag_tdi" LOC = "C7" | PULLDOWN ; +#NET "jtag_tdo" LOC = "F8" | SLEW = FAST | DRIVE = 8 ; +#NET "jtag_tck" LOC = "E8" | PULLDOWN ; + +#net "jtag_gnd" loc = "k2"; #put it to a non connected FPGA pin (starter kit schematic BANK3) +#net "jtag_vref" loc = "k7"; #put it to a non connected FPGA pin (starter kit schematic BANK3) + +# +# End of file. +#
rc-1.0/backend/spartan3e_starter_kit_eth/spartan3e_starter_kit_eth.ucf Property changes : Added: svn:executable ## -0,0 +1 ## +* \ No newline at end of property Index: rc-1.0/backend/spartan3e_starter_kit_eth/board.h =================================================================== --- rc-1.0/backend/spartan3e_starter_kit_eth/board.h (nonexistent) +++ rc-1.0/backend/spartan3e_starter_kit_eth/board.h (revision 109) @@ -0,0 +1,40 @@ +#ifndef _BOARD_H_ +#define _BOARD_H_ + +#define MC_ENABLED 0 + +#define IC_ENABLE 0 +#define IC_SIZE 8192 +#define DC_ENABLE 0 +#define DC_SIZE 8192 + + +#define IN_CLK 10000000 + + +#define STACK_SIZE 0x00180 + +#define UART_BAUD_RATE 19200 + +#define UART_BASE 0x90000000 +#define UART_IRQ 2 +#define ETH_BASE 0x92000000 +#define ETH_IRQ 4 +#define I2C_BASE 0x9D000000 +#define I2C_IRQ 3 +#define CAN_BASE 0x94000000 +#define CAN_IRQ 5 + +#define MC_BASE_ADDR 0x60000000 +#define SPI_BASE 0xa0000000 + +#define ETH_DATA_BASE 0xa8000000 /* Address for ETH_DATA */ + +#define ETH_MACADDR0 0x00 +#define ETH_MACADDR1 0x12 +#define ETH_MACADDR2 0x34 +#define ETH_MACADDR3 0x56 +#define ETH_MACADDR4 0x78 +#define ETH_MACADDR5 0x9a + +#endif
rc-1.0/backend/spartan3e_starter_kit_eth/board.h Property changes : Added: svn:executable ## -0,0 +1 ## +* \ No newline at end of property Index: rc-1.0/backend/spartan3e_starter_kit_eth/orp.ld =================================================================== --- rc-1.0/backend/spartan3e_starter_kit_eth/orp.ld (nonexistent) +++ rc-1.0/backend/spartan3e_starter_kit_eth/orp.ld (revision 109) @@ -0,0 +1,60 @@ +MEMORY + { + reset : ORIGIN = 0x00000000, LENGTH = 0x00000200 + vectors : ORIGIN = 0x00000200, LENGTH = 0x00001000 + ram : ORIGIN = 0x00001200, LENGTH = 0x00002E00 /*0x8000 total*/ + } + +SECTIONS +{ + .reset : + { + *(.reset) + } > reset + + + + .vectors : + { + _vec_start = .; + *(.vectors) + _vec_end = .; + } > vectors + + .text : + { + *(.text) + } > ram + + .rodata : + { + *(.rodata) + *(.rodata.*) + } > ram + + .icm : + { + _icm_start = .; + *(.icm) + _icm_end = .; + } > ram + + .data : + { + _dst_beg = .; + *(.data) + _dst_end = .; + } > ram + + .bss : + { + *(.bss) + } > ram + + .stack (NOLOAD) : + { + *(.stack) + _src_addr = .; + } > ram + +}
rc-1.0/backend/spartan3e_starter_kit_eth/orp.ld Property changes : Added: svn:executable ## -0,0 +1 ## +* \ No newline at end of property Index: rc-1.0/backend/ml509/ml509.ucf =================================================================== --- rc-1.0/backend/ml509/ml509.ucf (nonexistent) +++ rc-1.0/backend/ml509/ml509.ucf (revision 109) @@ -0,0 +1,45 @@ +NET clk LOC="AH15" | PERIOD=10ns | IOSTANDARD=LVCMOS33; # Bank 4, Vcco=3.3V, No DCI +NET reset LOC="E9" | PULLUP | IOSTANDARD=LVDCI_33; # Bank 20, Vcco=3.3V, DCI using 49.9 ohm resistors +NET uart_srx LOC="AG15" | IOSTANDARD=LVCMOS33; # Bank 4, Vcco=3.3V, No DCI +NET uart_stx LOC="AG20" | IOSTANDARD=LVCMOS33; # Bank 4, Vcco=3.3V, No DCI + +## #------------------------------------------------------------------------------ +## # IO Pad Location Constraints / Properties for Ethernet +## #------------------------------------------------------------------------------ + +#NET eth_col LOC = B32 | IOSTANDARD = LVCMOS25 | IOBDELAY=NONE; +#NET eth_crs LOC = E34 | IOSTANDARD = LVCMOS25 | IOBDELAY=NONE; +#NET eth_rx_dv LOC = E32 | IOSTANDARD = LVCMOS25 | IOBDELAY=NONE; +#NET eth_rx_clk LOC = H17 | IOSTANDARD = LVCMOS25; +#NET eth_rxd<3> LOC = C32 | IOSTANDARD = LVCMOS25 | IOBDELAY=NONE; +#NET eth_rxd<2> LOC = C33 | IOSTANDARD = LVCMOS25 | IOBDELAY=NONE; +#NET eth_rxd<1> LOC = B33 | IOSTANDARD = LVCMOS25 | IOBDELAY=NONE; +#NET eth_rxd<0> LOC = A33 | IOSTANDARD = LVCMOS25 | IOBDELAY=NONE; + +#NET eth_rx_er LOC = E33 | IOSTANDARD = LVCMOS25 | IOBDELAY=NONE; +#NET eth_tx_clk LOC = K17 | IOSTANDARD = LVCMOS25; +#NET eth_trste LOC = J14 | IOSTANDARD = LVCMOS25 | PULLUP | TIG; # PHY_RESET pin on phy +#NET eth_txd<3> LOC = AH10 | IOSTANDARD = LVDCI_33; +#NET eth_txd<2> LOC = AH9 | IOSTANDARD = LVDCI_33; +#NET eth_txd<1> LOC = AE11 | IOSTANDARD = LVDCI_33; +#NET eth_txd<0> LOC = AF11 | IOSTANDARD = LVDCI_33; +#NET eth_tx_en LOC = AJ10 | IOSTANDARD = LVDCI_33; +#NET eth_tx_er LOC = AJ9 | IOSTANDARD = LVDCI_33; + +## PHY Serial Management Interface pins +#NET eth_mdc LOC = H19 | IOSTANDARD = LVCMOS25; +#NET eth_mdio LOC = H13 | IOSTANDARD = LVCMOS25; + +## # Timing Constraints (these are recommended in documentation and +## # are unaltered except for the TIG) +#NET "eth_rx_clk_BUFGP" TNM_NET = "RXCLK_GRP"; +#NET "eth_tx_clk_BUFGP" TNM_NET = "TXCLK_GRP"; +#TIMESPEC "TSTXOUT" = FROM "TXCLK_GRP" TO "PADS" 10 ns; +#TIMESPEC "TSRXIN" = FROM "PADS" TO "RXCLK_GRP" 6 ns; + +## # Timing ignores (to specify unconstrained paths) +#FIXME? NET "*clkgen0/wb_clk_o" TNM_NET = "sys_clk"; # Wishbone clock +#TIMESPEC "TS_PHYTX_OPB" = FROM "TXCLK_GRP" TO "sys_clk" TIG; +#TIMESPEC "TS_OPB_PHYTX" = FROM "sys_clk" TO "TXCLK_GRP" TIG; +#TIMESPEC "TS_PHYRX_OPB" = FROM "RXCLK_GRP" TO "sys_clk" TIG; +#TIMESPEC "TS_OPB_PHYRX" = FROM "sys_clk" TO "RXCLK_GRP" TIG; Index: rc-1.0/sim/run/generate_bench =================================================================== --- rc-1.0/sim/run/generate_bench (nonexistent) +++ rc-1.0/sim/run/generate_bench (revision 109) @@ -0,0 +1,2 @@ +#!/bin/sh +iverilog -c ../../prj/sim/minsoc_verilog.src -o minsoc_bench
rc-1.0/sim/run/generate_bench Property changes : Added: svn:executable ## -0,0 +1 ## +* \ No newline at end of property Index: rc-1.0/sim/run/start_server =================================================================== --- rc-1.0/sim/run/start_server (nonexistent) +++ rc-1.0/sim/run/start_server (revision 109) @@ -0,0 +1,2 @@ +#!/bin/sh +adv_jtag_bridge -x0 -l 0:4 -c 0x8 vpi
rc-1.0/sim/run/start_server Property changes : Added: svn:executable ## -0,0 +1 ## +* \ No newline at end of property Index: rc-1.0/sim/run/run_bench =================================================================== --- rc-1.0/sim/run/run_bench (nonexistent) +++ rc-1.0/sim/run/run_bench (revision 109) @@ -0,0 +1,2 @@ +#!/bin/sh +vvp -M ../../bench/verilog/vpi/ -mjp-io-vpi minsoc_bench +file_name=$1
rc-1.0/sim/run/run_bench Property changes : Added: svn:executable ## -0,0 +1 ## +* \ No newline at end of property Index: rc-1.0/sim/modelsim/compile_design.bat =================================================================== --- rc-1.0/sim/modelsim/compile_design.bat (nonexistent) +++ rc-1.0/sim/modelsim/compile_design.bat (revision 109) @@ -0,0 +1,5 @@ +@echo off +vlog -incr -work minsoc -f ../../prj/sim/minsoc_verilog.src +::vcom -work minsoc -f ../../prj/sim/minsoc_vhdl.src +echo Finished... +set /p exit=Press ENTER to close this window... Index: rc-1.0/sim/modelsim/compile_design.sh =================================================================== --- rc-1.0/sim/modelsim/compile_design.sh (nonexistent) +++ rc-1.0/sim/modelsim/compile_design.sh (revision 109) @@ -0,0 +1,4 @@ +#!/bin/bash + +vlog -incr -work minsoc -f ../../prj/sim/minsoc_verilog.src +#vcom -work minsoc -f ../../prj/sim/minsoc_vhdl.src
rc-1.0/sim/modelsim/compile_design.sh Property changes : Added: svn:executable ## -0,0 +1 ## +* \ No newline at end of property Index: rc-1.0/sim/modelsim/run_sim.bat =================================================================== --- rc-1.0/sim/modelsim/run_sim.bat (nonexistent) +++ rc-1.0/sim/modelsim/run_sim.bat (revision 109) @@ -0,0 +1,8 @@ +@echo off +set /p target_firmware=Input the target firmware hex file along with its path. Ex: "..\..\sw\uart\uart-nocache.hex": +if EXIST %target_firmware% ( +vsim -lib minsoc minsoc_bench -pli ../../bench/verilog/vpi/jp-io-vpi.dll +file_name=%target_firmware% +) else ( +echo %target_firmware% could not be found. +set /p exit=Press ENTER to close this window... +) \ No newline at end of file Index: rc-1.0/sim/modelsim/prepare_modelsim.bat =================================================================== --- rc-1.0/sim/modelsim/prepare_modelsim.bat (nonexistent) +++ rc-1.0/sim/modelsim/prepare_modelsim.bat (revision 109) @@ -0,0 +1,5 @@ +@echo off +vlib minsoc +vmap minsoc ./minsoc +echo Finished... +set /p exit=Press ENTER to close this window... \ No newline at end of file Index: rc-1.0/sim/modelsim/prepare_modelsim.sh =================================================================== --- rc-1.0/sim/modelsim/prepare_modelsim.sh (nonexistent) +++ rc-1.0/sim/modelsim/prepare_modelsim.sh (revision 109) @@ -0,0 +1,4 @@ +#!/bin/bash + +vlib minsoc +vmap minsoc ./minsoc
rc-1.0/sim/modelsim/prepare_modelsim.sh Property changes : Added: svn:executable ## -0,0 +1 ## +* \ No newline at end of property Index: rc-1.0/sim/modelsim/run_sim.sh =================================================================== --- rc-1.0/sim/modelsim/run_sim.sh (nonexistent) +++ rc-1.0/sim/modelsim/run_sim.sh (revision 109) @@ -0,0 +1,3 @@ +#!/bin/bash + +vsim -lib minsoc minsoc_bench -pli ../../bench/verilog/vpi/jp-io-vpi.so +file_name=$1
rc-1.0/sim/modelsim/run_sim.sh Property changes : Added: svn:executable ## -0,0 +1 ## +* \ No newline at end of property Index: rc-1.0/sim/results/wave.do.sav =================================================================== --- rc-1.0/sim/results/wave.do.sav (nonexistent) +++ rc-1.0/sim/results/wave.do.sav (revision 109) @@ -0,0 +1,49 @@ +[size] 1280 1001 +[pos] -1 -1 +*-29.000000 16828000000 285000000 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 +[treeopen] minsoc_bench. +[treeopen] minsoc_bench.minsoc_top_0. +@28 +minsoc_bench.reset +minsoc_bench.minsoc_top_0.or1200_top.iwb_cyc_o +minsoc_bench.minsoc_top_0.or1200_top.iwb_stb_o +minsoc_bench.minsoc_top_0.or1200_top.iwb_we_o +@22 +minsoc_bench.minsoc_top_0.or1200_top.iwb_adr_o[31:0] +minsoc_bench.minsoc_top_0.or1200_top.iwb_dat_i[31:0] +@28 +minsoc_bench.minsoc_top_0.or1200_top.iwb_ack_i +minsoc_bench.minsoc_top_0.or1200_top.dwb_cyc_o +minsoc_bench.minsoc_top_0.or1200_top.dwb_stb_o +minsoc_bench.minsoc_top_0.or1200_top.dwb_we_o +@22 +minsoc_bench.minsoc_top_0.or1200_top.dwb_adr_o[31:0] +minsoc_bench.minsoc_top_0.or1200_top.dwb_dat_o[31:0] +@28 +minsoc_bench.minsoc_top_0.or1200_top.dwb_ack_i +@22 +minsoc_bench.minsoc_top_0.or1200_top.or1200_cpu.or1200_sprs.sr[15:0] +minsoc_bench.minsoc_top_0.or1200_top.or1200_cpu.or1200_operandmuxes.rf_dataa[31:0] +minsoc_bench.minsoc_top_0.or1200_top.or1200_cpu.or1200_operandmuxes.rf_datab[31:0] +@28 +minsoc_bench.minsoc_top_0.or1200_top.or1200_cpu.or1200_alu.flag +minsoc_bench.minsoc_top_0.or1200_top.or1200_cpu.or1200_alu.flag_we +@22 +minsoc_bench.minsoc_top_0.or1200_top.or1200_cpu.or1200_alu.result[31:0] +minsoc_bench.minsoc_top_0.or1200_top.or1200_cpu.or1200_alu.alu_op[3:0] +minsoc_bench.minsoc_top_0.or1200_top.or1200_cpu.or1200_operandmuxes.operand_a[31:0] +minsoc_bench.minsoc_top_0.or1200_top.or1200_cpu.or1200_operandmuxes.operand_b[31:0] +@28 +minsoc_bench.uart_stx +minsoc_bench.minsoc_top_0.uart_top.wb_cyc_i +minsoc_bench.minsoc_top_0.uart_top.wb_stb_i +minsoc_bench.minsoc_top_0.uart_top.wb_we_i +@22 +minsoc_bench.minsoc_top_0.uart_top.wb_adr_i[4:0] +minsoc_bench.minsoc_top_0.uart_top.wb_dat8_i[7:0] +minsoc_bench.minsoc_top_0.uart_top.wb_dat8_o[7:0] +@28 +minsoc_bench.minsoc_top_0.uart_top.wb_ack_o +minsoc_bench.minsoc_top_0.spi_flash_ss[1:0] +minsoc_bench.minsoc_top_0.spi_flash_sclk +minsoc_bench.minsoc_top_0.spi_flash_miso
rc-1.0/sim/results/wave.do.sav Property changes : Added: svn:executable ## -0,0 +1 ## +* \ No newline at end of property Index: rc-1.0/doc/README.txt =================================================================== --- rc-1.0/doc/README.txt (nonexistent) +++ rc-1.0/doc/README.txt (revision 109) @@ -0,0 +1,22 @@ +Welcome to MinSoC. + +In order to put the system up and running, you should first visit MinSoC's Wiki +that can be found at (http://www.minsoc.com). There, you will find guidance +to retrieve and install the required tools, simulate and synthesize the design, +and to run and debug the first firmware on your FPGA. + +IMPORTANT: By any arisen problems, doubts or special requirements, take a look +into the FAQ pages (also in this very Wiki). It includes possible adaptations +you can easily make to the system, solutions for the most reported problems +using MinSoC and the Advanced Debug System, and even some tweak possibilities. +If you have a problem which is not described there or you cannot make it work, +please send us an email to . + +FINALLY: My system is up and running, what do I do next? The real system +documentation is the minsoc.pdf document. It gives a thorough insight into +MinSoC, its goals, design and ideas. It helps you to better understand the +system and can give you a good idea of what to do next, after your system is up +and running. + +Enjoy your time, +Raul Fajardo Index: rc-1.0/doc/src/minsoc.odt =================================================================== Cannot display: file marked as a binary type. svn:mime-type = application/octet-stream Index: rc-1.0/doc/src/minsoc.odt =================================================================== --- rc-1.0/doc/src/minsoc.odt (nonexistent) +++ rc-1.0/doc/src/minsoc.odt (revision 109)
rc-1.0/doc/src/minsoc.odt Property changes : Added: svn:mime-type ## -0,0 +1 ## +application/octet-stream \ No newline at end of property Index: rc-1.0/doc/src/figures/or1200.gif =================================================================== Cannot display: file marked as a binary type. svn:mime-type = application/octet-stream Index: rc-1.0/doc/src/figures/or1200.gif =================================================================== --- rc-1.0/doc/src/figures/or1200.gif (nonexistent) +++ rc-1.0/doc/src/figures/or1200.gif (revision 109)
rc-1.0/doc/src/figures/or1200.gif Property changes : Added: svn:mime-type ## -0,0 +1 ## +application/octet-stream \ No newline at end of property Index: rc-1.0/doc/src/figures/soc.odg =================================================================== Cannot display: file marked as a binary type. svn:mime-type = application/octet-stream Index: rc-1.0/doc/src/figures/soc.odg =================================================================== --- rc-1.0/doc/src/figures/soc.odg (nonexistent) +++ rc-1.0/doc/src/figures/soc.odg (revision 109)
rc-1.0/doc/src/figures/soc.odg Property changes : Added: svn:executable ## -0,0 +1 ## +* \ No newline at end of property Added: svn:mime-type ## -0,0 +1 ## +application/octet-stream \ No newline at end of property Index: rc-1.0/doc/minsoc.pdf =================================================================== Cannot display: file marked as a binary type. svn:mime-type = application/octet-stream Index: rc-1.0/doc/minsoc.pdf =================================================================== --- rc-1.0/doc/minsoc.pdf (nonexistent) +++ rc-1.0/doc/minsoc.pdf (revision 109)
rc-1.0/doc/minsoc.pdf Property changes : Added: svn:executable ## -0,0 +1 ## +* \ No newline at end of property Added: svn:mime-type ## -0,0 +1 ## +application/octet-stream \ No newline at end of property Index: rc-1.0/doc/lgpl-3.0.txt =================================================================== --- rc-1.0/doc/lgpl-3.0.txt (nonexistent) +++ rc-1.0/doc/lgpl-3.0.txt (revision 109) @@ -0,0 +1,165 @@ + GNU LESSER GENERAL PUBLIC LICENSE + Version 3, 29 June 2007 + + Copyright (C) 2007 Free Software Foundation, Inc. + Everyone is permitted to copy and distribute verbatim copies + of this license document, but changing it is not allowed. + + + This version of the GNU Lesser General Public License incorporates +the terms and conditions of version 3 of the GNU General Public +License, supplemented by the additional permissions listed below. + + 0. Additional Definitions. + + As used herein, "this License" refers to version 3 of the GNU Lesser +General Public License, and the "GNU GPL" refers to version 3 of the GNU +General Public License. + + "The Library" refers to a covered work governed by this License, +other than an Application or a Combined Work as defined below. + + An "Application" is any work that makes use of an interface provided +by the Library, but which is not otherwise based on the Library. +Defining a subclass of a class defined by the Library is deemed a mode +of using an interface provided by the Library. + + A "Combined Work" is a work produced by combining or linking an +Application with the Library. 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rc-1.0/doc/lgpl-3.0.txt Property changes : Added: svn:executable ## -0,0 +1 ## +* \ No newline at end of property Index: rc-1.0/rtl/verilog/xilinx_dcm.v =================================================================== --- rc-1.0/rtl/verilog/xilinx_dcm.v (nonexistent) +++ rc-1.0/rtl/verilog/xilinx_dcm.v (revision 109) @@ -0,0 +1,226 @@ + +`include "minsoc_defines.v" + +module xilinx_dcm( + clk_i, + clk_o +); + +// +// Parameters +// + parameter divisor = 2; + +input clk_i; +output clk_o; + + +`ifdef SPARTAN2 + `define XILINX_DLL +`elsif VIRTEX + `define XILINX_DLL +`endif // !SPARTAN2/VIRTEX + +`ifdef SPARTAN3 + `define XILINX_DCM +`elsif VIRTEX2 + `define XILINX_DCM +`endif // !SPARTAN3/VIRTEX2 + +`ifdef SPARTAN3E + `define XILINX_DCM_SP +`elsif SPARTAN3A + `define XILINX_DCM_SP +`endif // !SPARTAN3E/SPARTAN3A + +`ifdef VIRTEX4 + `define XILINX_DCM_ADV + `define XILINX_DCM_COMPONENT "VIRTEX4" +`elsif VIRTEX5 + `define XILINX_DCM_ADV + `define XILINX_DCM_COMPONENT "VIRTEX5" +`endif // !VIRTEX4/VIRTEX5 + + +wire CLKIN_IN; +wire CLKDV_OUT; + +assign CLKIN_IN = clk_i; +assign clk_o = CLKDV_OUT; + +wire CLKIN_IBUFG; +wire CLK0_BUF; +wire CLKFB_IN; +wire CLKDV_BUF; + +`ifdef XILINX_FPGA + +IBUFG CLKIN_IBUFG_INST ( + .I(CLKIN_IN), + .O(CLKIN_IBUFG) +); + +BUFG CLK0_BUFG_INST ( + .I(CLK0_BUF), + .O(CLKFB_IN) +); + +BUFG CLKDV_BUFG_INST ( + .I(CLKDV_BUF), + .O(CLKDV_OUT) +); + +`ifdef XILINX_DLL + +CLKDLL #( + .CLKDV_DIVIDE(divisor), // Divide by: 1.5,2.0,2.5,3.0,4.0,5.0,8.0 or 16.0 + .DUTY_CYCLE_CORRECTION("TRUE"), // Duty cycle correction, TRUE or FALSE + .FACTORY_JF(16'hC080), // FACTORY JF Values + .STARTUP_WAIT("FALSE") // Delay config DONE until DLL LOCK, TRUE/FALSE +) CLKDLL_inst ( + .CLK0(CLK0_BUF), // 0 degree DLL CLK output + .CLK180(), // 180 degree DLL CLK output + .CLK270(), // 270 degree DLL CLK output + .CLK2X(), // 2X DLL CLK output + .CLK90(), // 90 degree DLL CLK output + .CLKDV(CLKDV_BUF), // Divided DLL CLK out (CLKDV_DIVIDE) + .LOCKED(), // DLL LOCK status output + .CLKFB(CLKFB_IN), // DLL clock feedback + .CLKIN(CLKIN_IBUFG), // Clock input (from IBUFG, BUFG or DLL) + .RST(1'b0) // DLL asynchronous reset input +); + +`elsif XILINX_DCM + +DCM #( + .SIM_MODE("SAFE"), // Simulation: "SAFE" vs. "FAST", see "Synthesis and Simulation Design Guide" for details + .CLKDV_DIVIDE(divisor), // Divide by: 1.5,2.0,2.5,3.0,3.5,4.0,4.5,5.0,5.5,6.0,6.5 + // 7.0,7.5,8.0,9.0,10.0,11.0,12.0,13.0,14.0,15.0 or 16.0 + .CLKFX_DIVIDE(1), // Can be any integer from 1 to 32 + .CLKFX_MULTIPLY(4), // Can be any integer from 2 to 32 + .CLKIN_DIVIDE_BY_2("FALSE"), // TRUE/FALSE to enable CLKIN divide by two feature + .CLKIN_PERIOD(0.0), // Specify period of input clock + .CLKOUT_PHASE_SHIFT("NONE"), // Specify phase shift of NONE, FIXED or VARIABLE + .CLK_FEEDBACK("1X"), // Specify clock feedback of NONE, 1X or 2X + .DESKEW_ADJUST("SYSTEM_SYNCHRONOUS"), // SOURCE_SYNCHRONOUS, SYSTEM_SYNCHRONOUS or + // an integer from 0 to 15 + .DFS_FREQUENCY_MODE("LOW"), // HIGH or LOW frequency mode for frequency synthesis + .DLL_FREQUENCY_MODE("LOW"), // HIGH or LOW frequency mode for DLL + .DUTY_CYCLE_CORRECTION("TRUE"), // Duty cycle correction, TRUE or FALSE + .FACTORY_JF(16'hC080), // FACTORY JF values + .PHASE_SHIFT(0), // Amount of fixed phase shift from -255 to 255 + .STARTUP_WAIT("FALSE") // Delay configuration DONE until DCM LOCK, TRUE/FALSE +) DCM_inst ( + .CLK0(CLK0_BUF), // 0 degree DCM CLK output + .CLK180(), // 180 degree DCM CLK output + .CLK270(), // 270 degree DCM CLK output + .CLK2X(), // 2X DCM CLK output + .CLK2X180(), // 2X, 180 degree DCM CLK out + .CLK90(), // 90 degree DCM CLK output + .CLKDV(CLKDV_BUF), // Divided DCM CLK out (CLKDV_DIVIDE) + .CLKFX(), // DCM CLK synthesis out (M/D) + .CLKFX180(), // 180 degree CLK synthesis out + .LOCKED(), // DCM LOCK status output + .PSDONE(), // Dynamic phase adjust done output + .STATUS(), // 8-bit DCM status bits output + .CLKFB(CLKFB_IN), // DCM clock feedback + .CLKIN(CLKIN_IBUFG), // Clock input (from IBUFG, BUFG or DCM) + .PSCLK(1'b0), // Dynamic phase adjust clock input + .PSEN(1'b0), // Dynamic phase adjust enable input + .PSINCDEC(1'b0), // Dynamic phase adjust increment/decrement + .RST(1'b0) // DCM asynchronous reset input +); + +`elsif XILINX_DCM_SP + +DCM_SP #( + .CLKDV_DIVIDE(divisor), // Divide by: 1.5,2.0,2.5,3.0,3.5,4.0,4.5,5.0,5.5,6.0,6.5 + // 7.0,7.5,8.0,9.0,10.0,11.0,12.0,13.0,14.0,15.0 or 16.0 + .CLKFX_DIVIDE(1), // Can be any integer from 1 to 32 + .CLKFX_MULTIPLY(4), // Can be any integer from 2 to 32 + .CLKIN_DIVIDE_BY_2("FALSE"), // TRUE/FALSE to enable CLKIN divide by two feature + .CLKIN_PERIOD(0.0), // Specify period of input clock + .CLKOUT_PHASE_SHIFT("NONE"), // Specify phase shift of NONE, FIXED or VARIABLE + .CLK_FEEDBACK("1X"), // Specify clock feedback of NONE, 1X or 2X + .DESKEW_ADJUST("SYSTEM_SYNCHRONOUS"), // SOURCE_SYNCHRONOUS, SYSTEM_SYNCHRONOUS or + // an integer from 0 to 15 + .DLL_FREQUENCY_MODE("LOW"), // HIGH or LOW frequency mode for DLL + .DUTY_CYCLE_CORRECTION("TRUE"), // Duty cycle correction, TRUE or FALSE + .PHASE_SHIFT(0), // Amount of fixed phase shift from -255 to 255 + .STARTUP_WAIT("FALSE") // Delay configuration DONE until DCM LOCK, TRUE/FALSE +) DCM_SP_inst ( + .CLK0(CLK0_BUF), // 0 degree DCM CLK output + .CLK180(), // 180 degree DCM CLK output + .CLK270(), // 270 degree DCM CLK output + .CLK2X(), // 2X DCM CLK output + .CLK2X180(), // 2X, 180 degree DCM CLK out + .CLK90(), // 90 degree DCM CLK output + .CLKDV(CLKDV_BUF), // Divided DCM CLK out (CLKDV_DIVIDE) + .CLKFX(), // DCM CLK synthesis out (M/D) + .CLKFX180(), // 180 degree CLK synthesis out + .LOCKED(), // DCM LOCK status output + .PSDONE(), // Dynamic phase adjust done output + .STATUS(), // 8-bit DCM status bits output + .CLKFB(CLKFB_IN), // DCM clock feedback + .CLKIN(CLKIN_IBUFG), // Clock input (from IBUFG, BUFG or DCM) + .PSCLK(1'b0), // Dynamic phase adjust clock input + .PSEN(1'b0), // Dynamic phase adjust enable input + .PSINCDEC(1'b0), // Dynamic phase adjust increment/decrement + .RST(1'b0) // DCM asynchronous reset input +); + +`elsif XILINX_DCM_ADV + +DCM_ADV #( + .CLKDV_DIVIDE(divisor), // Divide by: 1.5,2.0,2.5,3.0,3.5,4.0,4.5,5.0,5.5,6.0,6.5 + // 7.0,7.5,8.0,9.0,10.0,11.0,12.0,13.0,14.0,15.0 or 16.0 + .CLKFX_DIVIDE(1), // Can be any integer from 1 to 32 + .CLKFX_MULTIPLY(4), // Can be any integer from 2 to 32 + .CLKIN_DIVIDE_BY_2("FALSE"), // TRUE/FALSE to enable CLKIN divide by two feature + .CLKIN_PERIOD(10.0), // Specify period of input clock in ns from 1.25 to 1000.00 + .CLKOUT_PHASE_SHIFT("NONE"), // Specify phase shift mode of NONE, FIXED, + // VARIABLE_POSITIVE, VARIABLE_CENTER or DIRECT + .CLK_FEEDBACK("1X"), // Specify clock feedback of NONE, 1X or 2X + .DCM_AUTOCALIBRATION("TRUE"), // DCM calibration circuitry "TRUE"/"FALSE" + .DCM_PERFORMANCE_MODE("MAX_SPEED"), // Can be MAX_SPEED or MAX_RANGE + .DESKEW_ADJUST("SYSTEM_SYNCHRONOUS"), // SOURCE_SYNCHRONOUS, SYSTEM_SYNCHRONOUS or + // an integer from 0 to 15 + .DFS_FREQUENCY_MODE("LOW"), // HIGH or LOW frequency mode for frequency synthesis + .DLL_FREQUENCY_MODE("LOW"), // LOW, HIGH, or HIGH_SER frequency mode for DLL + .DUTY_CYCLE_CORRECTION("TRUE"), // Duty cycle correction, "TRUE"/"FALSE" + .FACTORY_JF(16'hf0f0), // FACTORY JF value suggested to be set to 16’hf0f0 + .PHASE_SHIFT(0), // Amount of fixed phase shift from -255 to 1023 + .SIM_DEVICE(`XILINX_DCM_COMPONENT), // Set target device, "VIRTEX4" or "VIRTEX5" + .STARTUP_WAIT("FALSE") // Delay configuration DONE until DCM LOCK, "TRUE"/"FALSE" +) DCM_ADV_inst ( + .CLK0(CLK0_BUF), // 0 degree DCM CLK output + .CLK180(), // 180 degree DCM CLK output + .CLK270(), // 270 degree DCM CLK output + .CLK2X(), // 2X DCM CLK output + .CLK2X180(), // 2X, 180 degree DCM CLK out + .CLK90(), // 90 degree DCM CLK output + .CLKDV(CLKDV_BUF), // Divided DCM CLK out (CLKDV_DIVIDE) + .CLKFX(), // DCM CLK synthesis out (M/D) + .CLKFX180(), // 180 degree CLK synthesis out + .DO(), // 16-bit data output for Dynamic Reconfiguration Port (DRP) + .DRDY(), // Ready output signal from the DRP + .LOCKED(), // DCM LOCK status output + .PSDONE(), // Dynamic phase adjust done output + .CLKFB(CLKFB_IN), // DCM clock feedback + .CLKIN(CLKIN_IBUFG), // Clock input (from IBUFG, BUFG or DCM) + .DADDR(7'h00), // 7-bit address for the DRP + .DCLK(1'b0), // Clock for the DRP + .DEN(1'b0), // Enable input for the DRP + .DI(16'h0000), // 16-bit data input for the DRP + .DWE(1'b0), // Active high allows for writing configuration memory + .PSCLK(1'b0), // Dynamic phase adjust clock input + .PSEN(1'b0), // Dynamic phase adjust enable input + .PSINCDEC(1'b0), // Dynamic phase adjust increment/decrement + .RST(1'b0) // DCM asynchronous reset input +); + +`endif // !XILINX_DLL/XILINX_DCM/XILINX_DCM_SP/XILINX_DCM_ADV +`endif // !XILINX_FPGA + + +endmodule Index: rc-1.0/rtl/verilog/minsoc_top.v =================================================================== --- rc-1.0/rtl/verilog/minsoc_top.v (nonexistent) +++ rc-1.0/rtl/verilog/minsoc_top.v (revision 109) @@ -0,0 +1,998 @@ +`include "minsoc_defines.v" +`include "or1200_defines.v" + +module minsoc_top ( + clk,reset + + //JTAG ports +`ifdef GENERIC_TAP + , jtag_tdi,jtag_tms,jtag_tck, + jtag_tdo,jtag_vref,jtag_gnd +`endif + + //SPI ports +`ifdef START_UP + , spi_flash_mosi, spi_flash_miso, spi_flash_sclk, spi_flash_ss +`endif + + //UART ports +`ifdef UART + , uart_stx,uart_srx +`endif + + // Ethernet ports +`ifdef ETHERNET + , eth_col, eth_crs, eth_trste, eth_tx_clk, + eth_tx_en, eth_tx_er, eth_txd, eth_rx_clk, + eth_rx_dv, eth_rx_er, eth_rxd, eth_fds_mdint, + eth_mdc, eth_mdio +`endif +); + +// +// I/O Ports +// + + input clk; + input reset; + +// +// SPI controller external i/f wires +// +`ifdef START_UP +output spi_flash_mosi; +input spi_flash_miso; +output spi_flash_sclk; +output [1:0] spi_flash_ss; +`endif + +// +// UART +// +`ifdef UART + output uart_stx; + input uart_srx; +`endif + +// +// Ethernet +// +`ifdef ETHERNET +output eth_tx_er; +input eth_tx_clk; +output eth_tx_en; +output [3:0] eth_txd; +input eth_rx_er; +input eth_rx_clk; +input eth_rx_dv; +input [3:0] eth_rxd; +input eth_col; +input eth_crs; +output eth_trste; +input eth_fds_mdint; +inout eth_mdio; +output eth_mdc; +`endif + +// +// JTAG +// +`ifdef GENERIC_TAP + input jtag_tdi; + input jtag_tms; + input jtag_tck; + output jtag_tdo; + output jtag_vref; + output jtag_gnd; + + +assign jtag_vref = 1'b1; +assign jtag_gnd = 1'b0; +`endif + +wire rstn; + +`ifdef POSITIVE_RESET +assign rstn = ~reset; +`elsif NEGATIVE_RESET +assign rstn = reset; +`endif + +// +// Internal wires +// + +// +// Debug core master i/f wires +// +wire [31:0] wb_dm_adr_o; +wire [31:0] wb_dm_dat_i; +wire [31:0] wb_dm_dat_o; +wire [3:0] wb_dm_sel_o; +wire wb_dm_we_o; +wire wb_dm_stb_o; +wire wb_dm_cyc_o; +wire wb_dm_ack_i; +wire wb_dm_err_i; + +// +// Debug <-> RISC wires +// +wire [3:0] dbg_lss; +wire [1:0] dbg_is; +wire [10:0] dbg_wp; +wire dbg_bp; +wire [31:0] dbg_dat_dbg; +wire [31:0] dbg_dat_risc; +wire [31:0] dbg_adr; +wire dbg_ewt; +wire dbg_stall; +wire dbg_we; +wire dbg_stb; +wire dbg_ack; + +// +// RISC instruction master i/f wires +// +wire [31:0] wb_rim_adr_o; +wire wb_rim_cyc_o; +wire [31:0] wb_rim_dat_i; +wire [31:0] wb_rim_dat_o; +wire [3:0] wb_rim_sel_o; +wire wb_rim_ack_i; +wire wb_rim_err_i; +wire wb_rim_rty_i = 1'b0; +wire wb_rim_we_o; +wire wb_rim_stb_o; +wire [31:0] wb_rif_dat_i; +wire wb_rif_ack_i; + +// +// RISC data master i/f wires +// +wire [31:0] wb_rdm_adr_o; +wire wb_rdm_cyc_o; +wire [31:0] wb_rdm_dat_i; +wire [31:0] wb_rdm_dat_o; +wire [3:0] wb_rdm_sel_o; +wire wb_rdm_ack_i; +wire wb_rdm_err_i; +wire wb_rdm_rty_i = 1'b0; +wire wb_rdm_we_o; +wire wb_rdm_stb_o; + +// +// RISC misc +// +wire [`OR1200_PIC_INTS-1:0] pic_ints; + +// +// Flash controller slave i/f wires +// +wire [31:0] wb_fs_dat_i; +wire [31:0] wb_fs_dat_o; +wire [31:0] wb_fs_adr_i; +wire [3:0] wb_fs_sel_i; +wire wb_fs_we_i; +wire wb_fs_cyc_i; +wire wb_fs_stb_i; +wire wb_fs_ack_o; +wire wb_fs_err_o; + +// +// SPI controller slave i/f wires +// +wire [31:0] wb_sp_dat_i; +wire [31:0] wb_sp_dat_o; +wire [31:0] wb_sp_adr_i; +wire [3:0] wb_sp_sel_i; +wire wb_sp_we_i; +wire wb_sp_cyc_i; +wire wb_sp_stb_i; +wire wb_sp_ack_o; +wire wb_sp_err_o; + +// +// SPI controller external i/f wires +// +wire spi_flash_mosi; +wire spi_flash_miso; +wire spi_flash_sclk; +wire [1:0] spi_flash_ss; + +// +// SRAM controller slave i/f wires +// +wire [31:0] wb_ss_dat_i; +wire [31:0] wb_ss_dat_o; +wire [31:0] wb_ss_adr_i; +wire [3:0] wb_ss_sel_i; +wire wb_ss_we_i; +wire wb_ss_cyc_i; +wire wb_ss_stb_i; +wire wb_ss_ack_o; +wire wb_ss_err_o; + +// +// Ethernet core master i/f wires +// +wire [31:0] wb_em_adr_o; +wire [31:0] wb_em_dat_i; +wire [31:0] wb_em_dat_o; +wire [3:0] wb_em_sel_o; +wire wb_em_we_o; +wire wb_em_stb_o; +wire wb_em_cyc_o; +wire wb_em_ack_i; +wire wb_em_err_i; + +// +// Ethernet core slave i/f wires +// +wire [31:0] wb_es_dat_i; +wire [31:0] wb_es_dat_o; +wire [31:0] wb_es_adr_i; +wire [3:0] wb_es_sel_i; +wire wb_es_we_i; +wire wb_es_cyc_i; +wire wb_es_stb_i; +wire wb_es_ack_o; +wire wb_es_err_o; + +// +// Ethernet external i/f wires +// +wire eth_mdo; +wire eth_mdoe; + +// +// UART16550 core slave i/f wires +// +wire [31:0] wb_us_dat_i; +wire [31:0] wb_us_dat_o; +wire [31:0] wb_us_adr_i; +wire [3:0] wb_us_sel_i; +wire wb_us_we_i; +wire wb_us_cyc_i; +wire wb_us_stb_i; +wire wb_us_ack_o; +wire wb_us_err_o; + +// +// UART external i/f wires +// +wire uart_stx; +wire uart_srx; + +// +// Reset debounce +// +reg rst_r; +reg wb_rst; + +// +// Global clock +// +wire wb_clk; + +// +// Reset debounce +// +always @(posedge wb_clk or negedge rstn) + if (~rstn) + rst_r <= 1'b1; + else + rst_r <= #1 1'b0; + +// +// Reset debounce +// +always @(posedge wb_clk) + wb_rst <= #1 rst_r; + +// +// Clock Divider +// +minsoc_clock_manager # +( + .divisor(`CLOCK_DIVISOR) +) +clk_adjust ( + .clk_i(clk), + .clk_o(wb_clk) +); + +// +// Unused WISHBONE signals +// +assign wb_us_err_o = 1'b0; +assign wb_fs_err_o = 1'b0; +assign wb_sp_err_o = 1'b0; + +// +// Unused interrupts +// +assign pic_ints[`APP_INT_RES1] = 'b0; +assign pic_ints[`APP_INT_RES2] = 'b0; +assign pic_ints[`APP_INT_RES3] = 'b0; +assign pic_ints[`APP_INT_PS2] = 'b0; + +// +// Ethernet tri-state +// +`ifdef ETHERNET +assign eth_mdio = eth_mdoe ? eth_mdo : 1'bz; +assign eth_trste = `ETH_RESET; +`endif + + +// +// RISC Instruction address for Flash +// +// Until first access to real Flash area, +// CPU instruction is fixed to jump to the Flash area. +// After Flash area is accessed, CPU instructions +// come from the tc_top (wishbone "switch"). +// +`ifdef START_UP +reg jump_flash; +reg [3:0] rif_counter; +reg [31:0] rif_dat_int; +reg rif_ack_int; + +always @(posedge wb_clk or negedge rstn) +begin + if (!rstn) begin + jump_flash <= #1 1'b1; + rif_counter <= 4'h0; + rif_ack_int <= 1'b0; + end + else begin + rif_ack_int <= 1'b0; + + if (wb_rim_cyc_o && (wb_rim_adr_o[31:32-`APP_ADDR_DEC_W] == `APP_ADDR_FLASH)) + jump_flash <= #1 1'b0; + + if ( jump_flash == 1'b1 ) begin + if ( wb_rim_cyc_o && wb_rim_stb_o && ~wb_rim_we_o ) + rif_ack_int <= 1'b1; + + if ( rif_ack_int == 1'b1 ) begin + rif_counter <= rif_counter + 1'b1; + rif_ack_int <= 1'b0; + end + end + end +end + +always @ (rif_counter) +begin + case ( rif_counter ) + 4'h0: rif_dat_int = { `OR1200_OR32_MOVHI , 5'h01 , 4'h0 , 1'b0 , `APP_ADDR_FLASH , 8'h00 }; + 4'h1: rif_dat_int = { `OR1200_OR32_ORI , 5'h01 , 5'h01 , 16'h0000 }; + 4'h2: rif_dat_int = { `OR1200_OR32_JR , 10'h000 , 5'h01 , 11'h000 }; + 4'h3: rif_dat_int = { `OR1200_OR32_NOP , 10'h000 , 16'h0000 }; + default: rif_dat_int = 32'h0000_0000; + endcase +end + +assign wb_rif_dat_i = jump_flash ? rif_dat_int : wb_rim_dat_i; + +assign wb_rif_ack_i = jump_flash ? rif_ack_int : wb_rim_ack_i; + +`else +assign wb_rif_dat_i = wb_rim_dat_i; +assign wb_rif_ack_i = wb_rim_ack_i; +`endif + + +// +// TAP<->dbg_interface +// +wire jtag_tck; +wire debug_tdi; +wire debug_tdo; +wire capture_dr; +wire shift_dr; +wire pause_dr; +wire update_dr; + +wire debug_select; +wire test_logic_reset; + +// +// Instantiation of the development i/f +// +adbg_top dbg_top ( + + // JTAG pins + .tck_i ( jtag_tck ), + .tdi_i ( debug_tdi ), + .tdo_o ( debug_tdo ), + .rst_i ( test_logic_reset ), //cable without rst + + // Boundary Scan signals + .capture_dr_i ( capture_dr ), + .shift_dr_i ( shift_dr ), + .pause_dr_i ( pause_dr ), + .update_dr_i ( update_dr ), + + .debug_select_i( debug_select ), + // WISHBONE common + .wb_clk_i ( wb_clk ), + + // WISHBONE master interface + .wb_adr_o ( wb_dm_adr_o ), + .wb_dat_i ( wb_dm_dat_i ), + .wb_dat_o ( wb_dm_dat_o ), + .wb_sel_o ( wb_dm_sel_o ), + .wb_we_o ( wb_dm_we_o ), + .wb_stb_o ( wb_dm_stb_o ), + .wb_cyc_o ( wb_dm_cyc_o ), + .wb_ack_i ( wb_dm_ack_i ), + .wb_err_i ( wb_dm_err_i ), + .wb_cti_o ( ), + .wb_bte_o ( ), + + // RISC signals + .cpu0_clk_i ( wb_clk ), + .cpu0_addr_o ( dbg_adr ), + .cpu0_data_i ( dbg_dat_risc ), + .cpu0_data_o ( dbg_dat_dbg ), + .cpu0_bp_i ( dbg_bp ), + .cpu0_stall_o( dbg_stall ), + .cpu0_stb_o ( dbg_stb ), + .cpu0_we_o ( dbg_we ), + .cpu0_ack_i ( dbg_ack ), + .cpu0_rst_o ( ) + +); + +// +// JTAG TAP controller instantiation +// +`ifdef GENERIC_TAP +tap_top tap_top( + // JTAG pads + .tms_pad_i(jtag_tms), + .tck_pad_i(jtag_tck), + .trstn_pad_i(rstn), + .tdi_pad_i(jtag_tdi), + .tdo_pad_o(jtag_tdo), + .tdo_padoe_o( ), + + // TAP states + .test_logic_reset_o( test_logic_reset ), + .run_test_idle_o(), + .shift_dr_o(shift_dr), + .pause_dr_o(pause_dr), + .update_dr_o(update_dr), + .capture_dr_o(capture_dr), + + // Select signals for boundary scan or mbist + .extest_select_o(), + .sample_preload_select_o(), + .mbist_select_o(), + .debug_select_o(debug_select), + + // TDO signal that is connected to TDI of sub-modules. + .tdi_o(debug_tdi), + + // TDI signals from sub-modules + .debug_tdo_i(debug_tdo), // from debug module + .bs_chain_tdo_i(1'b0), // from Boundary Scan Chain + .mbist_tdo_i(1'b0) // from Mbist Chain +); +`elsif FPGA_TAP +`ifdef ALTERA_FPGA +altera_virtual_jtag tap_top( + .tck_o(jtag_tck), + .debug_tdo_i(debug_tdo), + .tdi_o(debug_tdi), + .test_logic_reset_o(test_logic_reset), + .run_test_idle_o(), + .shift_dr_o(shift_dr), + .capture_dr_o(capture_dr), + .pause_dr_o(pause_dr), + .update_dr_o(update_dr), + .debug_select_o(debug_select) +); +`elsif XILINX_FPGA +minsoc_xilinx_internal_jtag tap_top( + .tck_o( jtag_tck ), + .debug_tdo_i( debug_tdo ), + .tdi_o( debug_tdi ), + + .test_logic_reset_o( test_logic_reset ), + .run_test_idle_o( ), + + .shift_dr_o( shift_dr ), + .capture_dr_o( capture_dr ), + .pause_dr_o( pause_dr ), + .update_dr_o( update_dr ), + .debug_select_o( debug_select ) +); +`endif // !FPGA_TAP + +`endif // !GENERIC_TAP + +// +// Instantiation of the OR1200 RISC +// +or1200_top or1200_top ( + + // Common + .rst_i ( wb_rst ), + .clk_i ( wb_clk ), +`ifdef OR1200_CLMODE_1TO2 + .clmode_i ( 2'b01 ), +`else +`ifdef OR1200_CLMODE_1TO4 + .clmode_i ( 2'b11 ), +`else + .clmode_i ( 2'b00 ), +`endif +`endif + + // WISHBONE Instruction Master + .iwb_clk_i ( wb_clk ), + .iwb_rst_i ( wb_rst ), + .iwb_cyc_o ( wb_rim_cyc_o ), + .iwb_adr_o ( wb_rim_adr_o ), + .iwb_dat_i ( wb_rif_dat_i ), + .iwb_dat_o ( wb_rim_dat_o ), + .iwb_sel_o ( wb_rim_sel_o ), + .iwb_ack_i ( wb_rif_ack_i ), + .iwb_err_i ( wb_rim_err_i ), + .iwb_rty_i ( wb_rim_rty_i ), + .iwb_we_o ( wb_rim_we_o ), + .iwb_stb_o ( wb_rim_stb_o ), + + // WISHBONE Data Master + .dwb_clk_i ( wb_clk ), + .dwb_rst_i ( wb_rst ), + .dwb_cyc_o ( wb_rdm_cyc_o ), + .dwb_adr_o ( wb_rdm_adr_o ), + .dwb_dat_i ( wb_rdm_dat_i ), + .dwb_dat_o ( wb_rdm_dat_o ), + .dwb_sel_o ( wb_rdm_sel_o ), + .dwb_ack_i ( wb_rdm_ack_i ), + .dwb_err_i ( wb_rdm_err_i ), + .dwb_rty_i ( wb_rdm_rty_i ), + .dwb_we_o ( wb_rdm_we_o ), + .dwb_stb_o ( wb_rdm_stb_o ), + + // Debug + .dbg_stall_i ( dbg_stall ), + .dbg_dat_i ( dbg_dat_dbg ), + .dbg_adr_i ( dbg_adr ), + .dbg_ewt_i ( 1'b0 ), + .dbg_lss_o ( dbg_lss ), + .dbg_is_o ( dbg_is ), + .dbg_wp_o ( dbg_wp ), + .dbg_bp_o ( dbg_bp ), + .dbg_dat_o ( dbg_dat_risc ), + .dbg_ack_o ( dbg_ack ), + .dbg_stb_i ( dbg_stb ), + .dbg_we_i ( dbg_we ), + + // Power Management + .pm_clksd_o ( ), + .pm_cpustall_i ( 1'b0 ), + .pm_dc_gate_o ( ), + .pm_ic_gate_o ( ), + .pm_dmmu_gate_o ( ), + .pm_immu_gate_o ( ), + .pm_tt_gate_o ( ), + .pm_cpu_gate_o ( ), + .pm_wakeup_o ( ), + .pm_lvolt_o ( ), + + // Interrupts + .pic_ints_i ( pic_ints ) +); + +// +// Startup OR1k +// +`ifdef START_UP +OR1K_startup OR1K_startup0 +( + .wb_adr_i(wb_fs_adr_i[6:2]), + .wb_stb_i(wb_fs_stb_i), + .wb_cyc_i(wb_fs_cyc_i), + .wb_dat_o(wb_fs_dat_o), + .wb_ack_o(wb_fs_ack_o), + .wb_clk(wb_clk), + .wb_rst(wb_rst) +); + +spi_flash_top # +( + .divider(0), + .divider_len(2) +) +spi_flash_top0 +( + .wb_clk_i(wb_clk), + .wb_rst_i(wb_rst), + .wb_adr_i(wb_sp_adr_i[4:2]), + .wb_dat_i(wb_sp_dat_i), + .wb_dat_o(wb_sp_dat_o), + .wb_sel_i(wb_sp_sel_i), + .wb_we_i(wb_sp_we_i), + .wb_stb_i(wb_sp_stb_i), + .wb_cyc_i(wb_sp_cyc_i), + .wb_ack_o(wb_sp_ack_o), + + .mosi_pad_o(spi_flash_mosi), + .miso_pad_i(spi_flash_miso), + .sclk_pad_o(spi_flash_sclk), + .ss_pad_o(spi_flash_ss) +); +`else +assign wb_fs_dat_o = 32'h0000_0000; +assign wb_fs_ack_o = 1'b0; +assign wb_sp_dat_o = 32'h0000_0000; +assign wb_sp_ack_o = 1'b0; +`endif + +// +// Instantiation of the SRAM controller +// +`ifdef MEMORY_MODEL +minsoc_memory_model # +`else +minsoc_onchip_ram_top # +`endif +( + .adr_width(`MEMORY_ADR_WIDTH) //16 blocks of 2048 bytes memory 32768 +) +onchip_ram_top ( + + // WISHBONE common + .wb_clk_i ( wb_clk ), + .wb_rst_i ( wb_rst ), + + // WISHBONE slave + .wb_dat_i ( wb_ss_dat_i ), + .wb_dat_o ( wb_ss_dat_o ), + .wb_adr_i ( wb_ss_adr_i ), + .wb_sel_i ( wb_ss_sel_i ), + .wb_we_i ( wb_ss_we_i ), + .wb_cyc_i ( wb_ss_cyc_i ), + .wb_stb_i ( wb_ss_stb_i ), + .wb_ack_o ( wb_ss_ack_o ), + .wb_err_o ( wb_ss_err_o ) +); + +// +// Instantiation of the UART16550 +// +`ifdef UART +uart_top uart_top ( + + // WISHBONE common + .wb_clk_i ( wb_clk ), + .wb_rst_i ( wb_rst ), + + // WISHBONE slave + .wb_adr_i ( wb_us_adr_i[4:0] ), + .wb_dat_i ( wb_us_dat_i ), + .wb_dat_o ( wb_us_dat_o ), + .wb_we_i ( wb_us_we_i ), + .wb_stb_i ( wb_us_stb_i ), + .wb_cyc_i ( wb_us_cyc_i ), + .wb_ack_o ( wb_us_ack_o ), + .wb_sel_i ( wb_us_sel_i ), + + // Interrupt request + .int_o ( pic_ints[`APP_INT_UART] ), + + // UART signals + // serial input/output + .stx_pad_o ( uart_stx ), + .srx_pad_i ( uart_srx ), + + // modem signals + .rts_pad_o ( ), + .cts_pad_i ( 1'b0 ), + .dtr_pad_o ( ), + .dsr_pad_i ( 1'b0 ), + .ri_pad_i ( 1'b0 ), + .dcd_pad_i ( 1'b0 ) +); +`else +assign wb_us_dat_o = 32'h0000_0000; +assign wb_us_ack_o = 1'b0; + +assign pic_ints[`APP_INT_UART] = 1'b0; +`endif + +// +// Instantiation of the Ethernet 10/100 MAC +// +`ifdef ETHERNET +ethmac ethmac ( + + // WISHBONE common + .wb_clk_i ( wb_clk ), + .wb_rst_i ( wb_rst ), + + // WISHBONE slave + .wb_dat_i ( wb_es_dat_i ), + .wb_dat_o ( wb_es_dat_o ), + .wb_adr_i ( wb_es_adr_i[11:2] ), + .wb_sel_i ( wb_es_sel_i ), + .wb_we_i ( wb_es_we_i ), + .wb_cyc_i ( wb_es_cyc_i ), + .wb_stb_i ( wb_es_stb_i ), + .wb_ack_o ( wb_es_ack_o ), + .wb_err_o ( wb_es_err_o ), + + // WISHBONE master + .m_wb_adr_o ( wb_em_adr_o ), + .m_wb_sel_o ( wb_em_sel_o ), + .m_wb_we_o ( wb_em_we_o ), + .m_wb_dat_o ( wb_em_dat_o ), + .m_wb_dat_i ( wb_em_dat_i ), + .m_wb_cyc_o ( wb_em_cyc_o ), + .m_wb_stb_o ( wb_em_stb_o ), + .m_wb_ack_i ( wb_em_ack_i ), + .m_wb_err_i ( wb_em_err_i ), + + // TX + .mtx_clk_pad_i ( eth_tx_clk ), + .mtxd_pad_o ( eth_txd ), + .mtxen_pad_o ( eth_tx_en ), + .mtxerr_pad_o ( eth_tx_er ), + + // RX + .mrx_clk_pad_i ( eth_rx_clk ), + .mrxd_pad_i ( eth_rxd ), + .mrxdv_pad_i ( eth_rx_dv ), + .mrxerr_pad_i ( eth_rx_er ), + .mcoll_pad_i ( eth_col ), + .mcrs_pad_i ( eth_crs ), + + // MIIM + .mdc_pad_o ( eth_mdc ), + .md_pad_i ( eth_mdio ), + .md_pad_o ( eth_mdo ), + .md_padoe_o ( eth_mdoe ), + + // Interrupt + .int_o ( pic_ints[`APP_INT_ETH] ) +); +`else +assign wb_es_dat_o = 32'h0000_0000; +assign wb_es_ack_o = 1'b0; +assign wb_es_err_o = 1'b0; + +assign wb_em_adr_o = 32'h0000_0000; +assign wb_em_sel_o = 4'h0; +assign wb_em_we_o = 1'b0; +assign wb_em_dat_o = 32'h0000_0000; +assign wb_em_cyc_o = 1'b0; +assign wb_em_stb_o = 1'b0; + +assign pic_ints[`APP_INT_ETH] = 1'b0; +`endif + +// +// Instantiation of the Traffic COP +// +minsoc_tc_top #(`APP_ADDR_DEC_W, + `APP_ADDR_SRAM, + `APP_ADDR_DEC_W, + `APP_ADDR_FLASH, + `APP_ADDR_DECP_W, + `APP_ADDR_PERIP, + `APP_ADDR_DEC_W, + `APP_ADDR_SPI, + `APP_ADDR_ETH, + `APP_ADDR_AUDIO, + `APP_ADDR_UART, + `APP_ADDR_PS2, + `APP_ADDR_RES1, + `APP_ADDR_RES2 + ) tc_top ( + + // WISHBONE common + .wb_clk_i ( wb_clk ), + .wb_rst_i ( wb_rst ), + + // WISHBONE Initiator 0 + .i0_wb_cyc_i ( 1'b0 ), + .i0_wb_stb_i ( 1'b0 ), + .i0_wb_adr_i ( 32'h0000_0000 ), + .i0_wb_sel_i ( 4'b0000 ), + .i0_wb_we_i ( 1'b0 ), + .i0_wb_dat_i ( 32'h0000_0000 ), + .i0_wb_dat_o ( ), + .i0_wb_ack_o ( ), + .i0_wb_err_o ( ), + + // WISHBONE Initiator 1 + .i1_wb_cyc_i ( wb_em_cyc_o ), + .i1_wb_stb_i ( wb_em_stb_o ), + .i1_wb_adr_i ( wb_em_adr_o ), + .i1_wb_sel_i ( wb_em_sel_o ), + .i1_wb_we_i ( wb_em_we_o ), + .i1_wb_dat_i ( wb_em_dat_o ), + .i1_wb_dat_o ( wb_em_dat_i ), + .i1_wb_ack_o ( wb_em_ack_i ), + .i1_wb_err_o ( wb_em_err_i ), + + // WISHBONE Initiator 2 + .i2_wb_cyc_i ( 1'b0 ), + .i2_wb_stb_i ( 1'b0 ), + .i2_wb_adr_i ( 32'h0000_0000 ), + .i2_wb_sel_i ( 4'b0000 ), + .i2_wb_we_i ( 1'b0 ), + .i2_wb_dat_i ( 32'h0000_0000 ), + .i2_wb_dat_o ( ), + .i2_wb_ack_o ( ), + .i2_wb_err_o ( ), + + // WISHBONE Initiator 3 + .i3_wb_cyc_i ( wb_dm_cyc_o ), + .i3_wb_stb_i ( wb_dm_stb_o ), + .i3_wb_adr_i ( wb_dm_adr_o ), + .i3_wb_sel_i ( wb_dm_sel_o ), + .i3_wb_we_i ( wb_dm_we_o ), + .i3_wb_dat_i ( wb_dm_dat_o ), + .i3_wb_dat_o ( wb_dm_dat_i ), + .i3_wb_ack_o ( wb_dm_ack_i ), + .i3_wb_err_o ( wb_dm_err_i ), + + // WISHBONE Initiator 4 + .i4_wb_cyc_i ( wb_rdm_cyc_o ), + .i4_wb_stb_i ( wb_rdm_stb_o ), + .i4_wb_adr_i ( wb_rdm_adr_o ), + .i4_wb_sel_i ( wb_rdm_sel_o ), + .i4_wb_we_i ( wb_rdm_we_o ), + .i4_wb_dat_i ( wb_rdm_dat_o ), + .i4_wb_dat_o ( wb_rdm_dat_i ), + .i4_wb_ack_o ( wb_rdm_ack_i ), + .i4_wb_err_o ( wb_rdm_err_i ), + + // WISHBONE Initiator 5 + .i5_wb_cyc_i ( wb_rim_cyc_o ), + .i5_wb_stb_i ( wb_rim_stb_o ), + .i5_wb_adr_i ( wb_rim_adr_o ), + .i5_wb_sel_i ( wb_rim_sel_o ), + .i5_wb_we_i ( wb_rim_we_o ), + .i5_wb_dat_i ( wb_rim_dat_o ), + .i5_wb_dat_o ( wb_rim_dat_i ), + .i5_wb_ack_o ( wb_rim_ack_i ), + .i5_wb_err_o ( wb_rim_err_i ), + + // WISHBONE Initiator 6 + .i6_wb_cyc_i ( 1'b0 ), + .i6_wb_stb_i ( 1'b0 ), + .i6_wb_adr_i ( 32'h0000_0000 ), + .i6_wb_sel_i ( 4'b0000 ), + .i6_wb_we_i ( 1'b0 ), + .i6_wb_dat_i ( 32'h0000_0000 ), + .i6_wb_dat_o ( ), + .i6_wb_ack_o ( ), + .i6_wb_err_o ( ), + + // WISHBONE Initiator 7 + .i7_wb_cyc_i ( 1'b0 ), + .i7_wb_stb_i ( 1'b0 ), + .i7_wb_adr_i ( 32'h0000_0000 ), + .i7_wb_sel_i ( 4'b0000 ), + .i7_wb_we_i ( 1'b0 ), + .i7_wb_dat_i ( 32'h0000_0000 ), + .i7_wb_dat_o ( ), + .i7_wb_ack_o ( ), + .i7_wb_err_o ( ), + + // WISHBONE Target 0 + .t0_wb_cyc_o ( wb_ss_cyc_i ), + .t0_wb_stb_o ( wb_ss_stb_i ), + .t0_wb_adr_o ( wb_ss_adr_i ), + .t0_wb_sel_o ( wb_ss_sel_i ), + .t0_wb_we_o ( wb_ss_we_i ), + .t0_wb_dat_o ( wb_ss_dat_i ), + .t0_wb_dat_i ( wb_ss_dat_o ), + .t0_wb_ack_i ( wb_ss_ack_o ), + .t0_wb_err_i ( wb_ss_err_o ), + + // WISHBONE Target 1 + .t1_wb_cyc_o ( wb_fs_cyc_i ), + .t1_wb_stb_o ( wb_fs_stb_i ), + .t1_wb_adr_o ( wb_fs_adr_i ), + .t1_wb_sel_o ( wb_fs_sel_i ), + .t1_wb_we_o ( wb_fs_we_i ), + .t1_wb_dat_o ( wb_fs_dat_i ), + .t1_wb_dat_i ( wb_fs_dat_o ), + .t1_wb_ack_i ( wb_fs_ack_o ), + .t1_wb_err_i ( wb_fs_err_o ), + + // WISHBONE Target 2 + .t2_wb_cyc_o ( wb_sp_cyc_i ), + .t2_wb_stb_o ( wb_sp_stb_i ), + .t2_wb_adr_o ( wb_sp_adr_i ), + .t2_wb_sel_o ( wb_sp_sel_i ), + .t2_wb_we_o ( wb_sp_we_i ), + .t2_wb_dat_o ( wb_sp_dat_i ), + .t2_wb_dat_i ( wb_sp_dat_o ), + .t2_wb_ack_i ( wb_sp_ack_o ), + .t2_wb_err_i ( wb_sp_err_o ), + + // WISHBONE Target 3 + .t3_wb_cyc_o ( wb_es_cyc_i ), + .t3_wb_stb_o ( wb_es_stb_i ), + .t3_wb_adr_o ( wb_es_adr_i ), + .t3_wb_sel_o ( wb_es_sel_i ), + .t3_wb_we_o ( wb_es_we_i ), + .t3_wb_dat_o ( wb_es_dat_i ), + .t3_wb_dat_i ( wb_es_dat_o ), + .t3_wb_ack_i ( wb_es_ack_o ), + .t3_wb_err_i ( wb_es_err_o ), + + // WISHBONE Target 4 + .t4_wb_cyc_o ( ), + .t4_wb_stb_o ( ), + .t4_wb_adr_o ( ), + .t4_wb_sel_o ( ), + .t4_wb_we_o ( ), + .t4_wb_dat_o ( ), + .t4_wb_dat_i ( 32'h0000_0000 ), + .t4_wb_ack_i ( 1'b0 ), + .t4_wb_err_i ( 1'b1 ), + + // WISHBONE Target 5 + .t5_wb_cyc_o ( wb_us_cyc_i ), + .t5_wb_stb_o ( wb_us_stb_i ), + .t5_wb_adr_o ( wb_us_adr_i ), + .t5_wb_sel_o ( wb_us_sel_i ), + .t5_wb_we_o ( wb_us_we_i ), + .t5_wb_dat_o ( wb_us_dat_i ), + .t5_wb_dat_i ( wb_us_dat_o ), + .t5_wb_ack_i ( wb_us_ack_o ), + .t5_wb_err_i ( wb_us_err_o ), + + // WISHBONE Target 6 + .t6_wb_cyc_o ( ), + .t6_wb_stb_o ( ), + .t6_wb_adr_o ( ), + .t6_wb_sel_o ( ), + .t6_wb_we_o ( ), + .t6_wb_dat_o ( ), + .t6_wb_dat_i ( 32'h0000_0000 ), + .t6_wb_ack_i ( 1'b0 ), + .t6_wb_err_i ( 1'b1 ), + + // WISHBONE Target 7 + .t7_wb_cyc_o ( ), + .t7_wb_stb_o ( ), + .t7_wb_adr_o ( ), + .t7_wb_sel_o ( ), + .t7_wb_we_o ( ), + .t7_wb_dat_o ( ), + .t7_wb_dat_i ( 32'h0000_0000 ), + .t7_wb_ack_i ( 1'b0 ), + .t7_wb_err_i ( 1'b1 ), + + // WISHBONE Target 8 + .t8_wb_cyc_o ( ), + .t8_wb_stb_o ( ), + .t8_wb_adr_o ( ), + .t8_wb_sel_o ( ), + .t8_wb_we_o ( ), + .t8_wb_dat_o ( ), + .t8_wb_dat_i ( 32'h0000_0000 ), + .t8_wb_ack_i ( 1'b0 ), + .t8_wb_err_i ( 1'b1 ) +); + +//initial begin +// $dumpvars(0); +// $dumpfile("dump.vcd"); +//end + +endmodule
rc-1.0/rtl/verilog/minsoc_top.v Property changes : Added: svn:executable ## -0,0 +1 ## +* \ No newline at end of property Index: rc-1.0/rtl/verilog/timescale.v =================================================================== --- rc-1.0/rtl/verilog/timescale.v (nonexistent) +++ rc-1.0/rtl/verilog/timescale.v (revision 109) @@ -0,0 +1 @@ +`timescale 10ns/1ns Index: rc-1.0/rtl/verilog/altera_pll.v =================================================================== --- rc-1.0/rtl/verilog/altera_pll.v (nonexistent) +++ rc-1.0/rtl/verilog/altera_pll.v (revision 109) @@ -0,0 +1,158 @@ + +`include "minsoc_defines.v" + +module altera_pll ( + inclk0, + c0); + + parameter FREQ_MULT = 1; + parameter FREQ_DIV = 1; + + input inclk0; + output c0; + + +`ifdef ARRIA_GX + localparam FAMILY = "Arria GX"; +`elsif ARRIA_II_GX + localparam FAMILY = "Arria II GX"; +`elsif CYCLONE_I + localparam FAMILY = "Cyclone I"; +`elsif CYCLONE_II + localparam FAMILY = "Cyclone II"; +`elsif CYCLONE_III + localparam FAMILY = "Cyclone III"; +`elsif CYCLONE_III_LS + localparam FAMILY = "Cyclone III LS"; +`elsif CYCLONE_IV_E + localparam FAMILY = "Cyclone IV E"; +`elsif CYCLONE_IV_GS + localparam FAMILY = "Cyclone IV GS"; +`elsif MAX_II + localparam FAMILY = "MAX II"; +`elsif MAX_V + localparam FAMILY = "MAX V"; +`elsif MAX3000A + localparam FAMILY = "MAX3000A"; +`elsif MAX7000AE + localparam FAMILY = "MAX7000AE"; +`elsif MAX7000B + localparam FAMILY = "MAX7000B"; +`elsif MAX7000S + localparam FAMILY = "MAX7000S"; +`elsif STRATIX + localparam FAMILY = "Stratix"; +`elsif STRATIX_II + defapram systemPll.FAMILY = "Stratix II"; +`elsif STRATIX_II_GX + localparam FAMILY = "Stratix II GX"; +`elsif STRATIX_III + localparam FAMILY = "Stratix III" +`endif + + + wire [4:0] sub_wire0; + wire [0:0] sub_wire4 = 1'h0; + wire [0:0] sub_wire1 = sub_wire0[0:0]; + wire c0 = sub_wire1; + wire sub_wire2 = inclk0; + wire [1:0] sub_wire3 = {sub_wire4, sub_wire2}; + +`ifdef ALTERA_FPGA + altpll altpll_component ( + .inclk (sub_wire3), + .clk (sub_wire0), + .activeclock (), + .areset (1'b0), + .clkbad (), + .clkena ({6{1'b1}}), + .clkloss (), + .clkswitch (1'b0), + .configupdate (1'b0), + .enable0 (), + .enable1 (), + .extclk (), + .extclkena ({4{1'b1}}), + .fbin (1'b1), + .fbmimicbidir (), + .fbout (), + .fref (), + .icdrclk (), + .locked (), + .pfdena (1'b1), + .phasecounterselect ({4{1'b1}}), + .phasedone (), + .phasestep (1'b1), + .phaseupdown (1'b1), + .pllena (1'b1), + .scanaclr (1'b0), + .scanclk (1'b0), + .scanclkena (1'b1), + .scandata (1'b0), + .scandataout (), + .scandone (), + .scanread (1'b0), + .scanwrite (1'b0), + .sclkout0 (), + .sclkout1 (), + .vcooverrange (), + .vcounderrange ()); + defparam + altpll_component.bandwidth_type = "AUTO", + altpll_component.clk0_divide_by = FREQ_DIV, + altpll_component.clk0_duty_cycle = 50, + altpll_component.clk0_multiply_by = FREQ_MULT, + altpll_component.clk0_phase_shift = "0", + altpll_component.compensate_clock = "CLK0", + altpll_component.inclk0_input_frequency = 20000, + altpll_component.intended_device_family = FAMILY, + altpll_component.lpm_hint = "CBX_MODULE_PREFIX=minsocPll", + altpll_component.lpm_type = "altpll", + altpll_component.operation_mode = "NORMAL", + altpll_component.pll_type = "AUTO", + altpll_component.port_activeclock = "PORT_UNUSED", + altpll_component.port_areset = "PORT_UNUSED", + altpll_component.port_clkbad0 = "PORT_UNUSED", + altpll_component.port_clkbad1 = "PORT_UNUSED", + altpll_component.port_clkloss = "PORT_UNUSED", + altpll_component.port_clkswitch = "PORT_UNUSED", + altpll_component.port_configupdate = "PORT_UNUSED", + altpll_component.port_fbin = "PORT_UNUSED", + altpll_component.port_inclk0 = "PORT_USED", + altpll_component.port_inclk1 = "PORT_UNUSED", + altpll_component.port_locked = "PORT_UNUSED", + altpll_component.port_pfdena = "PORT_UNUSED", + altpll_component.port_phasecounterselect = "PORT_UNUSED", + altpll_component.port_phasedone = "PORT_UNUSED", + altpll_component.port_phasestep = "PORT_UNUSED", + altpll_component.port_phaseupdown = "PORT_UNUSED", + altpll_component.port_pllena = "PORT_UNUSED", + altpll_component.port_scanaclr = "PORT_UNUSED", + altpll_component.port_scanclk = "PORT_UNUSED", + altpll_component.port_scanclkena = "PORT_UNUSED", + altpll_component.port_scandata = "PORT_UNUSED", + altpll_component.port_scandataout = "PORT_UNUSED", + altpll_component.port_scandone = "PORT_UNUSED", + altpll_component.port_scanread = "PORT_UNUSED", + altpll_component.port_scanwrite = "PORT_UNUSED", + altpll_component.port_clk0 = "PORT_USED", + altpll_component.port_clk1 = "PORT_UNUSED", + altpll_component.port_clk2 = "PORT_UNUSED", + altpll_component.port_clk3 = "PORT_UNUSED", + altpll_component.port_clk4 = "PORT_UNUSED", + altpll_component.port_clk5 = "PORT_UNUSED", + altpll_component.port_clkena0 = "PORT_UNUSED", + altpll_component.port_clkena1 = "PORT_UNUSED", + altpll_component.port_clkena2 = "PORT_UNUSED", + altpll_component.port_clkena3 = "PORT_UNUSED", + altpll_component.port_clkena4 = "PORT_UNUSED", + altpll_component.port_clkena5 = "PORT_UNUSED", + altpll_component.port_extclk0 = "PORT_UNUSED", + altpll_component.port_extclk1 = "PORT_UNUSED", + altpll_component.port_extclk2 = "PORT_UNUSED", + altpll_component.port_extclk3 = "PORT_UNUSED", + altpll_component.width_clock = 5; +`endif + +endmodule + Index: rc-1.0/rtl/verilog/minsoc_clock_manager.v =================================================================== --- rc-1.0/rtl/verilog/minsoc_clock_manager.v (nonexistent) +++ rc-1.0/rtl/verilog/minsoc_clock_manager.v (revision 109) @@ -0,0 +1,60 @@ + +`include "minsoc_defines.v" + +module minsoc_clock_manager( + clk_i, + clk_o +); + +// +// Parameters +// + parameter divisor = 2; + +input clk_i; +output clk_o; + +`ifdef NO_CLOCK_DIVISION +assign clk_o = clk_i; + +`elsif GENERIC_CLOCK_DIVISION +reg [31:0] clock_divisor; +reg clk_int; +always @ (posedge clk_i) +begin + clock_divisor <= clock_divisor + 1'b1; + if ( clock_divisor >= divisor/2 - 1 ) begin + clk_int <= ~clk_int; + clock_divisor <= 32'h0000_0000; + end +end +assign clk_o = clk_int; + +`elsif FPGA_CLOCK_DIVISION +`ifdef ALTERA_FPGA +altera_pll # +( + .FREQ_DIV(divisor) +) +minsoc_altera_pll +( + .inclk0(clk_i), + .c0(clk_o) +); + +`elsif XILINX_FPGA +xilinx_dcm # +( + .divisor(divisor) +) +minsoc_xilinx_dcm +( + .clk_i(clk_i), + .clk_o(clk_o) +); + +`endif // !ALTERA_FPGA/XILINX_FPGA +`endif // !NO_CLOCK_DIVISION/GENERIC_CLOCK_DIVISION/FPGA_CLOCK_DIVISION + + +endmodule
rc-1.0/rtl/verilog/minsoc_clock_manager.v Property changes : Added: svn:executable ## -0,0 +1 ## +* \ No newline at end of property Index: rc-1.0/rtl/verilog/minsoc_startup/spi_top.v =================================================================== --- rc-1.0/rtl/verilog/minsoc_startup/spi_top.v (nonexistent) +++ rc-1.0/rtl/verilog/minsoc_startup/spi_top.v (revision 109) @@ -0,0 +1,224 @@ +////////////////////////////////////////////////////////////////////// +//// //// +//// spi_top.v //// +//// //// +//// This file is part of the SPI IP core project //// +//// http://www.opencores.org/projects/spi/ //// +//// //// +//// Author(s): //// +//// - Simon Srot (simons@opencores.org) //// +//// //// +//// All additional information is avaliable in the Readme.txt //// +//// file. //// +//// //// +////////////////////////////////////////////////////////////////////// +//// //// +//// Copyright (C) 2002 Authors //// +//// //// +//// This source file may be used and distributed without //// +//// restriction provided that this copyright statement is not //// +//// removed from the file and that any derivative work contains //// +//// the original copyright notice and the associated disclaimer. //// +//// //// +//// This source file is free software; you can redistribute it //// +//// and/or modify it under the terms of the GNU Lesser General //// +//// Public License as published by the Free Software Foundation; //// +//// either version 2.1 of the License, or (at your option) any //// +//// later version. //// +//// //// +//// This source is distributed in the hope that it will be //// +//// useful, but WITHOUT ANY WARRANTY; without even the implied //// +//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR //// +//// PURPOSE. See the GNU Lesser General Public License for more //// +//// details. //// +//// //// +//// You should have received a copy of the GNU Lesser General //// +//// Public License along with this source; if not, download it //// +//// from http://www.opencores.org/lgpl.shtml //// +//// //// +////////////////////////////////////////////////////////////////////// + + +`include "spi_defines.v" +`include "timescale.v" + +module spi_flash_top + ( + // Wishbone signals + wb_clk_i, wb_rst_i, wb_adr_i, wb_dat_i, wb_dat_o, wb_sel_i, + wb_we_i, wb_stb_i, wb_cyc_i, wb_ack_o, + // SPI signals + ss_pad_o, sclk_pad_o, mosi_pad_o, miso_pad_i + ); + + parameter divider_len = 2; + parameter divider = 0; + + parameter Tp = 1; + + // Wishbone signals + input wb_clk_i; // master clock input + input wb_rst_i; // synchronous active high reset + input [4:2] wb_adr_i; // lower address bits + input [31:0] wb_dat_i; // databus input + output [31:0] wb_dat_o; // databus output + input [3:0] wb_sel_i; // byte select inputs + input wb_we_i; // write enable input + input wb_stb_i; // stobe/core select signal + input wb_cyc_i; // valid bus cycle input + output wb_ack_o; // bus cycle acknowledge output + + // SPI signals + output [`SPI_SS_NB-1:0] ss_pad_o; // slave select + output sclk_pad_o; // serial clock + output mosi_pad_o; // master out slave in + input miso_pad_i; // master in slave out + + reg [31:0] wb_dat_o; + reg wb_ack_o; + + // Internal signals + // reg [`SPI_DIVIDER_LEN-1:0] divider; // Divider register + wire [`SPI_CTRL_BIT_NB-1:0] ctrl; // Control and status register + reg [`SPI_SS_NB-1:0] ss; // Slave select register + wire [`SPI_MAX_CHAR-1:0] rx; // Rx register + + wire [5:0] char_len; + reg char_len_ctrl; // char len + reg go; // go + + wire spi_ctrl_sel; // ctrl register select + wire spi_tx_sel; // tx_l register select + wire spi_ss_sel; // ss register select + wire tip; // transfer in progress + wire pos_edge; // recognize posedge of sclk + wire neg_edge; // recognize negedge of sclk + wire last_bit; // marks last character bit + + wire rx_negedge; // miso is sampled on negative edge + wire tx_negedge; // mosi is driven on negative edge + wire lsb; // lsb first on line + wire ass; // automatic slave select + + // Address decoder + assign spi_ctrl_sel = wb_cyc_i & wb_stb_i & (wb_adr_i[`SPI_OFS_BITS] == `SPI_CTRL); + assign spi_tx_sel = wb_cyc_i & wb_stb_i & (wb_adr_i[`SPI_OFS_BITS] == `SPI_TX_0); + assign spi_ss_sel = wb_cyc_i & wb_stb_i & (wb_adr_i[`SPI_OFS_BITS] == `SPI_SS); + + // Read from registers + // Wb data out + always @(posedge wb_clk_i or posedge wb_rst_i) + begin + if (wb_rst_i) + wb_dat_o <= #Tp 32'b0; + else + case (wb_adr_i[`SPI_OFS_BITS]) + `SPI_RX_0: wb_dat_o <= rx; + `SPI_CTRL: wb_dat_o <= {18'd0, ctrl}; + `SPI_DEVIDE: wb_dat_o <= divider; + `SPI_SS: wb_dat_o <= {{32-`SPI_SS_NB{1'b0}}, ss}; + default: wb_dat_o <= rx; + endcase + end + + // Wb acknowledge + always @(posedge wb_clk_i or posedge wb_rst_i) + begin + if (wb_rst_i) + wb_ack_o <= #Tp 1'b0; + else + wb_ack_o <= #Tp wb_cyc_i & wb_stb_i & ~wb_ack_o; + end + + // Ctrl register + always @(posedge wb_clk_i or posedge wb_rst_i) + begin + if (wb_rst_i) + {go,char_len_ctrl} <= #Tp 2'b01; + else if(spi_ctrl_sel && wb_we_i && !tip) + begin + if (wb_sel_i[0]) + char_len_ctrl <= #Tp wb_dat_i[5]; + if (wb_sel_i[1]) + go <= #Tp wb_dat_i[8]; + end + else if(tip && last_bit && pos_edge) + go <= #Tp 1'b0; + end + + assign char_len = char_len_ctrl ? 6'd32 : 6'd8; +`ifdef SPI_CTRL_ASS + assign ass = 1'b1; +`else + assign ass = 1'b0; +`endif +`ifdef SPI_CTRL_LSB + assign lsb = 1'b1; +`else + assign lsb = 1'b0; +`endif +`ifdef SPI_CTRL_RX_NEGEDGE + assign rx_negedge = 1'b1; +`else + assign rx_negedge = 1'b0; +`endif +`ifdef SPI_CTRL_TX_NEGEDGE + assign tx_negedge = 1'b1; +`else + assign tx_negedge = 1'b0; +`endif + + assign ctrl = {ass,1'b0,lsb,tx_negedge,rx_negedge,go,1'b0,1'b0,char_len}; + + // Slave select register + always @(posedge wb_clk_i or posedge wb_rst_i) + if (wb_rst_i) + ss <= #Tp {`SPI_SS_NB{1'b0}}; + else if(spi_ss_sel && wb_we_i && !tip) + if (wb_sel_i[0]) + ss <= #Tp wb_dat_i[`SPI_SS_NB-1:0]; + + assign ss_pad_o = ~((ss & {`SPI_SS_NB{tip & ass}}) | (ss & {`SPI_SS_NB{!ass}})); + + spi_flash_clgen + # + ( + .divider_len(divider_len), + .divider(divider) + ) + clgen + ( + .clk_in(wb_clk_i), + .rst(wb_rst_i), + .go(go), + .enable(tip), + .last_clk(last_bit), + .clk_out(sclk_pad_o), + .pos_edge(pos_edge), + .neg_edge(neg_edge) + ); + + spi_flash_shift shift + ( + .clk(wb_clk_i), + .rst(wb_rst_i), + .len(char_len[`SPI_CHAR_LEN_BITS-1:0]), + .latch(spi_tx_sel & wb_we_i), + .byte_sel(wb_sel_i), + .go(go), + .pos_edge(pos_edge), + .neg_edge(neg_edge), + .lsb(lsb), + .rx_negedge(rx_negedge), + .tx_negedge(tx_negedge), + .tip(tip), + .last(last_bit), + .p_in(wb_dat_i), + .p_out(rx), + .s_clk(sclk_pad_o), + .s_in(miso_pad_i), + .s_out(mosi_pad_o) + ); + +endmodule +
rc-1.0/rtl/verilog/minsoc_startup/spi_top.v Property changes : Added: svn:executable ## -0,0 +1 ## +* \ No newline at end of property Index: rc-1.0/rtl/verilog/minsoc_startup/spi_clgen.v =================================================================== --- rc-1.0/rtl/verilog/minsoc_startup/spi_clgen.v (nonexistent) +++ rc-1.0/rtl/verilog/minsoc_startup/spi_clgen.v (revision 109) @@ -0,0 +1,110 @@ +////////////////////////////////////////////////////////////////////// +//// //// +//// spi_clgen.v //// +//// //// +//// This file is part of the SPI IP core project //// +//// http://www.opencores.org/projects/spi/ //// +//// //// +//// Author(s): //// +//// - Simon Srot (simons@opencores.org) //// +//// //// +//// All additional information is avaliable in the Readme.txt //// +//// file. //// +//// //// +////////////////////////////////////////////////////////////////////// +//// //// +//// Copyright (C) 2002 Authors //// +//// //// +//// This source file may be used and distributed without //// +//// restriction provided that this copyright statement is not //// +//// removed from the file and that any derivative work contains //// +//// the original copyright notice and the associated disclaimer. //// +//// //// +//// This source file is free software; you can redistribute it //// +//// and/or modify it under the terms of the GNU Lesser General //// +//// Public License as published by the Free Software Foundation; //// +//// either version 2.1 of the License, or (at your option) any //// +//// later version. //// +//// //// +//// This source is distributed in the hope that it will be //// +//// useful, but WITHOUT ANY WARRANTY; without even the implied //// +//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR //// +//// PURPOSE. See the GNU Lesser General Public License for more //// +//// details. //// +//// //// +//// You should have received a copy of the GNU Lesser General //// +//// Public License along with this source; if not, download it //// +//// from http://www.opencores.org/lgpl.shtml //// +//// //// +////////////////////////////////////////////////////////////////////// + +`include "spi_defines.v" +`include "timescale.v" + +module spi_flash_clgen (clk_in, rst, go, enable, last_clk, clk_out, pos_edge, neg_edge); + + parameter divider_len = 2; + parameter divider = 1; + + parameter Tp = 1; + + input clk_in; // input clock (system clock) + input rst; // reset + input enable; // clock enable + input go; // start transfer + input last_clk; // last clock + //input [spi_divider_len-1:0] divider; // clock divider (output clock is divided by this value) + output clk_out; // output clock + output pos_edge; // pulse marking positive edge of clk_out + output neg_edge; // pulse marking negative edge of clk_out + + reg clk_out; + reg pos_edge; + reg neg_edge; + + reg [divider_len-1:0] cnt; // clock counter + wire cnt_zero; // conter is equal to zero + wire cnt_one; // conter is equal to one + + + assign cnt_zero = cnt == {divider_len{1'b0}}; + assign cnt_one = cnt == {{divider_len-1{1'b0}}, 1'b1}; + + // Counter counts half period + always @(posedge clk_in or posedge rst) + begin + if(rst) + cnt <= #Tp {divider_len{1'b1}}; + else + begin + if(!enable || cnt_zero) + cnt <= #Tp divider; + else + cnt <= #Tp cnt - {{divider_len-1{1'b0}}, 1'b1}; + end + end + + // clk_out is asserted every other half period + always @(posedge clk_in or posedge rst) + begin + if(rst) + clk_out <= #Tp 1'b0; + else + clk_out <= #Tp (enable && cnt_zero && (!last_clk || clk_out)) ? ~clk_out : clk_out; + end + + // Pos and neg edge signals + always @(posedge clk_in or posedge rst) + begin + if(rst) + begin + pos_edge <= #Tp 1'b0; + neg_edge <= #Tp 1'b0; + end + else + begin + pos_edge <= #Tp (enable && !clk_out && cnt_one) || (!(|divider) && clk_out) || (!(|divider) && go && !enable); + neg_edge <= #Tp (enable && clk_out && cnt_one) || (!(|divider) && !clk_out && enable); + end + end +endmodule
rc-1.0/rtl/verilog/minsoc_startup/spi_clgen.v Property changes : Added: svn:executable ## -0,0 +1 ## +* \ No newline at end of property Index: rc-1.0/rtl/verilog/minsoc_startup/spi_shift.v =================================================================== --- rc-1.0/rtl/verilog/minsoc_startup/spi_shift.v (nonexistent) +++ rc-1.0/rtl/verilog/minsoc_startup/spi_shift.v (revision 109) @@ -0,0 +1,149 @@ +////////////////////////////////////////////////////////////////////// +//// //// +//// spi_shift.v //// +//// //// +//// This file is part of the SPI IP core project //// +//// http://www.opencores.org/projects/spi/ //// +//// //// +//// Author(s): //// +//// - Simon Srot (simons@opencores.org) //// +//// //// +//// All additional information is avaliable in the Readme.txt //// +//// file. //// +//// //// +////////////////////////////////////////////////////////////////////// +//// //// +//// Copyright (C) 2002 Authors //// +//// //// +//// This source file may be used and distributed without //// +//// restriction provided that this copyright statement is not //// +//// removed from the file and that any derivative work contains //// +//// the original copyright notice and the associated disclaimer. //// +//// //// +//// This source file is free software; you can redistribute it //// +//// and/or modify it under the terms of the GNU Lesser General //// +//// Public License as published by the Free Software Foundation; //// +//// either version 2.1 of the License, or (at your option) any //// +//// later version. //// +//// //// +//// This source is distributed in the hope that it will be //// +//// useful, but WITHOUT ANY WARRANTY; without even the implied //// +//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR //// +//// PURPOSE. See the GNU Lesser General Public License for more //// +//// details. //// +//// //// +//// You should have received a copy of the GNU Lesser General //// +//// Public License along with this source; if not, download it //// +//// from http://www.opencores.org/lgpl.shtml //// +//// //// +////////////////////////////////////////////////////////////////////// + +`include "spi_defines.v" +`include "timescale.v" + +module spi_flash_shift + ( + clk, rst, latch, byte_sel, len, go, + pos_edge, neg_edge, + lsb, rx_negedge, tx_negedge, + tip, last, + p_in, p_out, s_clk, s_in, s_out); + + parameter Tp = 1; + + input clk; // system clock + input rst; // reset + input latch; // latch signal for storing the data in shift register + input [3:0] byte_sel; // byte select signals for storing the data in shift register + input [`SPI_CHAR_LEN_BITS-1:0] len; // data len in bits (minus one) + input lsb; // lbs first on the line + input tx_negedge; + input rx_negedge; + input go; // start stansfer + input pos_edge; // recognize posedge of sclk + input neg_edge; // recognize negedge of sclk + output tip; // transfer in progress + output last; // last bit + input [31:0] p_in; // parallel in + output [`SPI_MAX_CHAR-1:0] p_out; // parallel out + input s_clk; // serial clock + input s_in; // serial in + output s_out; // serial out + + reg s_out; + reg tip; + + reg [`SPI_CHAR_LEN_BITS:0] cnt; // data bit count + reg [`SPI_MAX_CHAR-1:0] data; // shift register + wire [`SPI_CHAR_LEN_BITS:0] tx_bit_pos; // next bit position + wire [`SPI_CHAR_LEN_BITS:0] rx_bit_pos; // next bit position + wire rx_clk; // rx clock enable + wire tx_clk; // tx clock enable + + + assign p_out = data; + + assign tx_bit_pos = lsb ? {!(|len), len} - cnt : cnt - {{`SPI_CHAR_LEN_BITS{1'b0}},1'b1}; + assign rx_bit_pos = lsb ? {!(|len), len} - (rx_negedge ? cnt + {{`SPI_CHAR_LEN_BITS{1'b0}},1'b1} : cnt) : (rx_negedge ? cnt : cnt - {{`SPI_CHAR_LEN_BITS{1'b0}},1'b1}); + + assign last = !(|cnt); + + assign rx_clk = (rx_negedge ? neg_edge : pos_edge) && (!last || s_clk); + + assign tx_clk = (tx_negedge ? neg_edge : pos_edge) && !last; + + // Character bit counter + always @(posedge clk or posedge rst) + begin + if(rst) + cnt <= #Tp {`SPI_CHAR_LEN_BITS+1{1'b0}}; + else + begin + if(tip) + cnt <= #Tp pos_edge ? (cnt - {{`SPI_CHAR_LEN_BITS{1'b0}}, 1'b1}) : cnt; + else + cnt <= #Tp !(|len) ? {1'b1, {`SPI_CHAR_LEN_BITS{1'b0}}} : {1'b0, len}; + end + end + + // Transfer in progress + always @(posedge clk or posedge rst) + begin + if(rst) + tip <= #Tp 1'b0; + else if(go && ~tip) + tip <= #Tp 1'b1; + else if(tip && last && pos_edge) + tip <= #Tp 1'b0; + end + + // Sending bits to the line + always @(posedge clk or posedge rst) + begin + if (rst) + s_out <= #Tp 1'b0; + else + s_out <= #Tp (tx_clk || !tip) ? data[tx_bit_pos[`SPI_CHAR_LEN_BITS-1:0]] : s_out; + end + + // Receiving bits from the line + always @(posedge clk or posedge rst) + if (rst) + data <= #Tp `SPI_CHAR_RST; + else + if (latch & !tip) + begin + if (byte_sel[0]) + data[7:0] <= #Tp p_in[7:0]; + if (byte_sel[1]) + data[15:8] <= #Tp p_in[15:8]; + if (byte_sel[2]) + data[23:16] <= #Tp p_in[23:16]; + if (byte_sel[3]) + data[31:24] <= #Tp p_in[31:24]; + end + else + data[rx_bit_pos[`SPI_CHAR_LEN_BITS-1:0]] <= #Tp rx_clk ? s_in : data[rx_bit_pos[`SPI_CHAR_LEN_BITS-1:0]]; + +endmodule +
rc-1.0/rtl/verilog/minsoc_startup/spi_shift.v Property changes : Added: svn:executable ## -0,0 +1 ## +* \ No newline at end of property Index: rc-1.0/rtl/verilog/minsoc_startup/spi_defines.v =================================================================== --- rc-1.0/rtl/verilog/minsoc_startup/spi_defines.v (nonexistent) +++ rc-1.0/rtl/verilog/minsoc_startup/spi_defines.v (revision 109) @@ -0,0 +1,139 @@ +////////////////////////////////////////////////////////////////////// +//// //// +//// spi_define.v //// +//// //// +//// This file is part of the SPI IP core project //// +//// http://www.opencores.org/projects/spi/ //// +//// //// +//// Author(s): //// +//// - Simon Srot (simons@opencores.org) //// +//// //// +//// All additional information is avaliable in the Readme.txt //// +//// file. //// +//// //// +////////////////////////////////////////////////////////////////////// +//// //// +//// Copyright (C) 2002 Authors //// +//// //// +//// This source file may be used and distributed without //// +//// restriction provided that this copyright statement is not //// +//// removed from the file and that any derivative work contains //// +//// the original copyright notice and the associated disclaimer. //// +//// //// +//// This source file is free software; you can redistribute it //// +//// and/or modify it under the terms of the GNU Lesser General //// +//// Public License as published by the Free Software Foundation; //// +//// either version 2.1 of the License, or (at your option) any //// +//// later version. //// +//// //// +//// This source is distributed in the hope that it will be //// +//// useful, but WITHOUT ANY WARRANTY; without even the implied //// +//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR //// +//// PURPOSE. See the GNU Lesser General Public License for more //// +//// details. //// +//// //// +//// You should have received a copy of the GNU Lesser General //// +//// Public License along with this source; if not, download it //// +//// from http://www.opencores.org/lgpl.shtml //// +//// //// +////////////////////////////////////////////////////////////////////// + +// +// Number of bits used for devider register. If used in system with +// low frequency of system clock this can be reduced. +// Use SPI_DIVIDER_LEN for fine tuning theexact number. +// +`define SPI_DIVIDER_LEN_8 +//`define SPI_DIVIDER_LEN_16 +//`define SPI_DIVIDER_LEN_24 +//`define SPI_DIVIDER_LEN_32 + +`ifdef SPI_DIVIDER_LEN_8 + `define SPI_DIVIDER_LEN 4 // Can be set from 1 to 8 +`endif +`ifdef SPI_DIVIDER_LEN_16 + `define SPI_DIVIDER_LEN 16 // Can be set from 9 to 16 +`endif +`ifdef SPI_DIVIDER_LEN_24 + `define SPI_DIVIDER_LEN 24 // Can be set from 17 to 24 +`endif +`ifdef SPI_DIVIDER_LEN_32 + `define SPI_DIVIDER_LEN 32 // Can be set from 25 to 32 +`endif + +// +// Maximum nuber of bits that can be send/received at once. +// Use SPI_MAX_CHAR for fine tuning the exact number, when using +// SPI_MAX_CHAR_32, SPI_MAX_CHAR_24, SPI_MAX_CHAR_16, SPI_MAX_CHAR_8. +// +//`define SPI_MAX_CHAR_128 +//`define SPI_MAX_CHAR_64 +`define SPI_MAX_CHAR_32 +//`define SPI_MAX_CHAR_24 +//`define SPI_MAX_CHAR_16 +//`define SPI_MAX_CHAR_8 + +`ifdef SPI_MAX_CHAR_128 + `define SPI_MAX_CHAR 128 // Can only be set to 128 + `define SPI_CHAR_LEN_BITS 7 +`endif +`ifdef SPI_MAX_CHAR_64 + `define SPI_MAX_CHAR 64 // Can only be set to 64 + `define SPI_CHAR_LEN_BITS 6 +`endif +`ifdef SPI_MAX_CHAR_32 + `define SPI_MAX_CHAR 32 // Can be set from 25 to 32 + `define SPI_CHAR_LEN_BITS 6 + `define SPI_CHAR_RST 32'h03000000 +`endif +`ifdef SPI_MAX_CHAR_24 + `define SPI_MAX_CHAR 24 // Can be set from 17 to 24 + `define SPI_CHAR_LEN_BITS 5 +`endif +`ifdef SPI_MAX_CHAR_16 + `define SPI_MAX_CHAR 16 // Can be set from 9 to 16 + `define SPI_CHAR_LEN_BITS 4 +`endif +`ifdef SPI_MAX_CHAR_8 + `define SPI_MAX_CHAR 8 // Can be set from 1 to 8 + `define SPI_CHAR_LEN_BITS 3 +`endif + +// +// Number of device select signals. Use SPI_SS_NB for fine tuning the +// exact number. +// +`define SPI_SS_NB 2 // Can be set from 1 to 2 + +// +// Bits of WISHBONE address used for partial decoding of SPI registers. +// +`define SPI_OFS_BITS 4:2 + +// +// Register offset +// +`define SPI_RX_0 0 +`define SPI_RX_1 1 +`define SPI_RX_2 2 +`define SPI_RX_3 3 +`define SPI_TX_0 0 +`define SPI_TX_1 1 +`define SPI_TX_2 2 +`define SPI_TX_3 3 +`define SPI_CTRL 4 +`define SPI_DEVIDE 5 +`define SPI_SS 6 + +// +// Number of bits in ctrl register +// +`define SPI_CTRL_BIT_NB 14 +`define SPI_CTRL_BIT_RST 14'h420 +// +// Control register bits +// +//`define SPI_CTRL_LSB +`define SPI_CTRL_TX_NEGEDGE +//`define SPI_CTRL_RX_NEGEDGE +
rc-1.0/rtl/verilog/minsoc_startup/spi_defines.v Property changes : Added: svn:executable ## -0,0 +1 ## +* \ No newline at end of property Index: rc-1.0/rtl/verilog/minsoc_startup/OR1K_startup_generic.v =================================================================== --- rc-1.0/rtl/verilog/minsoc_startup/OR1K_startup_generic.v (nonexistent) +++ rc-1.0/rtl/verilog/minsoc_startup/OR1K_startup_generic.v (revision 109) @@ -0,0 +1,60 @@ + +`include "minsoc_defines.v" + +module OR1K_startup + ( + input [6:2] wb_adr_i, + input wb_stb_i, + input wb_cyc_i, + output reg [31:0] wb_dat_o, + output reg wb_ack_o, + input wb_clk, + input wb_rst + ); + + always @ (posedge wb_clk or posedge wb_rst) + if (wb_rst) + wb_dat_o <= 32'h15000000; + else + case (wb_adr_i) + 0 : wb_dat_o <= 32'h18000000; + 1 : wb_dat_o <= 32'hA8200000; + 2 : wb_dat_o <= { 16'h1880 , `APP_ADDR_SPI , 8'h00 }; + 3 : wb_dat_o <= 32'hA8A00520; + 4 : wb_dat_o <= 32'hA8600001; + 5 : wb_dat_o <= 32'h04000014; + 6 : wb_dat_o <= 32'hD4041818; + 7 : wb_dat_o <= 32'h04000012; + 8 : wb_dat_o <= 32'hD4040000; + 9 : wb_dat_o <= 32'hE0431804; + 10 : wb_dat_o <= 32'h0400000F; + 11 : wb_dat_o <= 32'h9C210008; + 12 : wb_dat_o <= 32'h0400000D; + 13 : wb_dat_o <= 32'hE1031804; + 14 : wb_dat_o <= 32'hE4080000; + 15 : wb_dat_o <= 32'h0FFFFFFB; + 16 : wb_dat_o <= 32'hD4081800; + 17 : wb_dat_o <= 32'h04000008; + 18 : wb_dat_o <= 32'h9C210004; + 19 : wb_dat_o <= 32'hD4011800; + 20 : wb_dat_o <= 32'hE4011000; + 21 : wb_dat_o <= 32'h0FFFFFFC; + 22 : wb_dat_o <= 32'hA8C00100; + 23 : wb_dat_o <= 32'h44003000; + 24 : wb_dat_o <= 32'hD4040018; + 25 : wb_dat_o <= 32'hD4042810; + 26 : wb_dat_o <= 32'h84640010; + 27 : wb_dat_o <= 32'hBC030520; + 28 : wb_dat_o <= 32'h13FFFFFE; + 29 : wb_dat_o <= 32'h15000000; + 30 : wb_dat_o <= 32'h44004800; + 31 : wb_dat_o <= 32'h84640000; + endcase + + always @ (posedge wb_clk or posedge wb_rst) + if (wb_rst) + wb_ack_o <= 1'b0; + else + wb_ack_o <= wb_stb_i & wb_cyc_i & !wb_ack_o; + +endmodule // OR1K_startup
rc-1.0/rtl/verilog/minsoc_startup/OR1K_startup_generic.v Property changes : Added: svn:executable ## -0,0 +1 ## +* \ No newline at end of property Index: rc-1.0/rtl/verilog/minsoc_tc_top.v =================================================================== --- rc-1.0/rtl/verilog/minsoc_tc_top.v (nonexistent) +++ rc-1.0/rtl/verilog/minsoc_tc_top.v (revision 109) @@ -0,0 +1,1684 @@ +////////////////////////////////////////////////////////////////////// +//// //// +//// Xess Traffic Cop //// +//// //// +//// This file is part of the OR1K test application //// +//// http://www.opencores.org/cores/or1k/ //// +//// //// +//// Description //// +//// This block connectes the RISC and peripheral controller //// +//// cores together. //// +//// //// +//// To Do: //// +//// - nothing really //// +//// //// +//// Author(s): //// +//// - Damjan Lampret, lampret@opencores.org //// +//// //// +////////////////////////////////////////////////////////////////////// +//// //// +//// Copyright (C) 2002 OpenCores //// +//// //// +//// This source file may be used and distributed without //// +//// restriction provided that this copyright statement is not //// +//// removed from the file and that any derivative work contains //// +//// the original copyright notice and the associated disclaimer. //// +//// //// +//// This source file is free software; you can redistribute it //// +//// and/or modify it under the terms of the GNU Lesser General //// +//// Public License as published by the Free Software Foundation; //// +//// either version 2.1 of the License, or (at your option) any //// +//// later version. //// +//// //// +//// This source is distributed in the hope that it will be //// +//// useful, but WITHOUT ANY WARRANTY; without even the implied //// +//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR //// +//// PURPOSE. See the GNU Lesser General Public License for more //// +//// details. //// +//// //// +//// You should have received a copy of the GNU Lesser General //// +//// Public License along with this source; if not, download it //// +//// from http://www.opencores.org/lgpl.shtml //// +//// //// +////////////////////////////////////////////////////////////////////// +// +// CVS Revision History +// +// $Log: tc_top.v,v $ +// Revision 1.4 2004/04/05 08:44:34 lampret +// Merged branch_qmem into main tree. +// +// Revision 1.2 2002/03/29 20:57:30 lampret +// Removed unused ports wb_clki and wb_rst_i +// +// Revision 1.1.1.1 2002/03/21 16:55:44 lampret +// First import of the "new" XESS XSV environment. +// +// +// + +// synopsys translate_off +`include "timescale.v" +// synopsys translate_on + +// +// Width of address bus +// +`define TC_AW 32 + +// +// Width of data bus +// +`define TC_DW 32 + +// +// Width of byte select bus +// +`define TC_BSW 4 + +// +// Width of WB target inputs (coming from WB slave) +// +// data bus width + ack + err +// +`define TC_TIN_W `TC_DW+1+1 + +// +// Width of WB initiator inputs (coming from WB masters) +// +// cyc + stb + address bus width + +// byte select bus width + we + data bus width +// +`define TC_IIN_W 1+1+1+`TC_AW+`TC_BSW+1+`TC_DW + +// +// Traffic Cop Top +// +module minsoc_tc_top ( + wb_clk_i, + wb_rst_i, + + i0_wb_cyc_i, + i0_wb_stb_i, + i0_wb_adr_i, + i0_wb_sel_i, + i0_wb_we_i, + i0_wb_dat_i, + i0_wb_dat_o, + i0_wb_ack_o, + i0_wb_err_o, + + i1_wb_cyc_i, + i1_wb_stb_i, + i1_wb_adr_i, + i1_wb_sel_i, + i1_wb_we_i, + i1_wb_dat_i, + i1_wb_dat_o, + i1_wb_ack_o, + i1_wb_err_o, + + i2_wb_cyc_i, + i2_wb_stb_i, + i2_wb_adr_i, + i2_wb_sel_i, + i2_wb_we_i, + i2_wb_dat_i, + i2_wb_dat_o, + i2_wb_ack_o, + i2_wb_err_o, + + i3_wb_cyc_i, + i3_wb_stb_i, + i3_wb_adr_i, + i3_wb_sel_i, + i3_wb_we_i, + i3_wb_dat_i, + i3_wb_dat_o, + i3_wb_ack_o, + i3_wb_err_o, + + i4_wb_cyc_i, + i4_wb_stb_i, + i4_wb_adr_i, + i4_wb_sel_i, + i4_wb_we_i, + i4_wb_dat_i, + i4_wb_dat_o, + i4_wb_ack_o, + i4_wb_err_o, + + i5_wb_cyc_i, + i5_wb_stb_i, + i5_wb_adr_i, + i5_wb_sel_i, + i5_wb_we_i, + i5_wb_dat_i, + i5_wb_dat_o, + i5_wb_ack_o, + i5_wb_err_o, + + i6_wb_cyc_i, + i6_wb_stb_i, + i6_wb_adr_i, + i6_wb_sel_i, + i6_wb_we_i, + i6_wb_dat_i, + i6_wb_dat_o, + i6_wb_ack_o, + i6_wb_err_o, + + i7_wb_cyc_i, + i7_wb_stb_i, + i7_wb_adr_i, + i7_wb_sel_i, + i7_wb_we_i, + i7_wb_dat_i, + i7_wb_dat_o, + i7_wb_ack_o, + i7_wb_err_o, + + t0_wb_cyc_o, + t0_wb_stb_o, + t0_wb_adr_o, + t0_wb_sel_o, + t0_wb_we_o, + t0_wb_dat_o, + t0_wb_dat_i, + t0_wb_ack_i, + t0_wb_err_i, + + t1_wb_cyc_o, + t1_wb_stb_o, + t1_wb_adr_o, + t1_wb_sel_o, + t1_wb_we_o, + t1_wb_dat_o, + t1_wb_dat_i, + t1_wb_ack_i, + t1_wb_err_i, + + t2_wb_cyc_o, + t2_wb_stb_o, + t2_wb_adr_o, + t2_wb_sel_o, + t2_wb_we_o, + t2_wb_dat_o, + t2_wb_dat_i, + t2_wb_ack_i, + t2_wb_err_i, + + t3_wb_cyc_o, + t3_wb_stb_o, + t3_wb_adr_o, + t3_wb_sel_o, + t3_wb_we_o, + t3_wb_dat_o, + t3_wb_dat_i, + t3_wb_ack_i, + t3_wb_err_i, + + t4_wb_cyc_o, + t4_wb_stb_o, + t4_wb_adr_o, + t4_wb_sel_o, + t4_wb_we_o, + t4_wb_dat_o, + t4_wb_dat_i, + t4_wb_ack_i, + t4_wb_err_i, + + t5_wb_cyc_o, + t5_wb_stb_o, + t5_wb_adr_o, + t5_wb_sel_o, + t5_wb_we_o, + t5_wb_dat_o, + t5_wb_dat_i, + t5_wb_ack_i, + t5_wb_err_i, + + t6_wb_cyc_o, + t6_wb_stb_o, + t6_wb_adr_o, + t6_wb_sel_o, + t6_wb_we_o, + t6_wb_dat_o, + t6_wb_dat_i, + t6_wb_ack_i, + t6_wb_err_i, + + t7_wb_cyc_o, + t7_wb_stb_o, + t7_wb_adr_o, + t7_wb_sel_o, + t7_wb_we_o, + t7_wb_dat_o, + t7_wb_dat_i, + t7_wb_ack_i, + t7_wb_err_i, + + t8_wb_cyc_o, + t8_wb_stb_o, + t8_wb_adr_o, + t8_wb_sel_o, + t8_wb_we_o, + t8_wb_dat_o, + t8_wb_dat_i, + t8_wb_ack_i, + t8_wb_err_i + +); + +// +// Parameters +// +parameter t0_addr_w = 4; +parameter t0_addr = 4'd8; +parameter t1_addr_w = 4; +parameter t1_addr = 4'd0; +parameter t28c_addr_w = 4; +parameter t28_addr = 4'd0; +parameter t28i_addr_w = 4; +parameter t2_addr = 4'd1; +parameter t3_addr = 4'd2; +parameter t4_addr = 4'd3; +parameter t5_addr = 4'd4; +parameter t6_addr = 4'd5; +parameter t7_addr = 4'd6; +parameter t8_addr = 4'd7; + +// +// I/O Ports +// +input wb_clk_i; +input wb_rst_i; + +// +// WB slave i/f connecting initiator 0 +// +input i0_wb_cyc_i; +input i0_wb_stb_i; +input [`TC_AW-1:0] i0_wb_adr_i; +input [`TC_BSW-1:0] i0_wb_sel_i; +input i0_wb_we_i; +input [`TC_DW-1:0] i0_wb_dat_i; +output [`TC_DW-1:0] i0_wb_dat_o; +output i0_wb_ack_o; +output i0_wb_err_o; + +// +// WB slave i/f connecting initiator 1 +// +input i1_wb_cyc_i; +input i1_wb_stb_i; +input [`TC_AW-1:0] i1_wb_adr_i; +input [`TC_BSW-1:0] i1_wb_sel_i; +input i1_wb_we_i; +input [`TC_DW-1:0] i1_wb_dat_i; +output [`TC_DW-1:0] i1_wb_dat_o; +output i1_wb_ack_o; +output i1_wb_err_o; + +// +// WB slave i/f connecting initiator 2 +// +input i2_wb_cyc_i; +input i2_wb_stb_i; +input [`TC_AW-1:0] i2_wb_adr_i; +input [`TC_BSW-1:0] i2_wb_sel_i; +input i2_wb_we_i; +input [`TC_DW-1:0] i2_wb_dat_i; +output [`TC_DW-1:0] i2_wb_dat_o; +output i2_wb_ack_o; +output i2_wb_err_o; + +// +// WB slave i/f connecting initiator 3 +// +input i3_wb_cyc_i; +input i3_wb_stb_i; +input [`TC_AW-1:0] i3_wb_adr_i; +input [`TC_BSW-1:0] i3_wb_sel_i; +input i3_wb_we_i; +input [`TC_DW-1:0] i3_wb_dat_i; +output [`TC_DW-1:0] i3_wb_dat_o; +output i3_wb_ack_o; +output i3_wb_err_o; + +// +// WB slave i/f connecting initiator 4 +// +input i4_wb_cyc_i; +input i4_wb_stb_i; +input [`TC_AW-1:0] i4_wb_adr_i; +input [`TC_BSW-1:0] i4_wb_sel_i; +input i4_wb_we_i; +input [`TC_DW-1:0] i4_wb_dat_i; +output [`TC_DW-1:0] i4_wb_dat_o; +output i4_wb_ack_o; +output i4_wb_err_o; + +// +// WB slave i/f connecting initiator 5 +// +input i5_wb_cyc_i; +input i5_wb_stb_i; +input [`TC_AW-1:0] i5_wb_adr_i; +input [`TC_BSW-1:0] i5_wb_sel_i; +input i5_wb_we_i; +input [`TC_DW-1:0] i5_wb_dat_i; +output [`TC_DW-1:0] i5_wb_dat_o; +output i5_wb_ack_o; +output i5_wb_err_o; + +// +// WB slave i/f connecting initiator 6 +// +input i6_wb_cyc_i; +input i6_wb_stb_i; +input [`TC_AW-1:0] i6_wb_adr_i; +input [`TC_BSW-1:0] i6_wb_sel_i; +input i6_wb_we_i; +input [`TC_DW-1:0] i6_wb_dat_i; +output [`TC_DW-1:0] i6_wb_dat_o; +output i6_wb_ack_o; +output i6_wb_err_o; + +// +// WB slave i/f connecting initiator 7 +// +input i7_wb_cyc_i; +input i7_wb_stb_i; +input [`TC_AW-1:0] i7_wb_adr_i; +input [`TC_BSW-1:0] i7_wb_sel_i; +input i7_wb_we_i; +input [`TC_DW-1:0] i7_wb_dat_i; +output [`TC_DW-1:0] i7_wb_dat_o; +output i7_wb_ack_o; +output i7_wb_err_o; + +// +// WB master i/f connecting target 0 +// +output t0_wb_cyc_o; +output t0_wb_stb_o; +output [`TC_AW-1:0] t0_wb_adr_o; +output [`TC_BSW-1:0] t0_wb_sel_o; +output t0_wb_we_o; +output [`TC_DW-1:0] t0_wb_dat_o; +input [`TC_DW-1:0] t0_wb_dat_i; +input t0_wb_ack_i; +input t0_wb_err_i; + +// +// WB master i/f connecting target 1 +// +output t1_wb_cyc_o; +output t1_wb_stb_o; +output [`TC_AW-1:0] t1_wb_adr_o; +output [`TC_BSW-1:0] t1_wb_sel_o; +output t1_wb_we_o; +output [`TC_DW-1:0] t1_wb_dat_o; +input [`TC_DW-1:0] t1_wb_dat_i; +input t1_wb_ack_i; +input t1_wb_err_i; + +// +// WB master i/f connecting target 2 +// +output t2_wb_cyc_o; +output t2_wb_stb_o; +output [`TC_AW-1:0] t2_wb_adr_o; +output [`TC_BSW-1:0] t2_wb_sel_o; +output t2_wb_we_o; +output [`TC_DW-1:0] t2_wb_dat_o; +input [`TC_DW-1:0] t2_wb_dat_i; +input t2_wb_ack_i; +input t2_wb_err_i; + +// +// WB master i/f connecting target 3 +// +output t3_wb_cyc_o; +output t3_wb_stb_o; +output [`TC_AW-1:0] t3_wb_adr_o; +output [`TC_BSW-1:0] t3_wb_sel_o; +output t3_wb_we_o; +output [`TC_DW-1:0] t3_wb_dat_o; +input [`TC_DW-1:0] t3_wb_dat_i; +input t3_wb_ack_i; +input t3_wb_err_i; + +// +// WB master i/f connecting target 4 +// +output t4_wb_cyc_o; +output t4_wb_stb_o; +output [`TC_AW-1:0] t4_wb_adr_o; +output [`TC_BSW-1:0] t4_wb_sel_o; +output t4_wb_we_o; +output [`TC_DW-1:0] t4_wb_dat_o; +input [`TC_DW-1:0] t4_wb_dat_i; +input t4_wb_ack_i; +input t4_wb_err_i; + +// +// WB master i/f connecting target 5 +// +output t5_wb_cyc_o; +output t5_wb_stb_o; +output [`TC_AW-1:0] t5_wb_adr_o; +output [`TC_BSW-1:0] t5_wb_sel_o; +output t5_wb_we_o; +output [`TC_DW-1:0] t5_wb_dat_o; +input [`TC_DW-1:0] t5_wb_dat_i; +input t5_wb_ack_i; +input t5_wb_err_i; + +// +// WB master i/f connecting target 6 +// +output t6_wb_cyc_o; +output t6_wb_stb_o; +output [`TC_AW-1:0] t6_wb_adr_o; +output [`TC_BSW-1:0] t6_wb_sel_o; +output t6_wb_we_o; +output [`TC_DW-1:0] t6_wb_dat_o; +input [`TC_DW-1:0] t6_wb_dat_i; +input t6_wb_ack_i; +input t6_wb_err_i; + +// +// WB master i/f connecting target 7 +// +output t7_wb_cyc_o; +output t7_wb_stb_o; +output [`TC_AW-1:0] t7_wb_adr_o; +output [`TC_BSW-1:0] t7_wb_sel_o; +output t7_wb_we_o; +output [`TC_DW-1:0] t7_wb_dat_o; +input [`TC_DW-1:0] t7_wb_dat_i; +input t7_wb_ack_i; +input t7_wb_err_i; + +// +// WB master i/f connecting target 8 +// +output t8_wb_cyc_o; +output t8_wb_stb_o; +output [`TC_AW-1:0] t8_wb_adr_o; +output [`TC_BSW-1:0] t8_wb_sel_o; +output t8_wb_we_o; +output [`TC_DW-1:0] t8_wb_dat_o; +input [`TC_DW-1:0] t8_wb_dat_i; +input t8_wb_ack_i; +input t8_wb_err_i; + +// +// Internal wires & registers +// + +// +// Outputs for initiators from both mi_to_st blocks +// +wire [`TC_DW-1:0] xi0_wb_dat_o; +wire xi0_wb_ack_o; +wire xi0_wb_err_o; +wire [`TC_DW-1:0] xi1_wb_dat_o; +wire xi1_wb_ack_o; +wire xi1_wb_err_o; +wire [`TC_DW-1:0] xi2_wb_dat_o; +wire xi2_wb_ack_o; +wire xi2_wb_err_o; +wire [`TC_DW-1:0] xi3_wb_dat_o; +wire xi3_wb_ack_o; +wire xi3_wb_err_o; +wire [`TC_DW-1:0] xi4_wb_dat_o; +wire xi4_wb_ack_o; +wire xi4_wb_err_o; +wire [`TC_DW-1:0] xi5_wb_dat_o; +wire xi5_wb_ack_o; +wire xi5_wb_err_o; +wire [`TC_DW-1:0] xi6_wb_dat_o; +wire xi6_wb_ack_o; +wire xi6_wb_err_o; +wire [`TC_DW-1:0] xi7_wb_dat_o; +wire xi7_wb_ack_o; +wire xi7_wb_err_o; +wire [`TC_DW-1:0] yi0_wb_dat_o; +wire yi0_wb_ack_o; +wire yi0_wb_err_o; +wire [`TC_DW-1:0] yi1_wb_dat_o; +wire yi1_wb_ack_o; +wire yi1_wb_err_o; +wire [`TC_DW-1:0] yi2_wb_dat_o; +wire yi2_wb_ack_o; +wire yi2_wb_err_o; +wire [`TC_DW-1:0] yi3_wb_dat_o; +wire yi3_wb_ack_o; +wire yi3_wb_err_o; +wire [`TC_DW-1:0] yi4_wb_dat_o; +wire yi4_wb_ack_o; +wire yi4_wb_err_o; +wire [`TC_DW-1:0] yi5_wb_dat_o; +wire yi5_wb_ack_o; +wire yi5_wb_err_o; +wire [`TC_DW-1:0] yi6_wb_dat_o; +wire yi6_wb_ack_o; +wire yi6_wb_err_o; +wire [`TC_DW-1:0] yi7_wb_dat_o; +wire yi7_wb_ack_o; +wire yi7_wb_err_o; + +// +// Intermediate signals connecting peripheral channel's +// mi_to_st and si_to_mt blocks. +// +wire z_wb_cyc_i; +wire z_wb_stb_i; +wire [`TC_AW-1:0] z_wb_adr_i; +wire [`TC_BSW-1:0] z_wb_sel_i; +wire z_wb_we_i; +wire [`TC_DW-1:0] z_wb_dat_i; +wire [`TC_DW-1:0] z_wb_dat_t; +wire z_wb_ack_t; +wire z_wb_err_t; + +// +// Outputs for initiators are ORed from both mi_to_st blocks +// +assign i0_wb_dat_o = xi0_wb_dat_o | yi0_wb_dat_o; +assign i0_wb_ack_o = xi0_wb_ack_o | yi0_wb_ack_o; +assign i0_wb_err_o = xi0_wb_err_o | yi0_wb_err_o; +assign i1_wb_dat_o = xi1_wb_dat_o | yi1_wb_dat_o; +assign i1_wb_ack_o = xi1_wb_ack_o | yi1_wb_ack_o; +assign i1_wb_err_o = xi1_wb_err_o | yi1_wb_err_o; +assign i2_wb_dat_o = xi2_wb_dat_o | yi2_wb_dat_o; +assign i2_wb_ack_o = xi2_wb_ack_o | yi2_wb_ack_o; +assign i2_wb_err_o = xi2_wb_err_o | yi2_wb_err_o; +assign i3_wb_dat_o = xi3_wb_dat_o | yi3_wb_dat_o; +assign i3_wb_ack_o = xi3_wb_ack_o | yi3_wb_ack_o; +assign i3_wb_err_o = xi3_wb_err_o | yi3_wb_err_o; +assign i4_wb_dat_o = xi4_wb_dat_o | yi4_wb_dat_o; +assign i4_wb_ack_o = xi4_wb_ack_o | yi4_wb_ack_o; +assign i4_wb_err_o = xi4_wb_err_o | yi4_wb_err_o; +assign i5_wb_dat_o = xi5_wb_dat_o | yi5_wb_dat_o; +assign i5_wb_ack_o = xi5_wb_ack_o | yi5_wb_ack_o; +assign i5_wb_err_o = xi5_wb_err_o | yi5_wb_err_o; +assign i6_wb_dat_o = xi6_wb_dat_o | yi6_wb_dat_o; +assign i6_wb_ack_o = xi6_wb_ack_o | yi6_wb_ack_o; +assign i6_wb_err_o = xi6_wb_err_o | yi6_wb_err_o; +assign i7_wb_dat_o = xi7_wb_dat_o | yi7_wb_dat_o; +assign i7_wb_ack_o = xi7_wb_ack_o | yi7_wb_ack_o; +assign i7_wb_err_o = xi7_wb_err_o | yi7_wb_err_o; + +// +// From initiators to target 0 +// +tc_mi_to_st #(t0_addr_w, t0_addr, + 0, t0_addr_w, t0_addr) t0_ch( + .wb_clk_i(wb_clk_i), + .wb_rst_i(wb_rst_i), + + .i0_wb_cyc_i(i0_wb_cyc_i), + .i0_wb_stb_i(i0_wb_stb_i), + .i0_wb_adr_i(i0_wb_adr_i), + .i0_wb_sel_i(i0_wb_sel_i), + .i0_wb_we_i(i0_wb_we_i), + .i0_wb_dat_i(i0_wb_dat_i), + .i0_wb_dat_o(xi0_wb_dat_o), + .i0_wb_ack_o(xi0_wb_ack_o), + .i0_wb_err_o(xi0_wb_err_o), + + .i1_wb_cyc_i(i1_wb_cyc_i), + .i1_wb_stb_i(i1_wb_stb_i), + .i1_wb_adr_i(i1_wb_adr_i), + .i1_wb_sel_i(i1_wb_sel_i), + .i1_wb_we_i(i1_wb_we_i), + .i1_wb_dat_i(i1_wb_dat_i), + .i1_wb_dat_o(xi1_wb_dat_o), + .i1_wb_ack_o(xi1_wb_ack_o), + .i1_wb_err_o(xi1_wb_err_o), + + .i2_wb_cyc_i(i2_wb_cyc_i), + .i2_wb_stb_i(i2_wb_stb_i), + .i2_wb_adr_i(i2_wb_adr_i), + .i2_wb_sel_i(i2_wb_sel_i), + .i2_wb_we_i(i2_wb_we_i), + .i2_wb_dat_i(i2_wb_dat_i), + .i2_wb_dat_o(xi2_wb_dat_o), + .i2_wb_ack_o(xi2_wb_ack_o), + .i2_wb_err_o(xi2_wb_err_o), + + .i3_wb_cyc_i(i3_wb_cyc_i), + .i3_wb_stb_i(i3_wb_stb_i), + .i3_wb_adr_i(i3_wb_adr_i), + .i3_wb_sel_i(i3_wb_sel_i), + .i3_wb_we_i(i3_wb_we_i), + .i3_wb_dat_i(i3_wb_dat_i), + .i3_wb_dat_o(xi3_wb_dat_o), + .i3_wb_ack_o(xi3_wb_ack_o), + .i3_wb_err_o(xi3_wb_err_o), + + .i4_wb_cyc_i(i4_wb_cyc_i), + .i4_wb_stb_i(i4_wb_stb_i), + .i4_wb_adr_i(i4_wb_adr_i), + .i4_wb_sel_i(i4_wb_sel_i), + .i4_wb_we_i(i4_wb_we_i), + .i4_wb_dat_i(i4_wb_dat_i), + .i4_wb_dat_o(xi4_wb_dat_o), + .i4_wb_ack_o(xi4_wb_ack_o), + .i4_wb_err_o(xi4_wb_err_o), + + .i5_wb_cyc_i(i5_wb_cyc_i), + .i5_wb_stb_i(i5_wb_stb_i), + .i5_wb_adr_i(i5_wb_adr_i), + .i5_wb_sel_i(i5_wb_sel_i), + .i5_wb_we_i(i5_wb_we_i), + .i5_wb_dat_i(i5_wb_dat_i), + .i5_wb_dat_o(xi5_wb_dat_o), + .i5_wb_ack_o(xi5_wb_ack_o), + .i5_wb_err_o(xi5_wb_err_o), + + .i6_wb_cyc_i(i6_wb_cyc_i), + .i6_wb_stb_i(i6_wb_stb_i), + .i6_wb_adr_i(i6_wb_adr_i), + .i6_wb_sel_i(i6_wb_sel_i), + .i6_wb_we_i(i6_wb_we_i), + .i6_wb_dat_i(i6_wb_dat_i), + .i6_wb_dat_o(xi6_wb_dat_o), + .i6_wb_ack_o(xi6_wb_ack_o), + .i6_wb_err_o(xi6_wb_err_o), + + .i7_wb_cyc_i(i7_wb_cyc_i), + .i7_wb_stb_i(i7_wb_stb_i), + .i7_wb_adr_i(i7_wb_adr_i), + .i7_wb_sel_i(i7_wb_sel_i), + .i7_wb_we_i(i7_wb_we_i), + .i7_wb_dat_i(i7_wb_dat_i), + .i7_wb_dat_o(xi7_wb_dat_o), + .i7_wb_ack_o(xi7_wb_ack_o), + .i7_wb_err_o(xi7_wb_err_o), + + .t0_wb_cyc_o(t0_wb_cyc_o), + .t0_wb_stb_o(t0_wb_stb_o), + .t0_wb_adr_o(t0_wb_adr_o), + .t0_wb_sel_o(t0_wb_sel_o), + .t0_wb_we_o(t0_wb_we_o), + .t0_wb_dat_o(t0_wb_dat_o), + .t0_wb_dat_i(t0_wb_dat_i), + .t0_wb_ack_i(t0_wb_ack_i), + .t0_wb_err_i(t0_wb_err_i) + +); + +// +// From initiators to targets 1-8 (upper part) +// +tc_mi_to_st #(t1_addr_w, t1_addr, + 1, t28c_addr_w, t28_addr) t18_ch_upper( + .wb_clk_i(wb_clk_i), + .wb_rst_i(wb_rst_i), + + .i0_wb_cyc_i(i0_wb_cyc_i), + .i0_wb_stb_i(i0_wb_stb_i), + .i0_wb_adr_i(i0_wb_adr_i), + .i0_wb_sel_i(i0_wb_sel_i), + .i0_wb_we_i(i0_wb_we_i), + .i0_wb_dat_i(i0_wb_dat_i), + .i0_wb_dat_o(yi0_wb_dat_o), + .i0_wb_ack_o(yi0_wb_ack_o), + .i0_wb_err_o(yi0_wb_err_o), + + .i1_wb_cyc_i(i1_wb_cyc_i), + .i1_wb_stb_i(i1_wb_stb_i), + .i1_wb_adr_i(i1_wb_adr_i), + .i1_wb_sel_i(i1_wb_sel_i), + .i1_wb_we_i(i1_wb_we_i), + .i1_wb_dat_i(i1_wb_dat_i), + .i1_wb_dat_o(yi1_wb_dat_o), + .i1_wb_ack_o(yi1_wb_ack_o), + .i1_wb_err_o(yi1_wb_err_o), + + .i2_wb_cyc_i(i2_wb_cyc_i), + .i2_wb_stb_i(i2_wb_stb_i), + .i2_wb_adr_i(i2_wb_adr_i), + .i2_wb_sel_i(i2_wb_sel_i), + .i2_wb_we_i(i2_wb_we_i), + .i2_wb_dat_i(i2_wb_dat_i), + .i2_wb_dat_o(yi2_wb_dat_o), + .i2_wb_ack_o(yi2_wb_ack_o), + .i2_wb_err_o(yi2_wb_err_o), + + .i3_wb_cyc_i(i3_wb_cyc_i), + .i3_wb_stb_i(i3_wb_stb_i), + .i3_wb_adr_i(i3_wb_adr_i), + .i3_wb_sel_i(i3_wb_sel_i), + .i3_wb_we_i(i3_wb_we_i), + .i3_wb_dat_i(i3_wb_dat_i), + .i3_wb_dat_o(yi3_wb_dat_o), + .i3_wb_ack_o(yi3_wb_ack_o), + .i3_wb_err_o(yi3_wb_err_o), + + .i4_wb_cyc_i(i4_wb_cyc_i), + .i4_wb_stb_i(i4_wb_stb_i), + .i4_wb_adr_i(i4_wb_adr_i), + .i4_wb_sel_i(i4_wb_sel_i), + .i4_wb_we_i(i4_wb_we_i), + .i4_wb_dat_i(i4_wb_dat_i), + .i4_wb_dat_o(yi4_wb_dat_o), + .i4_wb_ack_o(yi4_wb_ack_o), + .i4_wb_err_o(yi4_wb_err_o), + + .i5_wb_cyc_i(i5_wb_cyc_i), + .i5_wb_stb_i(i5_wb_stb_i), + .i5_wb_adr_i(i5_wb_adr_i), + .i5_wb_sel_i(i5_wb_sel_i), + .i5_wb_we_i(i5_wb_we_i), + .i5_wb_dat_i(i5_wb_dat_i), + .i5_wb_dat_o(yi5_wb_dat_o), + .i5_wb_ack_o(yi5_wb_ack_o), + .i5_wb_err_o(yi5_wb_err_o), + + .i6_wb_cyc_i(i6_wb_cyc_i), + .i6_wb_stb_i(i6_wb_stb_i), + .i6_wb_adr_i(i6_wb_adr_i), + .i6_wb_sel_i(i6_wb_sel_i), + .i6_wb_we_i(i6_wb_we_i), + .i6_wb_dat_i(i6_wb_dat_i), + .i6_wb_dat_o(yi6_wb_dat_o), + .i6_wb_ack_o(yi6_wb_ack_o), + .i6_wb_err_o(yi6_wb_err_o), + + .i7_wb_cyc_i(i7_wb_cyc_i), + .i7_wb_stb_i(i7_wb_stb_i), + .i7_wb_adr_i(i7_wb_adr_i), + .i7_wb_sel_i(i7_wb_sel_i), + .i7_wb_we_i(i7_wb_we_i), + .i7_wb_dat_i(i7_wb_dat_i), + .i7_wb_dat_o(yi7_wb_dat_o), + .i7_wb_ack_o(yi7_wb_ack_o), + .i7_wb_err_o(yi7_wb_err_o), + + .t0_wb_cyc_o(z_wb_cyc_i), + .t0_wb_stb_o(z_wb_stb_i), + .t0_wb_adr_o(z_wb_adr_i), + .t0_wb_sel_o(z_wb_sel_i), + .t0_wb_we_o(z_wb_we_i), + .t0_wb_dat_o(z_wb_dat_i), + .t0_wb_dat_i(z_wb_dat_t), + .t0_wb_ack_i(z_wb_ack_t), + .t0_wb_err_i(z_wb_err_t) + +); + +// +// From initiators to targets 1-8 (lower part) +// +tc_si_to_mt #(t1_addr_w, t1_addr, t28i_addr_w, t2_addr, t3_addr, + t4_addr, t5_addr, t6_addr, t7_addr, t8_addr) t18_ch_lower( + + .i0_wb_cyc_i(z_wb_cyc_i), + .i0_wb_stb_i(z_wb_stb_i), + .i0_wb_adr_i(z_wb_adr_i), + .i0_wb_sel_i(z_wb_sel_i), + .i0_wb_we_i(z_wb_we_i), + .i0_wb_dat_i(z_wb_dat_i), + .i0_wb_dat_o(z_wb_dat_t), + .i0_wb_ack_o(z_wb_ack_t), + .i0_wb_err_o(z_wb_err_t), + + .t0_wb_cyc_o(t1_wb_cyc_o), + .t0_wb_stb_o(t1_wb_stb_o), + .t0_wb_adr_o(t1_wb_adr_o), + .t0_wb_sel_o(t1_wb_sel_o), + .t0_wb_we_o(t1_wb_we_o), + .t0_wb_dat_o(t1_wb_dat_o), + .t0_wb_dat_i(t1_wb_dat_i), + .t0_wb_ack_i(t1_wb_ack_i), + .t0_wb_err_i(t1_wb_err_i), + + .t1_wb_cyc_o(t2_wb_cyc_o), + .t1_wb_stb_o(t2_wb_stb_o), + .t1_wb_adr_o(t2_wb_adr_o), + .t1_wb_sel_o(t2_wb_sel_o), + .t1_wb_we_o(t2_wb_we_o), + .t1_wb_dat_o(t2_wb_dat_o), + .t1_wb_dat_i(t2_wb_dat_i), + .t1_wb_ack_i(t2_wb_ack_i), + .t1_wb_err_i(t2_wb_err_i), + + .t2_wb_cyc_o(t3_wb_cyc_o), + .t2_wb_stb_o(t3_wb_stb_o), + .t2_wb_adr_o(t3_wb_adr_o), + .t2_wb_sel_o(t3_wb_sel_o), + .t2_wb_we_o(t3_wb_we_o), + .t2_wb_dat_o(t3_wb_dat_o), + .t2_wb_dat_i(t3_wb_dat_i), + .t2_wb_ack_i(t3_wb_ack_i), + .t2_wb_err_i(t3_wb_err_i), + + .t3_wb_cyc_o(t4_wb_cyc_o), + .t3_wb_stb_o(t4_wb_stb_o), + .t3_wb_adr_o(t4_wb_adr_o), + .t3_wb_sel_o(t4_wb_sel_o), + .t3_wb_we_o(t4_wb_we_o), + .t3_wb_dat_o(t4_wb_dat_o), + .t3_wb_dat_i(t4_wb_dat_i), + .t3_wb_ack_i(t4_wb_ack_i), + .t3_wb_err_i(t4_wb_err_i), + + .t4_wb_cyc_o(t5_wb_cyc_o), + .t4_wb_stb_o(t5_wb_stb_o), + .t4_wb_adr_o(t5_wb_adr_o), + .t4_wb_sel_o(t5_wb_sel_o), + .t4_wb_we_o(t5_wb_we_o), + .t4_wb_dat_o(t5_wb_dat_o), + .t4_wb_dat_i(t5_wb_dat_i), + .t4_wb_ack_i(t5_wb_ack_i), + .t4_wb_err_i(t5_wb_err_i), + + .t5_wb_cyc_o(t6_wb_cyc_o), + .t5_wb_stb_o(t6_wb_stb_o), + .t5_wb_adr_o(t6_wb_adr_o), + .t5_wb_sel_o(t6_wb_sel_o), + .t5_wb_we_o(t6_wb_we_o), + .t5_wb_dat_o(t6_wb_dat_o), + .t5_wb_dat_i(t6_wb_dat_i), + .t5_wb_ack_i(t6_wb_ack_i), + .t5_wb_err_i(t6_wb_err_i), + + .t6_wb_cyc_o(t7_wb_cyc_o), + .t6_wb_stb_o(t7_wb_stb_o), + .t6_wb_adr_o(t7_wb_adr_o), + .t6_wb_sel_o(t7_wb_sel_o), + .t6_wb_we_o(t7_wb_we_o), + .t6_wb_dat_o(t7_wb_dat_o), + .t6_wb_dat_i(t7_wb_dat_i), + .t6_wb_ack_i(t7_wb_ack_i), + .t6_wb_err_i(t7_wb_err_i), + + .t7_wb_cyc_o(t8_wb_cyc_o), + .t7_wb_stb_o(t8_wb_stb_o), + .t7_wb_adr_o(t8_wb_adr_o), + .t7_wb_sel_o(t8_wb_sel_o), + .t7_wb_we_o(t8_wb_we_o), + .t7_wb_dat_o(t8_wb_dat_o), + .t7_wb_dat_i(t8_wb_dat_i), + .t7_wb_ack_i(t8_wb_ack_i), + .t7_wb_err_i(t8_wb_err_i) + +); + +endmodule + +// +// Multiple initiator to single target +// +module tc_mi_to_st ( + wb_clk_i, + wb_rst_i, + + i0_wb_cyc_i, + i0_wb_stb_i, + i0_wb_adr_i, + i0_wb_sel_i, + i0_wb_we_i, + i0_wb_dat_i, + i0_wb_dat_o, + i0_wb_ack_o, + i0_wb_err_o, + + i1_wb_cyc_i, + i1_wb_stb_i, + i1_wb_adr_i, + i1_wb_sel_i, + i1_wb_we_i, + i1_wb_dat_i, + i1_wb_dat_o, + i1_wb_ack_o, + i1_wb_err_o, + + i2_wb_cyc_i, + i2_wb_stb_i, + i2_wb_adr_i, + i2_wb_sel_i, + i2_wb_we_i, + i2_wb_dat_i, + i2_wb_dat_o, + i2_wb_ack_o, + i2_wb_err_o, + + i3_wb_cyc_i, + i3_wb_stb_i, + i3_wb_adr_i, + i3_wb_sel_i, + i3_wb_we_i, + i3_wb_dat_i, + i3_wb_dat_o, + i3_wb_ack_o, + i3_wb_err_o, + + i4_wb_cyc_i, + i4_wb_stb_i, + i4_wb_adr_i, + i4_wb_sel_i, + i4_wb_we_i, + i4_wb_dat_i, + i4_wb_dat_o, + i4_wb_ack_o, + i4_wb_err_o, + + i5_wb_cyc_i, + i5_wb_stb_i, + i5_wb_adr_i, + i5_wb_sel_i, + i5_wb_we_i, + i5_wb_dat_i, + i5_wb_dat_o, + i5_wb_ack_o, + i5_wb_err_o, + + i6_wb_cyc_i, + i6_wb_stb_i, + i6_wb_adr_i, + i6_wb_sel_i, + i6_wb_we_i, + i6_wb_dat_i, + i6_wb_dat_o, + i6_wb_ack_o, + i6_wb_err_o, + + i7_wb_cyc_i, + i7_wb_stb_i, + i7_wb_adr_i, + i7_wb_sel_i, + i7_wb_we_i, + i7_wb_dat_i, + i7_wb_dat_o, + i7_wb_ack_o, + i7_wb_err_o, + + t0_wb_cyc_o, + t0_wb_stb_o, + t0_wb_adr_o, + t0_wb_sel_o, + t0_wb_we_o, + t0_wb_dat_o, + t0_wb_dat_i, + t0_wb_ack_i, + t0_wb_err_i + +); + +// +// Parameters +// +parameter t0_addr_w = 2; +parameter t0_addr = 2'b00; +parameter multitarg = 1'b0; +parameter t17_addr_w = 2; +parameter t17_addr = 2'b00; + +// +// I/O Ports +// +input wb_clk_i; +input wb_rst_i; + +// +// WB slave i/f connecting initiator 0 +// +input i0_wb_cyc_i; +input i0_wb_stb_i; +input [`TC_AW-1:0] i0_wb_adr_i; +input [`TC_BSW-1:0] i0_wb_sel_i; +input i0_wb_we_i; +input [`TC_DW-1:0] i0_wb_dat_i; +output [`TC_DW-1:0] i0_wb_dat_o; +output i0_wb_ack_o; +output i0_wb_err_o; + +// +// WB slave i/f connecting initiator 1 +// +input i1_wb_cyc_i; +input i1_wb_stb_i; +input [`TC_AW-1:0] i1_wb_adr_i; +input [`TC_BSW-1:0] i1_wb_sel_i; +input i1_wb_we_i; +input [`TC_DW-1:0] i1_wb_dat_i; +output [`TC_DW-1:0] i1_wb_dat_o; +output i1_wb_ack_o; +output i1_wb_err_o; + +// +// WB slave i/f connecting initiator 2 +// +input i2_wb_cyc_i; +input i2_wb_stb_i; +input [`TC_AW-1:0] i2_wb_adr_i; +input [`TC_BSW-1:0] i2_wb_sel_i; +input i2_wb_we_i; +input [`TC_DW-1:0] i2_wb_dat_i; +output [`TC_DW-1:0] i2_wb_dat_o; +output i2_wb_ack_o; +output i2_wb_err_o; + +// +// WB slave i/f connecting initiator 3 +// +input i3_wb_cyc_i; +input i3_wb_stb_i; +input [`TC_AW-1:0] i3_wb_adr_i; +input [`TC_BSW-1:0] i3_wb_sel_i; +input i3_wb_we_i; +input [`TC_DW-1:0] i3_wb_dat_i; +output [`TC_DW-1:0] i3_wb_dat_o; +output i3_wb_ack_o; +output i3_wb_err_o; + +// +// WB slave i/f connecting initiator 4 +// +input i4_wb_cyc_i; +input i4_wb_stb_i; +input [`TC_AW-1:0] i4_wb_adr_i; +input [`TC_BSW-1:0] i4_wb_sel_i; +input i4_wb_we_i; +input [`TC_DW-1:0] i4_wb_dat_i; +output [`TC_DW-1:0] i4_wb_dat_o; +output i4_wb_ack_o; +output i4_wb_err_o; + +// +// WB slave i/f connecting initiator 5 +// +input i5_wb_cyc_i; +input i5_wb_stb_i; +input [`TC_AW-1:0] i5_wb_adr_i; +input [`TC_BSW-1:0] i5_wb_sel_i; +input i5_wb_we_i; +input [`TC_DW-1:0] i5_wb_dat_i; +output [`TC_DW-1:0] i5_wb_dat_o; +output i5_wb_ack_o; +output i5_wb_err_o; + +// +// WB slave i/f connecting initiator 6 +// +input i6_wb_cyc_i; +input i6_wb_stb_i; +input [`TC_AW-1:0] i6_wb_adr_i; +input [`TC_BSW-1:0] i6_wb_sel_i; +input i6_wb_we_i; +input [`TC_DW-1:0] i6_wb_dat_i; +output [`TC_DW-1:0] i6_wb_dat_o; +output i6_wb_ack_o; +output i6_wb_err_o; + +// +// WB slave i/f connecting initiator 7 +// +input i7_wb_cyc_i; +input i7_wb_stb_i; +input [`TC_AW-1:0] i7_wb_adr_i; +input [`TC_BSW-1:0] i7_wb_sel_i; +input i7_wb_we_i; +input [`TC_DW-1:0] i7_wb_dat_i; +output [`TC_DW-1:0] i7_wb_dat_o; +output i7_wb_ack_o; +output i7_wb_err_o; + +// +// WB master i/f connecting target +// +output t0_wb_cyc_o; +output t0_wb_stb_o; +output [`TC_AW-1:0] t0_wb_adr_o; +output [`TC_BSW-1:0] t0_wb_sel_o; +output t0_wb_we_o; +output [`TC_DW-1:0] t0_wb_dat_o; +input [`TC_DW-1:0] t0_wb_dat_i; +input t0_wb_ack_i; +input t0_wb_err_i; + +// +// Internal wires & registers +// +wire [`TC_IIN_W-1:0] i0_in, i1_in, + i2_in, i3_in, + i4_in, i5_in, + i6_in, i7_in; +wire [`TC_TIN_W-1:0] i0_out, i1_out, + i2_out, i3_out, + i4_out, i5_out, + i6_out, i7_out; +wire [`TC_IIN_W-1:0] t0_out; +wire [`TC_TIN_W-1:0] t0_in; +wire [7:0] req_i; +wire [2:0] req_won; +reg req_cont; +reg [2:0] req_r; + +// +// Group WB initiator 0 i/f inputs and outputs +// +assign i0_in = {i0_wb_cyc_i, i0_wb_stb_i, i0_wb_adr_i, + i0_wb_sel_i, i0_wb_we_i, i0_wb_dat_i}; +assign {i0_wb_da