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URL https://opencores.org/ocsvn/minsoc/minsoc/trunk

Subversion Repositories minsoc

Compare Revisions

  • This comparison shows the changes necessary to convert path
    /minsoc/tags/release-0.9/sim/bin
    from Rev 31 to Rev 42
    Reverse comparison

Rev 31 → Rev 42

/minsoc_model.txt
0,0 → 1,138
+incdir+../../bench/verilog
+incdir+../../bench/verilog/vpi
+incdir+../../bench/verilog/sim_lib
+incdir+../../rtl/verilog
+incdir+../../rtl/verilog/minsoc_startup
+incdir+../../rtl/verilog/or1200/rtl/verilog
+incdir+../../rtl/verilog/adv_debug_sys/Hardware/adv_dbg_if/rtl/verilog
+incdir+../../rtl/verilog/adv_debug_sys/Hardware/jtag/tap/rtl/verilog
+incdir+../../rtl/verilog/adv_debug_sys/Software/adv_jtag_bridge/sim_rtl
+incdir+../../rtl/verilog/uart16550/rtl/verilog
+incdir+../../rtl/verilog/ethmac/rtl/verilog
../../bench/verilog/minsoc_bench_defines.v
../../bench/verilog/minsoc_bench.v
../../bench/verilog/minsoc_memory_model.v
../../bench/verilog/vpi/dbg_comm_vpi.v
../../bench/verilog/sim_lib/fpga_memory_primitives.v
../../rtl/verilog/minsoc_top.v
../../rtl/verilog/minsoc_startup/spi_top.v
../../rtl/verilog/minsoc_startup/spi_defines.v
../../rtl/verilog/minsoc_startup/spi_shift.v
../../rtl/verilog/minsoc_startup/spi_clgen.v
../../rtl/verilog/minsoc_startup/OR1K_startup_generic.v
../../rtl/verilog/minsoc_tc_top.v
../../rtl/verilog/minsoc_onchip_ram.v
../../rtl/verilog/minsoc_clock_manager.v
#../../rtl/verilog/minsoc_onchip_ram_top.v
../../rtl/verilog/minsoc_defines.v
../../rtl/verilog/or1200/rtl/verilog/or1200_spram_512x20.v
../../rtl/verilog/or1200/rtl/verilog/or1200_spram_64x24.v
../../rtl/verilog/or1200/rtl/verilog/or1200_du.v
../../rtl/verilog/or1200/rtl/verilog/or1200_spram_2048x32_bw.v
../../rtl/verilog/or1200/rtl/verilog/or1200_rf.v
../../rtl/verilog/or1200/rtl/verilog/or1200_alu.v
../../rtl/verilog/or1200/rtl/verilog/or1200_dmmu_top.v
../../rtl/verilog/or1200/rtl/verilog/or1200_lsu.v
../../rtl/verilog/or1200/rtl/verilog/or1200_spram_1024x32.v
../../rtl/verilog/or1200/rtl/verilog/or1200_dc_top.v
../../rtl/verilog/or1200/rtl/verilog/or1200_cpu.v
../../rtl/verilog/or1200/rtl/verilog/or1200_gmultp2_32x32.v
../../rtl/verilog/or1200/rtl/verilog/or1200_immu_top.v
../../rtl/verilog/or1200/rtl/verilog/or1200_dpram_256x32.v
../../rtl/verilog/or1200/rtl/verilog/or1200_tt.v
../../rtl/verilog/or1200/rtl/verilog/or1200_iwb_biu.v
../../rtl/verilog/or1200/rtl/verilog/or1200_rfram_generic.v
../../rtl/verilog/or1200/rtl/verilog/or1200_dc_tag.v
../../rtl/verilog/or1200/rtl/verilog/or1200_spram_2048x8.v
../../rtl/verilog/or1200/rtl/verilog/or1200_immu_tlb.v
../../rtl/verilog/or1200/rtl/verilog/or1200_ic_tag.v
../../rtl/verilog/or1200/rtl/verilog/or1200_spram_64x14.v
../../rtl/verilog/or1200/rtl/verilog/or1200_spram_32x24.v
../../rtl/verilog/or1200/rtl/verilog/or1200_dpram_32x32.v
../../rtl/verilog/or1200/rtl/verilog/or1200_xcv_ram32x8d.v
../../rtl/verilog/or1200/rtl/verilog/or1200_spram_1024x8.v
../../rtl/verilog/or1200/rtl/verilog/or1200_mem2reg.v
../../rtl/verilog/or1200/rtl/verilog/or1200_pm.v
../../rtl/verilog/or1200/rtl/verilog/or1200_spram_256x21.v
../../rtl/verilog/or1200/rtl/verilog/or1200_operandmuxes.v
../../rtl/verilog/or1200/rtl/verilog/or1200_pic.v
../../rtl/verilog/or1200/rtl/verilog/or1200_cfgr.v
../../rtl/verilog/or1200/rtl/verilog/or1200_if.v
../../rtl/verilog/or1200/rtl/verilog/or1200_qmem_top.v
../../rtl/verilog/or1200/rtl/verilog/or1200_genpc.v
../../rtl/verilog/or1200/rtl/verilog/or1200_defines.v
../../rtl/verilog/or1200/rtl/verilog/or1200_wbmux.v
../../rtl/verilog/or1200/rtl/verilog/or1200_ic_ram.v
../../rtl/verilog/or1200/rtl/verilog/or1200_dmmu_tlb.v
../../rtl/verilog/or1200/rtl/verilog/or1200_sb_fifo.v
../../rtl/verilog/or1200/rtl/verilog/or1200_sprs.v
../../rtl/verilog/or1200/rtl/verilog/or1200_tpram_32x32.v
../../rtl/verilog/or1200/rtl/verilog/or1200_ctrl.v
../../rtl/verilog/or1200/rtl/verilog/or1200_sb.v
../../rtl/verilog/or1200/rtl/verilog/or1200_mult_mac.v
../../rtl/verilog/or1200/rtl/verilog/or1200_ic_fsm.v
../../rtl/verilog/or1200/rtl/verilog/or1200_amultp2_32x32.v
../../rtl/verilog/or1200/rtl/verilog/or1200_reg2mem.v
../../rtl/verilog/or1200/rtl/verilog/or1200_spram_2048x32.v
../../rtl/verilog/or1200/rtl/verilog/or1200_except.v
../../rtl/verilog/or1200/rtl/verilog/or1200_top.v
../../rtl/verilog/or1200/rtl/verilog/or1200_ic_top.v
../../rtl/verilog/or1200/rtl/verilog/or1200_dc_ram.v
../../rtl/verilog/or1200/rtl/verilog/or1200_spram_1024x32_bw.v
../../rtl/verilog/or1200/rtl/verilog/or1200_freeze.v
../../rtl/verilog/or1200/rtl/verilog/or1200_spram_128x32.v
../../rtl/verilog/or1200/rtl/verilog/or1200_dc_fsm.v
../../rtl/verilog/or1200/rtl/verilog/or1200_wb_biu.v
../../rtl/verilog/or1200/rtl/verilog/or1200_spram_64x22.v
../../rtl/verilog/or1200/rtl/verilog/or1200_fpu.v
../../rtl/verilog/or1200/rtl/verilog/or1200_spram.v
../../rtl/verilog/or1200/rtl/verilog/or1200_spram_32_bw.v
../../rtl/verilog/or1200/rtl/verilog/or1200_dpram.v
../../rtl/verilog/adv_debug_sys/Hardware/adv_dbg_if/rtl/verilog/adbg_wb_biu.v
../../rtl/verilog/adv_debug_sys/Hardware/adv_dbg_if/rtl/verilog/adbg_wb_module.v
../../rtl/verilog/adv_debug_sys/Hardware/adv_dbg_if/rtl/verilog/adbg_or1k_module.v
../../rtl/verilog/adv_debug_sys/Hardware/adv_dbg_if/rtl/verilog/adbg_wb_defines.v
../../rtl/verilog/adv_debug_sys/Hardware/adv_dbg_if/rtl/verilog/adbg_defines.v
../../rtl/verilog/adv_debug_sys/Hardware/adv_dbg_if/rtl/verilog/adbg_crc32.v
../../rtl/verilog/adv_debug_sys/Hardware/adv_dbg_if/rtl/verilog/adbg_or1k_biu.v
../../rtl/verilog/adv_debug_sys/Hardware/adv_dbg_if/rtl/verilog/adbg_or1k_defines.v
../../rtl/verilog/adv_debug_sys/Hardware/adv_dbg_if/rtl/verilog/adbg_or1k_status_reg.v
../../rtl/verilog/adv_debug_sys/Hardware/adv_dbg_if/rtl/verilog/adbg_top.v
../../rtl/verilog/adv_debug_sys/Hardware/jtag/tap/rtl/verilog/tap_top.v
../../rtl/verilog/adv_debug_sys/Hardware/jtag/tap/rtl/verilog/tap_defines.v
../../rtl/verilog/uart16550/rtl/verilog/uart_top.v
../../rtl/verilog/uart16550/rtl/verilog/uart_sync_flops.v
../../rtl/verilog/uart16550/rtl/verilog/uart_transmitter.v
../../rtl/verilog/uart16550/rtl/verilog/uart_debug_if.v
../../rtl/verilog/uart16550/rtl/verilog/uart_wb.v
../../rtl/verilog/uart16550/rtl/verilog/uart_receiver.v
../../rtl/verilog/uart16550/rtl/verilog/uart_tfifo.v
../../rtl/verilog/uart16550/rtl/verilog/uart_regs.v
../../rtl/verilog/uart16550/rtl/verilog/uart_rfifo.v
../../rtl/verilog/uart16550/rtl/verilog/uart_defines.v
../../rtl/verilog/uart16550/rtl/verilog/raminfr.v
../../rtl/verilog/ethmac/rtl/verilog/eth_cop.v
../../rtl/verilog/ethmac/rtl/verilog/eth_registers.v
../../rtl/verilog/ethmac/rtl/verilog/eth_rxethmac.v
../../rtl/verilog/ethmac/rtl/verilog/eth_miim.v
../../rtl/verilog/ethmac/rtl/verilog/eth_top.v
../../rtl/verilog/ethmac/rtl/verilog/eth_rxaddrcheck.v
../../rtl/verilog/ethmac/rtl/verilog/eth_outputcontrol.v
../../rtl/verilog/ethmac/rtl/verilog/eth_rxstatem.v
../../rtl/verilog/ethmac/rtl/verilog/eth_txethmac.v
../../rtl/verilog/ethmac/rtl/verilog/eth_wishbone.v
../../rtl/verilog/ethmac/rtl/verilog/eth_maccontrol.v
../../rtl/verilog/ethmac/rtl/verilog/eth_txstatem.v
../../rtl/verilog/ethmac/rtl/verilog/eth_defines.v
../../rtl/verilog/ethmac/rtl/verilog/eth_spram_256x32.v
../../rtl/verilog/ethmac/rtl/verilog/eth_shiftreg.v
../../rtl/verilog/ethmac/rtl/verilog/eth_clockgen.v
../../rtl/verilog/ethmac/rtl/verilog/eth_crc.v
../../rtl/verilog/ethmac/rtl/verilog/eth_rxcounters.v
../../rtl/verilog/ethmac/rtl/verilog/eth_macstatus.v
../../rtl/verilog/ethmac/rtl/verilog/eth_random.v
../../rtl/verilog/ethmac/rtl/verilog/eth_register.v
../../rtl/verilog/ethmac/rtl/verilog/eth_fifo.v
../../rtl/verilog/ethmac/rtl/verilog/eth_receivecontrol.v
../../rtl/verilog/ethmac/rtl/verilog/eth_transmitcontrol.v
../../rtl/verilog/ethmac/rtl/verilog/eth_txcounters.v
minsoc_model.txt Property changes : Added: svn:executable ## -0,0 +1 ## +* \ No newline at end of property Index: minsoc_memory.txt =================================================================== --- minsoc_memory.txt (nonexistent) +++ minsoc_memory.txt (revision 42) @@ -0,0 +1,138 @@ ++incdir+../../bench/verilog ++incdir+../../bench/verilog/vpi ++incdir+../../bench/verilog/sim_lib ++incdir+../../rtl/verilog ++incdir+../../rtl/verilog/minsoc_startup ++incdir+../../rtl/verilog/or1200/rtl/verilog ++incdir+../../rtl/verilog/adv_debug_sys/Hardware/adv_dbg_if/rtl/verilog ++incdir+../../rtl/verilog/adv_debug_sys/Hardware/jtag/tap/rtl/verilog ++incdir+../../rtl/verilog/adv_debug_sys/Software/adv_jtag_bridge/sim_rtl ++incdir+../../rtl/verilog/uart16550/rtl/verilog ++incdir+../../rtl/verilog/ethmac/rtl/verilog +../../bench/verilog/minsoc_bench_defines.v +../../bench/verilog/minsoc_bench.v +#../../bench/verilog/minsoc_memory_model.v +../../bench/verilog/vpi/dbg_comm_vpi.v +../../bench/verilog/sim_lib/fpga_memory_primitives.v +../../rtl/verilog/minsoc_top.v +../../rtl/verilog/minsoc_startup/spi_top.v +../../rtl/verilog/minsoc_startup/spi_defines.v +../../rtl/verilog/minsoc_startup/spi_shift.v +../../rtl/verilog/minsoc_startup/spi_clgen.v +../../rtl/verilog/minsoc_startup/OR1K_startup_generic.v +../../rtl/verilog/minsoc_tc_top.v +../../rtl/verilog/minsoc_onchip_ram.v +../../rtl/verilog/minsoc_clock_manager.v +../../rtl/verilog/minsoc_onchip_ram_top.v +../../rtl/verilog/minsoc_defines.v +../../rtl/verilog/or1200/rtl/verilog/or1200_spram_512x20.v +../../rtl/verilog/or1200/rtl/verilog/or1200_spram_64x24.v +../../rtl/verilog/or1200/rtl/verilog/or1200_du.v +../../rtl/verilog/or1200/rtl/verilog/or1200_spram_2048x32_bw.v +../../rtl/verilog/or1200/rtl/verilog/or1200_rf.v +../../rtl/verilog/or1200/rtl/verilog/or1200_alu.v +../../rtl/verilog/or1200/rtl/verilog/or1200_dmmu_top.v +../../rtl/verilog/or1200/rtl/verilog/or1200_lsu.v +../../rtl/verilog/or1200/rtl/verilog/or1200_spram_1024x32.v +../../rtl/verilog/or1200/rtl/verilog/or1200_dc_top.v +../../rtl/verilog/or1200/rtl/verilog/or1200_cpu.v +../../rtl/verilog/or1200/rtl/verilog/or1200_gmultp2_32x32.v +../../rtl/verilog/or1200/rtl/verilog/or1200_immu_top.v +../../rtl/verilog/or1200/rtl/verilog/or1200_dpram_256x32.v +../../rtl/verilog/or1200/rtl/verilog/or1200_tt.v +../../rtl/verilog/or1200/rtl/verilog/or1200_iwb_biu.v +../../rtl/verilog/or1200/rtl/verilog/or1200_rfram_generic.v +../../rtl/verilog/or1200/rtl/verilog/or1200_dc_tag.v +../../rtl/verilog/or1200/rtl/verilog/or1200_spram_2048x8.v +../../rtl/verilog/or1200/rtl/verilog/or1200_immu_tlb.v +../../rtl/verilog/or1200/rtl/verilog/or1200_ic_tag.v +../../rtl/verilog/or1200/rtl/verilog/or1200_spram_64x14.v +../../rtl/verilog/or1200/rtl/verilog/or1200_spram_32x24.v +../../rtl/verilog/or1200/rtl/verilog/or1200_dpram_32x32.v +../../rtl/verilog/or1200/rtl/verilog/or1200_xcv_ram32x8d.v +../../rtl/verilog/or1200/rtl/verilog/or1200_spram_1024x8.v +../../rtl/verilog/or1200/rtl/verilog/or1200_mem2reg.v +../../rtl/verilog/or1200/rtl/verilog/or1200_pm.v +../../rtl/verilog/or1200/rtl/verilog/or1200_spram_256x21.v +../../rtl/verilog/or1200/rtl/verilog/or1200_operandmuxes.v +../../rtl/verilog/or1200/rtl/verilog/or1200_pic.v +../../rtl/verilog/or1200/rtl/verilog/or1200_cfgr.v +../../rtl/verilog/or1200/rtl/verilog/or1200_if.v +../../rtl/verilog/or1200/rtl/verilog/or1200_qmem_top.v +../../rtl/verilog/or1200/rtl/verilog/or1200_genpc.v +../../rtl/verilog/or1200/rtl/verilog/or1200_defines.v +../../rtl/verilog/or1200/rtl/verilog/or1200_wbmux.v +../../rtl/verilog/or1200/rtl/verilog/or1200_ic_ram.v +../../rtl/verilog/or1200/rtl/verilog/or1200_dmmu_tlb.v +../../rtl/verilog/or1200/rtl/verilog/or1200_sb_fifo.v +../../rtl/verilog/or1200/rtl/verilog/or1200_sprs.v +../../rtl/verilog/or1200/rtl/verilog/or1200_tpram_32x32.v +../../rtl/verilog/or1200/rtl/verilog/or1200_ctrl.v +../../rtl/verilog/or1200/rtl/verilog/or1200_sb.v +../../rtl/verilog/or1200/rtl/verilog/or1200_mult_mac.v +../../rtl/verilog/or1200/rtl/verilog/or1200_ic_fsm.v +../../rtl/verilog/or1200/rtl/verilog/or1200_amultp2_32x32.v +../../rtl/verilog/or1200/rtl/verilog/or1200_reg2mem.v +../../rtl/verilog/or1200/rtl/verilog/or1200_spram_2048x32.v +../../rtl/verilog/or1200/rtl/verilog/or1200_except.v +../../rtl/verilog/or1200/rtl/verilog/or1200_top.v +../../rtl/verilog/or1200/rtl/verilog/or1200_ic_top.v +../../rtl/verilog/or1200/rtl/verilog/or1200_dc_ram.v +../../rtl/verilog/or1200/rtl/verilog/or1200_spram_1024x32_bw.v +../../rtl/verilog/or1200/rtl/verilog/or1200_freeze.v +../../rtl/verilog/or1200/rtl/verilog/or1200_spram_128x32.v +../../rtl/verilog/or1200/rtl/verilog/or1200_dc_fsm.v +../../rtl/verilog/or1200/rtl/verilog/or1200_wb_biu.v +../../rtl/verilog/or1200/rtl/verilog/or1200_spram_64x22.v +../../rtl/verilog/or1200/rtl/verilog/or1200_fpu.v +../../rtl/verilog/or1200/rtl/verilog/or1200_spram.v +../../rtl/verilog/or1200/rtl/verilog/or1200_spram_32_bw.v +../../rtl/verilog/or1200/rtl/verilog/or1200_dpram.v +../../rtl/verilog/adv_debug_sys/Hardware/adv_dbg_if/rtl/verilog/adbg_wb_biu.v +../../rtl/verilog/adv_debug_sys/Hardware/adv_dbg_if/rtl/verilog/adbg_wb_module.v +../../rtl/verilog/adv_debug_sys/Hardware/adv_dbg_if/rtl/verilog/adbg_or1k_module.v +../../rtl/verilog/adv_debug_sys/Hardware/adv_dbg_if/rtl/verilog/adbg_wb_defines.v +../../rtl/verilog/adv_debug_sys/Hardware/adv_dbg_if/rtl/verilog/adbg_defines.v +../../rtl/verilog/adv_debug_sys/Hardware/adv_dbg_if/rtl/verilog/adbg_crc32.v +../../rtl/verilog/adv_debug_sys/Hardware/adv_dbg_if/rtl/verilog/adbg_or1k_biu.v +../../rtl/verilog/adv_debug_sys/Hardware/adv_dbg_if/rtl/verilog/adbg_or1k_defines.v +../../rtl/verilog/adv_debug_sys/Hardware/adv_dbg_if/rtl/verilog/adbg_or1k_status_reg.v +../../rtl/verilog/adv_debug_sys/Hardware/adv_dbg_if/rtl/verilog/adbg_top.v +../../rtl/verilog/adv_debug_sys/Hardware/jtag/tap/rtl/verilog/tap_top.v +../../rtl/verilog/adv_debug_sys/Hardware/jtag/tap/rtl/verilog/tap_defines.v +../../rtl/verilog/uart16550/rtl/verilog/uart_top.v +../../rtl/verilog/uart16550/rtl/verilog/uart_sync_flops.v +../../rtl/verilog/uart16550/rtl/verilog/uart_transmitter.v +../../rtl/verilog/uart16550/rtl/verilog/uart_debug_if.v +../../rtl/verilog/uart16550/rtl/verilog/uart_wb.v +../../rtl/verilog/uart16550/rtl/verilog/uart_receiver.v +../../rtl/verilog/uart16550/rtl/verilog/uart_tfifo.v +../../rtl/verilog/uart16550/rtl/verilog/uart_regs.v +../../rtl/verilog/uart16550/rtl/verilog/uart_rfifo.v +../../rtl/verilog/uart16550/rtl/verilog/uart_defines.v +../../rtl/verilog/uart16550/rtl/verilog/raminfr.v +../../rtl/verilog/ethmac/rtl/verilog/eth_cop.v +../../rtl/verilog/ethmac/rtl/verilog/eth_registers.v +../../rtl/verilog/ethmac/rtl/verilog/eth_rxethmac.v +../../rtl/verilog/ethmac/rtl/verilog/eth_miim.v +../../rtl/verilog/ethmac/rtl/verilog/eth_top.v +../../rtl/verilog/ethmac/rtl/verilog/eth_rxaddrcheck.v +../../rtl/verilog/ethmac/rtl/verilog/eth_outputcontrol.v +../../rtl/verilog/ethmac/rtl/verilog/eth_rxstatem.v +../../rtl/verilog/ethmac/rtl/verilog/eth_txethmac.v +../../rtl/verilog/ethmac/rtl/verilog/eth_wishbone.v +../../rtl/verilog/ethmac/rtl/verilog/eth_maccontrol.v +../../rtl/verilog/ethmac/rtl/verilog/eth_txstatem.v +../../rtl/verilog/ethmac/rtl/verilog/eth_defines.v +../../rtl/verilog/ethmac/rtl/verilog/eth_spram_256x32.v +../../rtl/verilog/ethmac/rtl/verilog/eth_shiftreg.v +../../rtl/verilog/ethmac/rtl/verilog/eth_clockgen.v +../../rtl/verilog/ethmac/rtl/verilog/eth_crc.v +../../rtl/verilog/ethmac/rtl/verilog/eth_rxcounters.v +../../rtl/verilog/ethmac/rtl/verilog/eth_macstatus.v +../../rtl/verilog/ethmac/rtl/verilog/eth_random.v +../../rtl/verilog/ethmac/rtl/verilog/eth_register.v +../../rtl/verilog/ethmac/rtl/verilog/eth_fifo.v +../../rtl/verilog/ethmac/rtl/verilog/eth_receivecontrol.v +../../rtl/verilog/ethmac/rtl/verilog/eth_transmitcontrol.v +../../rtl/verilog/ethmac/rtl/verilog/eth_txcounters.v
minsoc_memory.txt Property changes : Added: svn:executable ## -0,0 +1 ## +* \ No newline at end of property

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