OpenCores

0,0 → 1,65

0,0 → 1,70

setup/cable-install.sh Property changes : Added: svn:executable ## -0,0 +1 ## +* \ No newline at end of property Index: setup/minsoc-install.sh =================================================================== --- setup/minsoc-install.sh (nonexistent) +++ setup/minsoc-install.sh (revision 42) @@ -0,0 +1,74 @@ +#!/bin/bash +# Xanthopoulos Constantinos +# Installing cable drivers for the impact to work +# under Debian Squeeze. + + +# ===== CONFIGURATIONS ===== +# ========================== + +# Where should I put the dir. minsoc? +# ex. /home/conx/Thesis/ +DIR_TO_INSTALL="" + + +# ===== SCRIPT ====== +# =================== +export DEBUG=0; +. conxshlib.sh + +if [ `whoami` == "root" ]; +then + errormsg "You shouldn't be root for this script to run."; +fi; + +if [ ! -d $DIR_TO_INSTALL ] +then + errormsg "Directory doesn't exist. Please create it"; +fi; + +cd $DIR_TO_INSTALL + +if [ ! -f "minsoc.tar.gz" ]; +then + execcmd "Download minsoc" "wget http://xanthopoulos.info/pub/minsoc.tar.gz" +fi + +if [ -d "minsoc" ] +then + rm minsoc -rf +fi + +execcmd "Un-tar minsoc" "tar xf minsoc.tar.gz" + +cecho "I will now start to compile everything that's needed"; + +cd minsoc/sw/utils + +execcmd "Make utils" "make" + +cd ../support + +execcmd "Make support tools" "make" + +cd ../drivers + +execcmd "Make drivers" "make" + +cd ../gpio + +execcmd "Make GPIO" "make" + +cd ../uart + +execcmd "Make UART" "make" + +cd ${DIR_TO_INSTALL}/minsoc/rtl/verilog/adv_debug_sys/Software/adv_jtag_bridge + +cecho "Installing FTDI headers! You will be asked to give root pass" + +execcmd "Install FTDI headers" "su -c \"aptitude install libftdi-dev\""; + +execcmd "Make adv_jtag_bridge" "make" + +cecho "Installation Finised"

setup/minsoc-install.sh Property changes : Added: svn:executable ## -0,0 +1 ## +* \ No newline at end of property Index: setup/README =================================================================== --- setup/README (nonexistent) +++ setup/README (revision 42) @@ -0,0 +1,24 @@ +===== STEPS ===== + +A. Install Cable Drivers: + - Edit the cable-install.sh file and set the variable ISE_PATH to the directory + where you have installed ISE (that directory must contain a directory ISE_DS). + - Run the script: ./cable-install.sh + - When finished type lsusb and you should get a line similar to + "Bus 001 Device 005: ID 03fd:0008 Xilinx, Inc." where the ID + should be as shown (03fd:0008). + - You should be able to run IMPACT and see the devices in the JTAG chain. + +B. Install GNU Toolchain for OR: + - Edit the toolchain-install.sh file and set the variables DIR_TO_INSTALL and + KERNEL_ARCH as explained in the file. + - Run the script: ./toolchain-install.sh + - When finished you should be able to run or32-elf-gdb in a new terminal. + +C. Install minsoc: + - Edit the minsoc-install.sh file and the variable DIR_TO_INSTALL. + - Run the script: ./minsoc-install.sh + - When finished you should have a working copy of minsoc project in the + specified directory. + +Hope it works! Index: setup/toolchain-install.sh =================================================================== --- setup/toolchain-install.sh (nonexistent) +++ setup/toolchain-install.sh (revision 42) @@ -0,0 +1,51 @@ +#!/bin/bash +# Xanthopoulos Constantinos +# Installing OR GNU Toolchain. +# Only tested in Debian Squeeze. + + +# ===== CONFIGURATIONS ===== +# ========================== + +# Where will I put the binaries? +# ex. /opt/openrisc/bin +DIR_TO_INSTALL=""; + +# Debian's kernel architecture {32,64} +# ex. KERNEL_ARCH="32" +KERNEL_ARCH="" + +# ===== SCRIPT ====== +# =================== +export DEBUG=0; +. conxshlib.sh + +if [ `whoami` == "root" ]; +then + errormsg "You shouldn't be root for this script to run."; +fi; + +if [ ! -d $DIR_TO_INSTALL ] +then + errormsg "Directory doesn't exist. Please create it"; +fi; + +execcmd "Change permissions" "chmod 777 $DIR_TO_INSTALL"; + +cd $DIR_TO_INSTALL; + +if [ $KERNEL_ARCH == "32" ]; +then + execcmd "Download toolchain (it may take a while)" "wget ftp://ocuser:oc@opencores.org/toolchain/or32-elf-linux-x86.tar.bz2"; +elif [ $KERNEL_ARCH == "64"]; +then + execcmd "Download toolchain (it may take a while)" "wget ftp://ocuser:oc@opencores.org/toolchain/or32-elf-linux-x86_64.tar.bz2"; +else + errormsg "Not a correct architecture. Check Configurations"; +fi + +execcmd "Un-tar" "tar xf *bz2"; + +execcmd "Adding toolchain to PATH" "echo \"PATH=\\\$PATH:$DIR_TO_INSTALL/or32-elf/bin/\" >> /home/$(whoami)/.bashrc;"; + +cecho "Install completed"

setup/toolchain-install.sh Property changes : Added: svn:executable ## -0,0 +1 ## +* \ No newline at end of property Index: .directory =================================================================== --- .directory (nonexistent) +++ .directory (revision 42) @@ -0,0 +1,4 @@ +[Dolphin] +Timestamp=2011,3,1,12,36,19 +Version=2 +ViewMode=1 Index: initialized_onchip_ram/minsoc_onchip_ram_top_altera.v =================================================================== --- initialized_onchip_ram/minsoc_onchip_ram_top_altera.v (nonexistent) +++ initialized_onchip_ram/minsoc_onchip_ram_top_altera.v (revision 42) @@ -0,0 +1,310 @@ +////////////////////////////////////////////////////////////////////// +//// //// +//// Generic Wishbone controller for //// +//// Single-Port Synchronous RAM //// +//// //// +//// This file is part of memory library available from //// +//// http://www.opencores.org/cvsweb.shtml/minsoc/ //// +//// //// +//// Description //// +//// This Wishbone controller connects to the wrapper of //// +//// the single-port synchronous memory interface. //// +//// Besides universal memory due to onchip_ram it provides a //// +//// generic way to set the depth of the memory. //// +//// //// +//// To Do: //// +//// //// +//// Author(s): //// +//// - Raul Fajardo, rfajardo@gmail.com //// +//// //// +////////////////////////////////////////////////////////////////////// +//// //// +//// Copyright (C) 2000 Authors and OPENCORES.ORG //// +//// //// +//// This source file may be used and distributed without //// +//// restriction provided that this copyright statement is not //// +//// removed from the file and that any derivative work contains //// +//// the original copyright notice and the associated disclaimer. //// +//// //// +//// This source file is free software; you can redistribute it //// +//// and/or modify it under the terms of the GNU Lesser General //// +//// Public License as published by the Free Software Foundation; //// +//// either version 2.1 of the License, or (at your option) any //// +//// later version. //// +//// //// +//// This source is distributed in the hope that it will be //// +//// useful, but WITHOUT ANY WARRANTY; without even the implied //// +//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR //// +//// PURPOSE. See the GNU Lesser General Public License for more //// +//// details. //// +//// //// +//// You should have received a copy of the GNU Lesser General //// +//// Public License along with this source; if not, download it //// +//// from http://www.gnu.org/licenses/lgpl.html //// +//// //// +////////////////////////////////////////////////////////////////////// +// +// Revision History +// +// Revision 1.1 2009/10/02 16:49 fajardo +// Not using the oe signal (output enable) from +// memories, instead multiplexing the outputs +// between the different instantiated blocks +// +// +// Revision 1.0 2009/08/18 15:15:00 fajardo +// Created interface and tested +// +`include "minsoc_defines.v" + +`define mem_init_file "uart-nocache.mif" //specific memory initalization file name, which can be intel hex(.hex) or Altera mif file + //if no initalization file used, give a name of "UNUSED" + +module minsoc_onchip_ram_top ( + wb_clk_i, wb_rst_i, + + wb_dat_i, wb_dat_o, wb_adr_i, wb_sel_i, wb_we_i, wb_cyc_i, + wb_stb_i, wb_ack_o, wb_err_o +); + +// +// Parameters +// +parameter adr_width = 13; //Memory address width, is composed by blocks of aw_int, is not allowed to be less than 12 +localparam aw_int = 11; //11 = 2048 +localparam blocks = (1<<(adr_width-aw_int)); //generated memory contains "blocks" memory blocks of 2048x32 2048 depth x32 bit data + +// +// I/O Ports +// +input wb_clk_i; +input wb_rst_i; + +// +// WB slave i/f +// +input [31:0] wb_dat_i; +output [31:0] wb_dat_o; +input [31:0] wb_adr_i; +input [3:0] wb_sel_i; +input wb_we_i; +input wb_cyc_i; +input wb_stb_i; +output wb_ack_o; +output wb_err_o; + +// +// Internal regs and wires +// +wire we; +wire [3:0] be_i; +wire [31:0] wb_dat_o; +reg ack_we; +reg ack_re; +// +// Aliases and simple assignments +// +assign wb_ack_o = ack_re | ack_we; +assign wb_err_o = wb_cyc_i & wb_stb_i & (|wb_adr_i[23:adr_width+2]); // If Access to > (8-bit leading prefix ignored) +assign we = wb_cyc_i & wb_stb_i & wb_we_i & (|wb_sel_i[3:0]); +assign be_i = (wb_cyc_i & wb_stb_i) * wb_sel_i; + +// +// Write acknowledge +// +always @ (negedge wb_clk_i or posedge wb_rst_i) +begin +if (wb_rst_i) + ack_we <= 1'b0; + else + if (wb_cyc_i & wb_stb_i & wb_we_i & ~ack_we) + ack_we <= #1 1'b1; + else + ack_we <= #1 1'b0; +end + +// +// read acknowledge +// +always @ (posedge wb_clk_i or posedge wb_rst_i) +begin + if (wb_rst_i) + ack_re <= 1'b0; + else + if (wb_cyc_i & wb_stb_i & ~wb_err_o & ~wb_we_i & ~ack_re) + ack_re <= #1 1'b1; + else + ack_re <= #1 1'b0; +end + +`ifdef ALTERA_FPGA //only for altera memory initialization + +//2^adr_width x 32bit single-port ram. +altsyncram altsyncram_component ( + .wren_a (we), + .clock0 (wb_clk_i), + .byteena_a (be_i), + .address_a (wb_adr_i[adr_width+1:2]), + .data_a (wb_dat_i), + .q_a (wb_dat_o), + .aclr0 (1'b0), + .aclr1 (1'b0), + .address_b (1'b1), + .addressstall_a (1'b0), + .addressstall_b (1'b0), + .byteena_b (1'b1), + .clock1 (1'b1), + .clocken0 (1'b1), + .clocken1 (1'b1), + .clocken2 (1'b1), + .clocken3 (1'b1), + .data_b (1'b1), + .eccstatus (), + .q_b (), + .rden_a (1'b1), + .rden_b (1'b1), + .wren_b (1'b0)); + defparam + altsyncram_component.clock_enable_input_a = "BYPASS", + altsyncram_component.clock_enable_output_a = "BYPASS", + altsyncram_component.init_file = `mem_init_file, + altsyncram_component.intended_device_family = "Stratix III", + altsyncram_component.lpm_hint = "ENABLE_RUNTIME_MOD=NO", + altsyncram_component.lpm_type = "altsyncram", + altsyncram_component.operation_mode = "SINGLE_PORT", + altsyncram_component.outdata_aclr_a = "NONE", + altsyncram_component.outdata_reg_a = "UNREGISTERED", + altsyncram_component.power_up_uninitialized = "FALSE", + altsyncram_component.read_during_write_mode_port_a = "NEW_DATA_NO_NBE_READ", + altsyncram_component.numwords_a = (1<>(j+1)); k=k+1) begin : MUX + if (j==0) begin + mux2 # + ( + .dw(32) + ) + mux_int( + .sel( wb_adr_i[aw_int+2+j] ), + .in1( int_dat_o[k*2] ), + .in2( int_dat_o[k*2+1] ), + .out( mux_out[k] ) + ); + end + else begin + mux2 # + ( + .dw(32) + ) + mux_int( + .sel( wb_adr_i[aw_int+2+j] ), + .in1( mux_out[(mux_in_nr-(mux_in_nr>>(j-1)))+k*2] ), + .in2( mux_out[(mux_in_nr-(mux_in_nr>>(j-1)))+k*2+1] ), + .out( mux_out[(mux_in_nr-(mux_in_nr>>j))+k] ) + ); + end + end + end +endgenerate + +//last output = total output +assign wb_dat_o = mux_out[mux_out_nr-1]; + +//(mux_in_nr-(mux_in_nr>>j)): +//-Given sum of 2^i | i = x -> y series can be resumed to 2^(y+1)-2^x +//so, with this expression I'm evaluating how many times the internal loop has been run + +wire [blocks-1:0] bank; + +generate +genvar i; + for (i=0; i < blocks; i=i+1) begin : MEM + + assign bank[i] = wb_adr_i[adr_width+1:aw_int+2] == i; + + //BANK0 + minsoc_onchip_ram block_ram_0 ( + .clk(wb_clk_i), + .rst(wb_rst_i), + .addr(wb_adr_i[aw_int+1:2]), + .di(wb_dat_i[7:0]), + .doq(int_dat_o[i][7:0]), + .we(we & bank[i]), + .oe(1'b1), + .ce(be_i[0]) + ); + + + minsoc_onchip_ram block_ram_1 ( + .clk(wb_clk_i), + .rst(wb_rst_i), + .addr(wb_adr_i[aw_int+1:2]), + .di(wb_dat_i[15:8]), + .doq(int_dat_o[i][15:8]), + .we(we & bank[i]), + .oe(1'b1), + .ce(be_i[1]) + ); + + minsoc_onchip_ram block_ram_2 ( + .clk(wb_clk_i), + .rst(wb_rst_i), + .addr(wb_adr_i[aw_int+1:2]), + .di(wb_dat_i[23:16]), + .doq(int_dat_o[i][23:16]), + .we(we & bank[i]), + .oe(1'b1), + .ce(be_i[2]) + ); + + minsoc_onchip_ram block_ram_3 ( + .clk(wb_clk_i), + .rst(wb_rst_i), + .addr(wb_adr_i[aw_int+1:2]), + .di(wb_dat_i[31:24]), + .doq(int_dat_o[i][31:24]), + .we(we & bank[i]), + .oe(1'b1), + .ce(be_i[3]) + ); + + end +endgenerate +`endif + +endmodule + +module mux2(sel,in1,in2,out); + +parameter dw = 32; + +input sel; +input [dw-1:0] in1, in2; +output reg [dw-1:0] out; + +always @ (sel or in1 or in2) +begin + case (sel) + 1'b0: out = in1; + 1'b1: out = in2; + endcase +end + +endmodule Index: initialized_onchip_ram/bin2init.py =================================================================== --- initialized_onchip_ram/bin2init.py (nonexistent) +++ initialized_onchip_ram/bin2init.py (revision 42) @@ -0,0 +1,212 @@ +""" +***************************************************************************** + * + H E A D E R I N F O R M A T I O N * + * +***************************************************************************** +Project Name : SysPy (System Python) + http://cgi.di.uoa.gr/~evlog/syspy.html + +File Name : bin2init.py + +Created by : Evangelos Logaras + + +***************************************************************************** + * + C O P Y R I G H T N O T I C E * + * +***************************************************************************** + + This library is free software; you can redistribute it and/or + modify it under the terms of the GNU Lesser General Public + License as published by the Free Software Foundation; + version 2.1 of the License, a copy of which is available from + http://www.gnu.org/licenses/old-licenses/lgpl-2.1.txt. + + This library is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + Lesser General Public License for more details. + + You should have received a copy of the GNU Lesser General Public + License along with this library; if not, write to the Free Software + Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA + + +***************************************************************************** + * + D E S C R I P T I O N * + * +***************************************************************************** + + Generates block_ram.init file from binary images. Binary images are first converted in hex files + using bin2hex.c file, provided with the ORPSoC v2 project. bin2hex executable must exist in the same folder with this script. + + Currently init file is generated for Xilinx's RAMB16_S9 BRAMs + + Usage: python bin2init.py (Python 2.6) +""" + +import commands +import sys + + +# Python's variable declarations +#---------------------------------------------------------------------------------------------------------------------------------- +y = ' ' +mem_arr = [] +block_ram_num = 4 +block0 = [] +block1 = [] +block2 = [] +block3 = [] +block_ram = [block3, block2, block1, block0] +init_arr = [] +mem_size2 = 8192 +mem_count = 0 +bram_count = -1 +init_count = -1 +hex_count = 0 +zero_pad = '' +filename = '' +#---------------------------------------------------------------------------------------------------------------------------------- + +# Exceptions' class +#---------------------------------------------------------------------------------------------------------------------------------- +class MyExceptions(Exception): + def __init__(self, value): + self.value = value + def __str__(self): + return repr(self.value) +#---------------------------------------------------------------------------------------------------------------------------------- + +# Raising exception if a *.bin file is not provided as an argument +#---------------------------------------------------------------------------------------------------------------------------------- +filename = sys.argv[len(sys.argv) - 1] + +if (filename.find(".bin") == -1): + raise MyExceptions("*.bin file required") +#---------------------------------------------------------------------------------------------------------------------------------- + +i = filename.find(".bin") + +filename = filename[:i] + +# Deleting old *.hex and *.bin files +#---------------------------------------------------------------------------------------------------------------------------------- +commands.getoutput("rm " + filename + ".hex") +commands.getoutput("rm " + filename + ".init") +#---------------------------------------------------------------------------------------------------------------------------------- + +## Calling bin2hex executable to convert *.bin file to *.hex +commands.getoutput("./bin2hex " + filename + ".bin 4 > "+ filename + ".hex") + +# Opening the *.hex and the *.init file +#---------------------------------------------------------------------------------------------------------------------------------- +hexFile = open(filename + ".hex", 'r') +initFile = open(filename + ".init", 'w') +#---------------------------------------------------------------------------------------------------------------------------------- + +# Reading the *.hex file and appending its contents to mem_arr[] +#---------------------------------------------------------------------------------------------------------------------------------- +y = ' ' +hex_count = 0 +while(y): + hex_count = hex_count + 1 + if (hex_count == 127): + mem_arr.append("00000000") + + y = hexFile.readline() + mem_arr.append(y) +#---------------------------------------------------------------------------------------------------------------------------------- + +# Reading mem_arr[] and creating the contents of BRAMs +#---------------------------------------------------------------------------------------------------------------------------------- +for i in range(len(mem_arr)): + bram_count = bram_count + 1 + if (bram_count < 32): + block_ram[0].append(mem_arr[i][6:8]) + block_ram[1].append(mem_arr[i][4:6]) + block_ram[2].append(mem_arr[i][2:4]) + block_ram[3].append(mem_arr[i][0:2]) + + elif (bram_count >= 32): + bram_count = 0 + + init_count = init_count + 1 + + if (init_count >= 64): + init_count = 0 + mem_count = mem_count + 1 + + hex_init_count = str(hex(init_count)) + hex_init_count = hex_init_count[2:] + hex_init_count = hex_init_count.upper() + if (init_count < 16): + hex_init_count = '0' + hex_init_count + + + for j in range((block_ram_num - 1), -1, -1): + if (j == (block_ram_num - 1)): + init_arr.append(";\ndefparam MEM[" + str(mem_count) + "].block_ram_" + str(j) + ".INIT_" + hex_init_count + " = 256'h") + block_ram[j].reverse() + for k in range(len(block_ram[j])): + init_arr.append(block_ram[j][k].replace("\n", '')) + else: + init_arr.append(";\ndefparam MEM[" + str(mem_count) + "].block_ram_" + str(j) + ".INIT_" + hex_init_count + " = 256'h") + block_ram[j].reverse() + for k in range(len(block_ram[j])): + init_arr.append(block_ram[j][k].replace("\n", '')) + + block_ram[0] = [] + block_ram[1] = [] + block_ram[2] = [] + block_ram[3] = [] + + block_ram[0].append(mem_arr[i][6:8]) + block_ram[1].append(mem_arr[i][4:6]) + block_ram[2].append(mem_arr[i][2:4]) + block_ram[3].append(mem_arr[i][0:2]) + + +if (bram_count != -1): + init_count = init_count + 1 + hex_init_count = str(hex(init_count)) + hex_init_count = hex_init_count[2:] + hex_init_count = hex_init_count.upper() + if (init_count < 16): + hex_init_count = '0' + hex_init_count + + if (init_count == 0): + for j in range(64 - 2 * bram_count): + zero_pad = zero_pad + '0' + else: + for j in range(64 - 2 * bram_count): + zero_pad = zero_pad + '0' + + for j in range((block_ram_num - 1), -1, -1): + init_arr.append(";\ndefparam MEM[" + str(mem_count) + "].block_ram_" + str(j) + ".INIT_" + hex_init_count + " = 256'h") + block_ram[j].reverse() + init_arr.append(zero_pad) + for k in range(len(block_ram[j])): + init_arr.append(block_ram[j][k].replace("\n", '')) + +init_arr.append(';') +#---------------------------------------------------------------------------------------------------------------------------------- + +# Writing BRAMs contetns to *.init file +#---------------------------------------------------------------------------------------------------------------------------------- +i = init_arr[0].find(";/n") + +init_arr[0] = init_arr[0][i + 2:] + +for i in range(len(init_arr)): + initFile.write(init_arr[i]) +#---------------------------------------------------------------------------------------------------------------------------------- + +# Closing the *.hex and the *.init file +#---------------------------------------------------------------------------------------------------------------------------------- +hexFile.close() +initFile.close() +#---------------------------------------------------------------------------------------------------------------------------------- Index: initialized_onchip_ram/minsoc_onchip_ram_top_xilinx.v =================================================================== --- initialized_onchip_ram/minsoc_onchip_ram_top_xilinx.v (nonexistent) +++ initialized_onchip_ram/minsoc_onchip_ram_top_xilinx.v (revision 42) @@ -0,0 +1,312 @@ +////////////////////////////////////////////////////////////////////// +//// //// +//// Generic Wishbone controller for //// +//// Single-Port Synchronous RAM //// +//// //// +//// This file is part of memory library available from //// +//// http://www.opencores.org/cvsweb.shtml/minsoc/ //// +//// //// +//// Description //// +//// This Wishbone controller connects to the wrapper of //// +//// the single-port synchronous memory interface. //// +//// Besides universal memory due to onchip_ram it provides a //// +//// generic way to set the depth of the memory. //// +//// //// +//// To Do: //// +//// //// +//// Author(s): //// +//// - Raul Fajardo, rfajardo@gmail.com //// +//// //// +////////////////////////////////////////////////////////////////////// +//// //// +//// Copyright (C) 2000 Authors and OPENCORES.ORG //// +//// //// +//// This source file may be used and distributed without //// +//// restriction provided that this copyright statement is not //// +//// removed from the file and that any derivative work contains //// +//// the original copyright notice and the associated disclaimer. //// +//// //// +//// This source file is free software; you can redistribute it //// +//// and/or modify it under the terms of the GNU Lesser General //// +//// Public License as published by the Free Software Foundation; //// +//// either version 2.1 of the License, or (at your option) any //// +//// later version. //// +//// //// +//// This source is distributed in the hope that it will be //// +//// useful, but WITHOUT ANY WARRANTY; without even the implied //// +//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR //// +//// PURPOSE. See the GNU Lesser General Public License for more //// +//// details. //// +//// //// +//// You should have received a copy of the GNU Lesser General //// +//// Public License along with this source; if not, download it //// +//// from http://www.gnu.org/licenses/lgpl.html //// +//// //// +////////////////////////////////////////////////////////////////////// +// +// Revision History +// +// Revision 1.1 2009/10/02 16:49 fajardo +// Not using the oe signal (output enable) from +// memories, instead multiplexing the outputs +// between the different instantiated blocks +// +// +// Revision 1.0 2009/08/18 15:15:00 fajardo +// Created interface and tested +// +`include "minsoc_defines.v" + +module minsoc_onchip_ram_top ( + wb_clk_i, wb_rst_i, + + wb_dat_i, wb_dat_o, wb_adr_i, wb_sel_i, wb_we_i, wb_cyc_i, + wb_stb_i, wb_ack_o, wb_err_o +); + +// +// Parameters +// +parameter adr_width = 13; //Memory address width, is composed by blocks of aw_int, is not allowed to be less than 12 +localparam aw_int = 11; //11 = 2048 +localparam blocks = (1<<(adr_width-aw_int)); //generated memory contains "blocks" memory blocks of 2048x32 2048 depth x32 bit data + +// +// I/O Ports +// +input wb_clk_i; +input wb_rst_i; + +// +// WB slave i/f +// +input [31:0] wb_dat_i; +output [31:0] wb_dat_o; +input [31:0] wb_adr_i; +input [3:0] wb_sel_i; +input wb_we_i; +input wb_cyc_i; +input wb_stb_i; +output wb_ack_o; +output wb_err_o; + +// +// Internal regs and wires +// +wire we; +wire [3:0] be_i; +wire [31:0] wb_dat_o; +reg ack_we; +reg ack_re; +// +// Aliases and simple assignments +// +assign wb_ack_o = ack_re | ack_we; +assign wb_err_o = wb_cyc_i & wb_stb_i & (|wb_adr_i[23:adr_width+2]); // If Access to > (8-bit leading prefix ignored) +assign we = wb_cyc_i & wb_stb_i & wb_we_i & (|wb_sel_i[3:0]); +assign be_i = (wb_cyc_i & wb_stb_i) * wb_sel_i; + +// +// Write acknowledge +// +always @ (negedge wb_clk_i or posedge wb_rst_i) +begin +if (wb_rst_i) + ack_we <= 1'b0; + else + if (wb_cyc_i & wb_stb_i & wb_we_i & ~ack_we) + ack_we <= #1 1'b1; + else + ack_we <= #1 1'b0; +end + +// +// read acknowledge +// +always @ (posedge wb_clk_i or posedge wb_rst_i) +begin + if (wb_rst_i) + ack_re <= 1'b0; + else + if (wb_cyc_i & wb_stb_i & ~wb_err_o & ~wb_we_i & ~ack_re) + ack_re <= #1 1'b1; + else + ack_re <= #1 1'b0; +end + +//Generic (multiple inputs x 1 output) MUX +localparam mux_in_nr = blocks; +localparam slices = adr_width-aw_int; +localparam mux_out_nr = blocks-1; + +wire [31:0] int_dat_o[0:mux_in_nr-1]; +wire [31:0] mux_out[0:mux_out_nr-1]; + +generate +genvar j, k; + for (j=0; j>(j+1)); k=k+1) begin : MUX + if (j==0) begin + mux21 # + ( + .dw(32) + ) + mux_int( + .sel( wb_adr_i[aw_int+2+j] ), + .in1( int_dat_o[k*2] ), + .in2( int_dat_o[k*2+1] ), + .out( mux_out[k] ) + ); + end + else begin + mux21 # + ( + .dw(32) + ) + mux_int( + .sel( wb_adr_i[aw_int+2+j] ), + .in1( mux_out[(mux_in_nr-(mux_in_nr>>(j-1)))+k*2] ), + .in2( mux_out[(mux_in_nr-(mux_in_nr>>(j-1)))+k*2+1] ), + .out( mux_out[(mux_in_nr-(mux_in_nr>>j))+k] ) + ); + end + end + end +endgenerate + +//last output = total output +assign wb_dat_o = mux_out[mux_out_nr-1]; + +//(mux_in_nr-(mux_in_nr>>j)): +//-Given sum of 2^i | i = x -> y series can be resumed to 2^(y+1)-2^x +//so, with this expression I'm evaluating how many times the internal loop has been run + +wire [blocks-1:0] bank; + +generate +genvar i; + for (i=0; i < blocks; i=i+1) begin : MEM + + assign bank[i] = wb_adr_i[adr_width+1:aw_int+2] == i; + + //BANK0 +/* minsoc_onchip_ram block_ram_0 ( + .clk(wb_clk_i), + .rst(wb_rst_i), + .addr(wb_adr_i[aw_int+1:2]), + .di(wb_dat_i[7:0]), + .doq(int_dat_o[i][7:0]), + .we(we & bank[i]), + .oe(1'b1), + .ce(be_i[0]) + ); +*/ + RAMB16_S9 block_ram_0( + .CLK(wb_clk_i), + .SSR(wb_rst_i), + .ADDR(wb_adr_i[aw_int+1:2]), + .DI(wb_dat_i[7:0]), + .DIP(1'b0), + .EN(be_i[0]), + .WE(we & bank[i]), + .DO(int_dat_o[i][7:0]), + .DOP() + ); + +/* + minsoc_onchip_ram block_ram_1 ( + .clk(wb_clk_i), + .rst(wb_rst_i), + .addr(wb_adr_i[aw_int+1:2]), + .di(wb_dat_i[15:8]), + .doq(int_dat_o[i][15:8]), + .we(we & bank[i]), + .oe(1'b1), + .ce(be_i[1]) + ); +*/ + RAMB16_S9 block_ram_1( + .CLK(wb_clk_i), + .SSR(wb_rst_i), + .ADDR(wb_adr_i[aw_int+1:2]), + .DI(wb_dat_i[15:8]), + .DIP(1'b0), + .EN(be_i[1]), + .WE(we & bank[i]), + .DO(int_dat_o[i][15:8]), + .DOP() + ); +/* + minsoc_onchip_ram block_ram_2 ( + .clk(wb_clk_i), + .rst(wb_rst_i), + .addr(wb_adr_i[aw_int+1:2]), + .di(wb_dat_i[23:16]), + .doq(int_dat_o[i][23:16]), + .we(we & bank[i]), + .oe(1'b1), + .ce(be_i[2]) + ); +*/ + RAMB16_S9 block_ram_2( + .CLK(wb_clk_i), + .SSR(wb_rst_i), + .ADDR(wb_adr_i[aw_int+1:2]), + .DI(wb_dat_i[23:16]), + .DIP(1'b0), + .EN(be_i[2]), + .WE(we & bank[i]), + .DO(int_dat_o[i][23:16]), + .DOP() + ); + +/* + minsoc_onchip_ram block_ram_3 ( + .clk(wb_clk_i), + .rst(wb_rst_i), + .addr(wb_adr_i[aw_int+1:2]), + .di(wb_dat_i[31:24]), + .doq(int_dat_o[i][31:24]), + .we(we & bank[i]), + .oe(1'b1), + .ce(be_i[3]) + ); +*/ + RAMB16_S9 block_ram_3( + .CLK(wb_clk_i), + .SSR(wb_rst_i), + .ADDR(wb_adr_i[aw_int+1:2]), + .DI(wb_dat_i[31:24]), + .DIP(1'b0), + .EN(be_i[3]), + .WE(we & bank[i]), + .DO(int_dat_o[i][31:24]), + .DOP() + ); + + end +endgenerate + +`ifdef BLOCK_RAM_INIT +`include "block_ram.init" +`endif + +endmodule + +module mux21(sel,in1,in2,out); + +parameter dw = 32; + +input sel; +input [dw-1:0] in1, in2; +output reg [dw-1:0] out; + +always @ (sel or in1 or in2) +begin + case (sel) + 1'b0: out = in1; + 1'b1: out = in2; + endcase +end + +endmodule Index: synthesis_makefile/guideTop.pdf =================================================================== Cannot display: file marked as a binary type. svn:mime-type = application/octet-stream Index: synthesis_makefile/guideTop.pdf =================================================================== --- synthesis_makefile/guideTop.pdf (nonexistent) +++ synthesis_makefile/guideTop.pdf (revision 42)

synthesis_makefile/guideTop.pdf Property changes : Added: svn:mime-type ## -0,0 +1 ## +application/octet-stream \ No newline at end of property Index: synthesis_makefile/Makefile =================================================================== --- synthesis_makefile/Makefile (nonexistent) +++ synthesis_makefile/Makefile (revision 42) @@ -0,0 +1,107 @@ +ROOT = /home/mdhicks2/Desktop/softPatch/baseSoC +MINSOC = $(ROOT)/minsoc +MINSOC_RTL = $(MINSOC)/rtl/verilog +UART_RTL = $(ROOT)/uart16550/rtl/verilog +ADV_DEBUG_ROOT = $(ROOT)/adv_debug_sys/Hardware +DEBUG_RTL = $(ADV_DEBUG_ROOT)/adv_dbg_if/rtl/verilog +XIL_DEBUG_RTL = $(ADV_DEBUG_ROOT)/xilinx_internal_jtag/rtl/verilog +OR1200_RTL = $(ROOT)/or1200/rtl/verilog + +help: + @echo " all: Synthesize and implement the SoC, then generate a bit stream" + @echo " soc: Synthesize the SoC" + @echo " translate: Convert the SoC's ngc file to an ngd file for mapping" + @echo " map: Express the SoC netlist in the target hardware" + @echo " par: Place the target hardware, then route the wires" + @echo " bitgen: Generate a programming file for the target FPGA" + @echo " clean: Delete all superfluous files generated by Xilinx tools" + @echo " distclean: Delete all generated files" + @echo " uart: Synthesize the UART" + @echo " debug: Synthesize the debug interface" + @echo " xilDebug: Synthesize the Xilinx JTAG user interface" + @echo " or1200: Synthesize the OR1200 processor" +all: minsoc_top.ngc minsoc.ngd minsoc.ncd minsoc_par.ncd minsoc.bit +soc: minsoc_top.ngc +translate: minsoc.ngd +map: minsoc.ncd +par: minsoc_par.ncd +bitgen: minsoc.bit + +distclean: + rm -f _xmsgs xst *.{ngc,ncd,ngd,bit,xst,xrpt,srp,lso,log} +clean: + rm -f _xmsgs xst *.{xst,xrpt,srp,lso,log} + +minsoc_top.ngc: $(MINSOC_RTL)/*.v buildSupport/*.xst buildSupport/*.prj #uart_top.ngc adbg_top.ngc xilinx_internal_jtag.ngc or1200_top.ngc + xst -ifn "buildSupport/minsoc_top.xst" + rm -f minsoc_top_xst.xrpt + rm -f minsoc_top.srp + rm -f minsoc_top.lso + rm -rf _xmsgs + rm -rf xst +uart: uart_top.ngc +uart_top.ngc: $(UART_RTL)/*.v buildSupport/uart_top.xst buildSupport/uart_top.prj + xst -ifn "buildSupport/uart_top.xst" + rm -f uart_top_xst.xrpt + rm -f uart_top.srp + rm -f uart_top.lso + rm -rf _xmsgs + rm -rf xst +debug: adbg_top.ngc +adbg_top.ngc: $(DEBUG_RTL)/*.v buildSupport/adbg_top.xst buildSupport/adbg_top.prj + xst -ifn "buildSupport/adbg_top.xst" + rm -f adbg_top_xst.xrpt + rm -f adbg_top.srp + rm -f adbg_top.lso + rm -rf _xmsgs + rm -rf xst +xilDebug: xilinx_internal_jtag.ngc +xilinx_internal_jtag.ngc: $(XIL_DEBUG_RTL)/*.v buildSupport/xilinx_internal_jtag.xst buildSupport/xilinx_internal_jtag.prj + xst -ifn "buildSupport/xilinx_internal_jtag.xst" + rm -f xilinx_internal_jtag_xst.xrpt + rm -f xilinx_internal_jtag.srp + rm -f xilinx_internal_jtag.lso + rm -rf _xmsgs + rm -rf xst +or1200: or1200_top.ngc +or1200_top.ngc: $(OR1200_RTL)/*.v buildSupport/or1200_top.xst buildSupport/or1200_top.prj + xst -ifn "buildSupport/or1200_top.xst" + rm -f or1200_top_xst.xrpt + rm -f or1200_top.srp + rm -f or1200_top.lso + rm -rf _xmsgs + rm -rf xst +minsoc.ngd: $(MINSOC)/backend/ml509.ucf minsoc_top.ngc + ngdbuild -p xc5vlx110t-ff1136-3 -uc $(MINSOC)/backend/ml509.ucf -aul -aut minsoc_top.ngc minsoc.ngd + rm -rf netlist.lst + rm -rf minsoc.bld + rm -rf minsoc*.xrpt + rm -rf xlnx_auto_0_xdb + rm -rf _xmsgs +minsoc.ncd : minsoc.ngd + map -bp -timing -cm speed -equivalent_register_removal on -global_opt speed -logic_opt on -mt 2 -ol high -power off -register_duplication on -retiming on -w -xe n minsoc.ngd + rm -rf minsoc.map + rm -rf minsoc.mrp + rm -rf minsoc.ngm + rm -rf minsoc.pcf + rm -rf minsoc.psr + rm -rf minsoc*.xml + rm -rf minsoc_top*.xrpt + rm -rf _xmsgs +minsoc_par.ncd: minsoc.ncd + par -mt 4 -ol high -w -xe n minsoc.ncd minsoc_par.ncd + rm -rf minsoc_par.pad + rm -rf minsoc_par.par + rm -rf minsoc_par.ptwx + rm -rf minsoc_par.unroutes + rm -rf minsoc_par.xpi + rm -rf minsoc_par_pad* + rm -rf minsoc_top*.xrpt + rm -rf _xmsgs +minsoc.bit: minsoc_par.ncd + bitgen -d -w minsoc_par.ncd minsoc.bit + rm -rf minsoc.bgn + rm -rf *.xwbt + rm -rf *.xml + rm -rf *.log + rm -rf _xmsgs Index: assembly_new_toolchain/reset.S =================================================================== --- assembly_new_toolchain/reset.S (nonexistent) +++ assembly_new_toolchain/reset.S (revision 42) @@ -0,0 +1,113 @@ +/* Support file for c based tests */ +#include "spr_defs.h" +#include "board.h" +#include "mc.h" + + .section .stack + .space STACK_SIZE +_stack: + + .section .reset, "ax" + + .org 0x100 +_reset_vector: + l.nop + l.nop + l.addi r2,r0,0x0 + l.addi r3,r0,0x0 + l.addi r4,r0,0x0 + l.addi r5,r0,0x0 + l.addi r6,r0,0x0 + l.addi r7,r0,0x0 + l.addi r8,r0,0x0 + l.addi r9,r0,0x0 + l.addi r10,r0,0x0 + l.addi r11,r0,0x0 + l.addi r12,r0,0x0 + l.addi r13,r0,0x0 + l.addi r14,r0,0x0 + l.addi r15,r0,0x0 + l.addi r16,r0,0x0 + l.addi r17,r0,0x0 + l.addi r18,r0,0x0 + l.addi r19,r0,0x0 + l.addi r20,r0,0x0 + l.addi r21,r0,0x0 + l.addi r22,r0,0x0 + l.addi r23,r0,0x0 + l.addi r24,r0,0x0 + l.addi r25,r0,0x0 + l.addi r26,r0,0x0 + l.addi r27,r0,0x0 + l.addi r28,r0,0x0 + l.addi r29,r0,0x0 + l.addi r30,r0,0x0 + l.addi r31,r0,0x0 + +/* + l.movhi r3,hi(MC_BASE_ADDR) + l.ori r3,r3,MC_BA_MASK + l.addi r5,r0,0x00 + l.sw 0(r3),r5 + */ + l.movhi r3,hi(_start) + l.ori r3,r3,lo(_start) + l.jr r3 + l.nop + + .section .text + +_start: + +.if IC | DC + /* Flush IC and/or DC */ + l.addi r10,r0,0 + l.addi r11,r0,0 + l.addi r12,r0,0 +.if IC + l.addi r11,r0,IC_SIZE +.endif +.if DC + l.addi r12,r0,DC_SIZE +.endif + l.sfleu r12,r11 + l.bf loop + l.nop + l.add r11,r0,r12 +loop: +.if IC + l.mtspr r0,r10,SPR_ICBIR +.endif +.if DC + l.mtspr r0,r10,SPR_DCBIR +.endif + l.sfne r10,r11 + l.bf loop + l.addi r10,r10,16 + + /* Enable IC and/or DC */ + l.addi r10,r0,(SPR_SR_SM) +.if IC + l.ori r10,r10,(SPR_SR_ICE) +.endif +.if DC + l.ori r10,r10,(SPR_SR_DCE) +.endif + l.mtspr r0,r10,SPR_SR + l.nop + l.nop + l.nop + l.nop + l.nop +.endif + + /* Set stack pointer */ + l.movhi r1,hi(_stack) + l.ori r1,r1,lo(_stack) + + /* Jump to main */ + l.movhi r2,hi(reset) + l.ori r2,r2,lo(reset) + l.jr r2 + l.nop + Index: assembly_new_toolchain/except.S =================================================================== --- assembly_new_toolchain/except.S (nonexistent) +++ assembly_new_toolchain/except.S (revision 42) @@ -0,0 +1,276 @@ +#include "spr_defs.h" + +// Linked from 0x200, so subtract 0x200 from each .org +.section .vectors, "ax" + +/* +.org 0x100 + +_reset: + l.nop + l.j _reset_except + l.nop +*/ +.org 0x000 + +_except_200: + l.nop + l.addi r1,r1,-116 //free 29 words of stack (stack is r1) + l.sw 0x18(r1),r9 //save register r9(return addr) to stack + l.jal store_regs //save registers r3-r31 (except r9) to stack (r9 is changed here) + l.nop + + l.movhi r9,hi(end_except) //set return addr to end_except instruction + l.ori r9,r9,lo(end_except) //set return addr to end_except instruction + l.j buserr_except + l.nop + +.org 0x100 + +_except_300: + l.nop + l.addi r1,r1,-116 //free 29 words of stack (stack is r1) + l.sw 0x18(r1),r9 //save register r9(return addr) to stack + l.jal store_regs //save registers r3-r31 (except r9) to stack (r9 is changed here) + l.nop + + l.movhi r9,hi(end_except) //set return addr to end_except instruction + l.ori r9,r9,lo(end_except) //set return addr to end_except instruction + l.j dpf_except + l.nop + +.org 0x200 + +_except_400: + l.nop + l.addi r1,r1,-116 //free 29 words of stack (stack is r1) + l.sw 0x18(r1),r9 //save register r9(return addr) to stack + l.jal store_regs //save registers r3-r31 (except r9) to stack (r9 is changed here) + l.nop + + l.movhi r9,hi(end_except) //set return addr to end_except instruction + l.ori r9,r9,lo(end_except) //set return addr to end_except instruction + l.j ipf_except + l.nop + +.org 0x300 + +_except_500: + l.nop + l.addi r1,r1,-116 //free 29 words of stack (stack is r1) + l.sw 0x18(r1),r9 //save register r9(return addr) to stack + l.jal store_regs //save registers r3-r31 (except r9) to stack (r9 is changed here) + l.nop + + l.movhi r9,hi(end_except) //set return addr to end_except instruction + l.ori r9,r9,lo(end_except) //set return addr to end_except instruction + l.j tick_except + l.nop + +.org 0x400 + +_except_600: + l.nop + l.addi r1,r1,-116 //free 29 words of stack (stack is r1) + l.sw 0x18(r1),r9 //save register r9(return addr) to stack + l.jal store_regs //save registers r3-r31 (except r9) to stack (r9 is changed here) + l.nop + + l.movhi r9,hi(end_except) //set return addr to end_except instruction + l.ori r9,r9,lo(end_except) //set return addr to end_except instruction + l.j align_except + l.nop + +.org 0x500 + +_except_700: + l.nop + l.addi r1,r1,-116 //free 29 words of stack (stack is r1) + l.sw 0x18(r1),r9 //save register r9(return addr) to stack + l.jal store_regs //save registers r3-r31 (except r9) to stack (r9 is changed here) + l.nop + + l.movhi r9,hi(end_except) //set return addr to end_except instruction + l.ori r9,r9,lo(end_except) //set return addr to end_except instruction + l.j illegal_except + l.nop + +.org 0x600 + +_except_800: + l.nop + l.addi r1,r1,-116 //free 29 words of stack (stack is r1) + l.sw 0x18(r1),r9 //save register r9(return addr) to stack + l.jal store_regs //save registers r3-r31 (except r9) to stack (r9 is changed here) + l.nop + + l.movhi r9,hi(end_except) //set return addr to end_except instruction + l.ori r9,r9,lo(end_except) //set return addr to end_except instruction + l.j ext_except //jmp to C interrupt handler (returns later to end_except) + l.nop + + +.org 0x700 + +_except_900: + l.nop + l.addi r1,r1,-116 //free 29 words of stack (stack is r1) + l.sw 0x18(r1),r9 //save register r9(return addr) to stack + l.jal store_regs //save registers r3-r31 (except r9) to stack (r9 is changed here) + l.nop + + l.movhi r9,hi(end_except) //set return addr to end_except instruction + l.ori r9,r9,lo(end_except) //set return addr to end_except instruction + l.j dtlbmiss_except + l.nop + +.org 0x800 + +_except_a00: + l.nop + l.addi r1,r1,-116 //free 29 words of stack (stack is r1) + l.sw 0x18(r1),r9 //save register r9(return addr) to stack + l.jal store_regs //save registers r3-r31 (except r9) to stack (r9 is changed here) + l.nop + + l.movhi r9,hi(end_except) //set return addr to end_except instruction + l.ori r9,r9,lo(end_except) //set return addr to end_except instruction + l.j itlbmiss_except + l.nop + +.org 0x900 + +_except_b00: + l.nop + l.addi r1,r1,-116 //free 29 words of stack (stack is r1) + l.sw 0x18(r1),r9 //save register r9(return addr) to stack + l.jal store_regs //save registers r3-r31 (except r9) to stack (r9 is changed here) + l.nop + + l.movhi r9,hi(end_except) //set return addr to end_except instruction + l.ori r9,r9,lo(end_except) //set return addr to end_except instruction + l.j range_except + l.nop + +.org 0xa00 + +_except_c00: + l.nop + l.addi r1,r1,-116 //free 29 words of stack (stack is r1) + l.sw 0x18(r1),r9 //save register r9(return addr) to stack + l.jal store_regs //save registers r3-r31 (except r9) to stack (r9 is changed here) + l.nop + + l.movhi r9,hi(end_except) //set return addr to end_except instruction + l.ori r9,r9,lo(end_except) //set return addr to end_except instruction + l.j syscall_except + l.nop + +.org 0xb00 + +_except_d00: + l.nop + l.addi r1,r1,-116 //free 29 words of stack (stack is r1) + l.sw 0x18(r1),r9 //save register r9(return addr) to stack + l.jal store_regs //save registers r3-r31 (except r9) to stack (r9 is changed here) + l.nop + + l.movhi r9,hi(end_except) //set return addr to end_except instruction + l.ori r9,r9,lo(end_except) //set return addr to end_except instruction + l.j res1_except + l.nop + +.org 0xc00 + +_except_e00: + l.nop + l.addi r1,r1,-116 //free 29 words of stack (stack is r1) + l.sw 0x18(r1),r9 //save register r9(return addr) to stack + l.jal store_regs //save registers r3-r31 (except r9) to stack (r9 is changed here) + l.nop + + l.movhi r9,hi(end_except) //set return addr to end_except instruction + l.ori r9,r9,lo(end_except) //set return addr to end_except instruction + l.j trap_except + l.nop + +.org 0xd00 + +_except_f00: + l.nop + l.addi r1,r1,-116 //free 29 words of stack (stack is r1) + l.sw 0x18(r1),r9 //save register r9(return addr) to stack + l.jal store_regs //save registers r3-r31 (except r9) to stack (r9 is changed here) + l.nop + + l.movhi r9,hi(end_except) //set return addr to end_except instruction + l.ori r9,r9,lo(end_except) //set return addr to end_except instruction + l.j res2_except + l.nop + +store_regs: //save registers r3-r31 (except r9) to stack + l.sw 0x00(r1),r3 + l.sw 0x04(r1),r4 + l.sw 0x08(r1),r5 + l.sw 0x0c(r1),r6 + l.sw 0x10(r1),r7 + l.sw 0x14(r1),r8 + l.sw 0x1c(r1),r10 + l.sw 0x20(r1),r11 + l.sw 0x24(r1),r12 + l.sw 0x28(r1),r13 + l.sw 0x2c(r1),r14 + l.sw 0x30(r1),r15 + l.sw 0x34(r1),r16 + l.sw 0x38(r1),r17 + l.sw 0x3c(r1),r18 + l.sw 0x40(r1),r19 + l.sw 0x44(r1),r20 + l.sw 0x48(r1),r21 + l.sw 0x4c(r1),r22 + l.sw 0x50(r1),r23 + l.sw 0x54(r1),r24 + l.sw 0x58(r1),r25 + l.sw 0x5c(r1),r26 + l.sw 0x60(r1),r27 + l.sw 0x64(r1),r28 + l.sw 0x68(r1),r29 + l.sw 0x6c(r1),r30 + l.sw 0x70(r1),r31 + l.jr r9 + l.nop + +end_except: //load back registers from stack r3-r31 + l.lwz r3,0x00(r1) + l.lwz r4,0x04(r1) + l.lwz r5,0x08(r1) + l.lwz r6,0x0c(r1) + l.lwz r7,0x10(r1) + l.lwz r8,0x14(r1) + l.lwz r9,0x18(r1) + l.lwz r10,0x1c(r1) + l.lwz r11,0x20(r1) + l.lwz r12,0x24(r1) + l.lwz r13,0x28(r1) + l.lwz r14,0x2c(r1) + l.lwz r15,0x30(r1) + l.lwz r16,0x34(r1) + l.lwz r17,0x38(r1) + l.lwz r18,0x3c(r1) + l.lwz r19,0x40(r1) + l.lwz r20,0x44(r1) + l.lwz r21,0x48(r1) + l.lwz r22,0x4c(r1) + l.lwz r23,0x50(r1) + l.lwz r24,0x54(r1) + l.lwz r25,0x58(r1) + l.lwz r26,0x5c(r1) + l.lwz r27,0x60(r1) + l.lwz r28,0x64(r1) + l.lwz r29,0x68(r1) + l.lwz r30,0x6c(r1) + l.lwz r31,0x70(r1) + l.addi r1,r1,116 //free stack places + l.rfe //recover SR register and prior PC (jumps back to program) + l.nop + Index: minsoc_tc_top_B3.v =================================================================== --- minsoc_tc_top_B3.v (nonexistent) +++ minsoc_tc_top_B3.v (revision 42) @@ -0,0 +1,1883 @@ +////////////////////////////////////////////////////////////////////// +//// //// +//// Xess Traffic Cop //// +//// //// +//// This file is part of the OR1K test application //// +//// http://www.opencores.org/cores/or1k/ //// +//// //// +//// Description //// +//// This block connectes the RISC and peripheral controller //// +//// cores together. //// +//// //// +//// To Do: //// +//// - nothing really //// +//// //// +//// Author(s): //// +//// - Damjan Lampret, lampret@opencores.org //// +//// //// +////////////////////////////////////////////////////////////////////// +//// //// +//// Copyright (C) 2002 OpenCores //// +//// //// +//// This source file may be used and distributed without //// +//// restriction provided that this copyright statement is not //// +//// removed from the file and that any derivative work contains //// +//// the original copyright notice and the associated disclaimer. //// +//// //// +//// This source file is free software; you can redistribute it //// +//// and/or modify it under the terms of the GNU Lesser General //// +//// Public License as published by the Free Software Foundation; //// +//// either version 2.1 of the License, or (at your option) any //// +//// later version. //// +//// //// +//// This source is distributed in the hope that it will be //// +//// useful, but WITHOUT ANY WARRANTY; without even the implied //// +//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR //// +//// PURPOSE. See the GNU Lesser General Public License for more //// +//// details. //// +//// //// +//// You should have received a copy of the GNU Lesser General //// +//// Public License along with this source; if not, download it //// +//// from http://www.opencores.org/lgpl.shtml //// +//// //// +////////////////////////////////////////////////////////////////////// +// +// CVS Revision History +// +// $Log: tc_top.v,v $ +// Revision 1.4 2004/04/05 08:44:34 lampret +// Merged branch_qmem into main tree. +// +// Revision 1.2 2002/03/29 20:57:30 lampret +// Removed unused ports wb_clki and wb_rst_i +// +// Revision 1.1.1.1 2002/03/21 16:55:44 lampret +// First import of the "new" XESS XSV environment. +// +// +// + +// synopsys translate_off +`include "timescale.v" +// synopsys translate_on + +// +// Width of address bus +// +`define TC_AW 32 + +// +// Width of data bus +// +`define TC_DW 32 + +// +// Width of byte select bus +// +`define TC_BSW 4 + +// +// Width of WB target inputs (coming from WB slave) +// +// data bus width + ack + err +// +`define TC_TIN_W `TC_DW+1+1 + +// +// Width of WB initiator inputs (coming from WB masters) +// +// cyc + stb + address bus width + +// byte select bus width + we + data bus width +// +`define TC_IIN_W 1+1+1+`TC_AW+`TC_BSW+1+`TC_DW + +// +// Traffic Cop Top +// +module minsoc_tc_top ( + wb_clk_i, + wb_rst_i, + + i0_wb_cyc_i, + i0_wb_stb_i, + i0_wb_adr_i, + i0_wb_sel_i, + i0_wb_we_i, + i0_wb_dat_i, + i0_wb_dat_o, + i0_wb_ack_o, + i0_wb_err_o, + i0_wb_cti_i, + i0_wb_bte_i, + + i1_wb_cyc_i, + i1_wb_stb_i, + i1_wb_adr_i, + i1_wb_sel_i, + i1_wb_we_i, + i1_wb_dat_i, + i1_wb_dat_o, + i1_wb_ack_o, + i1_wb_err_o, + i1_wb_cti_i, + i1_wb_bte_i, + + i2_wb_cyc_i, + i2_wb_stb_i, + i2_wb_adr_i, + i2_wb_sel_i, + i2_wb_we_i, + i2_wb_dat_i, + i2_wb_dat_o, + i2_wb_ack_o, + i2_wb_err_o, + i2_wb_cti_i, + i2_wb_bte_i, + + i3_wb_cyc_i, + i3_wb_stb_i, + i3_wb_adr_i, + i3_wb_sel_i, + i3_wb_we_i, + i3_wb_dat_i, + i3_wb_dat_o, + i3_wb_ack_o, + i3_wb_err_o, + i3_wb_cti_i, + i3_wb_bte_i, + + i4_wb_cyc_i, + i4_wb_stb_i, + i4_wb_adr_i, + i4_wb_sel_i, + i4_wb_we_i, + i4_wb_dat_i, + i4_wb_dat_o, + i4_wb_ack_o, + i4_wb_err_o, + i4_wb_cti_i, + i4_wb_bte_i, + + i5_wb_cyc_i, + i5_wb_stb_i, + i5_wb_adr_i, + i5_wb_sel_i, + i5_wb_we_i, + i5_wb_dat_i, + i5_wb_dat_o, + i5_wb_ack_o, + i5_wb_err_o, + i5_wb_cti_i, + i5_wb_bte_i, + + i6_wb_cyc_i, + i6_wb_stb_i, + i6_wb_adr_i, + i6_wb_sel_i, + i6_wb_we_i, + i6_wb_dat_i, + i6_wb_dat_o, + i6_wb_ack_o, + i6_wb_err_o, + i6_wb_cti_i, + i6_wb_bte_i, + + i7_wb_cyc_i, + i7_wb_stb_i, + i7_wb_adr_i, + i7_wb_sel_i, + i7_wb_we_i, + i7_wb_dat_i, + i7_wb_dat_o, + i7_wb_ack_o, + i7_wb_err_o, + i7_wb_cti_i, + i7_wb_bte_i, + + t0_wb_cyc_o, + t0_wb_stb_o, + t0_wb_adr_o, + t0_wb_sel_o, + t0_wb_we_o, + t0_wb_dat_o, + t0_wb_dat_i, + t0_wb_ack_i, + t0_wb_err_i, + t0_wb_cti_o, + t0_wb_bte_o, + + t1_wb_cyc_o, + t1_wb_stb_o, + t1_wb_adr_o, + t1_wb_sel_o, + t1_wb_we_o, + t1_wb_dat_o, + t1_wb_dat_i, + t1_wb_ack_i, + t1_wb_err_i, + t1_wb_cti_o, + t1_wb_bte_o, + + t2_wb_cyc_o, + t2_wb_stb_o, + t2_wb_adr_o, + t2_wb_sel_o, + t2_wb_we_o, + t2_wb_dat_o, + t2_wb_dat_i, + t2_wb_ack_i, + t2_wb_err_i, + t2_wb_cti_o, + t2_wb_bte_o, + + t3_wb_cyc_o, + t3_wb_stb_o, + t3_wb_adr_o, + t3_wb_sel_o, + t3_wb_we_o, + t3_wb_dat_o, + t3_wb_dat_i, + t3_wb_ack_i, + t3_wb_err_i, + t3_wb_cti_o, + t3_wb_bte_o, + + t4_wb_cyc_o, + t4_wb_stb_o, + t4_wb_adr_o, + t4_wb_sel_o, + t4_wb_we_o, + t4_wb_dat_o, + t4_wb_dat_i, + t4_wb_ack_i, + t4_wb_err_i, + t4_wb_cti_o, + t4_wb_bte_o, + + t5_wb_cyc_o, + t5_wb_stb_o, + t5_wb_adr_o, + t5_wb_sel_o, + t5_wb_we_o, + t5_wb_dat_o, + t5_wb_dat_i, + t5_wb_ack_i, + t5_wb_err_i, + t5_wb_cti_o, + t5_wb_bte_o, + + t6_wb_cyc_o, + t6_wb_stb_o, + t6_wb_adr_o, + t6_wb_sel_o, + t6_wb_we_o, + t6_wb_dat_o, + t6_wb_dat_i, + t6_wb_ack_i, + t6_wb_err_i, + t6_wb_cti_o, + t6_wb_bte_o, + + t7_wb_cyc_o, + t7_wb_stb_o, + t7_wb_adr_o, + t7_wb_sel_o, + t7_wb_we_o, + t7_wb_dat_o, + t7_wb_dat_i, + t7_wb_ack_i, + t7_wb_err_i, + t7_wb_cti_o, + t7_wb_bte_o, + + t8_wb_cyc_o, + t8_wb_stb_o, + t8_wb_adr_o, + t8_wb_sel_o, + t8_wb_we_o, + t8_wb_dat_o, + t8_wb_dat_i, + t8_wb_ack_i, + t8_wb_err_i, + t8_wb_cti_o, + t8_wb_bte_o + + +); + +// +// Parameters +// +parameter t0_addr_w = 4; +parameter t0_addr = 4'd8; +parameter t1_addr_w = 4; +parameter t1_addr = 4'd0; +parameter t28c_addr_w = 4; +parameter t28_addr = 4'd0; +parameter t28i_addr_w = 4; +parameter t2_addr = 4'd1; +parameter t3_addr = 4'd2; +parameter t4_addr = 4'd3; +parameter t5_addr = 4'd4; +parameter t6_addr = 4'd5; +parameter t7_addr = 4'd6; +parameter t8_addr = 4'd7; + +// +// I/O Ports +// +input wb_clk_i; +input wb_rst_i; +// +// WB slave i/f connecting initiator 0 +// +input i0_wb_cyc_i; +input i0_wb_stb_i; +input [`TC_AW-1:0] i0_wb_adr_i; +input [`TC_BSW-1:0] i0_wb_sel_i; +input i0_wb_we_i; +input [`TC_DW-1:0] i0_wb_dat_i; +output [`TC_DW-1:0] i0_wb_dat_o; +output i0_wb_ack_o; +output i0_wb_err_o; +input [2:0] i0_wb_cti_i; +input [1:0] i0_wb_bte_i; + +// +// WB slave i/f connecting initiator 1 +// +input i1_wb_cyc_i; +input i1_wb_stb_i; +input [`TC_AW-1:0] i1_wb_adr_i; +input [`TC_BSW-1:0] i1_wb_sel_i; +input i1_wb_we_i; +input [`TC_DW-1:0] i1_wb_dat_i; +output [`TC_DW-1:0] i1_wb_dat_o; +output i1_wb_ack_o; +output i1_wb_err_o; +input [2:0] i1_wb_cti_i; +input [1:0] i1_wb_bte_i; + +// +// WB slave i/f connecting initiator 2 +// +input i2_wb_cyc_i; +input i2_wb_stb_i; +input [`TC_AW-1:0] i2_wb_adr_i; +input [`TC_BSW-1:0] i2_wb_sel_i; +input i2_wb_we_i; +input [`TC_DW-1:0] i2_wb_dat_i; +output [`TC_DW-1:0] i2_wb_dat_o; +output i2_wb_ack_o; +output i2_wb_err_o; +input [2:0] i2_wb_cti_i; +input [1:0] i2_wb_bte_i; + +// +// WB slave i/f connecting initiator 3 +// +input i3_wb_cyc_i; +input i3_wb_stb_i; +input [`TC_AW-1:0] i3_wb_adr_i; +input [`TC_BSW-1:0] i3_wb_sel_i; +input i3_wb_we_i; +input [`TC_DW-1:0] i3_wb_dat_i; +output [`TC_DW-1:0] i3_wb_dat_o; +output i3_wb_ack_o; +output i3_wb_err_o; +input [2:0] i3_wb_cti_i; +input [1:0] i3_wb_bte_i; + +// +// WB slave i/f connecting initiator 4 +// +input i4_wb_cyc_i; +input i4_wb_stb_i; +input [`TC_AW-1:0] i4_wb_adr_i; +input [`TC_BSW-1:0] i4_wb_sel_i; +input i4_wb_we_i; +input [`TC_DW-1:0] i4_wb_dat_i; +output [`TC_DW-1:0] i4_wb_dat_o; +output i4_wb_ack_o; +output i4_wb_err_o; +input [2:0] i4_wb_cti_i; +input [1:0] i4_wb_bte_i; + +// +// WB slave i/f connecting initiator 5 +// +input i5_wb_cyc_i; +input i5_wb_stb_i; +input [`TC_AW-1:0] i5_wb_adr_i; +input [`TC_BSW-1:0] i5_wb_sel_i; +input i5_wb_we_i; +input [`TC_DW-1:0] i5_wb_dat_i; +output [`TC_DW-1:0] i5_wb_dat_o; +output i5_wb_ack_o; +output i5_wb_err_o; +input [2:0] i5_wb_cti_i; +input [1:0] i5_wb_bte_i; + +// +// WB slave i/f connecting initiator 6 +// +input i6_wb_cyc_i; +input i6_wb_stb_i; +input [`TC_AW-1:0] i6_wb_adr_i; +input [`TC_BSW-1:0] i6_wb_sel_i; +input i6_wb_we_i; +input [`TC_DW-1:0] i6_wb_dat_i; +output [`TC_DW-1:0] i6_wb_dat_o; +output i6_wb_ack_o; +output i6_wb_err_o; +input [2:0] i6_wb_cti_i; +input [1:0] i6_wb_bte_i; + +// +// WB slave i/f connecting initiator 7 +// +input i7_wb_cyc_i; +input i7_wb_stb_i; +input [`TC_AW-1:0] i7_wb_adr_i; +input [`TC_BSW-1:0] i7_wb_sel_i; +input i7_wb_we_i; +input [`TC_DW-1:0] i7_wb_dat_i; +output [`TC_DW-1:0] i7_wb_dat_o; +output i7_wb_ack_o; +output i7_wb_err_o; +input [2:0] i7_wb_cti_i; +input [1:0] i7_wb_bte_i; + +// +// WB master i/f connecting target 0 +// +output t0_wb_cyc_o; +output t0_wb_stb_o; +output [`TC_AW-1:0] t0_wb_adr_o; +output [`TC_BSW-1:0] t0_wb_sel_o; +output t0_wb_we_o; +output [`TC_DW-1:0] t0_wb_dat_o; +input [`TC_DW-1:0] t0_wb_dat_i; +input t0_wb_ack_i; +input t0_wb_err_i; +output [2:0] t0_wb_cti_o; +output [1:0] t0_wb_bte_o; + +// +// WB master i/f connecting target 1 +// +output t1_wb_cyc_o; +output t1_wb_stb_o; +output [`TC_AW-1:0] t1_wb_adr_o; +output [`TC_BSW-1:0] t1_wb_sel_o; +output t1_wb_we_o; +output [`TC_DW-1:0] t1_wb_dat_o; +input [`TC_DW-1:0] t1_wb_dat_i; +input t1_wb_ack_i; +input t1_wb_err_i; +output [2:0] t1_wb_cti_o; +output [1:0] t1_wb_bte_o; + +// +// WB master i/f connecting target 2 +// +output t2_wb_cyc_o; +output t2_wb_stb_o; +output [`TC_AW-1:0] t2_wb_adr_o; +output [`TC_BSW-1:0] t2_wb_sel_o; +output t2_wb_we_o; +output [`TC_DW-1:0] t2_wb_dat_o; +input [`TC_DW-1:0] t2_wb_dat_i; +input t2_wb_ack_i; +input t2_wb_err_i; +output [2:0] t2_wb_cti_o; +output [1:0] t2_wb_bte_o; + +// +// WB master i/f connecting target 3 +// +output t3_wb_cyc_o; +output t3_wb_stb_o; +output [`TC_AW-1:0] t3_wb_adr_o; +output [`TC_BSW-1:0] t3_wb_sel_o; +output t3_wb_we_o; +output [`TC_DW-1:0] t3_wb_dat_o; +input [`TC_DW-1:0] t3_wb_dat_i; +input t3_wb_ack_i; +input t3_wb_err_i; +output [2:0] t3_wb_cti_o; +output [1:0] t3_wb_bte_o; + +// +// WB master i/f connecting target 4 +// +output t4_wb_cyc_o; +output t4_wb_stb_o; +output [`TC_AW-1:0] t4_wb_adr_o; +output [`TC_BSW-1:0] t4_wb_sel_o; +output t4_wb_we_o; +output [`TC_DW-1:0] t4_wb_dat_o; +input [`TC_DW-1:0] t4_wb_dat_i; +input t4_wb_ack_i; +input t4_wb_err_i; +output [2:0] t4_wb_cti_o; +output [1:0] t4_wb_bte_o; + +// +// WB master i/f connecting target 5 +// +output t5_wb_cyc_o; +output t5_wb_stb_o; +output [`TC_AW-1:0] t5_wb_adr_o; +output [`TC_BSW-1:0] t5_wb_sel_o; +output t5_wb_we_o; +output [`TC_DW-1:0] t5_wb_dat_o; +input [`TC_DW-1:0] t5_wb_dat_i; +input t5_wb_ack_i; +input t5_wb_err_i; +output [2:0] t5_wb_cti_o; +output [1:0] t5_wb_bte_o; + +// +// WB master i/f connecting target 6 +// +output t6_wb_cyc_o; +output t6_wb_stb_o; +output [`TC_AW-1:0] t6_wb_adr_o; +output [`TC_BSW-1:0] t6_wb_sel_o; +output t6_wb_we_o; +output [`TC_DW-1:0] t6_wb_dat_o; +input [`TC_DW-1:0] t6_wb_dat_i; +input t6_wb_ack_i; +input t6_wb_err_i; +output [2:0] t6_wb_cti_o; +output [1:0] t6_wb_bte_o; + +// +// WB master i/f connecting target 7 +// +output t7_wb_cyc_o; +output t7_wb_stb_o; +output [`TC_AW-1:0] t7_wb_adr_o; +output [`TC_BSW-1:0] t7_wb_sel_o; +output t7_wb_we_o; +output [`TC_DW-1:0] t7_wb_dat_o; +input [`TC_DW-1:0] t7_wb_dat_i; +input t7_wb_ack_i; +input t7_wb_err_i; +output [2:0] t7_wb_cti_o; +output [1:0] t7_wb_bte_o; + +// +// WB master i/f connecting target 8 +// +output t8_wb_cyc_o; +output t8_wb_stb_o; +output [`TC_AW-1:0] t8_wb_adr_o; +output [`TC_BSW-1:0] t8_wb_sel_o; +output t8_wb_we_o; +output [`TC_DW-1:0] t8_wb_dat_o; +input [`TC_DW-1:0] t8_wb_dat_i; +input t8_wb_ack_i; +input t8_wb_err_i; +output [2:0] t8_wb_cti_o; +output [1:0] t8_wb_bte_o; + + +// +// Internal wires & registers +// + +// +// Outputs for initiators from both mi_to_st blocks +// +wire [`TC_DW-1:0] xi0_wb_dat_o; +wire xi0_wb_ack_o; +wire xi0_wb_err_o; +wire [`TC_DW-1:0] xi1_wb_dat_o; +wire xi1_wb_ack_o; +wire xi1_wb_err_o; +wire [`TC_DW-1:0] xi2_wb_dat_o; +wire xi2_wb_ack_o; +wire xi2_wb_err_o; +wire [`TC_DW-1:0] xi3_wb_dat_o; +wire xi3_wb_ack_o; +wire xi3_wb_err_o; +wire [`TC_DW-1:0] xi4_wb_dat_o; +wire xi4_wb_ack_o; +wire xi4_wb_err_o; +wire [`TC_DW-1:0] xi5_wb_dat_o; +wire xi5_wb_ack_o; +wire xi5_wb_err_o; +wire [`TC_DW-1:0] xi6_wb_dat_o; +wire xi6_wb_ack_o; +wire xi6_wb_err_o; +wire [`TC_DW-1:0] xi7_wb_dat_o; +wire xi7_wb_ack_o; +wire xi7_wb_err_o; +wire [`TC_DW-1:0] yi0_wb_dat_o; +wire yi0_wb_ack_o; +wire yi0_wb_err_o; +wire [`TC_DW-1:0] yi1_wb_dat_o; +wire yi1_wb_ack_o; +wire yi1_wb_err_o; +wire [`TC_DW-1:0] yi2_wb_dat_o; +wire yi2_wb_ack_o; +wire yi2_wb_err_o; +wire [`TC_DW-1:0] yi3_wb_dat_o; +wire yi3_wb_ack_o; +wire yi3_wb_err_o; +wire [`TC_DW-1:0] yi4_wb_dat_o; +wire yi4_wb_ack_o; +wire yi4_wb_err_o; +wire [`TC_DW-1:0] yi5_wb_dat_o; +wire yi5_wb_ack_o; +wire yi5_wb_err_o; +wire [`TC_DW-1:0] yi6_wb_dat_o; +wire yi6_wb_ack_o; +wire yi6_wb_err_o; +wire [`TC_DW-1:0] yi7_wb_dat_o; +wire yi7_wb_ack_o; +wire yi7_wb_err_o; + +// +// Intermediate signals connecting peripheral channel's +// mi_to_st and si_to_mt blocks. +// +wire z_wb_cyc_i; +wire z_wb_stb_i; +wire [`TC_AW-1:0] z_wb_adr_i; +wire [`TC_BSW-1:0] z_wb_sel_i; +wire z_wb_we_i; +wire [`TC_DW-1:0] z_wb_dat_i; +wire [`TC_DW-1:0] z_wb_dat_t; +wire z_wb_ack_t; +wire z_wb_err_t; +wire [2:0] z_wb_cti_i; +wire [1:0] z_wb_bte_i; + +// +// Outputs for initiators are ORed from both mi_to_st blocks +// +assign i0_wb_dat_o = xi0_wb_dat_o | yi0_wb_dat_o; +assign i0_wb_ack_o = xi0_wb_ack_o | yi0_wb_ack_o; +assign i0_wb_err_o = xi0_wb_err_o | yi0_wb_err_o; +assign i1_wb_dat_o = xi1_wb_dat_o | yi1_wb_dat_o; +assign i1_wb_ack_o = xi1_wb_ack_o | yi1_wb_ack_o; +assign i1_wb_err_o = xi1_wb_err_o | yi1_wb_err_o; +assign i2_wb_dat_o = xi2_wb_dat_o | yi2_wb_dat_o; +assign i2_wb_ack_o = xi2_wb_ack_o | yi2_wb_ack_o; +assign i2_wb_err_o = xi2_wb_err_o | yi2_wb_err_o; +assign i3_wb_dat_o = xi3_wb_dat_o | yi3_wb_dat_o; +assign i3_wb_ack_o = xi3_wb_ack_o | yi3_wb_ack_o; +assign i3_wb_err_o = xi3_wb_err_o | yi3_wb_err_o; +assign i4_wb_dat_o = xi4_wb_dat_o | yi4_wb_dat_o; +assign i4_wb_ack_o = xi4_wb_ack_o | yi4_wb_ack_o; +assign i4_wb_err_o = xi4_wb_err_o | yi4_wb_err_o; +assign i5_wb_dat_o = xi5_wb_dat_o | yi5_wb_dat_o; +assign i5_wb_ack_o = xi5_wb_ack_o | yi5_wb_ack_o; +assign i5_wb_err_o = xi5_wb_err_o | yi5_wb_err_o; +assign i6_wb_dat_o = xi6_wb_dat_o | yi6_wb_dat_o; +assign i6_wb_ack_o = xi6_wb_ack_o | yi6_wb_ack_o; +assign i6_wb_err_o = xi6_wb_err_o | yi6_wb_err_o; +assign i7_wb_dat_o = xi7_wb_dat_o | yi7_wb_dat_o; +assign i7_wb_ack_o = xi7_wb_ack_o | yi7_wb_ack_o; +assign i7_wb_err_o = xi7_wb_err_o | yi7_wb_err_o; + +// +// From initiators to target 0 +// +tc_mi_to_st #(t0_addr_w, t0_addr, + 0, t0_addr_w, t0_addr) t0_ch( + .wb_clk_i(wb_clk_i), + .wb_rst_i(wb_rst_i), + .i0_wb_cyc_i(i0_wb_cyc_i), + .i0_wb_stb_i(i0_wb_stb_i), + .i0_wb_adr_i(i0_wb_adr_i), + .i0_wb_sel_i(i0_wb_sel_i), + .i0_wb_we_i(i0_wb_we_i), + .i0_wb_dat_i(i0_wb_dat_i), + .i0_wb_dat_o(xi0_wb_dat_o), + .i0_wb_ack_o(xi0_wb_ack_o), + .i0_wb_err_o(xi0_wb_err_o), + .i0_wb_cti_i(i0_wb_cti_i), + .i0_wb_bte_i(i0_wb_bte_i), + + .i1_wb_cyc_i(i1_wb_cyc_i), + .i1_wb_stb_i(i1_wb_stb_i), + .i1_wb_adr_i(i1_wb_adr_i), + .i1_wb_sel_i(i1_wb_sel_i), + .i1_wb_we_i(i1_wb_we_i), + .i1_wb_dat_i(i1_wb_dat_i), + .i1_wb_dat_o(xi1_wb_dat_o), + .i1_wb_ack_o(xi1_wb_ack_o), + .i1_wb_err_o(xi1_wb_err_o), + .i1_wb_cti_i(i1_wb_cti_i), + .i1_wb_bte_i(i1_wb_bte_i), + + .i2_wb_cyc_i(i2_wb_cyc_i), + .i2_wb_stb_i(i2_wb_stb_i), + .i2_wb_adr_i(i2_wb_adr_i), + .i2_wb_sel_i(i2_wb_sel_i), + .i2_wb_we_i(i2_wb_we_i), + .i2_wb_dat_i(i2_wb_dat_i), + .i2_wb_dat_o(xi2_wb_dat_o), + .i2_wb_ack_o(xi2_wb_ack_o), + .i2_wb_err_o(xi2_wb_err_o), + .i2_wb_cti_i(i2_wb_cti_i), + .i2_wb_bte_i(i2_wb_bte_i), + + .i3_wb_cyc_i(i3_wb_cyc_i), + .i3_wb_stb_i(i3_wb_stb_i), + .i3_wb_adr_i(i3_wb_adr_i), + .i3_wb_sel_i(i3_wb_sel_i), + .i3_wb_we_i(i3_wb_we_i), + .i3_wb_dat_i(i3_wb_dat_i), + .i3_wb_dat_o(xi3_wb_dat_o), + .i3_wb_ack_o(xi3_wb_ack_o), + .i3_wb_err_o(xi3_wb_err_o), + .i3_wb_cti_i(i3_wb_cti_i), + .i3_wb_bte_i(i3_wb_bte_i), + + .i4_wb_cyc_i(i4_wb_cyc_i), + .i4_wb_stb_i(i4_wb_stb_i), + .i4_wb_adr_i(i4_wb_adr_i), + .i4_wb_sel_i(i4_wb_sel_i), + .i4_wb_we_i(i4_wb_we_i), + .i4_wb_dat_i(i4_wb_dat_i), + .i4_wb_dat_o(xi4_wb_dat_o), + .i4_wb_ack_o(xi4_wb_ack_o), + .i4_wb_err_o(xi4_wb_err_o), + .i4_wb_cti_i(i4_wb_cti_i), + .i4_wb_bte_i(i4_wb_bte_i), + + .i5_wb_cyc_i(i5_wb_cyc_i), + .i5_wb_stb_i(i5_wb_stb_i), + .i5_wb_adr_i(i5_wb_adr_i), + .i5_wb_sel_i(i5_wb_sel_i), + .i5_wb_we_i(i5_wb_we_i), + .i5_wb_dat_i(i5_wb_dat_i), + .i5_wb_dat_o(xi5_wb_dat_o), + .i5_wb_ack_o(xi5_wb_ack_o), + .i5_wb_err_o(xi5_wb_err_o), + .i5_wb_cti_i(i5_wb_cti_i), + .i5_wb_bte_i(i5_wb_bte_i), + + .i6_wb_cyc_i(i6_wb_cyc_i), + .i6_wb_stb_i(i6_wb_stb_i), + .i6_wb_adr_i(i6_wb_adr_i), + .i6_wb_sel_i(i6_wb_sel_i), + .i6_wb_we_i(i6_wb_we_i), + .i6_wb_dat_i(i6_wb_dat_i), + .i6_wb_dat_o(xi6_wb_dat_o), + .i6_wb_ack_o(xi6_wb_ack_o), + .i6_wb_err_o(xi6_wb_err_o), + .i6_wb_cti_i(i6_wb_cti_i), + .i6_wb_bte_i(i6_wb_bte_i), + + .i7_wb_cyc_i(i7_wb_cyc_i), + .i7_wb_stb_i(i7_wb_stb_i), + .i7_wb_adr_i(i7_wb_adr_i), + .i7_wb_sel_i(i7_wb_sel_i), + .i7_wb_we_i(i7_wb_we_i), + .i7_wb_dat_i(i7_wb_dat_i), + .i7_wb_dat_o(xi7_wb_dat_o), + .i7_wb_ack_o(xi7_wb_ack_o), + .i7_wb_err_o(xi7_wb_err_o), + .i7_wb_cti_i(i7_wb_cti_i), + .i7_wb_bte_i(i7_wb_bte_i), + + + .t0_wb_cyc_o(t0_wb_cyc_o), + .t0_wb_stb_o(t0_wb_stb_o), + .t0_wb_adr_o(t0_wb_adr_o), + .t0_wb_sel_o(t0_wb_sel_o), + .t0_wb_we_o(t0_wb_we_o), + .t0_wb_dat_o(t0_wb_dat_o), + .t0_wb_dat_i(t0_wb_dat_i), + .t0_wb_ack_i(t0_wb_ack_i), + .t0_wb_err_i(t0_wb_err_i), + .t0_wb_cti_o(t0_wb_cti_o), + .t0_wb_bte_o(t0_wb_bte_o) + +); + +// +// From initiators to targets 1-8 (upper part) +// +tc_mi_to_st #(t1_addr_w, t1_addr, + 1, t28c_addr_w, t28_addr) t18_ch_upper( + .wb_clk_i(wb_clk_i), + .wb_rst_i(wb_rst_i), + .i0_wb_cyc_i(i0_wb_cyc_i), + .i0_wb_stb_i(i0_wb_stb_i), + .i0_wb_adr_i(i0_wb_adr_i), + .i0_wb_sel_i(i0_wb_sel_i), + .i0_wb_we_i(i0_wb_we_i), + .i0_wb_dat_i(i0_wb_dat_i), + .i0_wb_dat_o(yi0_wb_dat_o), + .i0_wb_ack_o(yi0_wb_ack_o), + .i0_wb_err_o(yi0_wb_err_o), + .i0_wb_cti_i(i0_wb_cti_i), + .i0_wb_bte_i(i0_wb_bte_i), + + .i1_wb_cyc_i(i1_wb_cyc_i), + .i1_wb_stb_i(i1_wb_stb_i), + .i1_wb_adr_i(i1_wb_adr_i), + .i1_wb_sel_i(i1_wb_sel_i), + .i1_wb_we_i(i1_wb_we_i), + .i1_wb_dat_i(i1_wb_dat_i), + .i1_wb_dat_o(yi1_wb_dat_o), + .i1_wb_ack_o(yi1_wb_ack_o), + .i1_wb_err_o(yi1_wb_err_o), + .i1_wb_cti_i(i1_wb_cti_i), + .i1_wb_bte_i(i1_wb_bte_i), + + .i2_wb_cyc_i(i2_wb_cyc_i), + .i2_wb_stb_i(i2_wb_stb_i), + .i2_wb_adr_i(i2_wb_adr_i), + .i2_wb_sel_i(i2_wb_sel_i), + .i2_wb_we_i(i2_wb_we_i), + .i2_wb_dat_i(i2_wb_dat_i), + .i2_wb_dat_o(yi2_wb_dat_o), + .i2_wb_ack_o(yi2_wb_ack_o), + .i2_wb_err_o(yi2_wb_err_o), + .i2_wb_cti_i(i2_wb_cti_i), + .i2_wb_bte_i(i2_wb_bte_i), + + .i3_wb_cyc_i(i3_wb_cyc_i), + .i3_wb_stb_i(i3_wb_stb_i), + .i3_wb_adr_i(i3_wb_adr_i), + .i3_wb_sel_i(i3_wb_sel_i), + .i3_wb_we_i(i3_wb_we_i), + .i3_wb_dat_i(i3_wb_dat_i), + .i3_wb_dat_o(yi3_wb_dat_o), + .i3_wb_ack_o(yi3_wb_ack_o), + .i3_wb_err_o(yi3_wb_err_o), + .i3_wb_cti_i(i3_wb_cti_i), + .i3_wb_bte_i(i3_wb_bte_i), + + .i4_wb_cyc_i(i4_wb_cyc_i), + .i4_wb_stb_i(i4_wb_stb_i), + .i4_wb_adr_i(i4_wb_adr_i), + .i4_wb_sel_i(i4_wb_sel_i), + .i4_wb_we_i(i4_wb_we_i), + .i4_wb_dat_i(i4_wb_dat_i), + .i4_wb_dat_o(yi4_wb_dat_o), + .i4_wb_ack_o(yi4_wb_ack_o), + .i4_wb_err_o(yi4_wb_err_o), + .i4_wb_cti_i(i4_wb_cti_i), + .i4_wb_bte_i(i4_wb_bte_i), + + .i5_wb_cyc_i(i5_wb_cyc_i), + .i5_wb_stb_i(i5_wb_stb_i), + .i5_wb_adr_i(i5_wb_adr_i), + .i5_wb_sel_i(i5_wb_sel_i), + .i5_wb_we_i(i5_wb_we_i), + .i5_wb_dat_i(i5_wb_dat_i), + .i5_wb_dat_o(yi5_wb_dat_o), + .i5_wb_ack_o(yi5_wb_ack_o), + .i5_wb_err_o(yi5_wb_err_o), + .i5_wb_cti_i(i5_wb_cti_i), + .i5_wb_bte_i(i5_wb_bte_i), + + .i6_wb_cyc_i(i6_wb_cyc_i), + .i6_wb_stb_i(i6_wb_stb_i), + .i6_wb_adr_i(i6_wb_adr_i), + .i6_wb_sel_i(i6_wb_sel_i), + .i6_wb_we_i(i6_wb_we_i), + .i6_wb_dat_i(i6_wb_dat_i), + .i6_wb_dat_o(yi6_wb_dat_o), + .i6_wb_ack_o(yi6_wb_ack_o), + .i6_wb_err_o(yi6_wb_err_o), + .i6_wb_cti_i(i6_wb_cti_i), + .i6_wb_bte_i(i6_wb_bte_i), + + .i7_wb_cyc_i(i7_wb_cyc_i), + .i7_wb_stb_i(i7_wb_stb_i), + .i7_wb_adr_i(i7_wb_adr_i), + .i7_wb_sel_i(i7_wb_sel_i), + .i7_wb_we_i(i7_wb_we_i), + .i7_wb_dat_i(i7_wb_dat_i), + .i7_wb_dat_o(yi7_wb_dat_o), + .i7_wb_ack_o(yi7_wb_ack_o), + .i7_wb_err_o(yi7_wb_err_o), + .i7_wb_cti_i(i7_wb_cti_i), + .i7_wb_bte_i(i7_wb_bte_i), + + + .t0_wb_cyc_o(z_wb_cyc_i), + .t0_wb_stb_o(z_wb_stb_i), + .t0_wb_adr_o(z_wb_adr_i), + .t0_wb_sel_o(z_wb_sel_i), + .t0_wb_we_o(z_wb_we_i), + .t0_wb_dat_o(z_wb_dat_i), + .t0_wb_dat_i(z_wb_dat_t), + .t0_wb_ack_i(z_wb_ack_t), + .t0_wb_err_i(z_wb_err_t), + .t0_wb_cti_o(z_wb_cti_i), + .t0_wb_bte_o(z_wb_bte_i) + +); + +// +// From initiators to targets 1-8 (lower part) +// +tc_si_to_mt #(t1_addr_w, t1_addr, t28i_addr_w, t2_addr, t3_addr, + t4_addr, t5_addr, t6_addr, t7_addr, t8_addr) t18_ch_lower( + + + .i0_wb_cyc_i(z_wb_cyc_i), + .i0_wb_stb_i(z_wb_stb_i), + .i0_wb_adr_i(z_wb_adr_i), + .i0_wb_sel_i(z_wb_sel_i), + .i0_wb_we_i(z_wb_we_i), + .i0_wb_dat_i(z_wb_dat_i), + .i0_wb_dat_o(z_wb_dat_t), + .i0_wb_ack_o(z_wb_ack_t), + .i0_wb_err_o(z_wb_err_t), + .i0_wb_cti_i(z_wb_cti_i), + .i0_wb_bte_i(z_wb_bte_i), + + .t0_wb_cyc_o(t1_wb_cyc_o), + .t0_wb_stb_o(t1_wb_stb_o), + .t0_wb_adr_o(t1_wb_adr_o), + .t0_wb_sel_o(t1_wb_sel_o), + .t0_wb_we_o(t1_wb_we_o), + .t0_wb_dat_o(t1_wb_dat_o), + .t0_wb_dat_i(t1_wb_dat_i), + .t0_wb_ack_i(t1_wb_ack_i), + .t0_wb_err_i(t1_wb_err_i), + .t0_wb_cti_o(t1_wb_cti_o), + .t0_wb_bte_o(t1_wb_bte_o), + + .t1_wb_cyc_o(t2_wb_cyc_o), + .t1_wb_stb_o(t2_wb_stb_o), + .t1_wb_adr_o(t2_wb_adr_o), + .t1_wb_sel_o(t2_wb_sel_o), + .t1_wb_we_o(t2_wb_we_o), + .t1_wb_dat_o(t2_wb_dat_o), + .t1_wb_dat_i(t2_wb_dat_i), + .t1_wb_ack_i(t2_wb_ack_i), + .t1_wb_err_i(t2_wb_err_i), + .t1_wb_cti_o(t2_wb_cti_o), + .t1_wb_bte_o(t2_wb_bte_o), + + .t2_wb_cyc_o(t3_wb_cyc_o), + .t2_wb_stb_o(t3_wb_stb_o), + .t2_wb_adr_o(t3_wb_adr_o), + .t2_wb_sel_o(t3_wb_sel_o), + .t2_wb_we_o(t3_wb_we_o), + .t2_wb_dat_o(t3_wb_dat_o), + .t2_wb_dat_i(t3_wb_dat_i), + .t2_wb_ack_i(t3_wb_ack_i), + .t2_wb_err_i(t3_wb_err_i), + .t2_wb_cti_o(t3_wb_cti_o), + .t2_wb_bte_o(t3_wb_bte_o), + + .t3_wb_cyc_o(t4_wb_cyc_o), + .t3_wb_stb_o(t4_wb_stb_o), + .t3_wb_adr_o(t4_wb_adr_o), + .t3_wb_sel_o(t4_wb_sel_o), + .t3_wb_we_o(t4_wb_we_o), + .t3_wb_dat_o(t4_wb_dat_o), + .t3_wb_dat_i(t4_wb_dat_i), + .t3_wb_ack_i(t4_wb_ack_i), + .t3_wb_err_i(t4_wb_err_i), + .t3_wb_cti_o(t4_wb_cti_o), + .t3_wb_bte_o(t4_wb_bte_o), + + .t4_wb_cyc_o(t5_wb_cyc_o), + .t4_wb_stb_o(t5_wb_stb_o), + .t4_wb_adr_o(t5_wb_adr_o), + .t4_wb_sel_o(t5_wb_sel_o), + .t4_wb_we_o(t5_wb_we_o), + .t4_wb_dat_o(t5_wb_dat_o), + .t4_wb_dat_i(t5_wb_dat_i), + .t4_wb_ack_i(t5_wb_ack_i), + .t4_wb_err_i(t5_wb_err_i), + .t4_wb_cti_o(t5_wb_cti_o), + .t4_wb_bte_o(t5_wb_bte_o), + + .t5_wb_cyc_o(t6_wb_cyc_o), + .t5_wb_stb_o(t6_wb_stb_o), + .t5_wb_adr_o(t6_wb_adr_o), + .t5_wb_sel_o(t6_wb_sel_o), + .t5_wb_we_o(t6_wb_we_o), + .t5_wb_dat_o(t6_wb_dat_o), + .t5_wb_dat_i(t6_wb_dat_i), + .t5_wb_ack_i(t6_wb_ack_i), + .t5_wb_err_i(t6_wb_err_i), + .t5_wb_cti_o(t6_wb_cti_o), + .t5_wb_bte_o(t6_wb_bte_o), + + .t6_wb_cyc_o(t7_wb_cyc_o), + .t6_wb_stb_o(t7_wb_stb_o), + .t6_wb_adr_o(t7_wb_adr_o), + .t6_wb_sel_o(t7_wb_sel_o), + .t6_wb_we_o(t7_wb_we_o), + .t6_wb_dat_o(t7_wb_dat_o), + .t6_wb_dat_i(t7_wb_dat_i), + .t6_wb_ack_i(t7_wb_ack_i), + .t6_wb_err_i(t7_wb_err_i), + .t6_wb_cti_o(t7_wb_cti_o), + .t6_wb_bte_o(t7_wb_bte_o), + + .t7_wb_cyc_o(t8_wb_cyc_o), + .t7_wb_stb_o(t8_wb_stb_o), + .t7_wb_adr_o(t8_wb_adr_o), + .t7_wb_sel_o(t8_wb_sel_o), + .t7_wb_we_o(t8_wb_we_o), + .t7_wb_dat_o(t8_wb_dat_o), + .t7_wb_dat_i(t8_wb_dat_i), + .t7_wb_ack_i(t8_wb_ack_i), + .t7_wb_err_i(t8_wb_err_i), + .t7_wb_cti_o(t8_wb_cti_o), + .t7_wb_bte_o(t8_wb_bte_o), + + +); + +endmodule + +// +// Multiple initiator to single target +// +module tc_mi_to_st ( + wb_clk_i, + wb_rst_i, + i0_wb_cyc_i, + i0_wb_stb_i, + i0_wb_adr_i, + i0_wb_sel_i, + i0_wb_we_i, + i0_wb_dat_i, + i0_wb_dat_o, + i0_wb_ack_o, + i0_wb_err_o, + i0_wb_cti_i, + i0_wb_bte_i, + + i1_wb_cyc_i, + i1_wb_stb_i, + i1_wb_adr_i, + i1_wb_sel_i, + i1_wb_we_i, + i1_wb_dat_i, + i1_wb_dat_o, + i1_wb_ack_o, + i1_wb_err_o, + i1_wb_cti_i, + i1_wb_bte_i, + + i2_wb_cyc_i, + i2_wb_stb_i, + i2_wb_adr_i, + i2_wb_sel_i, + i2_wb_we_i, + i2_wb_dat_i, + i2_wb_dat_o, + i2_wb_ack_o, + i2_wb_err_o, + i2_wb_cti_i, + i2_wb_bte_i, + + i3_wb_cyc_i, + i3_wb_stb_i, + i3_wb_adr_i, + i3_wb_sel_i, + i3_wb_we_i, + i3_wb_dat_i, + i3_wb_dat_o, + i3_wb_ack_o, + i3_wb_err_o, + i3_wb_cti_i, + i3_wb_bte_i, + + i4_wb_cyc_i, + i4_wb_stb_i, + i4_wb_adr_i, + i4_wb_sel_i, + i4_wb_we_i, + i4_wb_dat_i, + i4_wb_dat_o, + i4_wb_ack_o, + i4_wb_err_o, + i4_wb_cti_i, + i4_wb_bte_i, + + i5_wb_cyc_i, + i5_wb_stb_i, + i5_wb_adr_i, + i5_wb_sel_i, + i5_wb_we_i, + i5_wb_dat_i, + i5_wb_dat_o, + i5_wb_ack_o, + i5_wb_err_o, + i5_wb_cti_i, + i5_wb_bte_i, + + i6_wb_cyc_i, + i6_wb_stb_i, + i6_wb_adr_i, + i6_wb_sel_i, + i6_wb_we_i, + i6_wb_dat_i, + i6_wb_dat_o, + i6_wb_ack_o, + i6_wb_err_o, + i6_wb_cti_i, + i6_wb_bte_i, + + i7_wb_cyc_i, + i7_wb_stb_i, + i7_wb_adr_i, + i7_wb_sel_i, + i7_wb_we_i, + i7_wb_dat_i, + i7_wb_dat_o, + i7_wb_ack_o, + i7_wb_err_o, + i7_wb_cti_i, + i7_wb_bte_i, + + + t0_wb_cyc_o, + t0_wb_stb_o, + t0_wb_adr_o, + t0_wb_sel_o, + t0_wb_we_o, + t0_wb_dat_o, + t0_wb_dat_i, + t0_wb_ack_i, + t0_wb_err_i, + t0_wb_cti_o, + t0_wb_bte_o + +); + +// +// Parameters +// +parameter t0_addr_w = 2; +parameter t0_addr = 2'b00; +parameter multitarg = 1'b0; +parameter t17_addr_w = 2; +parameter t17_addr = 2'b00; + +// +// I/O Ports +// +input wb_clk_i; +input wb_rst_i; +// +// WB slave i/f connecting initiator 0 +// +input i0_wb_cyc_i; +input i0_wb_stb_i; +input [`TC_AW-1:0] i0_wb_adr_i; +input [`TC_BSW-1:0] i0_wb_sel_i; +input i0_wb_we_i; +input [`TC_DW-1:0] i0_wb_dat_i; +output [`TC_DW-1:0] i0_wb_dat_o; +output i0_wb_ack_o; +output i0_wb_err_o; +input [2:0] i0_wb_cti_i; +input [1:0] i0_wb_bte_i; + +// +// WB slave i/f connecting initiator 1 +// +input i1_wb_cyc_i; +input i1_wb_stb_i; +input [`TC_AW-1:0] i1_wb_adr_i; +input [`TC_BSW-1:0] i1_wb_sel_i; +input i1_wb_we_i; +input [`TC_DW-1:0] i1_wb_dat_i; +output [`TC_DW-1:0] i1_wb_dat_o; +output i1_wb_ack_o; +output i1_wb_err_o; +input [2:0] i1_wb_cti_i; +input [1:0] i1_wb_bte_i; + +// +// WB slave i/f connecting initiator 2 +// +input i2_wb_cyc_i; +input i2_wb_stb_i; +input [`TC_AW-1:0] i2_wb_adr_i; +input [`TC_BSW-1:0] i2_wb_sel_i; +input i2_wb_we_i; +input [`TC_DW-1:0] i2_wb_dat_i; +output [`TC_DW-1:0] i2_wb_dat_o; +output i2_wb_ack_o; +output i2_wb_err_o; +input [2:0] i2_wb_cti_i; +input [1:0] i2_wb_bte_i; + +// +// WB slave i/f connecting initiator 3 +// +input i3_wb_cyc_i; +input i3_wb_stb_i; +input [`TC_AW-1:0] i3_wb_adr_i; +input [`TC_BSW-1:0] i3_wb_sel_i; +input i3_wb_we_i; +input [`TC_DW-1:0] i3_wb_dat_i; +output [`TC_DW-1:0] i3_wb_dat_o; +output i3_wb_ack_o; +output i3_wb_err_o; +input [2:0] i3_wb_cti_i; +input [1:0] i3_wb_bte_i; + +// +// WB slave i/f connecting initiator 4 +// +input i4_wb_cyc_i; +input i4_wb_stb_i; +input [`TC_AW-1:0] i4_wb_adr_i; +input [`TC_BSW-1:0] i4_wb_sel_i; +input i4_wb_we_i; +input [`TC_DW-1:0] i4_wb_dat_i; +output [`TC_DW-1:0] i4_wb_dat_o; +output i4_wb_ack_o; +output i4_wb_err_o; +input [2:0] i4_wb_cti_i; +input [1:0] i4_wb_bte_i; + +// +// WB slave i/f connecting initiator 5 +// +input i5_wb_cyc_i; +input i5_wb_stb_i; +input [`TC_AW-1:0] i5_wb_adr_i; +input [`TC_BSW-1:0] i5_wb_sel_i; +input i5_wb_we_i; +input [`TC_DW-1:0] i5_wb_dat_i; +output [`TC_DW-1:0] i5_wb_dat_o; +output i5_wb_ack_o; +output i5_wb_err_o; +input [2:0] i5_wb_cti_i; +input [1:0] i5_wb_bte_i; + +// +// WB slave i/f connecting initiator 6 +// +input i6_wb_cyc_i; +input i6_wb_stb_i; +input [`TC_AW-1:0] i6_wb_adr_i; +input [`TC_BSW-1:0] i6_wb_sel_i; +input i6_wb_we_i; +input [`TC_DW-1:0] i6_wb_dat_i; +output [`TC_DW-1:0] i6_wb_dat_o; +output i6_wb_ack_o; +output i6_wb_err_o; +input [2:0] i6_wb_cti_i; +input [1:0] i6_wb_bte_i; + +// +// WB slave i/f connecting initiator 7 +// +input i7_wb_cyc_i; +input i7_wb_stb_i; +input [`TC_AW-1:0] i7_wb_adr_i; +input [`TC_BSW-1:0] i7_wb_sel_i; +input i7_wb_we_i; +input [`TC_DW-1:0] i7_wb_dat_i; +output [`TC_DW-1:0] i7_wb_dat_o; +output i7_wb_ack_o; +output i7_wb_err_o; +input [2:0] i7_wb_cti_i; +input [1:0] i7_wb_bte_i; + + +// +// WB master i/f connecting target +// +output t0_wb_cyc_o; +output t0_wb_stb_o; +output [`TC_AW-1:0] t0_wb_adr_o; +output [`TC_BSW-1:0] t0_wb_sel_o; +output t0_wb_we_o; +output [`TC_DW-1:0] t0_wb_dat_o; +input [`TC_DW-1:0] t0_wb_dat_i; +input t0_wb_ack_i; +input t0_wb_err_i; +output [2:0] t0_wb_cti_o; +output [1:0] t0_wb_bte_o; + +// +// Internal wires & registers +// +wire [`TC_IIN_W-1:0] i0_in, i1_in, + i2_in, i3_in, + i4_in, i5_in, + i6_in, i7_in; +wire [`TC_TIN_W-1:0] i0_out, i1_out, + i2_out, i3_out, + i4_out, i5_out, + i6_out, i7_out; +wire [`TC_IIN_W-1:0] t0_out; +wire [`TC_TIN_W-1:0] t0_in; +wire [7:0] req_i; +wire [2:0] req_won; +reg req_cont; +reg [2:0] req_r; +// +// Group WB initiator 0 i/f inputs and outputs +// +assign i0_in = {i0_wb_cyc_i, i0_wb_stb_i, i0_wb_adr_i, + i0_wb_sel_i, i0_wb_we_i, i0_wb_dat_i, i0_wb_cti_i, i0_wb_bte_i}; +assign {i0_wb_dat_o, i0_wb_ack_o, i0_wb_err_o} = i0_out; + +// +// Group WB initiator 1 i/f inputs and outputs +// +assign i1_in = {i1_wb_cyc_i, i1_wb_stb_i, i1_wb_adr_i, + i1_wb_sel_i, i1_wb_we_i, i1_wb_dat_i, i1_wb_cti_i, i1_wb_bte_i}; +assign {i1_wb_dat_o, i1_wb_ack_o, i1_wb_err_o} = i1_out; + +// +// Group WB initiator 2 i/f inputs and outputs +// +assign i2_in = {i2_wb_cyc_i, i2_wb_stb_i, i2_wb_adr_i, + i2_wb_sel_i, i2_wb_we_i, i2_wb_dat_i, i2_wb_cti_i, i2_wb_bte_i}; +assign {i2_wb_dat_o, i2_wb_ack_o, i2_wb_err_o} = i2_out; + +// +// Group WB initiator 3 i/f inputs and outputs +// +assign i3_in = {i3_wb_cyc_i, i3_wb_stb_i, i3_wb_adr_i, + i3_wb_sel_i, i3_wb_we_i, i3_wb_dat_i, i3_wb_cti_i, i3_wb_bte_i}; +assign {i3_wb_dat_o, i3_wb_ack_o, i3_wb_err_o} = i3_out; + +// +// Group WB initiator 4 i/f inputs and outputs +// +assign i4_in = {i4_wb_cyc_i, i4_wb_stb_i, i4_wb_adr_i, + i4_wb_sel_i, i4_wb_we_i, i4_wb_dat_i, i4_wb_cti_i, i4_wb_bte_i}; +assign {i4_wb_dat_o, i4_wb_ack_o, i4_wb_err_o} = i4_out; + +// +// Group WB initiator 5 i/f inputs and outputs +// +assign i5_in = {i5_wb_cyc_i, i5_wb_stb_i, i5_wb_adr_i, + i5_wb_sel_i, i5_wb_we_i, i5_wb_dat_i, i5_wb_cti_i, i5_wb_bte_i}; +assign {i5_wb_dat_o, i5_wb_ack_o, i5_wb_err_o} = i5_out; + +// +// Group WB initiator 6 i/f inputs and outputs +// +assign i6_in = {i6_wb_cyc_i, i6_wb_stb_i, i6_wb_adr_i, + i6_wb_sel_i, i6_wb_we_i, i6_wb_dat_i, i6_wb_cti_i, i6_wb_bte_i}; +assign {i6_wb_dat_o, i6_wb_ack_o, i6_wb_err_o} = i6_out; + +// +// Group WB initiator 7 i/f inputs and outputs +// +assign i7_in = {i7_wb_cyc_i, i7_wb_stb_i, i7_wb_adr_i, + i7_wb_sel_i, i7_wb_we_i, i7_wb_dat_i, i7_wb_cti_i, i7_wb_bte_i}; +assign {i7_wb_dat_o, i7_wb_ack_o, i7_wb_err_o} = i7_out; + + +// +// Group WB target 0 i/f inputs and outputs +// +assign {t0_wb_cyc_o, t0_wb_stb_o, t0_wb_adr_o, + t0_wb_sel_o, t0_wb_we_o, t0_wb_dat_o, t0_wb_cti_o, t0_wb_bte_o} = t0_out; +assign t0_in = {t0_wb_dat_i, t0_wb_ack_i, t0_wb_err_i}; + +// +// Assign to WB initiator i/f outputs +// +// Either inputs from the target are assigned or zeros. +// +assign i0_out = (req_won == 3'd0) ? t0_in : {`TC_TIN_W{1'b0}}; +assign i1_out = (req_won == 3'd1) ? t0_in : {`TC_TIN_W{1'b0}}; +assign i2_out = (req_won == 3'd2) ? t0_in : {`TC_TIN_W{1'b0}}; +assign i3_out = (req_won == 3'd3) ? t0_in : {`TC_TIN_W{1'b0}}; +assign i4_out = (req_won == 3'd4) ? t0_in : {`TC_TIN_W{1'b0}}; +assign i5_out = (req_won == 3'd5) ? t0_in : {`TC_TIN_W{1'b0}}; +assign i6_out = (req_won == 3'd6) ? t0_in : {`TC_TIN_W{1'b0}}; +assign i7_out = (req_won == 3'd7) ? t0_in : {`TC_TIN_W{1'b0}}; + +// +// Assign to WB target i/f outputs +// +// Assign inputs from initiator to target outputs according to +// which initiator has won. If there is no request for the target, +// assign zeros. +// +assign t0_out = (req_won == 3'd0) ? i0_in : + (req_won == 3'd1) ? i1_in : + (req_won == 3'd2) ? i2_in : + (req_won == 3'd3) ? i3_in : + (req_won == 3'd4) ? i4_in : + (req_won == 3'd5) ? i5_in : + (req_won == 3'd6) ? i6_in : + (req_won == 3'd7) ? i7_in : {`TC_IIN_W{1'b0}}; + +// +// Determine if an initiator has address of the target. +// +assign req_i[0] = i0_wb_cyc_i & + ((i0_wb_adr_i[`TC_AW-1:`TC_AW-t0_addr_w] == t0_addr) | + multitarg & (i0_wb_adr_i[`TC_AW-1:`TC_AW-t17_addr_w] == t17_addr)); +assign req_i[1] = i1_wb_cyc_i & + ((i1_wb_adr_i[`TC_AW-1:`TC_AW-t0_addr_w] == t0_addr) | + multitarg & (i1_wb_adr_i[`TC_AW-1:`TC_AW-t17_addr_w] == t17_addr)); +assign req_i[2] = i2_wb_cyc_i & + ((i2_wb_adr_i[`TC_AW-1:`TC_AW-t0_addr_w] == t0_addr) | + multitarg & (i2_wb_adr_i[`TC_AW-1:`TC_AW-t17_addr_w] == t17_addr)); +assign req_i[3] = i3_wb_cyc_i & + ((i3_wb_adr_i[`TC_AW-1:`TC_AW-t0_addr_w] == t0_addr) | + multitarg & (i3_wb_adr_i[`TC_AW-1:`TC_AW-t17_addr_w] == t17_addr)); +assign req_i[4] = i4_wb_cyc_i & + ((i4_wb_adr_i[`TC_AW-1:`TC_AW-t0_addr_w] == t0_addr) | + multitarg & (i4_wb_adr_i[`TC_AW-1:`TC_AW-t17_addr_w] == t17_addr)); +assign req_i[5] = i5_wb_cyc_i & + ((i5_wb_adr_i[`TC_AW-1:`TC_AW-t0_addr_w] == t0_addr) | + multitarg & (i5_wb_adr_i[`TC_AW-1:`TC_AW-t17_addr_w] == t17_addr)); +assign req_i[6] = i6_wb_cyc_i & + ((i6_wb_adr_i[`TC_AW-1:`TC_AW-t0_addr_w] == t0_addr) | + multitarg & (i6_wb_adr_i[`TC_AW-1:`TC_AW-t17_addr_w] == t17_addr)); +assign req_i[7] = i7_wb_cyc_i & + ((i7_wb_adr_i[`TC_AW-1:`TC_AW-t0_addr_w] == t0_addr) | + multitarg & (i7_wb_adr_i[`TC_AW-1:`TC_AW-t17_addr_w] == t17_addr)); + +// +// Determine who gets current access to the target. +// +// If current initiator still asserts request, do nothing +// (keep current initiator). +// Otherwise check each initiator's request, starting from initiator 0 +// (highest priority). +// If there is no requests from initiators, park initiator 0. +// +assign req_won = req_cont ? req_r : + req_i[0] ? 3'd0 : + req_i[1] ? 3'd1 : + req_i[2] ? 3'd2 : + req_i[3] ? 3'd3 : + req_i[4] ? 3'd4 : + req_i[5] ? 3'd5 : + req_i[6] ? 3'd6 : + req_i[7] ? 3'd7 : 3'd0; + +// +// Check if current initiator still wants access to the target and if +// it does, assert req_cont. +// +always @(req_r or req_i) + case (req_r) // synopsys parallel_case + 3'd0: req_cont = req_i[0]; + 3'd1: req_cont = req_i[1]; + 3'd2: req_cont = req_i[2]; + 3'd3: req_cont = req_i[3]; + 3'd4: req_cont = req_i[4]; + 3'd5: req_cont = req_i[5]; + 3'd6: req_cont = req_i[6]; + 3'd7: req_cont = req_i[7]; + endcase + +// +// Register who has current access to the target. +// +always @(posedge wb_clk_i or posedge wb_rst_i) + if (wb_rst_i) + req_r <= #1 3'd0; + else + req_r <= #1 req_won; + +endmodule + +// +// Single initiator to multiple targets +// +module tc_si_to_mt ( + + i0_wb_cyc_i, + i0_wb_stb_i, + i0_wb_adr_i, + i0_wb_sel_i, + i0_wb_we_i, + i0_wb_dat_i, + i0_wb_dat_o, + i0_wb_ack_o, + i0_wb_err_o, + i0_wb_cti_i, + i0_wb_bte_i, + + t0_wb_cyc_o, + t0_wb_stb_o, + t0_wb_adr_o, + t0_wb_sel_o, + t0_wb_we_o, + t0_wb_dat_o, + t0_wb_dat_i, + t0_wb_ack_i, + t0_wb_err_i, + t0_wb_cti_o, + t0_wb_bte_o, + + t1_wb_cyc_o, + t1_wb_stb_o, + t1_wb_adr_o, + t1_wb_sel_o, + t1_wb_we_o, + t1_wb_dat_o, + t1_wb_dat_i, + t1_wb_ack_i, + t1_wb_err_i, + t1_wb_cti_o, + t1_wb_bte_o, + + t2_wb_cyc_o, + t2_wb_stb_o, + t2_wb_adr_o, + t2_wb_sel_o, + t2_wb_we_o, + t2_wb_dat_o, + t2_wb_dat_i, + t2_wb_ack_i, + t2_wb_err_i, + t2_wb_cti_o, + t2_wb_bte_o, + + t3_wb_cyc_o, + t3_wb_stb_o, + t3_wb_adr_o, + t3_wb_sel_o, + t3_wb_we_o, + t3_wb_dat_o, + t3_wb_dat_i, + t3_wb_ack_i, + t3_wb_err_i, + t3_wb_cti_o, + t3_wb_bte_o, + + t4_wb_cyc_o, + t4_wb_stb_o, + t4_wb_adr_o, + t4_wb_sel_o, + t4_wb_we_o, + t4_wb_dat_o, + t4_wb_dat_i, + t4_wb_ack_i, + t4_wb_err_i, + t4_wb_cti_o, + t4_wb_bte_o, + + t5_wb_cyc_o, + t5_wb_stb_o, + t5_wb_adr_o, + t5_wb_sel_o, + t5_wb_we_o, + t5_wb_dat_o, + t5_wb_dat_i, + t5_wb_ack_i, + t5_wb_err_i, + t5_wb_cti_o, + t5_wb_bte_o, + + t6_wb_cyc_o, + t6_wb_stb_o, + t6_wb_adr_o, + t6_wb_sel_o, + t6_wb_we_o, + t6_wb_dat_o, + t6_wb_dat_i, + t6_wb_ack_i, + t6_wb_err_i, + t6_wb_cti_o, + t6_wb_bte_o, + + t7_wb_cyc_o, + t7_wb_stb_o, + t7_wb_adr_o, + t7_wb_sel_o, + t7_wb_we_o, + t7_wb_dat_o, + t7_wb_dat_i, + t7_wb_ack_i, + t7_wb_err_i, + t7_wb_cti_o, + t7_wb_bte_o + + +); + +// +// Parameters +// +parameter t0_addr_w = 3; +parameter t0_addr = 3'd0; +parameter t17_addr_w = 3; +parameter t1_addr = 3'd1; +parameter t2_addr = 3'd2; +parameter t3_addr = 3'd3; +parameter t4_addr = 3'd4; +parameter t5_addr = 3'd5; +parameter t6_addr = 3'd6; +parameter t7_addr = 3'd7; + +// +// I/O Ports +// + +// +// WB slave i/f connecting initiator 0 +// +input i0_wb_cyc_i; +input i0_wb_stb_i; +input [`TC_AW-1:0] i0_wb_adr_i; +input [`TC_BSW-1:0] i0_wb_sel_i; +input i0_wb_we_i; +input [`TC_DW-1:0] i0_wb_dat_i; +output [`TC_DW-1:0] i0_wb_dat_o; +output i0_wb_ack_o; +output i0_wb_err_o; +input [2:0] i0_wb_cti_i; +input [1:0] i0_wb_bte_i; +// +// WB master i/f connecting target 0 +// +output t0_wb_cyc_o; +output t0_wb_stb_o; +output [`TC_AW-1:0] t0_wb_adr_o; +output [`TC_BSW-1:0] t0_wb_sel_o; +output t0_wb_we_o; +output [`TC_DW-1:0] t0_wb_dat_o; +input [`TC_DW-1:0] t0_wb_dat_i; +input t0_wb_ack_i; +input t0_wb_err_i; +output [2:0] t0_wb_cti_o; +output [1:0] t0_wb_bte_o; + +// +// WB master i/f connecting target 1 +// +output t1_wb_cyc_o; +output t1_wb_stb_o; +output [`TC_AW-1:0] t1_wb_adr_o; +output [`TC_BSW-1:0] t1_wb_sel_o; +output t1_wb_we_o; +output [`TC_DW-1:0] t1_wb_dat_o; +input [`TC_DW-1:0] t1_wb_dat_i; +input t1_wb_ack_i; +input t1_wb_err_i; +output [2:0] t1_wb_cti_o; +output [1:0] t1_wb_bte_o; + +// +// WB master i/f connecting target 2 +// +output t2_wb_cyc_o; +output t2_wb_stb_o; +output [`TC_AW-1:0] t2_wb_adr_o; +output [`TC_BSW-1:0] t2_wb_sel_o; +output t2_wb_we_o; +output [`TC_DW-1:0] t2_wb_dat_o; +input [`TC_DW-1:0] t2_wb_dat_i; +input t2_wb_ack_i; +input t2_wb_err_i; +output [2:0] t2_wb_cti_o; +output [1:0] t2_wb_bte_o; + +// +// WB master i/f connecting target 3 +// +output t3_wb_cyc_o; +output t3_wb_stb_o; +output [`TC_AW-1:0] t3_wb_adr_o; +output [`TC_BSW-1:0] t3_wb_sel_o; +output t3_wb_we_o; +output [`TC_DW-1:0] t3_wb_dat_o; +input [`TC_DW-1:0] t3_wb_dat_i; +input t3_wb_ack_i; +input t3_wb_err_i; +output [2:0] t3_wb_cti_o; +output [1:0] t3_wb_bte_o; + +// +// WB master i/f connecting target 4 +// +output t4_wb_cyc_o; +output t4_wb_stb_o; +output [`TC_AW-1:0] t4_wb_adr_o; +output [`TC_BSW-1:0] t4_wb_sel_o; +output t4_wb_we_o; +output [`TC_DW-1:0] t4_wb_dat_o; +input [`TC_DW-1:0] t4_wb_dat_i; +input t4_wb_ack_i; +input t4_wb_err_i; +output [2:0] t4_wb_cti_o; +output [1:0] t4_wb_bte_o; + +// +// WB master i/f connecting target 5 +// +output t5_wb_cyc_o; +output t5_wb_stb_o; +output [`TC_AW-1:0] t5_wb_adr_o; +output [`TC_BSW-1:0] t5_wb_sel_o; +output t5_wb_we_o; +output [`TC_DW-1:0] t5_wb_dat_o; +input [`TC_DW-1:0] t5_wb_dat_i; +input t5_wb_ack_i; +input t5_wb_err_i; +output [2:0] t5_wb_cti_o; +output [1:0] t5_wb_bte_o; + +// +// WB master i/f connecting target 6 +// +output t6_wb_cyc_o; +output t6_wb_stb_o; +output [`TC_AW-1:0] t6_wb_adr_o; +output [`TC_BSW-1:0] t6_wb_sel_o; +output t6_wb_we_o; +output [`TC_DW-1:0] t6_wb_dat_o; +input [`TC_DW-1:0] t6_wb_dat_i; +input t6_wb_ack_i; +input t6_wb_err_i; +output [2:0] t6_wb_cti_o; +output [1:0] t6_wb_bte_o; + +// +// WB master i/f connecting target 7 +// +output t7_wb_cyc_o; +output t7_wb_stb_o; +output [`TC_AW-1:0] t7_wb_adr_o; +output [`TC_BSW-1:0] t7_wb_sel_o; +output t7_wb_we_o; +output [`TC_DW-1:0] t7_wb_dat_o; +input [`TC_DW-1:0] t7_wb_dat_i; +input t7_wb_ack_i; +input t7_wb_err_i; +output [2:0] t7_wb_cti_o; +output [1:0] t7_wb_bte_o; + + +// +// Internal wires & registers +// +wire [`TC_IIN_W-1:0] i0_in; +wire [`TC_TIN_W-1:0] i0_out; +wire [`TC_IIN_W-1:0] t0_out, t1_out, + t2_out, t3_out, + t4_out, t5_out, + t6_out, t7_out; +wire [`TC_TIN_W-1:0] t0_in, t1_in, + t2_in, t3_in, + t4_in, t5_in, + t6_in, t7_in; +wire [7:0] req_t; + +// +// Group WB initiator 0 i/f inputs and outputs +// +assign i0_in = {i0_wb_cyc_i, i0_wb_stb_i, i0_wb_adr_i, + i0_wb_sel_i, i0_wb_we_i, i0_wb_dat_i, i0_wb_cti_i, i0_wb_bte_i}; +assign {i0_wb_dat_o, i0_wb_ack_o, i0_wb_err_o} = i0_out; +// +// Group WB target 0 i/f inputs and outputs +// +assign {t0_wb_cyc_o, t0_wb_stb_o, t0_wb_adr_o, +t0_wb_sel_o, t0_wb_we_o, t0_wb_dat_o, t0_wb_cti_o, t0_wb_bte_o} = t0_out; +assign t0_in = {t0_wb_dat_i, t0_wb_ack_i, t0_wb_err_i}; + +// +// Group WB target 1 i/f inputs and outputs +// +assign {t1_wb_cyc_o, t1_wb_stb_o, t1_wb_adr_o, +t1_wb_sel_o, t1_wb_we_o, t1_wb_dat_o, t1_wb_cti_o, t1_wb_bte_o} = t1_out; +assign t1_in = {t1_wb_dat_i, t1_wb_ack_i, t1_wb_err_i}; + +// +// Group WB target 2 i/f inputs and outputs +// +assign {t2_wb_cyc_o, t2_wb_stb_o, t2_wb_adr_o, +t2_wb_sel_o, t2_wb_we_o, t2_wb_dat_o, t2_wb_cti_o, t2_wb_bte_o} = t2_out; +assign t2_in = {t2_wb_dat_i, t2_wb_ack_i, t2_wb_err_i}; + +// +// Group WB target 3 i/f inputs and outputs +// +assign {t3_wb_cyc_o, t3_wb_stb_o, t3_wb_adr_o, +t3_wb_sel_o, t3_wb_we_o, t3_wb_dat_o, t3_wb_cti_o, t3_wb_bte_o} = t3_out; +assign t3_in = {t3_wb_dat_i, t3_wb_ack_i, t3_wb_err_i}; + +// +// Group WB target 4 i/f inputs and outputs +// +assign {t4_wb_cyc_o, t4_wb_stb_o, t4_wb_adr_o, +t4_wb_sel_o, t4_wb_we_o, t4_wb_dat_o, t4_wb_cti_o, t4_wb_bte_o} = t4_out; +assign t4_in = {t4_wb_dat_i, t4_wb_ack_i, t4_wb_err_i}; + +// +// Group WB target 5 i/f inputs and outputs +// +assign {t5_wb_cyc_o, t5_wb_stb_o, t5_wb_adr_o, +t5_wb_sel_o, t5_wb_we_o, t5_wb_dat_o, t5_wb_cti_o, t5_wb_bte_o} = t5_out; +assign t5_in = {t5_wb_dat_i, t5_wb_ack_i, t5_wb_err_i}; + +// +// Group WB target 6 i/f inputs and outputs +// +assign {t6_wb_cyc_o, t6_wb_stb_o, t6_wb_adr_o, +t6_wb_sel_o, t6_wb_we_o, t6_wb_dat_o, t6_wb_cti_o, t6_wb_bte_o} = t6_out; +assign t6_in = {t6_wb_dat_i, t6_wb_ack_i, t6_wb_err_i}; + +// +// Group WB target 7 i/f inputs and outputs +// +assign {t7_wb_cyc_o, t7_wb_stb_o, t7_wb_adr_o, +t7_wb_sel_o, t7_wb_we_o, t7_wb_dat_o, t7_wb_cti_o, t7_wb_bte_o} = t7_out; +assign t7_in = {t7_wb_dat_i, t7_wb_ack_i, t7_wb_err_i}; + +// +// Assign to WB target i/f outputs +// +// Either inputs from the initiator are assigned or zeros. +// +assign t0_out = req_t[0] ? i0_in : {`TC_IIN_W{1'b0}}; +assign t1_out = req_t[1] ? i0_in : {`TC_IIN_W{1'b0}}; +assign t2_out = req_t[2] ? i0_in : {`TC_IIN_W{1'b0}}; +assign t3_out = req_t[3] ? i0_in : {`TC_IIN_W{1'b0}}; +assign t4_out = req_t[4] ? i0_in : {`TC_IIN_W{1'b0}}; +assign t5_out = req_t[5] ? i0_in : {`TC_IIN_W{1'b0}}; +assign t6_out = req_t[6] ? i0_in : {`TC_IIN_W{1'b0}}; +assign t7_out = req_t[7] ? i0_in : {`TC_IIN_W{1'b0}}; + +// +// Assign to WB initiator i/f outputs +// +// Assign inputs from target to initiator outputs according to +// which target is accessed. If there is no request for a target, +// assign zeros. +// +assign i0_out = req_t[0] ? t0_in : + req_t[1] ? t1_in : + req_t[2] ? t2_in : + req_t[3] ? t3_in : + req_t[4] ? t4_in : + req_t[5] ? t5_in : + req_t[6] ? t6_in : + req_t[7] ? t7_in : {`TC_TIN_W{1'b0}}; + +// +// Determine which target is being accessed. +// +assign req_t[0] = i0_wb_cyc_i & (i0_wb_adr_i[`TC_AW-1:`TC_AW-t0_addr_w] == t0_addr); +assign req_t[1] = i0_wb_cyc_i & (i0_wb_adr_i[`TC_AW-1:`TC_AW-t17_addr_w] == t1_addr); +assign req_t[2] = i0_wb_cyc_i & (i0_wb_adr_i[`TC_AW-1:`TC_AW-t17_addr_w] == t2_addr); +assign req_t[3] = i0_wb_cyc_i & (i0_wb_adr_i[`TC_AW-1:`TC_AW-t17_addr_w] == t3_addr); +assign req_t[4] = i0_wb_cyc_i & (i0_wb_adr_i[`TC_AW-1:`TC_AW-t17_addr_w] == t4_addr); +assign req_t[5] = i0_wb_cyc_i & (i0_wb_adr_i[`TC_AW-1:`TC_AW-t17_addr_w] == t5_addr); +assign req_t[6] = i0_wb_cyc_i & (i0_wb_adr_i[`TC_AW-1:`TC_AW-t17_addr_w] == t6_addr); +assign req_t[7] = i0_wb_cyc_i & (i0_wb_adr_i[`TC_AW-1:`TC_AW-t17_addr_w] == t7_addr); + +endmodule Index: eth_transf_linux/eth1_mac_recv.c =================================================================== --- eth_transf_linux/eth1_mac_recv.c (nonexistent) +++ eth_transf_linux/eth1_mac_recv.c (revision 42) @@ -0,0 +1,118 @@ +#include + +#include + +//packet socket +#include +#include +#include + +//protocol +#include + +//netdevice stuff +#include +#include + +//file open stuff +#include +#include +#include + +//arp stuff +//#include + +#define MAC_ADDR_LEN 6 +typedef unsigned char MacAddress[MAC_ADDR_LEN]; + +int main() +{ + int socket_id, new_sock, iRet = -1; + int addrlen, bytesread, nfound =0; + + int i = 0; + + MacAddress localMac = {0x00, 0x00, 0xC0, 0x41, 0x36, 0xD3}; +// MacAddress localMac = {0xD3, 0x36, 0x41, 0xC0, 0x00, 0x00}; + + char buf[256]; + + struct sockaddr_ll my_addr; + + struct ifreq ethreq; + + int if_index; + + //create packet socket from type sock_dgram where headers are automatically thrown out + if ( ( socket_id = socket(PF_PACKET, SOCK_DGRAM, htons(ETH_P_ALL) ) ) < 0 ) + { + perror("socket"); + exit(1); + } + else + { + printf("Socket has been created: socket_number %d\n", socket_id); + } + + + //GET ethreq for if "eth1" + strncpy(ethreq.ifr_name,"eth1",IFNAMSIZ); + ioctl(socket_id, SIOCGIFFLAGS, ðreq); + //SET promisc mode for if ethreq +// ethreq.ifr_flags |= IFF_PROMISC; +// ioctl(socket_id, SIOCSIFFLAGS, ðreq); + //request index + ioctl(socket_id, SIOCGIFINDEX, ðreq); + + if_index = ethreq.ifr_ifindex; + + printf("This is the index of the interface: %d\n", if_index ); + + memset(&my_addr, '0', sizeof(my_addr) ); + + my_addr.sll_family = AF_PACKET; + my_addr.sll_protocol = htons(ETH_P_ALL); //defaults to socket protocol + my_addr.sll_ifindex = if_index; +// my_addr.sll_hatype = htons(ARPHRD_ETHER); +// my_addr.sll_pkttype = PACKET_OTHERHOST; + my_addr.sll_halen = 6; + memcpy( &(my_addr.sll_addr), localMac, MAC_ADDR_LEN ); + + //request hw_addres + ioctl(socket_id, SIOCGIFHWADDR, ðreq); + + printf("This is the address of my card: %d\n", my_addr.sll_addr[5] ); + + //bind to interface goten from ioctl SIOCGIFHWADDR directive (otherwise all packets are recved) + if ( bind( socket_id, (struct sockaddr *) &my_addr, sizeof(my_addr) ) ) + { + perror("bind"); + exit(1); + } + + struct sockaddr_ll from; + int fromlen; + + fromlen = sizeof(from); + + for (;;) + { + iRet = recvfrom(socket_id, buf, 256, 0, &from, &fromlen); + if ( iRet == -1 ) + { + perror("recvfrom"); + exit(1); + } + else + { + printf("Received %d bytes of data.\n", iRet); + printf("This is the received data:\n"); + for ( i = 0; i < iRet; i++) + printf("Byte %d: %X\n", i, (int)buf[i]); + printf("End of transmission!\n"); + } + } + + return 0; +} + Index: eth_transf_linux/eth1_mac_snd.c =================================================================== --- eth_transf_linux/eth1_mac_snd.c (nonexistent) +++ eth_transf_linux/eth1_mac_snd.c (revision 42) @@ -0,0 +1,139 @@ +#include + +#include + +//packet socket +#include +#include +#include + +//protocol +#include + +//netdevice stuff +#include +#include + +//file open stuff +#include +#include +#include + +//arp stuff +//#include + +#define MAC_ADDR_LEN 6 +typedef unsigned char MacAddress[MAC_ADDR_LEN]; + +int main() +{ + int socket_id, new_sock, iRet = -1; + int addrlen, bytesread, nfound =0; + + int i = 0; + + MacAddress localMac = {0x00, 0x00, 0xC0, 0x41, 0x36, 0xD3}; + MacAddress extMac = {0x55, 0x47, 0x34, 0x22, 0x88, 0x92}; +// MacAddress extMac = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00}; + + char buf[256]; + + struct sockaddr_ll my_addr; + + struct ifreq ethreq; + + int if_index; + + if ( ( socket_id = socket(PF_PACKET, SOCK_DGRAM, htons(ETH_P_ALL) ) ) < 0 ) + { + perror("socket"); + exit(1); + } + else + { + printf("Socket has been created: socket_number %d\n", socket_id); + } + + + //GET ethreq for if "eth1" + strncpy(ethreq.ifr_name,"eth1",IFNAMSIZ); + ioctl(socket_id, SIOCGIFFLAGS, ðreq); + //SET promisc mode for if ethreq +// ethreq.ifr_flags |= IFF_PROMISC; +// ioctl(socket_id, SIOCSIFFLAGS, ðreq); + //request index + ioctl(socket_id, SIOCGIFINDEX, ðreq); + if_index = ethreq.ifr_ifindex; + + printf("This is the index of the interface: %d\n", if_index ); + + memset(&my_addr, '0', sizeof(my_addr) ); + + my_addr.sll_family = AF_PACKET; + my_addr.sll_protocol = htons(ETH_P_ALL); //defaults to socket protocol + my_addr.sll_ifindex = if_index; +// my_addr.sll_hatype = htons(ARPHRD_ETHER); +// my_addr.sll_pkttype = PACKET_OTHERHOST; + my_addr.sll_halen = 6; + memcpy( &(my_addr.sll_addr), localMac, MAC_ADDR_LEN ); + + //request hw_addres + ioctl(socket_id, SIOCGIFHWADDR, ðreq); + + printf("This is the address of my card: %d\n", my_addr.sll_addr[5] ); + + if ( bind( socket_id, (struct sockaddr *) &my_addr, sizeof(my_addr) ) ) + { + perror("bind"); + exit(1); + } + + struct sockaddr_ll addr_to; + int addr_toLen; + + addr_toLen = sizeof(addr_to); + + memset(&addr_to, '0', sizeof(addr_to) ); + + addr_to.sll_family = AF_PACKET; + addr_to.sll_ifindex = if_index; + addr_to.sll_halen = 6; + memcpy( &(addr_to.sll_addr), extMac, MAC_ADDR_LEN ); + + for (i=0; i<256 ; i++ ) + buf[i] = 0; + + //first 2 bytes are gathered with length and are ignored + buf[0] = 0xAA; + buf[1] = 0xAA; + //now it gets to fpga: send opcode 0xBA8 + buf[2] = 0xBA; + buf[3] = 0x87; + //opcode sent + buf[4] = 0xAA; + buf[5] = 0xAA; + buf[6] = 0xAA; + buf[7] = 0xAA; + buf[8] = 0xAA; + buf[9] = 0xAA; + buf[10] = 0xAA; + buf[11] = 0xAA; + +// for (;;) +// { + iRet = sendto(socket_id, buf, 46, 0, (struct sockaddr *) &addr_to, addr_toLen); + if ( iRet == -1 ) + { + perror("sendto"); + exit(1); + } + else + { +// printf("%s\n", buf); + printf("Data sent!\nExiting...\n"); + } +// } + + return 0; +} + Index: gpio/rtl/gpio_defines.v =================================================================== --- gpio/rtl/gpio_defines.v (nonexistent) +++ gpio/rtl/gpio_defines.v (revision 42) @@ -0,0 +1,326 @@ +////////////////////////////////////////////////////////////////////// +//// //// +//// WISHBONE GPIO Definitions //// +//// //// +//// This file is part of the GPIO project //// +//// http://www.opencores.org/cores/gpio/ //// +//// //// +//// Description //// +//// GPIO IP Definitions. //// +//// //// +//// To Do: //// +//// Nothing //// +//// //// +//// Author(s): //// +//// - Damjan Lampret, lampret@opencores.org //// +//// //// +////////////////////////////////////////////////////////////////////// +//// //// +//// Copyright (C) 2000 Authors and OPENCORES.ORG //// +//// //// +//// This source file may be used and distributed without //// +//// restriction provided that this copyright statement is not //// +//// removed from the file and that any derivative work contains //// +//// the original copyright notice and the associated disclaimer. //// +//// //// +//// This source file is free software; you can redistribute it //// +//// and/or modify it under the terms of the GNU Lesser General //// +//// Public License as published by the Free Software Foundation; //// +//// either version 2.1 of the License, or (at your option) any //// +//// later version. //// +//// //// +//// This source is distributed in the hope that it will be //// +//// useful, but WITHOUT ANY WARRANTY; without even the implied //// +//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR //// +//// PURPOSE. See the GNU Lesser General Public License for more //// +//// details. //// +//// //// +//// You should have received a copy of the GNU Lesser General //// +//// Public License along with this source; if not, download it //// +//// from http://www.opencores.org/lgpl.shtml //// +//// //// +////////////////////////////////////////////////////////////////////// +// +// CVS Revision History +// +// $Log: not supported by cvs2svn $ +// Revision 1.8 2003/12/17 13:00:52 gorand +// added ECLK and NEC registers, all tests passed. +// +// Revision 1.7 2003/12/01 17:10:44 simons +// ifndef directive is not supported by all tools. +// +// Revision 1.6 2003/11/06 13:59:07 gorand +// added support for 8-bit access to registers. +// +// Revision 1.2 2003/10/02 18:54:35 simons +// GPIO signals muxed with other peripherals, higland_board fixed. +// +// Revision 1.1.1.1 2003/06/24 09:09:23 simons +// This files were moved here from toplevel folder. +// +// Revision 1.1.1.1 2003/06/11 18:51:13 simons +// Initial import. +// +// Revision 1.5 2002/11/11 21:36:28 lampret +// Added ifdef to remove mux from clk_pad_i if mux is not allowed. This also removes RGPIO_CTRL[NEC]. +// +// Revision 1.4 2002/05/06 18:25:31 lampret +// negedge flops are enabled by default. +// +// Revision 1.3 2001/12/25 17:12:35 lampret +// Added RGPIO_INTS. +// +// Revision 1.2 2001/11/15 02:24:37 lampret +// Added GPIO_REGISTERED_WB_OUTPUTS, GPIO_REGISTERED_IO_OUTPUTS and GPIO_NO_NEGEDGE_FLOPS. +// +// Revision 1.1 2001/09/18 18:49:07 lampret +// Changed top level ptc into gpio_top. Changed defines.v into gpio_defines.v. +// +// Revision 1.1 2001/08/21 21:39:28 lampret +// Changed directory structure, port names and drfines. +// +// Revision 1.3 2001/07/15 00:21:10 lampret +// Registers can be omitted and will have certain default values +// +// Revision 1.2 2001/07/14 20:39:26 lampret +// Better configurability. +// +// Revision 1.1 2001/06/05 07:45:26 lampret +// Added initial RTL and test benches. There are still some issues with these files. +// +// + +// +// Number of GPIO I/O signals +// +// This is the most important parameter of the GPIO IP core. It defines how many +// I/O signals core has. Range is from 1 to 32. If more than 32 I/O signals are +// required, use several instances of GPIO IP core. +// +// Default is 16. +// +`define GPIO_IOS 31 + +//depending on number of GPIO_IOS, define this... +// for example: if there is 26 GPIO_IOS, define GPIO_LINES26 +// + +`define GPIO_LINES31 + +// +// Undefine this one if you don't want to remove GPIO block from your design +// but you also don't need it. When it is undefined, all GPIO ports still +// remain valid and the core can be synthesized however internally there is +// no GPIO funationality. +// +// Defined by default (duhh !). +// +`define GPIO_IMPLEMENTED + +// +// Define to register all WISHBONE outputs. +// +// Register outputs if you are using GPIO core as a block and synthesizing +// and place&routing it separately from the rest of the system. +// +// If you do not need registered outputs, you can save some area by not defining +// this macro. By default it is defined. +// +`define GPIO_REGISTERED_WB_OUTPUTS + +// +// Define to register all GPIO pad outputs. +// +// Register outputs if you are using GPIO core as a block and synthesizing +// and place&routing it separately from the rest of the system. +// +// If you do not need registered outputs, you can save some area by not defining +// this macro. By default it is defined. +// +`define GPIO_REGISTERED_IO_OUTPUTS + +// +// Implement aux feature. If this define is not defined also aux_i port and +// RGPIO_AUX register will be removed +// +// Defined by default. +// +//`define GPIO_AUX_IMPLEMENT + +// +// If this is not defined clk_pad_i will be removed. Input lines will be lached on +// positive edge of system clock +// if disabled defines GPIO_NO_NEGEDGE_FLOPS, GPIO_NO_CLKPAD_LOGIC will have no effect. +// +// Defined by default. +// +//`define GPIO_CLKPAD + +// +// Define to avoid using negative edge clock flip-flops for external clock +// (caused by NEC register. Instead an inverted external clock with +// positive edge clock flip-flops will be used. +// This define don't have any effect if GPIO_CLKPAD is not defined and if GPIO_SYNC_IN_CLK is defined +// +// By default it is not defined. +// +//`define GPIO_NO_NEGEDGE_FLOPS + +// +// If GPIO_NO_NEGEDGE_FLOPS is defined, a mux needs to be placed on external clock +// clk_pad_i to implement RGPIO_CTRL[NEC] functionality. If no mux is allowed on +// clock signal, enable the following define. +// This define don't have any effect if GPIO_CLKPAD is not defined and if GPIO_SYNC_IN_CLK is defined +// +// By default it is not defined. +// +//`define GPIO_NO_CLKPAD_LOGIC + + +// +// synchronization defines +// +// Two synchronization flops to input lineis added. +// system clock synchronization. +// +`define GPIO_SYNC_IN_WB + +// +// Add synchronization flops to external clock input line. Gpio will have just one clock domain, +// everithing will be synchronized to wishbone clock. External clock muas be at least 2-3x slower +// as systam clock. +// +`define GPIO_SYNC_CLK_WB + +// +// Add synchronization to input pads. synchronization to external clock. +// Don't hawe any effect if GPIO_SYNC_CLK_WB is defined. +// +//`define GPIO_SYNC_IN_CLK + +// +// Add synchronization flops between system clock and external clock. +// Only possible if external clock is enabled and clock synchroization is disabled. +// +//`define GPIO_SYNC_IN_CLK_WB + + + +// +// Undefine if you don't need to read GPIO registers except for RGPIO_IN register. +// When it is undefined all reads of GPIO registers return RGPIO_IN register. This +// is usually useful if you want really small area (for example when implemented in +// FPGA). +// +// To follow GPIO IP core specification document this one must be defined. Also to +// successfully run the test bench it must be defined. By default it is defined. +// +`define GPIO_READREGS + +// +// Full WISHBONE address decoding +// +// It is is undefined, partial WISHBONE address decoding is performed. +// Undefine it if you need to save some area. +// +// By default it is defined. +// +`define GPIO_FULL_DECODE + +// +// Strict 32-bit WISHBONE access +// +// If this one is defined, all WISHBONE accesses must be 32-bit. If it is +// not defined, err_o is asserted whenever 8- or 16-bit access is made. +// Undefine it if you need to save some area. +// +// By default it is defined. +// +//`define GPIO_STRICT_32BIT_ACCESS +// +`ifdef GPIO_STRICT_32BIT_ACCESS +`else +// added by gorand : +// if GPIO_STRICT_32BIT_ACCESS is not defined, +// depending on number of gpio I/O lines, the following are defined : +// if the number of I/O lines is in range 1-8, GPIO_WB_BYTES1 is defined, +// if the number of I/O lines is in range 9-16, GPIO_WB_BYTES2 is defined, +// if the number of I/O lines is in range 17-24, GPIO_WB_BYTES3 is defined, +// if the number of I/O lines is in range 25-32, GPIO_WB_BYTES4 is defined, + +`define GPIO_WB_BYTES4 +//`define GPIO_WB_BYTES3 +//`define GPIO_WB_BYTES2 +//`define GPIO_WB_BYTES1 + +`endif + +// +// WISHBONE address bits used for full decoding of GPIO registers. +// +`define GPIO_ADDRHH 7 +`define GPIO_ADDRHL 6 +`define GPIO_ADDRLH 1 +`define GPIO_ADDRLL 0 + +// +// Bits of WISHBONE address used for partial decoding of GPIO registers. +// +// Default 5:2. +// +`define GPIO_OFS_BITS `GPIO_ADDRHL-1:`GPIO_ADDRLH+1 + +// +// Addresses of GPIO registers +// +// To comply with GPIO IP core specification document they must go from +// address 0 to address 0x18 in the following order: RGPIO_IN, RGPIO_OUT, +// RGPIO_OE, RGPIO_INTE, RGPIO_PTRIG, RGPIO_AUX and RGPIO_CTRL +// +// If particular register is not needed, it's address definition can be omitted +// and the register will not be implemented. Instead a fixed default value will +// be used. +// +`define GPIO_RGPIO_IN 4'h0 // Address 0x00 +`define GPIO_RGPIO_OUT 4'h1 // Address 0x04 +`define GPIO_RGPIO_OE 4'h2 // Address 0x08 +`define GPIO_RGPIO_INTE 4'h3 // Address 0x0c +`define GPIO_RGPIO_PTRIG 4'h4 // Address 0x10 + +`ifdef GPIO_AUX_IMPLEMENT +`define GPIO_RGPIO_AUX 4'h5 // Address 0x14 +`endif // GPIO_AUX_IMPLEMENT + +`define GPIO_RGPIO_CTRL 4'h6 // Address 0x18 +`define GPIO_RGPIO_INTS 4'h7 // Address 0x1c + +`ifdef GPIO_CLKPAD +`define GPIO_RGPIO_ECLK 4'h8 // Address 0x20 +`define GPIO_RGPIO_NEC 4'h9 // Address 0x24 +`endif // GPIO_CLKPAD + +// +// Default values for unimplemented GPIO registers +// +`define GPIO_DEF_RGPIO_IN `GPIO_IOS'h0 +`define GPIO_DEF_RGPIO_OUT `GPIO_IOS'h0 +`define GPIO_DEF_RGPIO_OE `GPIO_IOS'h0 +`define GPIO_DEF_RGPIO_INTE `GPIO_IOS'h0 +`define GPIO_DEF_RGPIO_PTRIG `GPIO_IOS'h0 +`define GPIO_DEF_RGPIO_AUX `GPIO_IOS'h0 +`define GPIO_DEF_RGPIO_CTRL `GPIO_IOS'h0 +`define GPIO_DEF_RGPIO_ECLK `GPIO_IOS'h0 +`define GPIO_DEF_RGPIO_NEC `GPIO_IOS'h0 + + +// +// RGPIO_CTRL bits +// +// To comply with the GPIO IP core specification document they must go from +// bit 0 to bit 1 in the following order: INTE, INT +// +`define GPIO_RGPIO_CTRL_INTE 0 +`define GPIO_RGPIO_CTRL_INTS 1 + + Index: gpio/rtl/gpio_top.v =================================================================== --- gpio/rtl/gpio_top.v (nonexistent) +++ gpio/rtl/gpio_top.v (revision 42) @@ -0,0 +1,1135 @@ +////////////////////////////////////////////////////////////////////// +//// //// +//// WISHBONE General-Purpose I/O //// +//// //// +//// This file is part of the GPIO project //// +//// http://www.opencores.org/cores/gpio/ //// +//// //// +//// Description //// +//// Implementation of GPIO IP core according to //// +//// GPIO IP core specification document. //// +//// //// +//// To Do: //// +//// Nothing //// +//// //// +//// Author(s): //// +//// - Damjan Lampret, lampret@opencores.org //// +//// //// +////////////////////////////////////////////////////////////////////// +//// //// +//// Copyright (C) 2000 Authors and OPENCORES.ORG //// +//// //// +//// This source file may be used and distributed without //// +//// restriction provided that this copyright statement is not //// +//// removed from the file and that any derivative work contains //// +//// the original copyright notice and the associated disclaimer. //// +//// //// +//// This source file is free software; you can redistribute it //// +//// and/or modify it under the terms of the GNU Lesser General //// +//// Public License as published by the Free Software Foundation; //// +//// either version 2.1 of the License, or (at your option) any //// +//// later version. //// +//// //// +//// This source is distributed in the hope that it will be //// +//// useful, but WITHOUT ANY WARRANTY; without even the implied //// +//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR //// +//// PURPOSE. See the GNU Lesser General Public License for more //// +//// details. //// +//// //// +//// You should have received a copy of the GNU Lesser General //// +//// Public License along with this source; if not, download it //// +//// from http://www.opencores.org/lgpl.shtml //// +//// //// +////////////////////////////////////////////////////////////////////// +// +// CVS Revision History +// +// $Log: not supported by cvs2svn $ +// Revision 1.17 2004/05/05 08:21:00 andreje +// Bugfixes when GPIO_RGPIO_ECLK/GPIO_RGPIO_NEC disabled, gpio oe name change and set to active-high according to spec +// +// Revision 1.16 2003/12/17 13:00:52 gorand +// added ECLK and NEC registers, all tests passed. +// +// Revision 1.15 2003/11/10 23:21:22 gorand +// bug fixed. all tests passed. +// +// Revision 1.14 2003/11/06 13:59:07 gorand +// added support for 8-bit access to registers. +// +// Revision 1.13 2002/11/18 22:35:18 lampret +// Bug fix. Interrupts were also asserted when condition was not met. +// +// Revision 1.12 2002/11/11 21:36:28 lampret +// Added ifdef to remove mux from clk_pad_i if mux is not allowed. This also removes RGPIO_CTRL[NEC]. +// +// Revision 1.11 2002/03/13 20:56:28 lampret +// Removed zero padding as per Avi Shamli suggestion. +// +// Revision 1.10 2002/03/13 20:47:57 lampret +// Ports changed per Ran Aviram suggestions. +// +// Revision 1.9 2002/03/09 03:43:27 lampret +// Interrupt is asserted only when an input changes (code patch by Jacob Gorban) +// +// Revision 1.8 2002/01/14 19:06:28 lampret +// Changed registered WISHBONE outputs wb_ack_o/wb_err_o to follow WB specification. +// +// Revision 1.7 2001/12/25 17:21:21 lampret +// Fixed two typos. +// +// Revision 1.6 2001/12/25 17:12:35 lampret +// Added RGPIO_INTS. +// +// Revision 1.5 2001/12/12 20:35:53 lampret +// Fixing style. +// +// Revision 1.4 2001/12/12 07:12:58 lampret +// Fixed bug when wb_inta_o is registered (GPIO_WB_REGISTERED_OUTPUTS) +// +// Revision 1.3 2001/11/15 02:24:37 lampret +// Added GPIO_REGISTERED_WB_OUTPUTS, GPIO_REGISTERED_IO_OUTPUTS and GPIO_NO_NEGEDGE_FLOPS. +// +// Revision 1.2 2001/10/31 02:26:51 lampret +// Fixed wb_err_o. +// +// Revision 1.1 2001/09/18 18:49:07 lampret +// Changed top level ptc into gpio_top. Changed defines.v into gpio_defines.v. +// +// Revision 1.1 2001/08/21 21:39:28 lampret +// Changed directory structure, port names and drfines. +// +// Revision 1.2 2001/07/14 20:39:26 lampret +// Better configurability. +// +// Revision 1.1 2001/06/05 07:45:26 lampret +// Added initial RTL and test benches. There are still some issues with these files. +// +// + +// synopsys translate_off +`include "timescale.v" +// synopsys translate_on +`include "gpio_defines.v" + +module gpio_top( + // WISHBONE Interface + wb_clk_i, wb_rst_i, wb_cyc_i, wb_adr_i, wb_dat_i, wb_sel_i, wb_we_i, wb_stb_i, + wb_dat_o, wb_ack_o, wb_err_o, wb_inta_o, + +`ifdef GPIO_AUX_IMPLEMENT + // Auxiliary inputs interface + aux_i, +`endif // GPIO_AUX_IMPLEMENT + + // External GPIO Interface + ext_pad_i, ext_pad_o, ext_padoe_o +`ifdef GPIO_CLKPAD + , clk_pad_i +`endif +); + +parameter dw = 32; +parameter aw = `GPIO_ADDRHH+1; +parameter gw = `GPIO_IOS; +// +// WISHBONE Interface +// +input wb_clk_i; // Clock +input wb_rst_i; // Reset +input wb_cyc_i; // cycle valid input +input [aw-1:0] wb_adr_i; // address bus inputs +input [dw-1:0] wb_dat_i; // input data bus +input [3:0] wb_sel_i; // byte select inputs +input wb_we_i; // indicates write transfer +input wb_stb_i; // strobe input +output [dw-1:0] wb_dat_o; // output data bus +output wb_ack_o; // normal termination +output wb_err_o; // termination w/ error +output wb_inta_o; // Interrupt request output + +`ifdef GPIO_AUX_IMPLEMENT +// Auxiliary Inputs Interface +input [gw-1:0] aux_i; // Auxiliary inputs +`endif // GPIO_AUX_IMPLEMENT + +// +// External GPIO Interface +// +input [gw-1:0] ext_pad_i; // GPIO Inputs +`ifdef GPIO_CLKPAD +input clk_pad_i; // GPIO Eclk +`endif // GPIO_CLKPAD +output [gw-1:0] ext_pad_o; // GPIO Outputs +output [gw-1:0] ext_padoe_o; // GPIO output drivers enables + +`ifdef GPIO_IMPLEMENTED + +// +// GPIO Input Register (or no register) +// +`ifdef GPIO_RGPIO_IN +reg [gw-1:0] rgpio_in; // RGPIO_IN register +`else +wire [gw-1:0] rgpio_in; // No register +`endif + +// +// GPIO Output Register (or no register) +// +`ifdef GPIO_RGPIO_OUT +reg [gw-1:0] rgpio_out; // RGPIO_OUT register +`else +wire [gw-1:0] rgpio_out; // No register +`endif + +// +// GPIO Output Driver Enable Register (or no register) +// +`ifdef GPIO_RGPIO_OE +reg [gw-1:0] rgpio_oe; // RGPIO_OE register +`else +wire [gw-1:0] rgpio_oe; // No register +`endif + +// +// GPIO Interrupt Enable Register (or no register) +// +`ifdef GPIO_RGPIO_INTE +reg [gw-1:0] rgpio_inte; // RGPIO_INTE register +`else +wire [gw-1:0] rgpio_inte; // No register +`endif + +// +// GPIO Positive edge Triggered Register (or no register) +// +`ifdef GPIO_RGPIO_PTRIG +reg [gw-1:0] rgpio_ptrig; // RGPIO_PTRIG register +`else +wire [gw-1:0] rgpio_ptrig; // No register +`endif + +// +// GPIO Auxiliary select Register (or no register) +// +`ifdef GPIO_RGPIO_AUX +reg [gw-1:0] rgpio_aux; // RGPIO_AUX register +`else +wire [gw-1:0] rgpio_aux; // No register +`endif + +// +// GPIO Control Register (or no register) +// +`ifdef GPIO_RGPIO_CTRL +reg [1:0] rgpio_ctrl; // RGPIO_CTRL register +`else +wire [1:0] rgpio_ctrl; // No register +`endif + +// +// GPIO Interrupt Status Register (or no register) +// +`ifdef GPIO_RGPIO_INTS +reg [gw-1:0] rgpio_ints; // RGPIO_INTS register +`else +wire [gw-1:0] rgpio_ints; // No register +`endif + +// +// GPIO Enable Clock Register (or no register) +// +`ifdef GPIO_RGPIO_ECLK +reg [gw-1:0] rgpio_eclk; // RGPIO_ECLK register +`else +wire [gw-1:0] rgpio_eclk; // No register +`endif + +// +// GPIO Active Negative Edge Register (or no register) +// +`ifdef GPIO_RGPIO_NEC +reg [gw-1:0] rgpio_nec; // RGPIO_NEC register +`else +wire [gw-1:0] rgpio_nec; // No register +`endif + + +// +// Synchronization flops for input signals +// +`ifdef GPIO_SYNC_IN_WB +reg [gw-1:0] sync , + ext_pad_s ; +`else +wire [gw-1:0] ext_pad_s ; +`endif + + + +// +// Internal wires & regs +// +wire rgpio_out_sel; // RGPIO_OUT select +wire rgpio_oe_sel; // RGPIO_OE select +wire rgpio_inte_sel; // RGPIO_INTE select +wire rgpio_ptrig_sel;// RGPIO_PTRIG select +wire rgpio_aux_sel; // RGPIO_AUX select +wire rgpio_ctrl_sel; // RGPIO_CTRL select +wire rgpio_ints_sel; // RGPIO_INTS select +wire rgpio_eclk_sel ; +wire rgpio_nec_sel ; +wire full_decoding; // Full address decoding qualification +wire [gw-1:0] in_muxed; // Muxed inputs +wire wb_ack; // WB Acknowledge +wire wb_err; // WB Error +wire wb_inta; // WB Interrupt +reg [dw-1:0] wb_dat; // WB Data out +`ifdef GPIO_REGISTERED_WB_OUTPUTS +reg wb_ack_o; // WB Acknowledge +reg wb_err_o; // WB Error +reg wb_inta_o; // WB Interrupt +reg [dw-1:0] wb_dat_o; // WB Data out +`endif +wire [gw-1:0] out_pad; // GPIO Outputs +`ifdef GPIO_REGISTERED_IO_OUTPUTS +reg [gw-1:0] ext_pad_o; // GPIO Outputs +`endif +`ifdef GPIO_CLKPAD +wire [gw-1:0] extc_in; // Muxed inputs sampled by external clock +wire [gw-1:0] pext_clk; // External clock for posedge flops +reg [gw-1:0] pextc_sampled; // Posedge external clock sampled inputs +`ifdef GPIO_NO_NEGEDGE_FLOPS +`ifdef GPIO_NO_CLKPAD_LOGIC +`else +reg [gw-1:0] nextc_sampled; // Negedge external clock sampled inputs +`endif // GPIO_NO_CLKPAD_LOGIC +`else +reg [gw-1:0] nextc_sampled; // Negedge external clock sampled inputs +`endif +`endif // GPIO_CLKPAD + + +// +// All WISHBONE transfer terminations are successful except when: +// a) full address decoding is enabled and address doesn't match +// any of the GPIO registers +// b) wb_sel_i evaluation is enabled and one of the wb_sel_i inputs is zero +// + +// +// WB Acknowledge +// +assign wb_ack = wb_cyc_i & wb_stb_i & !wb_err_o; + +// +// Optional registration of WB Ack +// +`ifdef GPIO_REGISTERED_WB_OUTPUTS +always @(posedge wb_clk_i or posedge wb_rst_i) + if (wb_rst_i) + wb_ack_o <= #1 1'b0; + else + wb_ack_o <= #1 wb_ack & ~wb_ack_o & (!wb_err) ; +`else +assign wb_ack_o = wb_ack; +`endif + +// +// WB Error +// +`ifdef GPIO_FULL_DECODE +`ifdef GPIO_STRICT_32BIT_ACCESS +assign wb_err = wb_cyc_i & wb_stb_i & (!full_decoding | (wb_sel_i != 4'b1111)); +`else +assign wb_err = wb_cyc_i & wb_stb_i & !full_decoding; +`endif +`else +`ifdef GPIO_STRICT_32BIT_ACCESS +assign wb_err = wb_cyc_i & wb_stb_i & (wb_sel_i != 4'b1111); +`else +assign wb_err = 1'b0; +`endif +`endif + +// +// Optional registration of WB error +// +`ifdef GPIO_REGISTERED_WB_OUTPUTS +always @(posedge wb_clk_i or posedge wb_rst_i) + if (wb_rst_i) + wb_err_o <= #1 1'b0; + else + wb_err_o <= #1 wb_err & ~wb_err_o; +`else +assign wb_err_o = wb_err; +`endif + +// +// Full address decoder +// +`ifdef GPIO_FULL_DECODE +assign full_decoding = (wb_adr_i[`GPIO_ADDRHH:`GPIO_ADDRHL] == {`GPIO_ADDRHH-`GPIO_ADDRHL+1{1'b0}}) & + (wb_adr_i[`GPIO_ADDRLH:`GPIO_ADDRLL] == {`GPIO_ADDRLH-`GPIO_ADDRLL+1{1'b0}}); +`else +assign full_decoding = 1'b1; +`endif + +// +// GPIO registers address decoder +// +`ifdef GPIO_RGPIO_OUT +assign rgpio_out_sel = wb_cyc_i & wb_stb_i & (wb_adr_i[`GPIO_OFS_BITS] == `GPIO_RGPIO_OUT) & full_decoding; +`endif +`ifdef GPIO_RGPIO_OE +assign rgpio_oe_sel = wb_cyc_i & wb_stb_i & (wb_adr_i[`GPIO_OFS_BITS] == `GPIO_RGPIO_OE) & full_decoding; +`endif +`ifdef GPIO_RGPIO_INTE +assign rgpio_inte_sel = wb_cyc_i & wb_stb_i & (wb_adr_i[`GPIO_OFS_BITS] == `GPIO_RGPIO_INTE) & full_decoding; +`endif +`ifdef GPIO_RGPIO_PTRIG +assign rgpio_ptrig_sel = wb_cyc_i & wb_stb_i & (wb_adr_i[`GPIO_OFS_BITS] == `GPIO_RGPIO_PTRIG) & full_decoding; +`endif +`ifdef GPIO_RGPIO_AUX +assign rgpio_aux_sel = wb_cyc_i & wb_stb_i & (wb_adr_i[`GPIO_OFS_BITS] == `GPIO_RGPIO_AUX) & full_decoding; +`endif +`ifdef GPIO_RGPIO_CTRL +assign rgpio_ctrl_sel = wb_cyc_i & wb_stb_i & (wb_adr_i[`GPIO_OFS_BITS] == `GPIO_RGPIO_CTRL) & full_decoding; +`endif +`ifdef GPIO_RGPIO_INTS +assign rgpio_ints_sel = wb_cyc_i & wb_stb_i & (wb_adr_i[`GPIO_OFS_BITS] == `GPIO_RGPIO_INTS) & full_decoding; +`endif +`ifdef GPIO_RGPIO_ECLK +assign rgpio_eclk_sel = wb_cyc_i & wb_stb_i & (wb_adr_i[`GPIO_OFS_BITS] == `GPIO_RGPIO_ECLK) & full_decoding; +`endif +`ifdef GPIO_RGPIO_NEC +assign rgpio_nec_sel = wb_cyc_i & wb_stb_i & (wb_adr_i[`GPIO_OFS_BITS] == `GPIO_RGPIO_NEC) & full_decoding; +`endif + + +// +// Write to RGPIO_CTRL or update of RGPIO_CTRL[INT] bit +// +`ifdef GPIO_RGPIO_CTRL +always @(posedge wb_clk_i or posedge wb_rst_i) + if (wb_rst_i) + rgpio_ctrl <= #1 2'b0; + else if (rgpio_ctrl_sel && wb_we_i) + rgpio_ctrl <= #1 wb_dat_i[1:0]; + else if (rgpio_ctrl[`GPIO_RGPIO_CTRL_INTE]) + rgpio_ctrl[`GPIO_RGPIO_CTRL_INTS] <= #1 rgpio_ctrl[`GPIO_RGPIO_CTRL_INTS] | wb_inta_o; +`else +assign rgpio_ctrl = 2'h01; // RGPIO_CTRL[EN] = 1 +`endif + +// +// Write to RGPIO_OUT +// +`ifdef GPIO_RGPIO_OUT +always @(posedge wb_clk_i or posedge wb_rst_i) + if (wb_rst_i) + rgpio_out <= #1 {gw{1'b0}}; + else if (rgpio_out_sel && wb_we_i) + begin +`ifdef GPIO_STRICT_32BIT_ACCESS + rgpio_out <= #1 wb_dat_i[gw-1:0]; +`endif + +`ifdef GPIO_WB_BYTES4 + if ( wb_sel_i [3] == 1'b1 ) + rgpio_out [gw-1:24] <= #1 wb_dat_i [gw-1:24] ; + if ( wb_sel_i [2] == 1'b1 ) + rgpio_out [23:16] <= #1 wb_dat_i [23:16] ; + if ( wb_sel_i [1] == 1'b1 ) + rgpio_out [15:8] <= #1 wb_dat_i [15:8] ; + if ( wb_sel_i [0] == 1'b1 ) + rgpio_out [7:0] <= #1 wb_dat_i [7:0] ; +`endif +`ifdef GPIO_WB_BYTES3 + if ( wb_sel_i [2] == 1'b1 ) + rgpio_out [gw-1:16] <= #1 wb_dat_i [gw-1:16] ; + if ( wb_sel_i [1] == 1'b1 ) + rgpio_out [15:8] <= #1 wb_dat_i [15:8] ; + if ( wb_sel_i [0] == 1'b1 ) + rgpio_out [7:0] <= #1 wb_dat_i [7:0] ; +`endif +`ifdef GPIO_WB_BYTES2 + if ( wb_sel_i [1] == 1'b1 ) + rgpio_out [gw-1:8] <= #1 wb_dat_i [gw-1:8] ; + if ( wb_sel_i [0] == 1'b1 ) + rgpio_out [7:0] <= #1 wb_dat_i [7:0] ; +`endif +`ifdef GPIO_WB_BYTES1 + if ( wb_sel_i [0] == 1'b1 ) + rgpio_out [gw-1:0] <= #1 wb_dat_i [gw-1:0] ; +`endif + end + +`else +assign rgpio_out = `GPIO_DEF_RGPIO_OUT; // RGPIO_OUT = 0x0 +`endif + +// +// Write to RGPIO_OE. +// +`ifdef GPIO_RGPIO_OE +always @(posedge wb_clk_i or posedge wb_rst_i) + if (wb_rst_i) + rgpio_oe <= #1 {gw{1'b0}}; + else if (rgpio_oe_sel && wb_we_i) + begin +`ifdef GPIO_STRICT_32BIT_ACCESS + rgpio_oe <= #1 wb_dat_i[gw-1:0]; +`endif + +`ifdef GPIO_WB_BYTES4 + if ( wb_sel_i [3] == 1'b1 ) + rgpio_oe [gw-1:24] <= #1 wb_dat_i [gw-1:24] ; + if ( wb_sel_i [2] == 1'b1 ) + rgpio_oe [23:16] <= #1 wb_dat_i [23:16] ; + if ( wb_sel_i [1] == 1'b1 ) + rgpio_oe [15:8] <= #1 wb_dat_i [15:8] ; + if ( wb_sel_i [0] == 1'b1 ) + rgpio_oe [7:0] <= #1 wb_dat_i [7:0] ; +`endif +`ifdef GPIO_WB_BYTES3 + if ( wb_sel_i [2] == 1'b1 ) + rgpio_oe [gw-1:16] <= #1 wb_dat_i [gw-1:16] ; + if ( wb_sel_i [1] == 1'b1 ) + rgpio_oe [15:8] <= #1 wb_dat_i [15:8] ; + if ( wb_sel_i [0] == 1'b1 ) + rgpio_oe [7:0] <= #1 wb_dat_i [7:0] ; +`endif +`ifdef GPIO_WB_BYTES2 + if ( wb_sel_i [1] == 1'b1 ) + rgpio_oe [gw-1:8] <= #1 wb_dat_i [gw-1:8] ; + if ( wb_sel_i [0] == 1'b1 ) + rgpio_oe [7:0] <= #1 wb_dat_i [7:0] ; +`endif +`ifdef GPIO_WB_BYTES1 + if ( wb_sel_i [0] == 1'b1 ) + rgpio_oe [gw-1:0] <= #1 wb_dat_i [gw-1:0] ; +`endif + end + +`else +assign rgpio_oe = `GPIO_DEF_RGPIO_OE; // RGPIO_OE = 0x0 +`endif + +// +// Write to RGPIO_INTE +// +`ifdef GPIO_RGPIO_INTE +always @(posedge wb_clk_i or posedge wb_rst_i) + if (wb_rst_i) + rgpio_inte <= #1 {gw{1'b0}}; + else if (rgpio_inte_sel && wb_we_i) + begin +`ifdef GPIO_STRICT_32BIT_ACCESS + rgpio_inte <= #1 wb_dat_i[gw-1:0]; +`endif + +`ifdef GPIO_WB_BYTES4 + if ( wb_sel_i [3] == 1'b1 ) + rgpio_inte [gw-1:24] <= #1 wb_dat_i [gw-1:24] ; + if ( wb_sel_i [2] == 1'b1 ) + rgpio_inte [23:16] <= #1 wb_dat_i [23:16] ; + if ( wb_sel_i [1] == 1'b1 ) + rgpio_inte [15:8] <= #1 wb_dat_i [15:8] ; + if ( wb_sel_i [0] == 1'b1 ) + rgpio_inte [7:0] <= #1 wb_dat_i [7:0] ; +`endif +`ifdef GPIO_WB_BYTES3 + if ( wb_sel_i [2] == 1'b1 ) + rgpio_inte [gw-1:16] <= #1 wb_dat_i [gw-1:16] ; + if ( wb_sel_i [1] == 1'b1 ) + rgpio_inte [15:8] <= #1 wb_dat_i [15:8] ; + if ( wb_sel_i [0] == 1'b1 ) + rgpio_inte [7:0] <= #1 wb_dat_i [7:0] ; +`endif +`ifdef GPIO_WB_BYTES2 + if ( wb_sel_i [1] == 1'b1 ) + rgpio_inte [gw-1:8] <= #1 wb_dat_i [gw-1:8] ; + if ( wb_sel_i [0] == 1'b1 ) + rgpio_inte [7:0] <= #1 wb_dat_i [7:0] ; +`endif +`ifdef GPIO_WB_BYTES1 + if ( wb_sel_i [0] == 1'b1 ) + rgpio_inte [gw-1:0] <= #1 wb_dat_i [gw-1:0] ; +`endif + end + + +`else +assign rgpio_inte = `GPIO_DEF_RGPIO_INTE; // RGPIO_INTE = 0x0 +`endif + +// +// Write to RGPIO_PTRIG +// +`ifdef GPIO_RGPIO_PTRIG +always @(posedge wb_clk_i or posedge wb_rst_i) + if (wb_rst_i) + rgpio_ptrig <= #1 {gw{1'b0}}; + else if (rgpio_ptrig_sel && wb_we_i) + begin +`ifdef GPIO_STRICT_32BIT_ACCESS + rgpio_ptrig <= #1 wb_dat_i[gw-1:0]; +`endif + +`ifdef GPIO_WB_BYTES4 + if ( wb_sel_i [3] == 1'b1 ) + rgpio_ptrig [gw-1:24] <= #1 wb_dat_i [gw-1:24] ; + if ( wb_sel_i [2] == 1'b1 ) + rgpio_ptrig [23:16] <= #1 wb_dat_i [23:16] ; + if ( wb_sel_i [1] == 1'b1 ) + rgpio_ptrig [15:8] <= #1 wb_dat_i [15:8] ; + if ( wb_sel_i [0] == 1'b1 ) + rgpio_ptrig [7:0] <= #1 wb_dat_i [7:0] ; +`endif +`ifdef GPIO_WB_BYTES3 + if ( wb_sel_i [2] == 1'b1 ) + rgpio_ptrig [gw-1:16] <= #1 wb_dat_i [gw-1:16] ; + if ( wb_sel_i [1] == 1'b1 ) + rgpio_ptrig [15:8] <= #1 wb_dat_i [15:8] ; + if ( wb_sel_i [0] == 1'b1 ) + rgpio_ptrig [7:0] <= #1 wb_dat_i [7:0] ; +`endif +`ifdef GPIO_WB_BYTES2 + if ( wb_sel_i [1] == 1'b1 ) + rgpio_ptrig [gw-1:8] <= #1 wb_dat_i [gw-1:8] ; + if ( wb_sel_i [0] == 1'b1 ) + rgpio_ptrig [7:0] <= #1 wb_dat_i [7:0] ; +`endif +`ifdef GPIO_WB_BYTES1 + if ( wb_sel_i [0] == 1'b1 ) + rgpio_ptrig [gw-1:0] <= #1 wb_dat_i [gw-1:0] ; +`endif + end + +`else +assign rgpio_ptrig = `GPIO_DEF_RGPIO_PTRIG; // RGPIO_PTRIG = 0x0 +`endif + +// +// Write to RGPIO_AUX +// +`ifdef GPIO_RGPIO_AUX +always @(posedge wb_clk_i or posedge wb_rst_i) + if (wb_rst_i) + rgpio_aux <= #1 {gw{1'b0}}; + else if (rgpio_aux_sel && wb_we_i) + begin +`ifdef GPIO_STRICT_32BIT_ACCESS + rgpio_aux <= #1 wb_dat_i[gw-1:0]; +`endif + +`ifdef GPIO_WB_BYTES4 + if ( wb_sel_i [3] == 1'b1 ) + rgpio_aux [gw-1:24] <= #1 wb_dat_i [gw-1:24] ; + if ( wb_sel_i [2] == 1'b1 ) + rgpio_aux [23:16] <= #1 wb_dat_i [23:16] ; + if ( wb_sel_i [1] == 1'b1 ) + rgpio_aux [15:8] <= #1 wb_dat_i [15:8] ; + if ( wb_sel_i [0] == 1'b1 ) + rgpio_aux [7:0] <= #1 wb_dat_i [7:0] ; +`endif +`ifdef GPIO_WB_BYTES3 + if ( wb_sel_i [2] == 1'b1 ) + rgpio_aux [gw-1:16] <= #1 wb_dat_i [gw-1:16] ; + if ( wb_sel_i [1] == 1'b1 ) + rgpio_aux [15:8] <= #1 wb_dat_i [15:8] ; + if ( wb_sel_i [0] == 1'b1 ) + rgpio_aux [7:0] <= #1 wb_dat_i [7:0] ; +`endif +`ifdef GPIO_WB_BYTES2 + if ( wb_sel_i [1] == 1'b1 ) + rgpio_aux [gw-1:8] <= #1 wb_dat_i [gw-1:8] ; + if ( wb_sel_i [0] == 1'b1 ) + rgpio_aux [7:0] <= #1 wb_dat_i [7:0] ; +`endif +`ifdef GPIO_WB_BYTES1 + if ( wb_sel_i [0] == 1'b1 ) + rgpio_aux [gw-1:0] <= #1 wb_dat_i [gw-1:0] ; +`endif + end + +`else +assign rgpio_aux = `GPIO_DEF_RGPIO_AUX; // RGPIO_AUX = 0x0 +`endif + + +// +// Write to RGPIO_ECLK +// +`ifdef GPIO_RGPIO_ECLK +always @(posedge wb_clk_i or posedge wb_rst_i) + if (wb_rst_i) + rgpio_eclk <= #1 {gw{1'b0}}; + else if (rgpio_eclk_sel && wb_we_i) + begin +`ifdef GPIO_STRICT_32BIT_ACCESS + rgpio_eclk <= #1 wb_dat_i[gw-1:0]; +`endif + +`ifdef GPIO_WB_BYTES4 + if ( wb_sel_i [3] == 1'b1 ) + rgpio_eclk [gw-1:24] <= #1 wb_dat_i [gw-1:24] ; + if ( wb_sel_i [2] == 1'b1 ) + rgpio_eclk [23:16] <= #1 wb_dat_i [23:16] ; + if ( wb_sel_i [1] == 1'b1 ) + rgpio_eclk [15:8] <= #1 wb_dat_i [15:8] ; + if ( wb_sel_i [0] == 1'b1 ) + rgpio_eclk [7:0] <= #1 wb_dat_i [7:0] ; +`endif +`ifdef GPIO_WB_BYTES3 + if ( wb_sel_i [2] == 1'b1 ) + rgpio_eclk [gw-1:16] <= #1 wb_dat_i [gw-1:16] ; + if ( wb_sel_i [1] == 1'b1 ) + rgpio_eclk [15:8] <= #1 wb_dat_i [15:8] ; + if ( wb_sel_i [0] == 1'b1 ) + rgpio_eclk [7:0] <= #1 wb_dat_i [7:0] ; +`endif +`ifdef GPIO_WB_BYTES2 + if ( wb_sel_i [1] == 1'b1 ) + rgpio_eclk [gw-1:8] <= #1 wb_dat_i [gw-1:8] ; + if ( wb_sel_i [0] == 1'b1 ) + rgpio_eclk [7:0] <= #1 wb_dat_i [7:0] ; +`endif +`ifdef GPIO_WB_BYTES1 + if ( wb_sel_i [0] == 1'b1 ) + rgpio_eclk [gw-1:0] <= #1 wb_dat_i [gw-1:0] ; +`endif + end + + +`else +assign rgpio_eclk = `GPIO_DEF_RGPIO_ECLK; // RGPIO_ECLK = 0x0 +`endif + + + +// +// Write to RGPIO_NEC +// +`ifdef GPIO_RGPIO_NEC +always @(posedge wb_clk_i or posedge wb_rst_i) + if (wb_rst_i) + rgpio_nec <= #1 {gw{1'b0}}; + else if (rgpio_nec_sel && wb_we_i) + begin +`ifdef GPIO_STRICT_32BIT_ACCESS + rgpio_nec <= #1 wb_dat_i[gw-1:0]; +`endif + +`ifdef GPIO_WB_BYTES4 + if ( wb_sel_i [3] == 1'b1 ) + rgpio_nec [gw-1:24] <= #1 wb_dat_i [gw-1:24] ; + if ( wb_sel_i [2] == 1'b1 ) + rgpio_nec [23:16] <= #1 wb_dat_i [23:16] ; + if ( wb_sel_i [1] == 1'b1 ) + rgpio_nec [15:8] <= #1 wb_dat_i [15:8] ; + if ( wb_sel_i [0] == 1'b1 ) + rgpio_nec [7:0] <= #1 wb_dat_i [7:0] ; +`endif +`ifdef GPIO_WB_BYTES3 + if ( wb_sel_i [2] == 1'b1 ) + rgpio_nec [gw-1:16] <= #1 wb_dat_i [gw-1:16] ; + if ( wb_sel_i [1] == 1'b1 ) + rgpio_nec [15:8] <= #1 wb_dat_i [15:8] ; + if ( wb_sel_i [0] == 1'b1 ) + rgpio_nec [7:0] <= #1 wb_dat_i [7:0] ; +`endif +`ifdef GPIO_WB_BYTES2 + if ( wb_sel_i [1] == 1'b1 ) + rgpio_nec [gw-1:8] <= #1 wb_dat_i [gw-1:8] ; + if ( wb_sel_i [0] == 1'b1 ) + rgpio_nec [7:0] <= #1 wb_dat_i [7:0] ; +`endif +`ifdef GPIO_WB_BYTES1 + if ( wb_sel_i [0] == 1'b1 ) + rgpio_nec [gw-1:0] <= #1 wb_dat_i [gw-1:0] ; +`endif + end + + +`else +assign rgpio_nec = `GPIO_DEF_RGPIO_NEC; // RGPIO_NEC = 0x0 +`endif + +// +// synchronize inputs to systam clock +// +`ifdef GPIO_SYNC_IN_WB +always @(posedge wb_clk_i or posedge wb_rst_i) + if (wb_rst_i) begin + sync <= #1 {gw{1'b0}} ; + ext_pad_s <= #1 {gw{1'b0}} ; + end else begin + sync <= #1 ext_pad_i ; + ext_pad_s <= #1 sync ; + end +`else +assign ext_pad_s = ext_pad_i; +`endif // GPIO_SYNC_IN_WB + +// +// Latch into RGPIO_IN +// +`ifdef GPIO_RGPIO_IN +always @(posedge wb_clk_i or posedge wb_rst_i) + if (wb_rst_i) + rgpio_in <= #1 {gw{1'b0}}; + else + rgpio_in <= #1 in_muxed; +`else +assign rgpio_in = in_muxed; +`endif + +`ifdef GPIO_CLKPAD + +`ifdef GPIO_SYNC_CLK_WB +// +// external clock enabled +// synchronized to system clock +// (one clock domain) +// + +reg sync_clk, + clk_s , + clk_r ; +wire pedge , + nedge ; +wire [gw-1:0] pedge_vec , + nedge_vec ; +wire [gw-1:0] in_lach ; + +assign pedge = clk_s & !clk_r ; +assign nedge = !clk_s & clk_r ; +assign pedge_vec = {gw{pedge}} ; +assign nedge_vec = {gw{nedge}} ; + +assign in_lach = (~rgpio_nec & pedge_vec) | (rgpio_nec & nedge_vec) ; +assign extc_in = (in_lach & ext_pad_s) | (~in_lach & pextc_sampled) ; + +always @(posedge wb_clk_i or posedge wb_rst_i) + if (wb_rst_i) begin + sync_clk <= #1 1'b0 ; + clk_s <= #1 1'b0 ; + clk_r <= #1 1'b0 ; + end else begin + sync_clk <= #1 clk_pad_i ; + clk_s <= #1 sync_clk ; + clk_r <= #1 clk_s ; + end + +always @(posedge wb_clk_i or posedge wb_rst_i) + if (wb_rst_i) begin + pextc_sampled <= #1 {gw{1'b0}}; + end else begin + pextc_sampled <= #1 extc_in ; + end + +assign in_muxed = (rgpio_eclk & pextc_sampled) | (~rgpio_eclk & ext_pad_s) ; + +`else +// +// external clock enabled +// not synchronized to system clock +// (two clock domains) +// + +`ifdef GPIO_SYNC_IN_CLK_WB + +reg [gw-1:0] syn_extc , + extc_s ; + +always @(posedge wb_clk_i or posedge wb_rst_i) + if (wb_rst_i) begin + syn_extc <= #1 {gw{1'b0}}; + extc_s <= #1 {gw{1'b0}}; + end else begin + syn_extc <= #1 extc_in ; + extc_s <= #1 syn_extc; + end + +`else + +wire [gw-1:0] extc_s ; +assign extc_s = syn_extc ; + +`endif // GPIO_SYNC_IN_CLK_WB + +`ifdef GPIO_SYNC_IN_CLK +reg [gw-1:0] syn_pclk , + ext_pad_spc ; + +always @(posedge clk_pad_i or posedge wb_rst_i) + if (wb_rst_i) begin + syn_pclk <= #1 {gw{1'b0}} ; + ext_pad_spc <= #1 {gw{1'b0}} ; + end else begin + syn_pclk <= #1 ext_pad_i ; + ext_pad_spc <= #1 syn_pclk ; + end + +`else + +wire [gw-1:0] ext_pad_spc ; +assign ext_pad_spc = ext_pad_i ; + +`endif // GPIO_SYNC_IN_CLK + +always @(posedge clk_pad_i or posedge wb_rst_i) + if (wb_rst_i) begin + pextc_sampled <= #1 {gw{1'b0}}; + end else begin + pextc_sampled <= #1 ext_pad_spc ; + end + + +`ifdef GPIO_NO_NEGEDGE_FLOPS + +`ifdef GPIO_NO_CLKPAD_LOGIC + +assign extc_in = pextc_sampled; + +`else + +wire clk_n; +assign clk_n = !clk_pad_i; + +`ifdef GPIO_SYNC_IN_CLK +reg [gw-1:0] syn_nclk , + ext_pad_snc ; + +always @(posedge clk_n or posedge wb_rst_i) + if (wb_rst_i) begin + syn_nclk <= #1 {gw{1'b0}} ; + ext_pad_snc <= #1 {gw{1'b0}} ; + end else begin + syn_nclk <= #1 ext_pad_i ; + ext_pad_snc <= #1 syn_nclk ; + end + +`else + +wire [gw-1:0] ext_pad_snc ; +assign ext_pad_snc = ext_pad_i ; + +`endif // GPIO_SYNC_IN_CLK + +always @(posedge clk_n or posedge wb_rst_i) + if (wb_rst_i) begin + nextc_sampled <= #1 {gw{1'b0}}; + end else begin + nextc_sampled <= #1 ext_pad_snc ; + end + +assign extc_in = (~rgpio_nec & pextc_sampled) | (rgpio_nec & nextc_sampled) ; + +`endif // GPIO_NO_CLKPAD_LOGIC + + +`else + +`ifdef GPIO_SYNC_IN_CLK +reg [gw-1:0] syn_nclk , + ext_pad_snc ; + +always @(negedge clk_n or posedge wb_rst_i) + if (wb_rst_i) begin + syn_nclk <= #1 {gw{1'b0}} ; + ext_pad_snc <= #1 {gw{1'b0}} ; + end else begin + syn_nclk <= #1 ext_pad_i ; + ext_pad_snc <= #1 syn_nclk ; + end + +`else + +wire [gw-1:0] ext_pad_snc ; +assign ext_pad_snc = ext_pad_i ; + +`endif // GPIO_SYNC_IN_CLK + +always @(negedge clk_pad_i or posedge wb_rst_i) + if (wb_rst_i) begin + nextc_sampled <= #1 {gw{1'b0}}; + end else begin + nextc_sampled <= #1 ext_pad_snc ; + end + +assign extc_in = (~rgpio_nec & pextc_sampled) | (rgpio_nec & nextc_sampled) ; + +`endif // GPIO_NO_NEGEDGE_FLOPS + +assign in_muxed = (rgpio_eclk & extc_s) | (~rgpio_eclk & ext_pad_s) ; + + +`endif // GPIO_SYNC_CLK_WB + + +`else + +assign in_muxed = ext_pad_s ; + +`endif // GPIO_CLKPAD + + + +// +// Mux all registers when doing a read of GPIO registers +// +always @(wb_adr_i or rgpio_in or rgpio_out or rgpio_oe or rgpio_inte or + rgpio_ptrig or rgpio_aux or rgpio_ctrl or rgpio_ints or rgpio_eclk or rgpio_nec) + case (wb_adr_i[`GPIO_OFS_BITS]) // synopsys full_case parallel_case +`ifdef GPIO_READREGS + `ifdef GPIO_RGPIO_OUT + `GPIO_RGPIO_OUT: begin + wb_dat[dw-1:0] = rgpio_out; + end + `endif + `ifdef GPIO_RGPIO_OE + `GPIO_RGPIO_OE: begin + wb_dat[dw-1:0] = rgpio_oe; + end + `endif + `ifdef GPIO_RGPIO_INTE + `GPIO_RGPIO_INTE: begin + wb_dat[dw-1:0] = rgpio_inte; + end + `endif + `ifdef GPIO_RGPIO_PTRIG + `GPIO_RGPIO_PTRIG: begin + wb_dat[dw-1:0] = rgpio_ptrig; + end + `endif + `ifdef GPIO_RGPIO_NEC + `GPIO_RGPIO_NEC: begin + wb_dat[dw-1:0] = rgpio_nec; + end + `endif + `ifdef GPIO_RGPIO_ECLK + `GPIO_RGPIO_ECLK: begin + wb_dat[dw-1:0] = rgpio_eclk; + end + `endif + `ifdef GPIO_RGPIO_AUX + `GPIO_RGPIO_AUX: begin + wb_dat[dw-1:0] = rgpio_aux; + end + `endif + `ifdef GPIO_RGPIO_CTRL + `GPIO_RGPIO_CTRL: begin + wb_dat[1:0] = rgpio_ctrl; + wb_dat[dw-1:2] = {dw-2{1'b0}}; + end + `endif +`endif + `ifdef GPIO_RGPIO_INTS + `GPIO_RGPIO_INTS: begin + wb_dat[dw-1:0] = rgpio_ints; + end + `endif + default: begin + wb_dat[dw-1:0] = rgpio_in; + end + endcase + +// +// WB data output +// +`ifdef GPIO_REGISTERED_WB_OUTPUTS +always @(posedge wb_clk_i or posedge wb_rst_i) + if (wb_rst_i) + wb_dat_o <= #1 {dw{1'b0}}; + else + wb_dat_o <= #1 wb_dat; +`else +assign wb_dat_o = wb_dat; +`endif + +// +// RGPIO_INTS +// +`ifdef GPIO_RGPIO_INTS +always @(posedge wb_clk_i or posedge wb_rst_i) + if (wb_rst_i) + rgpio_ints <= #1 {gw{1'b0}}; + else if (rgpio_ints_sel && wb_we_i) + rgpio_ints <= #1 wb_dat_i[gw-1:0]; + else if (rgpio_ctrl[`GPIO_RGPIO_CTRL_INTE]) + rgpio_ints <= #1 (rgpio_ints | ((in_muxed ^ rgpio_in) & ~(in_muxed ^ rgpio_ptrig)) & rgpio_inte); +`else +assign rgpio_ints = (rgpio_ints | ((in_muxed ^ rgpio_in) & ~(in_muxed ^ rgpio_ptrig)) & rgpio_inte); +`endif + +// +// Generate interrupt request +// +assign wb_inta = |rgpio_ints ? rgpio_ctrl[`GPIO_RGPIO_CTRL_INTE] : 1'b0; + +// +// Optional registration of WB interrupt +// +`ifdef GPIO_REGISTERED_WB_OUTPUTS +always @(posedge wb_clk_i or posedge wb_rst_i) + if (wb_rst_i) + wb_inta_o <= #1 1'b0; + else + wb_inta_o <= #1 wb_inta; +`else +assign wb_inta_o = wb_inta; +`endif // GPIO_REGISTERED_WB_OUTPUTS + +// +// Output enables are RGPIO_OE bits +// +assign ext_padoe_o = rgpio_oe; + +// +// Generate GPIO outputs +// +`ifdef GPIO_AUX_IMPLEMENT +assign out_pad = rgpio_out & ~rgpio_aux | aux_i & rgpio_aux; +`else +assign out_pad = rgpio_out ; +`endif // GPIO_AUX_IMPLEMENT + +// +// Optional registration of GPIO outputs +// +`ifdef GPIO_REGISTERED_IO_OUTPUTS +always @(posedge wb_clk_i or posedge wb_rst_i) + if (wb_rst_i) + ext_pad_o <= #1 {gw{1'b0}}; + else + ext_pad_o <= #1 out_pad; +`else +assign ext_pad_o = out_pad; +`endif // GPIO_REGISTERED_IO_OUTPUTS + + +`else + +// +// When GPIO is not implemented, drive all outputs as would when RGPIO_CTRL +// is cleared and WISHBONE transfers complete with errors +// +assign wb_inta_o = 1'b0; +assign wb_ack_o = 1'b0; +assign wb_err_o = wb_cyc_i & wb_stb_i; +assign ext_padoe_o = {gw{1'b1}}; +assign ext_pad_o = {gw{1'b0}}; + +// +// Read GPIO registers +// +assign wb_dat_o = {dw{1'b0}}; + +`endif // GPIO_IMPLEMENTED + +endmodule + Index: gpio/rtl/minsoc_top.ucf =================================================================== --- gpio/rtl/minsoc_top.ucf (nonexistent) +++ gpio/rtl/minsoc_top.ucf (revision 42) @@ -0,0 +1,36 @@ + +NET "clk" LOC = E12; # 50 MHz on-board clock oscillator +NET "reset" LOC = T14; # Push Button BTN_NORTH + +# UART Peripheral +NET "uart_stx" LOC = E15; # RS232 Serial port ( DTE Connector ) +NET "uart_srx" LOC = F16; # + +# GPIO +NET "io_pins<0>" LOC = R20; +NET "io_pins<1>" LOC = T19; +NET "io_pins<2>" LOC = U20; +NET "io_pins<3>" LOC = U19; +NET "io_pins<4>" LOC = V19; +NET "io_pins<5>" LOC = V20; +NET "io_pins<6>" LOC = Y22; +NET "io_pins<7>" LOC = W21; + +NET "i_pins<0>" LOC = V8; +NET "i_pins<1>" LOC = U10; +NET "i_pins<2>" LOC = U8; +NET "i_pins<3>" LOC = T9; +NET "i_pins<4>" LOC = T16; +NET "i_pins<5>" LOC = U15; +#NET "i_pins<6>" LOC = ; +NET "i_pins<7>" LOC = T15; + +################################################################################# +# Pin constraints including the IOSTANDARD and DRIVE +# Reference : Spartan-3A/3AN FPGA Starter Kit Board User Guide ( UG334 v1.1 ) +################################################################################# + +#NET "clk" LOC = E12 | IOSTANDARD = LVCMOS33; +#NET "uart_stx" LOC = E15 | IOSTANDARD = LVCMOS33 | DRIVE = 8 | SLEW = SLOW ; +#NET "uart_srx" LOC = F16 | IOSTANDARD = LVCMOS33; +#NET "reset" LOC = T14 | IOSTANDARD = LVCMOS33 | PULLDOWN ; Index: gpio/rtl/minsoc_defines.v =================================================================== --- gpio/rtl/minsoc_defines.v (nonexistent) +++ gpio/rtl/minsoc_defines.v (revision 42) @@ -0,0 +1,130 @@ +// +// Define FPGA manufacturer +// +//`define GENERIC_FPGA +//`define ALTERA_FPGA +`define XILINX_FPGA + +// +// Define FPGA Model (comment all out for ALTERA) +// +//`define SPARTAN2 +//`define SPARTAN3 +//`define SPARTAN3E +`define SPARTAN3A +//`define VIRTEX +//`define VIRTEX2 +//`define VIRTEX4 +//`define VIRTEX5 + + +// +// Memory +// +`define MEMORY_ADR_WIDTH 13 //MEMORY_ADR_WIDTH IS NOT ALLOWED TO BE LESS THAN 12, memory is composed by blocks of address width 11 + //Address width of memory -> select memory depth, 2 powers MEMORY_ADR_WIDTH defines the memory depth + //the memory data width is 32 bit, memory amount in Bytes = 4*memory depth + +// +// Memory type (uncomment something if ASIC or generic memory) +// +//`define GENERIC_MEMORY +//`define AVANT_ATP +//`define VIRAGE_SSP +//`define VIRTUALSILICON_SSP + + +// +// TAP selection +// +//`define GENERIC_TAP +`define FPGA_TAP + +// +// Clock Division selection +// +//`define NO_CLOCK_DIVISION +//`define GENERIC_CLOCK_DIVISION +`define FPGA_CLOCK_DIVISION //Altera ALTPLL is not implemented, didn't find the code for its verilog instantiation + //if you selected altera and this, the GENERIC_CLOCK_DIVISION will be automatically taken + +// +// Define division +// +`define CLOCK_DIVISOR 5 //in case of GENERIC_CLOCK_DIVISION the real value will be rounded down to an even value + //in FPGA case, check minsoc_clock_manager for allowed divisors + //DO NOT USE CLOCK_DIVISOR = 1 COMMENT THE CLOCK DIVISION SELECTION INSTEAD + +// +// Reset polarity +// +//`define NEGATIVE_RESET; //rstn +`define POSITIVE_RESET; //rst + +// +// Start-up circuit (only necessary later to load firmware automatically from SPI memory) +// +//`define START_UP + +// +// Connected modules +// +`define UART +//`define ETHERNET +`define GPIO + +// +// Ethernet reset +// +//`define ETH_RESET 1'b0 +`define ETH_RESET 1'b1 + +// +// GPIO Pins +// +`define GPIO_HAS_INPUT_PINS +//`define GPIO_HAS_OUTPUT_PINS +`define GPIO_HAS_BIDIR_PINS + +`define GPIO_NUM_INPUT 4'd8 +`define GPIO_NUM_OUTPUT 4'd0 +`define GPIO_NUM_BIDIR 4'd8 + +// +// Interrupts +// +`define APP_INT_RES1 1:0 +`define APP_INT_UART 2 +`define APP_INT_RES2 3 +`define APP_INT_ETH 4 +`define APP_INT_PS2 5 +`define APP_INT_GPIO 6 +`define APP_INT_RES3 19:7 + +// +// Address map +// +`define APP_ADDR_DEC_W 8 +`define APP_ADDR_SRAM `APP_ADDR_DEC_W'h00 +`define APP_ADDR_FLASH `APP_ADDR_DEC_W'h04 +`define APP_ADDR_DECP_W 4 +`define APP_ADDR_PERIP `APP_ADDR_DECP_W'h9 +`define APP_ADDR_SPI `APP_ADDR_DEC_W'h97 +`define APP_ADDR_ETH `APP_ADDR_DEC_W'h92 +`define APP_ADDR_AUDIO `APP_ADDR_DEC_W'h9d +`define APP_ADDR_UART `APP_ADDR_DEC_W'h90 +`define APP_ADDR_PS2 `APP_ADDR_DEC_W'h94 +`define APP_ADDR_GPIO `APP_ADDR_DEC_W'h9e +`define APP_ADDR_RES2 `APP_ADDR_DEC_W'h9f + +// +// Set-up GENERIC_TAP, GENERIC_MEMORY if GENERIC_FPGA was chosen +// and GENERIC_CLOCK_DIVISION if NO_CLOCK_DIVISION was not set +// +`ifdef GENERIC_FPGA + `define GENERIC_TAP + `define GENERIC_MEMORY + `ifndef NO_CLOCK_DIVISION + `define GENERIC_CLOCK_DIVISION + `endif +`endif Index: gpio/rtl/minsoc_spartan_3a_starter_kit_ios.v =================================================================== --- gpio/rtl/minsoc_spartan_3a_starter_kit_ios.v (nonexistent) +++ gpio/rtl/minsoc_spartan_3a_starter_kit_ios.v (revision 42) @@ -0,0 +1,224 @@ +////////////////////////////////////////////////////////////////////////////////// +// Company: +// Engineer: +// +// Create Date: 11:51:27 10/29/2009 +// Design Name: +// Module Name: minsoc_spartan_3a_starter_kit_ios +// Project Name: +// Target Devices: +// Tool versions: +// Description: +// +// Dependencies: +// +// Revision: +// Revision 0.01 - File Created +// Additional Comments: +// +////////////////////////////////////////////////////////////////////////////////// + +module minsoc_spartan_3a_starter_kit_ios +( + // Signals from GPIO Core + ext_pad_o, + ext_pad_oe, + ext_pad_i, + + // Signals driving external pins + i_pins, + o_pins, + io_pins +); + parameter gpio_num = 32; + parameter i_line_num = 8; + parameter o_line_num = 8; + parameter io_line_num= 8; + + input [gpio_num-1:0] ext_pad_o; + input [gpio_num-1:0] ext_pad_oe; + output [gpio_num-1:0] ext_pad_i; + + input [i_line_num-1:0] i_pins; + output [o_line_num-1:0] o_pins; + inout [io_line_num-1:0] io_pins; + + IOBUF #( + .DRIVE(12), // Specify the output drive strength + .IBUF_DELAY_VALUE("0"), // Specify the amount of added input delay for the buffer, "0"-"16" (Spartan-3E only) + .IFD_DELAY_VALUE("AUTO"), // Specify the amount of added delay for input register, "AUTO", "0"-"8" (Spartan-3E only) + .IOSTANDARD("DEFAULT"), // Specify the I/O standard + .SLEW("SLOW") // Specify the output slew rate + ) IOBUF_inst_0 ( + .O(ext_pad_i[0]), // Buffer output + .IO(io_pins[0]), // Buffer inout port (connect directly to top-level port) + .I(ext_pad_o[0]), // Buffer input + .T(~ext_pad_oe[0]) // 3-state enable input + ); + + IOBUF #( + .DRIVE(12), // Specify the output drive strength + .IBUF_DELAY_VALUE("0"), // Specify the amount of added input delay for the buffer, "0"-"16" (Spartan-3E only) + .IFD_DELAY_VALUE("AUTO"), // Specify the amount of added delay for input register, "AUTO", "0"-"8" (Spartan-3E only) + .IOSTANDARD("DEFAULT"), // Specify the I/O standard + .SLEW("SLOW") // Specify the output slew rate + ) IOBUF_inst_1 ( + .O(ext_pad_i[1]), // Buffer output + .IO(io_pins[1]), // Buffer inout port (connect directly to top-level port) + .I(ext_pad_o[1]), // Buffer input + .T(~ext_pad_oe[1]) // 3-state enable input + ); + + IOBUF #( + .DRIVE(12), // Specify the output drive strength + .IBUF_DELAY_VALUE("0"), // Specify the amount of added input delay for the buffer, "0"-"16" (Spartan-3E only) + .IFD_DELAY_VALUE("AUTO"), // Specify the amount of added delay for input register, "AUTO", "0"-"8" (Spartan-3E only) + .IOSTANDARD("DEFAULT"), // Specify the I/O standard + .SLEW("SLOW") // Specify the output slew rate + ) IOBUF_inst_2 ( + .O(ext_pad_i[2]), // Buffer output + .IO(io_pins[2]), // Buffer inout port (connect directly to top-level port) + .I(ext_pad_o[2]), // Buffer input + .T(~ext_pad_oe[2]) // 3-state enable input + ); + + IOBUF #( + .DRIVE(12), // Specify the output drive strength + .IBUF_DELAY_VALUE("0"), // Specify the amount of added input delay for the buffer, "0"-"16" (Spartan-3E only) + .IFD_DELAY_VALUE("AUTO"), // Specify the amount of added delay for input register, "AUTO", "0"-"8" (Spartan-3E only) + .IOSTANDARD("DEFAULT"), // Specify the I/O standard + .SLEW("SLOW") // Specify the output slew rate + ) IOBUF_inst_3 ( + .O(ext_pad_i[3]), // Buffer output + .IO(io_pins[3]), // Buffer inout port (connect directly to top-level port) + .I(ext_pad_o[3]), // Buffer input + .T(~ext_pad_oe[3]) // 3-state enable input + ); + + IOBUF #( + .DRIVE(12), // Specify the output drive strength + .IBUF_DELAY_VALUE("0"), // Specify the amount of added input delay for the buffer, "0"-"16" (Spartan-3E only) + .IFD_DELAY_VALUE("AUTO"), // Specify the amount of added delay for input register, "AUTO", "0"-"8" (Spartan-3E only) + .IOSTANDARD("DEFAULT"), // Specify the I/O standard + .SLEW("SLOW") // Specify the output slew rate + ) IOBUF_inst_4 ( + .O(ext_pad_i[4]), // Buffer output + .IO(io_pins[4]), // Buffer inout port (connect directly to top-level port) + .I(ext_pad_o[4]), // Buffer input + .T(~ext_pad_oe[4]) // 3-state enable input + ); + + IOBUF #( + .DRIVE(12), // Specify the output drive strength + .IBUF_DELAY_VALUE("0"), // Specify the amount of added input delay for the buffer, "0"-"16" (Spartan-3E only) + .IFD_DELAY_VALUE("AUTO"), // Specify the amount of added delay for input register, "AUTO", "0"-"8" (Spartan-3E only) + .IOSTANDARD("DEFAULT"), // Specify the I/O standard + .SLEW("SLOW") // Specify the output slew rate + ) IOBUF_inst_5 ( + .O(ext_pad_i[5]), // Buffer output + .IO(io_pins[5]), // Buffer inout port (connect directly to top-level port) + .I(ext_pad_o[5]), // Buffer input + .T(~ext_pad_oe[5]) // 3-state enable input + ); + + IOBUF #( + .DRIVE(12), // Specify the output drive strength + .IBUF_DELAY_VALUE("0"), // Specify the amount of added input delay for the buffer, "0"-"16" (Spartan-3E only) + .IFD_DELAY_VALUE("AUTO"), // Specify the amount of added delay for input register, "AUTO", "0"-"8" (Spartan-3E only) + .IOSTANDARD("DEFAULT"), // Specify the I/O standard + .SLEW("SLOW") // Specify the output slew rate + ) IOBUF_inst_6 ( + .O(ext_pad_i[6]), // Buffer output + .IO(io_pins[6]), // Buffer inout port (connect directly to top-level port) + .I(ext_pad_o[6]), // Buffer input + .T(~ext_pad_oe[6]) // 3-state enable input + ); + + IOBUF #( + .DRIVE(12), // Specify the output drive strength + .IBUF_DELAY_VALUE("0"), // Specify the amount of added input delay for the buffer, "0"-"16" (Spartan-3E only) + .IFD_DELAY_VALUE("AUTO"), // Specify the amount of added delay for input register, "AUTO", "0"-"8" (Spartan-3E only) + .IOSTANDARD("DEFAULT"), // Specify the I/O standard + .SLEW("SLOW") // Specify the output slew rate + ) IOBUF_inst_7 ( + .O(ext_pad_i[7]), // Buffer output + .IO(io_pins[7]), // Buffer inout port (connect directly to top-level port) + .I(ext_pad_o[7]), // Buffer input + .T(~ext_pad_oe[7]) // 3-state enable input + ); + + + IBUF #( + .IBUF_DELAY_VALUE("0"), // Specify the amount of added input delay for // the buffer, "0"-"16" (Spartan-3E/3A only) + .IFD_DELAY_VALUE("AUTO"), // Specify the amount of added delay for input // register, "AUTO", "0"-"8" (Spartan-3E/3A only) + .IOSTANDARD("DEFAULT") // Specify the input I/O standard + )IBUF_inst_0 ( + .O(ext_pad_i[8]), // Buffer output + .I(i_pins[0]) // Buffer input (connect directly to top-level port) + ); + + IBUF #( + .IBUF_DELAY_VALUE("0"), // Specify the amount of added input delay for // the buffer, "0"-"16" (Spartan-3E/3A only) + .IFD_DELAY_VALUE("AUTO"), // Specify the amount of added delay for input // register, "AUTO", "0"-"8" (Spartan-3E/3A only) + .IOSTANDARD("DEFAULT") // Specify the input I/O standard + )IBUF_inst_1 ( + .O(ext_pad_i[9]), // Buffer output + .I(i_pins[1]) // Buffer input (connect directly to top-level port) + ); + + IBUF #( + .IBUF_DELAY_VALUE("0"), // Specify the amount of added input delay for // the buffer, "0"-"16" (Spartan-3E/3A only) + .IFD_DELAY_VALUE("AUTO"), // Specify the amount of added delay for input // register, "AUTO", "0"-"8" (Spartan-3E/3A only) + .IOSTANDARD("DEFAULT") // Specify the input I/O standard + )IBUF_inst_2 ( + .O(ext_pad_i[10]), // Buffer output + .I(i_pins[2]) // Buffer input (connect directly to top-level port) + ); + + IBUF #( + .IBUF_DELAY_VALUE("0"), // Specify the amount of added input delay for // the buffer, "0"-"16" (Spartan-3E/3A only) + .IFD_DELAY_VALUE("AUTO"), // Specify the amount of added delay for input // register, "AUTO", "0"-"8" (Spartan-3E/3A only) + .IOSTANDARD("DEFAULT") // Specify the input I/O standard + )IBUF_inst_3 ( + .O(ext_pad_i[11]), // Buffer output + .I(i_pins[3]) // Buffer input (connect directly to top-level port) + ); + + IBUF #( + .IBUF_DELAY_VALUE("0"), // Specify the amount of added input delay for // the buffer, "0"-"16" (Spartan-3E/3A only) + .IFD_DELAY_VALUE("AUTO"), // Specify the amount of added delay for input // register, "AUTO", "0"-"8" (Spartan-3E/3A only) + .IOSTANDARD("DEFAULT") // Specify the input I/O standard + )IBUF_inst_4 ( + .O(ext_pad_i[12]), // Buffer output + .I(i_pins[4]) // Buffer input (connect directly to top-level port) + ); + + IBUF #( + .IBUF_DELAY_VALUE("0"), // Specify the amount of added input delay for // the buffer, "0"-"16" (Spartan-3E/3A only) + .IFD_DELAY_VALUE("AUTO"), // Specify the amount of added delay for input // register, "AUTO", "0"-"8" (Spartan-3E/3A only) + .IOSTANDARD("DEFAULT") // Specify the input I/O standard + )IBUF_inst_5 ( + .O(ext_pad_i[13]), // Buffer output + .I(i_pins[5]) // Buffer input (connect directly to top-level port) + ); + + /* PUSH Button NORTH is RESET. + IBUF #( + .IBUF_DELAY_VALUE("0"), // Specify the amount of added input delay for // the buffer, "0"-"16" (Spartan-3E/3A only) + .IFD_DELAY_VALUE("AUTO"), // Specify the amount of added delay for input // register, "AUTO", "0"-"8" (Spartan-3E/3A only) + .IOSTANDARD("DEFAULT") // Specify the input I/O standard + )IBUF_inst_6 ( + .O(ext_pad_i[14]), // Buffer output + .I(i_pins[6]) // Buffer input (connect directly to top-level port) + ); + */ + + IBUF #( + .IBUF_DELAY_VALUE("0"), // Specify the amount of added input delay for // the buffer, "0"-"16" (Spartan-3E/3A only) + .IFD_DELAY_VALUE("AUTO"), // Specify the amount of added delay for input // register, "AUTO", "0"-"8" (Spartan-3E/3A only) + .IOSTANDARD("DEFAULT") // Specify the input I/O standard + )IBUF_inst_7 ( + .O(ext_pad_i[15]), // Buffer output + .I(i_pins[7]) // Buffer input (connect directly to top-level port) + ); +endmodule Index: gpio/rtl/minsoc_top.v =================================================================== --- gpio/rtl/minsoc_top.v (nonexistent) +++ gpio/rtl/minsoc_top.v (revision 42) @@ -0,0 +1,1105 @@ +`include "minsoc_defines.v" +`include "or1200_defines.v" + +`include "gpio_defines.v" + +module minsoc_top ( + clk,reset + + //JTAG ports +`ifdef GENERIC_TAP + , jtag_tdi,jtag_tms,jtag_tck, + jtag_tdo,jtag_vref,jtag_gnd +`endif + + //SPI ports +`ifdef START_UP + , spi_flash_mosi, spi_flash_miso, spi_flash_sclk, spi_flash_ss +`endif + + //UART ports +`ifdef UART + , uart_stx,uart_srx +`endif + + // Ethernet ports +`ifdef ETHERNET + , eth_col, eth_crs, eth_trste, eth_tx_clk, + eth_tx_en, eth_tx_er, eth_txd, eth_rx_clk, + eth_rx_dv, eth_rx_er, eth_rxd, eth_fds_mdint, + eth_mdc, eth_mdio +`endif + + // GPIO ports +`ifdef GPIO + `ifdef GPIO_HAS_INPUT_PINS + ,i_pins + `endif + `ifdef GPIO_HAS_OUTPUT_PINS + ,o_pins + `endif + `ifdef GPIO_HAS_BIDIR_PINS + ,io_pins + `endif +`endif +); + +// +// I/O Ports +// + + input clk; + input reset; + +// +// SPI controller external i/f wires +// +`ifdef START_UP +output spi_flash_mosi; +input spi_flash_miso; +output spi_flash_sclk; +output [1:0] spi_flash_ss; +`endif + +// +// UART +// +`ifdef UART + output uart_stx; + input uart_srx; +`endif + +// +// Ethernet +// +`ifdef ETHERNET +output eth_tx_er; +input eth_tx_clk; +output eth_tx_en; +output [3:0] eth_txd; +input eth_rx_er; +input eth_rx_clk; +input eth_rx_dv; +input [3:0] eth_rxd; +input eth_col; +input eth_crs; +output eth_trste; +input eth_fds_mdint; +inout eth_mdio; +output eth_mdc; +`endif + +// +// GPIO +// +`ifdef GPIO + `ifdef GPIO_HAS_INPUT_PINS + input [`GPIO_NUM_INPUT-1:0] i_pins; + `endif + `ifdef GPIO_HAS_OUTPUT_PINS + output [`GPIO_NUM_OUTPUT-1:0] o_pins; + `endif + `ifdef GPIO_HAS_BIDIR_PINS + inout [`GPIO_NUM_BIDIR-1:0] io_pins; + `endif +`endif + +// +// JTAG +// +`ifdef GENERIC_TAP + input jtag_tdi; + input jtag_tms; + input jtag_tck; + output jtag_tdo; + output jtag_vref; + output jtag_gnd; + + +assign jtag_vref = 1'b1; +assign jtag_gnd = 1'b0; +`endif + +wire rstn; + +`ifdef POSITIVE_RESET +assign rstn = ~reset; +`elsif NEGATIVE_RESET +assign rstn = reset; +`endif + +// +// Internal wires +// + +// +// Debug core master i/f wires +// +wire [31:0] wb_dm_adr_o; +wire [31:0] wb_dm_dat_i; +wire [31:0] wb_dm_dat_o; +wire [3:0] wb_dm_sel_o; +wire wb_dm_we_o; +wire wb_dm_stb_o; +wire wb_dm_cyc_o; +wire wb_dm_ack_i; +wire wb_dm_err_i; + +// +// Debug <-> RISC wires +// +wire [3:0] dbg_lss; +wire [1:0] dbg_is; +wire [10:0] dbg_wp; +wire dbg_bp; +wire [31:0] dbg_dat_dbg; +wire [31:0] dbg_dat_risc; +wire [31:0] dbg_adr; +wire dbg_ewt; +wire dbg_stall; +wire [2:0] dbg_op; //dbg_op[0] = dbg_we //dbg_op[2] = dbg_stb (didn't change for backward compatibility with DBG_IF_MODEL +wire dbg_ack; + +// +// RISC instruction master i/f wires +// +wire [31:0] wb_rim_adr_o; +wire wb_rim_cyc_o; +wire [31:0] wb_rim_dat_i; +wire [31:0] wb_rim_dat_o; +wire [3:0] wb_rim_sel_o; +wire wb_rim_ack_i; +wire wb_rim_err_i; +wire wb_rim_rty_i = 1'b0; +wire wb_rim_we_o; +wire wb_rim_stb_o; +wire [31:0] wb_rif_dat_i; +wire wb_rif_ack_i; + +// +// RISC data master i/f wires +// +wire [31:0] wb_rdm_adr_o; +wire wb_rdm_cyc_o; +wire [31:0] wb_rdm_dat_i; +wire [31:0] wb_rdm_dat_o; +wire [3:0] wb_rdm_sel_o; +wire wb_rdm_ack_i; +wire wb_rdm_err_i; +wire wb_rdm_rty_i = 1'b0; +wire wb_rdm_we_o; +wire wb_rdm_stb_o; + +// +// RISC misc +// +wire [19:0] pic_ints; + +// +// Flash controller slave i/f wires +// +wire [31:0] wb_fs_dat_i; +wire [31:0] wb_fs_dat_o; +wire [31:0] wb_fs_adr_i; +wire [3:0] wb_fs_sel_i; +wire wb_fs_we_i; +wire wb_fs_cyc_i; +wire wb_fs_stb_i; +wire wb_fs_ack_o; +wire wb_fs_err_o; + +// +// SPI controller slave i/f wires +// +wire [31:0] wb_sp_dat_i; +wire [31:0] wb_sp_dat_o; +wire [31:0] wb_sp_adr_i; +wire [3:0] wb_sp_sel_i; +wire wb_sp_we_i; +wire wb_sp_cyc_i; +wire wb_sp_stb_i; +wire wb_sp_ack_o; +wire wb_sp_err_o; + +// +// SPI controller external i/f wires +// +wire spi_flash_mosi; +wire spi_flash_miso; +wire spi_flash_sclk; +wire [1:0] spi_flash_ss; + +// +// SRAM controller slave i/f wires +// +wire [31:0] wb_ss_dat_i; +wire [31:0] wb_ss_dat_o; +wire [31:0] wb_ss_adr_i; +wire [3:0] wb_ss_sel_i; +wire wb_ss_we_i; +wire wb_ss_cyc_i; +wire wb_ss_stb_i; +wire wb_ss_ack_o; +wire wb_ss_err_o; + +// +// Ethernet core master i/f wires +// +wire [31:0] wb_em_adr_o; +wire [31:0] wb_em_dat_i; +wire [31:0] wb_em_dat_o; +wire [3:0] wb_em_sel_o; +wire wb_em_we_o; +wire wb_em_stb_o; +wire wb_em_cyc_o; +wire wb_em_ack_i; +wire wb_em_err_i; + +// +// Ethernet core slave i/f wires +// +wire [31:0] wb_es_dat_i; +wire [31:0] wb_es_dat_o; +wire [31:0] wb_es_adr_i; +wire [3:0] wb_es_sel_i; +wire wb_es_we_i; +wire wb_es_cyc_i; +wire wb_es_stb_i; +wire wb_es_ack_o; +wire wb_es_err_o; + +// +// Ethernet external i/f wires +// +wire eth_mdo; +wire eth_mdoe; + +// +// UART16550 core slave i/f wires +// +wire [31:0] wb_us_dat_i; +wire [31:0] wb_us_dat_o; +wire [31:0] wb_us_adr_i; +wire [3:0] wb_us_sel_i; +wire wb_us_we_i; +wire wb_us_cyc_i; +wire wb_us_stb_i; +wire wb_us_ack_o; +wire wb_us_err_o; + +// +// UART external i/f wires +// +wire uart_stx; +wire uart_srx; + +// +// GPIO core slave i/f wires +// +wire [31:0] wb_gpio_dat_i; +wire [31:0] wb_gpio_dat_o; +wire [31:0] wb_gpio_adr_i; +wire [3:0] wb_gpio_sel_i; +wire wb_gpio_we_i; +wire wb_gpio_cyc_i; +wire wb_gpio_stb_i; +wire wb_gpio_ack_o; +wire wb_gpio_err_o; + +// +// Interface to GPIO core - Device specific core +// +wire [`GPIO_IOS:0] ext_pad_o; +wire [`GPIO_IOS:0] ext_pad_i; +wire [`GPIO_IOS:0] ext_pad_oe_o; + +// +// Reset debounce +// +reg rst_r; +reg wb_rst; + +// +// Global clock +// +wire wb_clk; + +// +// Reset debounce +// +always @(posedge wb_clk or negedge rstn) + if (~rstn) + rst_r <= 1'b1; + else + rst_r <= #1 1'b0; + +// +// Reset debounce +// +always @(posedge wb_clk) + wb_rst <= #1 rst_r; + +// +// Clock Divider +// +minsoc_clock_manager # +( + .divisor(`CLOCK_DIVISOR) +) +clk_adjust ( + .clk_i(clk), + .clk_o(wb_clk) +); + +// +// Unused WISHBONE signals +// +assign wb_us_err_o = 1'b0; +assign wb_fs_err_o = 1'b0; +assign wb_sp_err_o = 1'b0; + +// +// Unused interrupts +// +assign pic_ints[`APP_INT_RES1] = 'b0; +assign pic_ints[`APP_INT_RES2] = 'b0; +assign pic_ints[`APP_INT_RES3] = 'b0; +assign pic_ints[`APP_INT_PS2] = 'b0; + +// +// Ethernet tri-state +// +`ifdef ETHERNET +assign eth_mdio = eth_mdoe ? eth_mdo : 1'bz; +assign eth_trste = `ETH_RESET; +`endif + + +// +// RISC Instruction address for Flash +// +// Until first access to real Flash area, +// CPU instruction is fixed to jump to the Flash area. +// After Flash area is accessed, CPU instructions +// come from the tc_top (wishbone "switch"). +// +`ifdef START_UP +reg jump_flash; +reg [3:0] rif_counter; +reg [31:0] rif_dat_int; +reg rif_ack_int; + +always @(posedge wb_clk or negedge rstn) +begin + if (!rstn) begin + jump_flash <= #1 1'b1; + rif_counter <= 4'h0; + rif_ack_int <= 1'b0; + end + else begin + rif_ack_int <= 1'b0; + + if (wb_rim_cyc_o && (wb_rim_adr_o[31:32-`APP_ADDR_DEC_W] == `APP_ADDR_FLASH)) + jump_flash <= #1 1'b0; + + if ( jump_flash == 1'b1 ) begin + if ( wb_rim_cyc_o && wb_rim_stb_o && ~wb_rim_we_o ) begin + rif_counter <= rif_counter + 1'b1; + rif_ack_int <= 1'b1; + end + end + end +end + +always @ (rif_counter) +begin + case ( rif_counter ) + 4'h0: rif_dat_int = { `OR1200_OR32_MOVHI , 5'h01 , 4'h0 , 1'b0 , `APP_ADDR_FLASH , 8'h00 }; + 4'h1: rif_dat_int = { `OR1200_OR32_ORI , 5'h01 , 5'h01 , 16'h0000 }; + 4'h2: rif_dat_int = { `OR1200_OR32_JR , 10'h000 , 5'h01 , 11'h000 }; + 4'h3: rif_dat_int = { `OR1200_OR32_NOP , 10'h000 , 16'h0000 }; + default: rif_dat_int = 32'h0000_0000; + endcase +end + +assign wb_rif_dat_i = jump_flash ? rif_dat_int : wb_rim_dat_i; + +assign wb_rif_ack_i = jump_flash ? rif_ack_int : wb_rim_ack_i; + +`else +assign wb_rif_dat_i = wb_rim_dat_i; +assign wb_rif_ack_i = wb_rim_ack_i; +`endif + + +// +// TAP<->dbg_interface +// +wire jtag_tck; +wire debug_tdi; +wire debug_tdo; +wire capture_dr; +wire shift_dr; +wire pause_dr; +wire update_dr; + +wire debug_select; +wire test_logic_reset; + +// +// Instantiation of the development i/f +// +adbg_top dbg_top ( + + // JTAG pins + .tck_i ( jtag_tck ), + .tdi_i ( debug_tdi ), + .tdo_o ( debug_tdo ), + .rst_i ( test_logic_reset ), //cable without rst + + // Boundary Scan signals + .capture_dr_i ( capture_dr ), + .shift_dr_i ( shift_dr ), + .pause_dr_i ( pause_dr ), + .update_dr_i ( update_dr ), + + .debug_select_i( debug_select ), + // WISHBONE common + .wb_clk_i ( wb_clk ), + + // WISHBONE master interface + .wb_adr_o ( wb_dm_adr_o ), + .wb_dat_i ( wb_dm_dat_i ), + .wb_dat_o ( wb_dm_dat_o ), + .wb_sel_o ( wb_dm_sel_o ), + .wb_we_o ( wb_dm_we_o ), + .wb_stb_o ( wb_dm_stb_o ), + .wb_cyc_o ( wb_dm_cyc_o ), + .wb_ack_i ( wb_dm_ack_i ), + .wb_err_i ( wb_dm_err_i ), + .wb_cti_o ( ), + .wb_bte_o ( ), + + // RISC signals + .cpu0_clk_i ( wb_clk ), + .cpu0_addr_o ( dbg_adr ), + .cpu0_data_i ( dbg_dat_risc ), + .cpu0_data_o ( dbg_dat_dbg ), + .cpu0_bp_i ( dbg_bp ), + .cpu0_stall_o( dbg_stall ), + .cpu0_stb_o ( dbg_op[2] ), + .cpu0_we_o ( dbg_op[0] ), + .cpu0_ack_i ( dbg_ack ), + .cpu0_rst_o ( ) + +); + +// +// JTAG TAP controller instantiation +// +`ifdef GENERIC_TAP +tap_top tap_top( + // JTAG pads + .tms_pad_i(jtag_tms), + .tck_pad_i(jtag_tck), + .trstn_pad_i(rstn), + .tdi_pad_i(jtag_tdi), + .tdo_pad_o(jtag_tdo), + .tdo_padoe_o( ), + + // TAP states + .test_logic_reset_o( test_logic_reset ), + .run_test_idle_o(), + .shift_dr_o(shift_dr), + .pause_dr_o(pause_dr), + .update_dr_o(update_dr), + .capture_dr_o(capture_dr), + + // Select signals for boundary scan or mbist + .extest_select_o(), + .sample_preload_select_o(), + .mbist_select_o(), + .debug_select_o(debug_select), + + // TDO signal that is connected to TDI of sub-modules. + .tdi_o(debug_tdi), + + // TDI signals from sub-modules + .debug_tdo_i(debug_tdo), // from debug module + .bs_chain_tdo_i(1'b0), // from Boundary Scan Chain + .mbist_tdo_i(1'b0) // from Mbist Chain +); +`elsif FPGA_TAP +`ifdef ALTERA_FPGA +altera_virtual_jtag tap_top( + .tck_o(jtag_tck), + .debug_tdo_o(debug_tdo), + .tdi_o(debug_tdi), + .test_logic_reset_o(test_logic_reset), + .run_test_idle_o(), + .shift_dr_o(shift_dr), + .capture_dr_o(capture_dr), + .pause_dr_o(pause_dr), + .update_dr_o(update_dr), + .debug_select_o(debug_select) +); +`elsif XILINX_FPGA +minsoc_xilinx_internal_jtag tap_top( + .tck_o( jtag_tck ), + .debug_tdo_i( debug_tdo ), + .tdi_o( debug_tdi ), + + .test_logic_reset_o( test_logic_reset ), + .run_test_idle_o( ), + + .shift_dr_o( shift_dr ), + .capture_dr_o( capture_dr ), + .pause_dr_o( pause_dr ), + .update_dr_o( update_dr ), + .debug_select_o( debug_select ) +); +`endif // !FPGA_TAP + +`endif // !GENERIC_TAP + +// +// Instantiation of the OR1200 RISC +// +or1200_top or1200_top ( + + // Common + .rst_i ( wb_rst ), + .clk_i ( wb_clk ), +`ifdef OR1200_CLMODE_1TO2 + .clmode_i ( 2'b01 ), +`else +`ifdef OR1200_CLMODE_1TO4 + .clmode_i ( 2'b11 ), +`else + .clmode_i ( 2'b00 ), +`endif +`endif + + // WISHBONE Instruction Master + .iwb_clk_i ( wb_clk ), + .iwb_rst_i ( wb_rst ), + .iwb_cyc_o ( wb_rim_cyc_o ), + .iwb_adr_o ( wb_rim_adr_o ), + .iwb_dat_i ( wb_rif_dat_i ), + .iwb_dat_o ( wb_rim_dat_o ), + .iwb_sel_o ( wb_rim_sel_o ), + .iwb_ack_i ( wb_rif_ack_i ), + .iwb_err_i ( wb_rim_err_i ), + .iwb_rty_i ( wb_rim_rty_i ), + .iwb_we_o ( wb_rim_we_o ), + .iwb_stb_o ( wb_rim_stb_o ), + + // WISHBONE Data Master + .dwb_clk_i ( wb_clk ), + .dwb_rst_i ( wb_rst ), + .dwb_cyc_o ( wb_rdm_cyc_o ), + .dwb_adr_o ( wb_rdm_adr_o ), + .dwb_dat_i ( wb_rdm_dat_i ), + .dwb_dat_o ( wb_rdm_dat_o ), + .dwb_sel_o ( wb_rdm_sel_o ), + .dwb_ack_i ( wb_rdm_ack_i ), + .dwb_err_i ( wb_rdm_err_i ), + .dwb_rty_i ( wb_rdm_rty_i ), + .dwb_we_o ( wb_rdm_we_o ), + .dwb_stb_o ( wb_rdm_stb_o ), + + // Debug + .dbg_stall_i ( dbg_stall ), + .dbg_dat_i ( dbg_dat_dbg ), + .dbg_adr_i ( dbg_adr ), + .dbg_ewt_i ( 1'b0 ), + .dbg_lss_o ( dbg_lss ), + .dbg_is_o ( dbg_is ), + .dbg_wp_o ( dbg_wp ), + .dbg_bp_o ( dbg_bp ), + .dbg_dat_o ( dbg_dat_risc ), + .dbg_ack_o ( dbg_ack ), + .dbg_stb_i ( dbg_op[2] ), + .dbg_we_i ( dbg_op[0] ), + + // Power Management + .pm_clksd_o ( ), + .pm_cpustall_i ( 1'b0 ), + .pm_dc_gate_o ( ), + .pm_ic_gate_o ( ), + .pm_dmmu_gate_o ( ), + .pm_immu_gate_o ( ), + .pm_tt_gate_o ( ), + .pm_cpu_gate_o ( ), + .pm_wakeup_o ( ), + .pm_lvolt_o ( ), + + // Interrupts + .pic_ints_i ( pic_ints ) +); + +// +// Startup OR1k +// +`ifdef START_UP +OR1K_startup OR1K_startup0 +( + .wb_adr_i(wb_fs_adr_i[6:2]), + .wb_stb_i(wb_fs_stb_i), + .wb_cyc_i(wb_fs_cyc_i), + .wb_dat_o(wb_fs_dat_o), + .wb_ack_o(wb_fs_ack_o), + .wb_clk(wb_clk), + .wb_rst(wb_rst) +); + +spi_flash_top # +( + .divider(0), + .divider_len(2) +) +spi_flash_top0 +( + .wb_clk_i(wb_clk), + .wb_rst_i(wb_rst), + .wb_adr_i(wb_sp_adr_i[4:2]), + .wb_dat_i(wb_sp_dat_i), + .wb_dat_o(wb_sp_dat_o), + .wb_sel_i(wb_sp_sel_i), + .wb_we_i(wb_sp_we_i), + .wb_stb_i(wb_sp_stb_i), + .wb_cyc_i(wb_sp_cyc_i), + .wb_ack_o(wb_sp_ack_o), + + .mosi_pad_o(spi_flash_mosi), + .miso_pad_i(spi_flash_miso), + .sclk_pad_o(spi_flash_sclk), + .ss_pad_o(spi_flash_ss) +); +`else +assign wb_fs_dat_o = 32'h0000_0000; +assign wb_fs_ack_o = 1'b0; +assign wb_sp_dat_o = 32'h0000_0000; +assign wb_sp_ack_o = 1'b0; +`endif + +// +// Instantiation of the SRAM controller +// +minsoc_onchip_ram_top # +( + .adr_width(`MEMORY_ADR_WIDTH) //16 blocks of 2048 bytes memory 32768 +) +onchip_ram_top ( + + // WISHBONE common + .wb_clk_i ( wb_clk ), + .wb_rst_i ( wb_rst ), + + // WISHBONE slave + .wb_dat_i ( wb_ss_dat_i ), + .wb_dat_o ( wb_ss_dat_o ), + .wb_adr_i ( wb_ss_adr_i ), + .wb_sel_i ( wb_ss_sel_i ), + .wb_we_i ( wb_ss_we_i ), + .wb_cyc_i ( wb_ss_cyc_i ), + .wb_stb_i ( wb_ss_stb_i ), + .wb_ack_o ( wb_ss_ack_o ), + .wb_err_o ( wb_ss_err_o ) +); + +// +// Instantiation of the UART16550 +// +`ifdef UART +uart_top uart_top ( + + // WISHBONE common + .wb_clk_i ( wb_clk ), + .wb_rst_i ( wb_rst ), + + // WISHBONE slave + .wb_adr_i ( wb_us_adr_i[4:0] ), + .wb_dat_i ( wb_us_dat_i ), + .wb_dat_o ( wb_us_dat_o ), + .wb_we_i ( wb_us_we_i ), + .wb_stb_i ( wb_us_stb_i ), + .wb_cyc_i ( wb_us_cyc_i ), + .wb_ack_o ( wb_us_ack_o ), + .wb_sel_i ( wb_us_sel_i ), + + // Interrupt request + .int_o ( pic_ints[`APP_INT_UART] ), + + // UART signals + // serial input/output + .stx_pad_o ( uart_stx ), + .srx_pad_i ( uart_srx ), + + // modem signals + .rts_pad_o ( ), + .cts_pad_i ( 1'b0 ), + .dtr_pad_o ( ), + .dsr_pad_i ( 1'b0 ), + .ri_pad_i ( 1'b0 ), + .dcd_pad_i ( 1'b0 ) +); +`else +assign wb_us_dat_o = 32'h0000_0000; +assign wb_us_ack_o = 1'b0; +`endif + + +// +// Instantiation of the GPIO +// +`ifdef GPIO +gpio_top #( .gw(`GPIO_IOS + 1) ) +gpio_top_inst ( + + // WISHBONE common + .wb_clk_i ( wb_clk ), + .wb_rst_i ( wb_rst ), + + // WISHBONE slave + .wb_adr_i ( wb_gpio_adr_i[4:0] ), + .wb_dat_i ( wb_gpio_dat_i ), + .wb_dat_o ( wb_gpio_dat_o ), + .wb_we_i ( wb_gpio_we_i ), + .wb_stb_i ( wb_gpio_stb_i ), + .wb_cyc_i ( wb_gpio_cyc_i ), + .wb_ack_o ( wb_gpio_ack_o ), + .wb_sel_i ( wb_gpio_sel_i ), + + // Interrupt request + .wb_inta_o ( pic_ints[`APP_INT_GPIO] ), + + // GPIO external signals + .ext_pad_o ( ext_pad_o ), + .ext_pad_i ( ext_pad_i ), + .ext_padoe_o( ext_pad_oe_o ) + +); + +minsoc_spartan_3a_starter_kit_ios #( .gpio_num(`GPIO_IOS + 1), + `ifdef GPIO_HAS_INPUT_PINS + .i_line_num(`GPIO_NUM_INPUT), + `endif + `ifdef GPIO_HAS_OUTPUT_PINS + .o_line_num(`GPIO_NUM_OUTPUT), + `endif + `ifdef GPIO_HAS_BIDIR_PINS + .io_line_num(`GPIO_NUM_BIDIR) + `endif +) minsoc_spartan_3a_starter_kit_ios_inst_0 ( + .ext_pad_o( ext_pad_o ), + .ext_pad_oe( ext_pad_oe_o ), + .ext_pad_i( ext_pad_i ), + `ifdef GPIO_HAS_INPUT_PINS + .i_pins( i_pins ), + `else + .i_pins( ), + `endif + `ifdef GPIO_HAS_OUTPUT_PINS + .o_pins( o_pins ), + `else + .o_pins( ), + `endif + `ifdef GPIO_HAS_BIDIR_PINS + .io_pins( io_pins ) + `else + .io_pins( ) + `endif +); + +`else +assign wb_gpio_dat_o = 32'h0000_0000; +assign wb_gpio_ack_o = 1'b0; +`endif + + + +// +// Instantiation of the Ethernet 10/100 MAC +// +`ifdef ETHERNET +eth_top eth_top ( + + // WISHBONE common + .wb_clk_i ( wb_clk ), + .wb_rst_i ( wb_rst ), + + // WISHBONE slave + .wb_dat_i ( wb_es_dat_i ), + .wb_dat_o ( wb_es_dat_o ), + .wb_adr_i ( wb_es_adr_i[11:2] ), + .wb_sel_i ( wb_es_sel_i ), + .wb_we_i ( wb_es_we_i ), + .wb_cyc_i ( wb_es_cyc_i ), + .wb_stb_i ( wb_es_stb_i ), + .wb_ack_o ( wb_es_ack_o ), + .wb_err_o ( wb_es_err_o ), + + // WISHBONE master + .m_wb_adr_o ( wb_em_adr_o ), + .m_wb_sel_o ( wb_em_sel_o ), + .m_wb_we_o ( wb_em_we_o ), + .m_wb_dat_o ( wb_em_dat_o ), + .m_wb_dat_i ( wb_em_dat_i ), + .m_wb_cyc_o ( wb_em_cyc_o ), + .m_wb_stb_o ( wb_em_stb_o ), + .m_wb_ack_i ( wb_em_ack_i ), + .m_wb_err_i ( wb_em_err_i ), + + // TX + .mtx_clk_pad_i ( eth_tx_clk ), + .mtxd_pad_o ( eth_txd ), + .mtxen_pad_o ( eth_tx_en ), + .mtxerr_pad_o ( eth_tx_er ), + + // RX + .mrx_clk_pad_i ( eth_rx_clk ), + .mrxd_pad_i ( eth_rxd ), + .mrxdv_pad_i ( eth_rx_dv ), + .mrxerr_pad_i ( eth_rx_er ), + .mcoll_pad_i ( eth_col ), + .mcrs_pad_i ( eth_crs ), + + // MIIM + .mdc_pad_o ( eth_mdc ), + .md_pad_i ( eth_mdio ), + .md_pad_o ( eth_mdo ), + .md_padoe_o ( eth_mdoe ), + + // Interrupt + .int_o ( pic_ints[`APP_INT_ETH] ) +); +`else +assign wb_es_dat_o = 32'h0000_0000; +assign wb_es_ack_o = 1'b0; + +assign wb_em_adr_o = 32'h0000_0000; +assign wb_em_sel_o = 4'h0; +assign wb_em_we_o = 1'b0; +assign wb_em_dat_o = 32'h0000_0000; +assign wb_em_cyc_o = 1'b0; +assign wb_em_stb_o = 1'b0; +`endif + +// +// Instantiation of the Traffic COP +// +minsoc_tc_top #(`APP_ADDR_DEC_W, + `APP_ADDR_SRAM, + `APP_ADDR_DEC_W, + `APP_ADDR_FLASH, + `APP_ADDR_DECP_W, + `APP_ADDR_PERIP, + `APP_ADDR_DEC_W, + `APP_ADDR_SPI, + `APP_ADDR_ETH, + `APP_ADDR_AUDIO, + `APP_ADDR_UART, + `APP_ADDR_PS2, + `APP_ADDR_GPIO, + `APP_ADDR_RES2 + ) tc_top ( + + // WISHBONE common + .wb_clk_i ( wb_clk ), + .wb_rst_i ( wb_rst ), + + // WISHBONE Initiator 0 + .i0_wb_cyc_i ( 1'b0 ), + .i0_wb_stb_i ( 1'b0 ), + .i0_wb_adr_i ( 32'h0000_0000 ), + .i0_wb_sel_i ( 4'b0000 ), + .i0_wb_we_i ( 1'b0 ), + .i0_wb_dat_i ( 32'h0000_0000 ), + .i0_wb_dat_o ( ), + .i0_wb_ack_o ( ), + .i0_wb_err_o ( ), + + // WISHBONE Initiator 1 + .i1_wb_cyc_i ( wb_em_cyc_o ), + .i1_wb_stb_i ( wb_em_stb_o ), + .i1_wb_adr_i ( wb_em_adr_o ), + .i1_wb_sel_i ( wb_em_sel_o ), + .i1_wb_we_i ( wb_em_we_o ), + .i1_wb_dat_i ( wb_em_dat_o ), + .i1_wb_dat_o ( wb_em_dat_i ), + .i1_wb_ack_o ( wb_em_ack_i ), + .i1_wb_err_o ( wb_em_err_i ), + + // WISHBONE Initiator 2 + .i2_wb_cyc_i ( 1'b0 ), + .i2_wb_stb_i ( 1'b0 ), + .i2_wb_adr_i ( 32'h0000_0000 ), + .i2_wb_sel_i ( 4'b0000 ), + .i2_wb_we_i ( 1'b0 ), + .i2_wb_dat_i ( 32'h0000_0000 ), + .i2_wb_dat_o ( ), + .i2_wb_ack_o ( ), + .i2_wb_err_o ( ), + + // WISHBONE Initiator 3 + .i3_wb_cyc_i ( wb_dm_cyc_o ), + .i3_wb_stb_i ( wb_dm_stb_o ), + .i3_wb_adr_i ( wb_dm_adr_o ), + .i3_wb_sel_i ( wb_dm_sel_o ), + .i3_wb_we_i ( wb_dm_we_o ), + .i3_wb_dat_i ( wb_dm_dat_o ), + .i3_wb_dat_o ( wb_dm_dat_i ), + .i3_wb_ack_o ( wb_dm_ack_i ), + .i3_wb_err_o ( wb_dm_err_i ), + + // WISHBONE Initiator 4 + .i4_wb_cyc_i ( wb_rdm_cyc_o ), + .i4_wb_stb_i ( wb_rdm_stb_o ), + .i4_wb_adr_i ( wb_rdm_adr_o ), + .i4_wb_sel_i ( wb_rdm_sel_o ), + .i4_wb_we_i ( wb_rdm_we_o ), + .i4_wb_dat_i ( wb_rdm_dat_o ), + .i4_wb_dat_o ( wb_rdm_dat_i ), + .i4_wb_ack_o ( wb_rdm_ack_i ), + .i4_wb_err_o ( wb_rdm_err_i ), + + // WISHBONE Initiator 5 + .i5_wb_cyc_i ( wb_rim_cyc_o ), + .i5_wb_stb_i ( wb_rim_stb_o ), + .i5_wb_adr_i ( wb_rim_adr_o ), + .i5_wb_sel_i ( wb_rim_sel_o ), + .i5_wb_we_i ( wb_rim_we_o ), + .i5_wb_dat_i ( wb_rim_dat_o ), + .i5_wb_dat_o ( wb_rim_dat_i ), + .i5_wb_ack_o ( wb_rim_ack_i ), + .i5_wb_err_o ( wb_rim_err_i ), + + // WISHBONE Initiator 6 + .i6_wb_cyc_i ( 1'b0 ), + .i6_wb_stb_i ( 1'b0 ), + .i6_wb_adr_i ( 32'h0000_0000 ), + .i6_wb_sel_i ( 4'b0000 ), + .i6_wb_we_i ( 1'b0 ), + .i6_wb_dat_i ( 32'h0000_0000 ), + .i6_wb_dat_o ( ), + .i6_wb_ack_o ( ), + .i6_wb_err_o ( ), + + // WISHBONE Initiator 7 + .i7_wb_cyc_i ( 1'b0 ), + .i7_wb_stb_i ( 1'b0 ), + .i7_wb_adr_i ( 32'h0000_0000 ), + .i7_wb_sel_i ( 4'b0000 ), + .i7_wb_we_i ( 1'b0 ), + .i7_wb_dat_i ( 32'h0000_0000 ), + .i7_wb_dat_o ( ), + .i7_wb_ack_o ( ), + .i7_wb_err_o ( ), + + // WISHBONE Target 0 + .t0_wb_cyc_o ( wb_ss_cyc_i ), + .t0_wb_stb_o ( wb_ss_stb_i ), + .t0_wb_adr_o ( wb_ss_adr_i ), + .t0_wb_sel_o ( wb_ss_sel_i ), + .t0_wb_we_o ( wb_ss_we_i ), + .t0_wb_dat_o ( wb_ss_dat_i ), + .t0_wb_dat_i ( wb_ss_dat_o ), + .t0_wb_ack_i ( wb_ss_ack_o ), + .t0_wb_err_i ( wb_ss_err_o ), + + // WISHBONE Target 1 + .t1_wb_cyc_o ( wb_fs_cyc_i ), + .t1_wb_stb_o ( wb_fs_stb_i ), + .t1_wb_adr_o ( wb_fs_adr_i ), + .t1_wb_sel_o ( wb_fs_sel_i ), + .t1_wb_we_o ( wb_fs_we_i ), + .t1_wb_dat_o ( wb_fs_dat_i ), + .t1_wb_dat_i ( wb_fs_dat_o ), + .t1_wb_ack_i ( wb_fs_ack_o ), + .t1_wb_err_i ( wb_fs_err_o ), + + // WISHBONE Target 2 + .t2_wb_cyc_o ( wb_sp_cyc_i ), + .t2_wb_stb_o ( wb_sp_stb_i ), + .t2_wb_adr_o ( wb_sp_adr_i ), + .t2_wb_sel_o ( wb_sp_sel_i ), + .t2_wb_we_o ( wb_sp_we_i ), + .t2_wb_dat_o ( wb_sp_dat_i ), + .t2_wb_dat_i ( wb_sp_dat_o ), + .t2_wb_ack_i ( wb_sp_ack_o ), + .t2_wb_err_i ( wb_sp_err_o ), + + // WISHBONE Target 3 + .t3_wb_cyc_o ( wb_es_cyc_i ), + .t3_wb_stb_o ( wb_es_stb_i ), + .t3_wb_adr_o ( wb_es_adr_i ), + .t3_wb_sel_o ( wb_es_sel_i ), + .t3_wb_we_o ( wb_es_we_i ), + .t3_wb_dat_o ( wb_es_dat_i ), + .t3_wb_dat_i ( wb_es_dat_o ), + .t3_wb_ack_i ( wb_es_ack_o ), + .t3_wb_err_i ( wb_es_err_o ), + + // WISHBONE Target 4 + .t4_wb_cyc_o ( ), + .t4_wb_stb_o ( ), + .t4_wb_adr_o ( ), + .t4_wb_sel_o ( ), + .t4_wb_we_o ( ), + .t4_wb_dat_o ( ), + .t4_wb_dat_i ( 32'h0000_0000 ), + .t4_wb_ack_i ( 1'b0 ), + .t4_wb_err_i ( 1'b1 ), + + // WISHBONE Target 5 + .t5_wb_cyc_o ( wb_us_cyc_i ), + .t5_wb_stb_o ( wb_us_stb_i ), + .t5_wb_adr_o ( wb_us_adr_i ), + .t5_wb_sel_o ( wb_us_sel_i ), + .t5_wb_we_o ( wb_us_we_i ), + .t5_wb_dat_o ( wb_us_dat_i ), + .t5_wb_dat_i ( wb_us_dat_o ), + .t5_wb_ack_i ( wb_us_ack_o ), + .t5_wb_err_i ( wb_us_err_o ), + + // WISHBONE Target 6 + .t6_wb_cyc_o ( ), + .t6_wb_stb_o ( ), + .t6_wb_adr_o ( ), + .t6_wb_sel_o ( ), + .t6_wb_we_o ( ), + .t6_wb_dat_o ( ), + .t6_wb_dat_i ( 32'h0000_0000 ), + .t6_wb_ack_i ( 1'b0 ), + .t6_wb_err_i ( 1'b1 ), + + // WISHBONE Target 7 + .t7_wb_cyc_o ( wb_gpio_cyc_i ), + .t7_wb_stb_o ( wb_gpio_stb_i ), + .t7_wb_adr_o ( wb_gpio_adr_i ), + .t7_wb_sel_o ( wb_gpio_sel_i ), + .t7_wb_we_o ( wb_gpio_we_i ), + .t7_wb_dat_o ( wb_gpio_dat_i ), + .t7_wb_dat_i ( wb_gpio_dat_o ), + .t7_wb_ack_i ( wb_gpio_ack_o ), + .t7_wb_err_i ( wb_gpio_err_o ), + + // WISHBONE Target 8 + .t8_wb_cyc_o ( ), + .t8_wb_stb_o ( ), + .t8_wb_adr_o ( ), + .t8_wb_sel_o ( ), + .t8_wb_we_o ( ), + .t8_wb_dat_o ( ), + .t8_wb_dat_i ( 32'h0000_0000 ), + .t8_wb_ack_i ( 1'b0 ), + .t8_wb_err_i ( 1'b1 ) +); + +//initial begin +// $dumpvars(0); +// $dumpfile("dump.vcd"); +//end + +endmodule Index: gpio/sw/gpio.c =================================================================== --- gpio/sw/gpio.c (nonexistent) +++ gpio/sw/gpio.c (revision 42) @@ -0,0 +1,225 @@ +#include "../support/support.h" +#include "../support/board.h" + +#include "../support/spr_defs.h" + +#include "../drivers/uart.h" + +#include "gpio.h" + +void gpio_init(gpio_t *gpio, long instance_num, unsigned long base_addr) +{ + int i = MIN_GPIO_BIT; + + if ( gpio != NULL ) { + gpio->instance_num = instance_num; + gpio->base_addr = (unsigned char*)base_addr; + for ( ;i<=MAX_GPIO_BIT;i++) + gpio->vectors[i].vec = NULL; + return; + } else { + // Print the error msgs here + // + uart_print_str("gpio inst in NULL.\n"); + return; + } +} + +void gpio_config_bit(gpio_t *gpio, unsigned long bit, iotype_t io) +{ + if ( gpio != NULL ) { + if ( io == IO_INPUT ) { + gpio->io_config |= (1 << bit); + *(unsigned long*)(gpio->base_addr + OE_REG_OFFSET) &= (~(1 << bit)); + } else { + gpio->io_config &= (~(1 << bit)); + *(unsigned long*)(gpio->base_addr + OE_REG_OFFSET) |= (1 << bit); + } + return; + } else { + // Print the error msgs here + // + uart_print_str("gpio inst in NULL.\n"); + return; + } +} + +void gpio_set_bit(gpio_t *gpio, unsigned long bit, unsigned long val) +{ + if ( gpio != NULL ) { + if ( val != 0 ) + *(unsigned long*)(gpio->base_addr + OUT_REG_OFFSET) |= (1 << bit); + else + *(unsigned long*)(gpio->base_addr + OUT_REG_OFFSET) &= (~(1 << bit)); + return; + } else { + // Print the error msgs here + // + uart_print_str("gpio inst in NULL.\n"); + return; + } +} + +void gpio_get_bit(gpio_t *gpio, unsigned long bit, unsigned long *val) +{ + unsigned long temp; + + if ( gpio != NULL ) { + temp = *(unsigned long*)(gpio->base_addr + IN_REG_OFFSET); + *val = (temp & (1 << bit))? 1 : 0; + return; + } else { + // Print the error msgs here + // + uart_print_str("gpio inst in NULL.\n"); + return; + } +} + + +void gpio_add_interrupt(gpio_t *gpio, unsigned int bit, edge_t edge,void (*func)() ) +{ + if ( gpio != NULL ) { + if ( ( gpio->io_config &(1 << bit)) != 0 ) { // Port bit is configured as IO_INPUT + // + // Disable the interrupts + // + *(unsigned long*)(gpio->base_addr + CTRL_REG_OFFSET) &= (~0x01); + + // Enable the interrupt bit + // + *(unsigned long*)(gpio->base_addr + INTE_REG_OFFSET) |= (1 << bit); + + // Enable the edge type + // + if ( edge == POS_EDGE ) + *(unsigned long*)(gpio->base_addr + PTRIG_REG_OFFSET) |= (1 << bit); + else + *(unsigned long*)(gpio->base_addr + PTRIG_REG_OFFSET) &= (~(1 << bit)); + + // Set the function vector + // + gpio->vectors[bit].vec = func; + + int_add( 6, gpio_interrupt, gpio ); + + // Re-enable the global control bit + // + *(unsigned long*)(gpio->base_addr + CTRL_REG_OFFSET) |= 0x01; + } else { + // Port is configured as IO_OUTPUT + uart_print_str("gpio pin is not an input pin.\n"); + return; + } + + } else { + // Print the error msgs here + // + uart_print_str("gpio inst in NULL.\n"); + return; + } + +} + +void gpio_interrupt(gpio_t *gpio) +{ + int i; + unsigned long int interrupt_status; + + if ( (*(unsigned long*)(gpio->base_addr + CTRL_REG_OFFSET)) & 0x02 ) + { + // Interrupt is pending here + // + interrupt_status = *(unsigned long*)(gpio->base_addr + INTS_REG_OFFSET); + + // Prioritize from lower bits(0) to higher ones(31) + // + + for ( i=MIN_GPIO_BIT; i<=MAX_GPIO_BIT; i++ ) { + if ( (interrupt_status & (1<base_addr + INTS_REG_OFFSET) &= (~( 1 << i )); + (gpio->vectors[i].vec)(); + } + } + + *(unsigned long*)(gpio->base_addr + CTRL_REG_OFFSET) &= (~0x02); + + } +} + +void hello_east() +{ + uart_print_str("Hello from PUSH Button EAST.\n"); +} + + +void hello_west() +{ + uart_print_str("Hello from PUSH Button WEST.\n"); +} + + +void hello_south() +{ + uart_print_str("Hello from PUSH Button SOUTH.\n"); +} + + + + +#define MAX_COUNT 10 + +int main() +{ + gpio_t gpio_1; + unsigned long t0, t1, t2, t3; + unsigned long count = 0; + + tick_init(); + uart_init(); + int_init(); + int_add(2,&uart_interrupt); + + gpio_init( &gpio_1, 1, GPIO_BASE ); + + gpio_config_bit( &gpio_1, LED_0, IO_OUTPUT); + gpio_config_bit( &gpio_1, LED_1, IO_OUTPUT); + gpio_config_bit( &gpio_1, LED_2, IO_OUTPUT); + gpio_config_bit( &gpio_1, LED_3, IO_OUTPUT); + gpio_config_bit( &gpio_1, LED_4, IO_OUTPUT); + gpio_config_bit( &gpio_1, LED_5, IO_OUTPUT); + gpio_config_bit( &gpio_1, LED_6, IO_OUTPUT); + gpio_config_bit( &gpio_1, LED_7, IO_OUTPUT); + + while ( count++ < MAX_COUNT ) { + gpio_set_bit( &gpio_1, LED_7, 0 ); + gpio_set_bit( &gpio_1, LED_0, 1 ); + udelay(); + gpio_set_bit( &gpio_1, LED_0, 0 ); + gpio_set_bit( &gpio_1, LED_1, 1 ); + udelay(); + gpio_set_bit( &gpio_1, LED_1, 0 ); + gpio_set_bit( &gpio_1, LED_2, 1 ); + udelay(); + gpio_set_bit( &gpio_1, LED_2, 0 ); + gpio_set_bit( &gpio_1, LED_3, 1 ); + udelay(); + gpio_set_bit( &gpio_1, LED_3, 0 ); + gpio_set_bit( &gpio_1, LED_4, 1 ); + udelay(); + gpio_set_bit( &gpio_1, LED_4, 0 ); + gpio_set_bit( &gpio_1, LED_5, 1 ); + udelay(); + gpio_set_bit( &gpio_1, LED_5, 0 ); + gpio_set_bit( &gpio_1, LED_6, 1 ); + udelay(); + gpio_set_bit( &gpio_1, LED_6, 0 ); + gpio_set_bit( &gpio_1, LED_7, 1 ); + udelay(); + } + + gpio_set_bit( &gpio_1, LED_7, 0 ); + + report(0xdeaddead); + or32_exit(0); +} Index: gpio/sw/udelay.c =================================================================== --- gpio/sw/udelay.c (nonexistent) +++ gpio/sw/udelay.c (revision 42) @@ -0,0 +1,13 @@ +#include "../support/support.h" +#include "../support/board.h" + +#include "../drivers/tick.h" + +extern int tick_int; + +void udelay(void) +{ + while (!tick_int); + tick_ack(); +} + Index: gpio/sw/gpio.h =================================================================== --- gpio/sw/gpio.h (nonexistent) +++ gpio/sw/gpio.h (revision 42) @@ -0,0 +1,76 @@ +#ifndef __GPIO_H__ + +#define __GPIO_H__ + +#define MIN_GPIO_BIT 0 +#define MAX_GPIO_BIT 31 + +#define TOTAL_GPIO_BITS ((MAX_GPIO_BIT-MIN_GPIO_BIT+1)) + + +#define IN_REG_OFFSET 0x00 +#define OUT_REG_OFFSET 0x04 +#define OE_REG_OFFSET 0x08 +#define INTE_REG_OFFSET 0x0C +#define PTRIG_REG_OFFSET 0x10 +#define AUX_REG_OFFSET 0x14 +#define CTRL_REG_OFFSET 0x18 +#define INTS_REG_OFFSET 0x1C +#define ECLK_REG_OFFSET 0x20 +#define NEC_REG_OFFSET 0x24 + + +typedef struct vector_t_ +{ + void (*vec)(); +} vector_t; + +typedef struct gpio_t_ +{ + volatile unsigned char *base_addr; + unsigned int instance_num; + unsigned int io_config; + vector_t vectors[TOTAL_GPIO_BITS]; +} gpio_t; + +typedef enum iotype_t_ +{ + IO_OUTPUT = 0, + IO_INPUT = 1 +} iotype_t; + +typedef enum edge_t_ +{ + NEG_EDGE = 0, + POS_EDGE = 1 +} edge_t; + + +#define LED_0 0x00 +#define LED_1 0x01 +#define LED_2 0x02 +#define LED_3 0x03 +#define LED_4 0x04 +#define LED_5 0x05 +#define LED_6 0x06 +#define LED_7 0x07 + +#define DIP_0 0x08 +#define DIP_1 0x09 +#define DIP_2 0x0A +#define DIP_3 0x0B + +#define PUSH_EAST 0x0C +#define PUSH_WEST 0x0D +#define PUSH_NORTH 0x0E +#define PUSH_SOUTH 0x0F + + +void gpio_init(gpio_t *, long, unsigned long); +void gpio_config_bit(gpio_t *, unsigned long, iotype_t); +void gpio_set_bit(gpio_t *, unsigned long, unsigned long); +void gpio_get_bit(gpio_t *, unsigned long, unsigned long *); +void gpio_add_interrupt(gpio_t *, unsigned int, edge_t,void (*func)() ); +void gpio_interrupt(gpio_t *gpio); + +#endif Index: gpio/sw/Makefile =================================================================== --- gpio/sw/Makefile (nonexistent) +++ gpio/sw/Makefile (revision 42) @@ -0,0 +1,26 @@ +include ../support/Makefile.inc +drivers = ../drivers/libdrivers.a +cases = gpio-nocache gpio-icdc +common = ../support/libsupport.a ../support/except.o + +all: $(cases) + +gpio-nocache: gpio.o udelay.o ../support/reset-nocache.o $(common) $(drivers) + $(OR32_TOOL_PREFIX)-gcc $(GCC_OPT) $(GCC_LIB_OPTS) -T ../support/orp.ld $? -o $@.or32 + $(OR32_TOOL_PREFIX)-objcopy -O binary $@.or32 $@.bin + ../utils/bin2hex $@.bin 1 -size_word > $@$(FLASH_MEM_HEX_FILE_SUFFIX).hex + ../utils/bin2vmem $@.bin > $@.vmem + + +gpio-icdc: gpio.o udelay.o ../support/reset-icdc.o $(common) $(drivers) + $(OR32_TOOL_PREFIX)-gcc $(GCC_OPT) $(GCC_LIB_OPTS) -T ../support/orp.ld $? -o $@.or32 + $(OR32_TOOL_PREFIX)-objcopy -O binary $@.or32 $@.bin + ../utils/bin2hex $@.bin 1 -size_word > $@$(FLASH_MEM_HEX_FILE_SUFFIX).hex + ../utils/bin2vmem $@.bin > $@.vmem + + +gpio.o: gpio.c + $(OR32_TOOL_PREFIX)-gcc $(GCC_OPT) $? -c -o $@ + +udelay.o: udelay.c + $(OR32_TOOL_PREFIX)-gcc $(GCC_OPT) $? -c -o $@ Index: gpio/sw/old/gpio.c =================================================================== --- gpio/sw/old/gpio.c (nonexistent) +++ gpio/sw/old/gpio.c (revision 42) @@ -0,0 +1,351 @@ +#include "../support/support.h" +#include "../support/board.h" +#include "../support/uart.h" + +#include "../support/spr_defs.h" + +#include "gpio.h" + + +void uart_print_str(char *); +void uart_print_long(unsigned long); + +// Dummy or32 except vectors +void buserr_except(){} +void dpf_except(){} +void ipf_except(){} +void lpint_except(){} +void align_except(){} +void illegal_except(){} +/*void hpint_except(){ + +}*/ +void dtlbmiss_except(){} +void itlbmiss_except(){} +void range_except(){} +void syscall_except(){} +void res1_except(){} +void trap_except(){} +void res2_except(){} + + +void uart_interrupt() +{ + char lala; + unsigned char interrupt_id; + interrupt_id = REG8(UART_BASE + UART_IIR); + if ( interrupt_id & UART_IIR_RDI ) + { + lala = uart_getc(); + uart_putc(lala+1); + } +} + + +void uart_print_str(char *p) +{ + while(*p != 0) { + uart_putc(*p); + p++; + } +} + +void uart_print_long(unsigned long ul) +{ + int i; + char c; + + + uart_print_str("0x"); + for(i=0; i<8; i++) { + + c = (char) (ul>>((7-i)*4)) & 0xf; + if(c >= 0x0 && c<=0x9) + c += '0'; + else + c += 'a' - 10; + uart_putc(c); + } + +} + +void uart_print_short(unsigned long ul) +{ + int i; + char c; + char flag=0; + + + uart_print_str("0x"); + for(i=0; i<8; i++) { + + c = (char) (ul>>((7-i)*4)) & 0xf; + if(c >= 0x0 && c<=0x9) + c += '0'; + else + c += 'a' - 10; + if ((c != '0') || (i==7)) + flag=1; + if(flag) + uart_putc(c); + } + +} + +/* + * + * + * + * + * + * + * + * + * + */ + +void gpio_init(gpio_t *gpio, long instance_num, unsigned long base_addr) +{ + int i = MIN_GPIO_BIT; + + if ( gpio != NULL ) { + gpio->instance_num = instance_num; + gpio->base_addr = (unsigned char*)base_addr; + for ( ;i<=MAX_GPIO_BIT;i++) + gpio->vectors[i].vec = NULL; + return; + } else { + // Print the error msgs here + // + uart_print_str("gpio inst in NULL.\n"); + return; + } +} + +void gpio_config_bit(gpio_t *gpio, unsigned long bit, iotype_t io) +{ + if ( gpio != NULL ) { + if ( io == IO_INPUT ) { + gpio->io_config |= (1 << bit); + *(unsigned long*)(gpio->base_addr + OE_REG_OFFSET) &= (~(1 << bit)); + } else { + gpio->io_config &= (~(1 << bit)); + *(unsigned long*)(gpio->base_addr + OE_REG_OFFSET) |= (1 << bit); + } + return; + } else { + // Print the error msgs here + // + uart_print_str("gpio inst in NULL.\n"); + return; + } +} + +void gpio_set_bit(gpio_t *gpio, unsigned long bit, unsigned long val) +{ + if ( gpio != NULL ) { + if ( val != 0 ) + *(unsigned long*)(gpio->base_addr + OUT_REG_OFFSET) |= (1 << bit); + else + *(unsigned long*)(gpio->base_addr + OUT_REG_OFFSET) &= (~(1 << bit)); + return; + } else { + // Print the error msgs here + // + uart_print_str("gpio inst in NULL.\n"); + return; + } +} + +void gpio_get_bit(gpio_t *gpio, unsigned long bit, unsigned long *val) +{ + unsigned long temp; + + if ( gpio != NULL ) { + temp = *(unsigned long*)(gpio->base_addr + IN_REG_OFFSET); + *val = (temp & (1 << bit))? 1 : 0; + return; + } else { + // Print the error msgs here + // + uart_print_str("gpio inst in NULL.\n"); + return; + } +} + + +void gpio_add_interrupt(gpio_t *gpio, unsigned int bit, edge_t edge,void (*func)() ) +{ + if ( gpio != NULL ) { + if ( ( gpio->io_config &(1 << bit)) != 0 ) { // Port bit is configured as IO_INPUT + // + // Disable the interrupts + // + *(unsigned long*)(gpio->base_addr + CTRL_REG_OFFSET) &= (~0x01); + + // Enable the interrupt bit + // + *(unsigned long*)(gpio->base_addr + INTE_REG_OFFSET) |= (1 << bit); + + // Enable the edge type + // + if ( edge == POS_EDGE ) + *(unsigned long*)(gpio->base_addr + PTRIG_REG_OFFSET) |= (1 << bit); + else + *(unsigned long*)(gpio->base_addr + PTRIG_REG_OFFSET) &= (~(1 << bit)); + + // Set the function vector + // + gpio->vectors[bit].vec = func; + + int_add( 6, gpio_interrupt, gpio ); + + // Re-enable the global control bit + // + *(unsigned long*)(gpio->base_addr + CTRL_REG_OFFSET) |= 0x01; + } else { + // Port is configured as IO_OUTPUT + uart_print_str("gpio pin is not an input pin.\n"); + return; + } + + } else { + // Print the error msgs here + // + uart_print_str("gpio inst in NULL.\n"); + return; + } + +} + +void gpio_interrupt(gpio_t *gpio) +{ + int i; + unsigned long int interrupt_status; + + if ( (*(unsigned long*)(gpio->base_addr + CTRL_REG_OFFSET)) & 0x02 ) + { + // Interrupt is pending here + // + interrupt_status = *(unsigned long*)(gpio->base_addr + INTS_REG_OFFSET); + + // Prioritize from lower bits(0) to higher ones(31) + // + + for ( i=MIN_GPIO_BIT; i<=MAX_GPIO_BIT; i++ ) { + if ( (interrupt_status & (1<base_addr + INTS_REG_OFFSET) &= (~( 1 << i )); + (gpio->vectors[i].vec)(); + } + } + + *(unsigned long*)(gpio->base_addr + CTRL_REG_OFFSET) &= (~0x02); + + } +} + +void hello_east() +{ + uart_print_str("Hello from PUSH Button EAST.\n"); +} + + +void hello_west() +{ + uart_print_str("Hello from PUSH Button WEST.\n"); +} + + +void hello_south() +{ + uart_print_str("Hello from PUSH Button SOUTH.\n"); +} + + + + +#define MAX_COUNT 10 + +int main() +{ + gpio_t gpio_1; + unsigned long t0, t1, t2, t3; + unsigned long count = 0; + + uart_init(); + int_init(); + int_add(2,&uart_interrupt); + + gpio_init( &gpio_1, 1, GPIO_BASE ); + + gpio_config_bit( &gpio_1, LED_0, IO_OUTPUT); + gpio_config_bit( &gpio_1, LED_1, IO_OUTPUT); + gpio_config_bit( &gpio_1, LED_2, IO_OUTPUT); + gpio_config_bit( &gpio_1, LED_3, IO_OUTPUT); + gpio_config_bit( &gpio_1, LED_4, IO_OUTPUT); + gpio_config_bit( &gpio_1, LED_5, IO_OUTPUT); + gpio_config_bit( &gpio_1, LED_6, IO_OUTPUT); + gpio_config_bit( &gpio_1, LED_7, IO_OUTPUT); + + gpio_config_bit( &gpio_1, DIP_0, IO_INPUT); + gpio_config_bit( &gpio_1, DIP_1, IO_INPUT); + gpio_config_bit( &gpio_1, DIP_2, IO_INPUT); + gpio_config_bit( &gpio_1, DIP_3, IO_INPUT); + + uart_print_str("Demo 1 : Check for running LED patterns on board ...\n"); + + while ( count++ < MAX_COUNT ) { + gpio_set_bit( &gpio_1, LED_7, 0 ); + gpio_set_bit( &gpio_1, LED_0, 1 ); + udelay( 100000 ); + gpio_set_bit( &gpio_1, LED_0, 0 ); + gpio_set_bit( &gpio_1, LED_1, 1 ); + udelay( 100000 ); + gpio_set_bit( &gpio_1, LED_1, 0 ); + gpio_set_bit( &gpio_1, LED_2, 1 ); + udelay( 100000 ); + gpio_set_bit( &gpio_1, LED_2, 0 ); + gpio_set_bit( &gpio_1, LED_3, 1 ); + udelay( 100000 ); + gpio_set_bit( &gpio_1, LED_3, 0 ); + gpio_set_bit( &gpio_1, LED_4, 1 ); + udelay( 100000 ); + gpio_set_bit( &gpio_1, LED_4, 0 ); + gpio_set_bit( &gpio_1, LED_5, 1 ); + udelay( 100000 ); + gpio_set_bit( &gpio_1, LED_5, 0 ); + gpio_set_bit( &gpio_1, LED_6, 1 ); + udelay( 100000 ); + gpio_set_bit( &gpio_1, LED_6, 0 ); + gpio_set_bit( &gpio_1, LED_7, 1 ); + udelay( 100000 ); + } + + gpio_set_bit( &gpio_1, LED_7, 0 ); + + gpio_config_bit( &gpio_1, PUSH_EAST, IO_INPUT); + gpio_add_interrupt( &gpio_1, PUSH_EAST, POS_EDGE, hello_east ); + gpio_config_bit( &gpio_1, PUSH_WEST, IO_INPUT); + gpio_add_interrupt( &gpio_1, PUSH_WEST, POS_EDGE, hello_west ); + gpio_config_bit( &gpio_1, PUSH_SOUTH, IO_INPUT); + gpio_add_interrupt( &gpio_1, PUSH_SOUTH, POS_EDGE, hello_south ); + + uart_print_str("Demo 2 : Press the DIP switches and watch corresponding LED glow ...\n"); + + + while (1) { + gpio_get_bit( &gpio_1, DIP_0, &t0 ); + gpio_get_bit( &gpio_1, DIP_1, &t1 ); + gpio_get_bit( &gpio_1, DIP_2, &t2 ); + gpio_get_bit( &gpio_1, DIP_3, &t3 ); + // + gpio_set_bit( &gpio_1, LED_0, t0 ); + gpio_set_bit( &gpio_1, LED_1, t1 ); + gpio_set_bit( &gpio_1, LED_2, t2 ); + gpio_set_bit( &gpio_1, LED_3, t3 ); + } + + + report(0xdeaddead); + or32_exit(0); +} Index: gpio/sw/old/udelay.c =================================================================== --- gpio/sw/old/udelay.c (nonexistent) +++ gpio/sw/old/udelay.c (revision 42) @@ -0,0 +1,17 @@ +#include "../support/support.h" +#include "../support/board.h" + + +void udelay(unsigned long); + +void udelay(unsigned long usecs) +{ + unsigned long i; + unsigned long cycles = usecs / (IN_CLK / 1000000 ); + unsigned long mem_dummy; + volatile unsigned long* ptr = &mem_dummy; + + for ( i=0; i< cycles; i++) + *ptr = 0xABCD; +} + Index: gpio/sw/old/gpio.h =================================================================== --- gpio/sw/old/gpio.h (nonexistent) +++ gpio/sw/old/gpio.h (revision 42) @@ -0,0 +1,76 @@ +#ifndef __GPIO_H__ + +#define __GPIO_H__ + +#define MIN_GPIO_BIT 0 +#define MAX_GPIO_BIT 31 + +#define TOTAL_GPIO_BITS ((MAX_GPIO_BIT-MIN_GPIO_BIT+1)) + + +#define IN_REG_OFFSET 0x00 +#define OUT_REG_OFFSET 0x04 +#define OE_REG_OFFSET 0x08 +#define INTE_REG_OFFSET 0x0C +#define PTRIG_REG_OFFSET 0x10 +#define AUX_REG_OFFSET 0x14 +#define CTRL_REG_OFFSET 0x18 +#define INTS_REG_OFFSET 0x1C +#define ECLK_REG_OFFSET 0x20 +#define NEC_REG_OFFSET 0x24 + + +typedef struct vector_t_ +{ + void (*vec)(); +} vector_t; + +typedef struct gpio_t_ +{ + volatile unsigned char *base_addr; + unsigned int instance_num; + unsigned int io_config; + vector_t vectors[TOTAL_GPIO_BITS]; +} gpio_t; + +typedef enum iotype_t_ +{ + IO_OUTPUT = 0, + IO_INPUT = 1 +} iotype_t; + +typedef enum edge_t_ +{ + NEG_EDGE = 0, + POS_EDGE = 1 +} edge_t; + + +#define LED_0 0x00 +#define LED_1 0x01 +#define LED_2 0x02 +#define LED_3 0x03 +#define LED_4 0x04 +#define LED_5 0x05 +#define LED_6 0x06 +#define LED_7 0x07 + +#define DIP_0 0x08 +#define DIP_1 0x09 +#define DIP_2 0x0A +#define DIP_3 0x0B + +#define PUSH_EAST 0x0C +#define PUSH_WEST 0x0D +#define PUSH_NORTH 0x0E +#define PUSH_SOUTH 0x0F + + +void gpio_init(gpio_t *, long, unsigned long); +void gpio_config_bit(gpio_t *, unsigned long, iotype_t); +void gpio_set_bit(gpio_t *, unsigned long, unsigned long); +void gpio_get_bit(gpio_t *, unsigned long, unsigned long *); +void gpio_add_interrupt(gpio_t *, unsigned int, edge_t,void (*func)() ); +void gpio_interrupt(gpio_t *gpio); + +#endif Index: gpio/sw/old/Makefile =================================================================== --- gpio/sw/old/Makefile (nonexistent) +++ gpio/sw/old/Makefile (revision 42) @@ -0,0 +1,26 @@ +include ../support/Makefile.inc +cases = gpio-nocache gpio-icdc +common = ../support/libsupport.a ../support/except.o + +all: $(cases) + +gpio-nocache: gpio.o udelay.o ../support/reset-nocache.o $(common) + $(OR32_TOOL_PREFIX)-gcc $(GCC_OPT) $(GCC_LIB_OPTS) -T ../support/orp.ld $? -o $@.or32 + $(OR32_TOOL_PREFIX)-objcopy -O binary $@.or32 $@.bin + ../utils/bin2hex $@.bin 1 -size_word > $@$(FLASH_MEM_HEX_FILE_SUFFIX).hex + ../utils/bin2vmem $@.bin > $@.vmem + + +gpio-icdc: gpio.o udelay.o ../support/reset-icdc.o + $(OR32_TOOL_PREFIX)-gcc $(GCC_OPT) $(GCC_LIB_OPTS) -T ../support/orp.ld $? -o $@.or32 $(common) + $(OR32_TOOL_PREFIX)-objcopy -O binary $@.or32 $@.bin + ../utils/bin2hex $@.bin 1 -size_word > $@$(FLASH_MEM_HEX_FILE_SUFFIX).hex + ../utils/bin2vmem $@.bin > $@.vmem + + +gpio.o: gpio.c + $(OR32_TOOL_PREFIX)-gcc $(GCC_OPT) $? -c -o $@ + +udelay.o: udelay.c + $(OR32_TOOL_PREFIX)-gcc $(GCC_OPT) $? -c -o $@ +

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