Subversion Repositories minsoc

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Rev 69 → Rev 70

1,6 → 1,3
`timescale 1ns/100ps
//set RTL for simulation, override FPGA specific definitions (JTAG TAP, MEMORY and CLOCK DIVIDER)
`define MEMORY_MODEL //simulation uses a memory model enabling INITIALIZE_MEMORY_MODEL. If you comment this, START_UP might be interesting.

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