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URL https://opencores.org/ocsvn/minsoc/minsoc/trunk

Subversion Repositories minsoc

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  • This comparison shows the changes necessary to convert path
    /minsoc/trunk/backend/spartan3e_starter_kit
    from Rev 66 to Rev 69
    Reverse comparison

Rev 66 → Rev 69

/configure
21,7 → 21,7
FIND_CONSTRAINT='CONSTRAINT_FILE'
 
BOARD_DIR=$BACKEND_DIR/$BOARD
BOARD_FILES=(board.h orp.ld minsoc_defines.v $CONSTRAINT_FILE)
BOARD_FILES=(board.h orp.ld minsoc_defines.v minsoc_bench_defines.v gcc-opt.mk $CONSTRAINT_FILE)
 
in_minsoc=`pwd | grep minsoc/backend/${BOARD}$`
if [ -z $in_minsoc ]
/gcc-opt.mk
0,0 → 1,7
GCC_OPT=-mhard-mul -mhard-div -g -nostdlib
/minsoc_bench_defines.v
0,0 → 1,29
 
`timescale 1ns/100ps
 
//set RTL for simulation, override FPGA specific definitions (JTAG TAP, MEMORY and CLOCK DIVIDER)
`define GENERIC_FPGA
`define MEMORY_MODEL //simulation uses a memory model enabling INITIALIZE_MEMORY_MODEL. If you comment this, START_UP might be interesting.
`define NO_CLOCK_DIVISION //if commented out, generic clock division is implemented (odd divisors are rounded down)
//~set RTL for simulation, override FPGA specific definitions (JTAG TAP, MEMORY and CLOCK DIVIDER)
 
`define FREQ_NUM_FOR_NS 1000000000
 
`define FREQ 25000000
`define CLK_PERIOD (`FREQ_NUM_FOR_NS/`FREQ)
 
`define ETH_PHY_FREQ 25000000
`define ETH_PHY_PERIOD (`FREQ_NUM_FOR_NS/`ETH_PHY_FREQ) //40ns
 
`define UART_BAUDRATE 115200
 
`define VPI_DEBUG
 
//`define VCD_OUTPUT
 
//`define START_UP //pass firmware over spi to or1k_startup
 
`define INITIALIZE_MEMORY_MODEL //instantaneously initialize memory model with firmware
//only use with the memory model.
//If you use the original memory (`define MEMORY_MODEL
//commented out), comment this too.
minsoc_bench_defines.v Property changes : Added: svn:executable ## -0,0 +1 ## +* \ No newline at end of property

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