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https://opencores.org/ocsvn/minsoc/minsoc/trunk
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- This comparison shows the changes necessary to convert path
/minsoc/trunk/backend/spartan3e_starter_kit_eth
- from Rev 70 to Rev 69
- ↔ Reverse comparison
Rev 70 → Rev 69
/minsoc_bench_defines.v
1,3 → 1,6
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`timescale 1ns/100ps |
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//set RTL for simulation, override FPGA specific definitions (JTAG TAP, MEMORY and CLOCK DIVIDER) |
`define GENERIC_FPGA |
`define MEMORY_MODEL //simulation uses a memory model enabling INITIALIZE_MEMORY_MODEL. If you comment this, START_UP might be interesting. |