OpenCores
URL https://opencores.org/ocsvn/minsoc/minsoc/trunk

Subversion Repositories minsoc

Compare Revisions

  • This comparison shows the changes necessary to convert path
    /minsoc/trunk/backend
    from Rev 105 to Rev 141
    Reverse comparison

Rev 105 → Rev 141

/spartan3a_dsp_kit/configure
34,7 → 34,7
echo "Possibly your minsoc directory is named differently, minsoc_trunk for example."
echo "Its name must be minsoc only."
echo ""
exit 1
exit 1
fi
 
echo ""
47,15 → 47,33
echo ""
echo ""
 
echo "Copying board specific SoC files from $BOARD_DIR to $BACKEND_DIR directory."
echo "__________________________________________________________________________"
echo ""
for file in "${BOARD_FILES[@]}"
do
if [ $file != NONE ]
then
echo "Copying $file, to backend directory..."
cp $BOARD_DIR/$file $BACKEND_DIR
fi
done
echo ""
echo ""
 
echo "Generating project files for simulation and synthesis..."
echo "__________________________________________________________________________"
echo ""
make -C $MINSOC_DIR/prj
echo "Generation complete."
echo "__________________________________________________________________________"
echo ""
echo ""
 
if [ $CONSTRAINT_FILE == 'NONE' ]
then
echo "Skipping synthesis preparation. Standard implementation can only be simulated."
echo ""
echo ""
else
echo "Device part for files under $SYNSRC_DIR will be patched and stored "
echo "temporarily."
79,21 → 97,8
sed "s/$FIND_CONSTRAINT/$CONSTRAINT_FILE/g" TMPFILE > TMPFILE2 && mv TMPFILE2 $SYN_DIR/$MAKEFILE
rm TMPFILE
cp $MAKEFILE_DIR/setup.bat $SYN_DIR/setup.bat
echo ""
echo ""
fi
echo ""
echo ""
 
 
echo "Copying board specific SoC files from $BOARD_DIR to $BACKEND_DIR directory."
echo "__________________________________________________________________________"
echo ""
for file in "${BOARD_FILES[@]}"
do
if [ $file != NONE ]
then
echo "Copying $file, to backend directory..."
cp $BOARD_DIR/$file $BACKEND_DIR
fi
done
echo ""
echo ""
echo "Configuration done."
/spartan3a_dsp_kit/minsoc_bench_defines.v
4,7 → 4,7
`define NO_CLOCK_DIVISION //if commented out, generic clock division is implemented (odd divisors are rounded down)
//~set RTL for simulation, override FPGA specific definitions (JTAG TAP, MEMORY and CLOCK DIVIDER)
 
`define FREQ_NUM_FOR_NS 1000000000
`define FREQ_NUM_FOR_NS 100000000
 
`define FREQ 25000000
`define CLK_PERIOD (`FREQ_NUM_FOR_NS/`FREQ)
24,3 → 24,6
//only use with the memory model.
//If you use the original memory (`define MEMORY_MODEL
//commented out), comment this too.
 
`define TEST_UART
//`define TEST_ETHERNET
/std/configure
47,15 → 47,33
echo ""
echo ""
 
echo "Copying board specific SoC files from $BOARD_DIR to $BACKEND_DIR directory."
echo "__________________________________________________________________________"
echo ""
for file in "${BOARD_FILES[@]}"
do
if [ $file != NONE ]
then
echo "Copying $file, to backend directory..."
cp $BOARD_DIR/$file $BACKEND_DIR
fi
done
echo ""
echo ""
 
echo "Generating project files for simulation and synthesis..."
echo "__________________________________________________________________________"
echo ""
make -C $MINSOC_DIR/prj
echo "Generation complete."
echo "__________________________________________________________________________"
echo ""
echo ""
 
if [ $CONSTRAINT_FILE == 'NONE' ]
then
echo "Skipping synthesis preparation. Standard implementation can only be simulated."
echo ""
echo ""
else
echo "Device part for files under $SYNSRC_DIR will be patched and stored "
echo "temporarily."
79,21 → 97,8
sed "s/$FIND_CONSTRAINT/$CONSTRAINT_FILE/g" TMPFILE > TMPFILE2 && mv TMPFILE2 $SYN_DIR/$MAKEFILE
rm TMPFILE
cp $MAKEFILE_DIR/setup.bat $SYN_DIR/setup.bat
echo ""
echo ""
fi
echo ""
echo ""
 
 
echo "Copying board specific SoC files from $BOARD_DIR to $BACKEND_DIR directory."
echo "__________________________________________________________________________"
echo ""
for file in "${BOARD_FILES[@]}"
do
if [ $file != NONE ]
then
echo "Copying $file, to backend directory..."
cp $BOARD_DIR/$file $BACKEND_DIR
fi
done
echo ""
echo ""
echo "Configuration done."
/std/minsoc_bench_defines.v
4,7 → 4,7
`define NO_CLOCK_DIVISION //if commented out, generic clock division is implemented (odd divisors are rounded down)
//~set RTL for simulation, override FPGA specific definitions (JTAG TAP, MEMORY and CLOCK DIVIDER)
 
`define FREQ_NUM_FOR_NS 1000000000
`define FREQ_NUM_FOR_NS 100000000
 
`define FREQ 25000000
`define CLK_PERIOD (`FREQ_NUM_FOR_NS/`FREQ)
24,3 → 24,6
//only use with the memory model.
//If you use the original memory (`define MEMORY_MODEL
//commented out), comment this too.
 
`define TEST_UART
//`define TEST_ETHERNET
/altera_3c25_board/configure
17,7 → 17,7
 
PROJECT_FILE=minsoc_top.qsf
 
SYN_FILES=(adbg_top.prj jtag_top.prj or1200_top.prj uart_top.prj minsoc_top.prj altera_virtual_jtag.prj)
SYN_FILES=(adbg_top.vprj jtag_top.vprj or1200_top.vprj uart_top.vprj minsoc_top.vprj altera_virtual_jtag.vhdprj)
MAKEFILE=Makefile
 
FIND_PART='DEVICE_PART'
52,15 → 52,31
echo ""
echo ""
 
echo "Copying board specific SoC files from $BOARD_DIR to $BACKEND_DIR directory."
echo "__________________________________________________________________________"
echo ""
for file in "${BOARD_FILES[@]}"
do
if [ $file != NONE ]
then
echo "Copying $file, to backend directory..."
cp $BOARD_DIR/$file $BACKEND_DIR
fi
done
 
echo "Generating project files for simulation and synthesis..."
echo "__________________________________________________________________________"
echo ""
make -C $MINSOC_DIR/prj
echo "Generation complete."
echo "__________________________________________________________________________"
echo ""
echo ""
 
if [ $CONSTRAINT_FILE == 'NONE' ]
then
echo "Skipping synthesis preparation. Standard implementation can only be simulated."
echo ""
echo ""
else
echo "Device part and family for files under $SYNSRC_DIR will patched and stored "
echo "temporarily."
88,21 → 104,9
echo "Copying Makefile from $MAKEFILE_DIR to synthesis directory, $SYN_DIR..."
cp $MAKEFILE_DIR/$MAKEFILE $SYN_DIR/$MAKEFILE
cp $MAKEFILE_DIR/setup.bat $SYN_DIR/setup.bat
echo "For synthesis help go to $SYN_DIR and type \"make\"."
echo ""
 
echo "Copying board specific SoC files from $BOARD_DIR to $BACKEND_DIR directory."
echo "__________________________________________________________________________"
echo ""
for file in "${BOARD_FILES[@]}"
do
if [ $file != NONE ]
then
echo "Copying $file, to backend directory..."
cp $BOARD_DIR/$file $BACKEND_DIR
fi
done
echo ""
echo "Configuration done."
echo "For synthesis help go to $SYN_DIR and type \"make\"."
fi
 
echo "Configuration done."
/altera_3c25_board/minsoc_bench_defines.v
4,7 → 4,7
`define NO_CLOCK_DIVISION //if commented out, generic clock division is implemented (odd divisors are rounded down)
//~set RTL for simulation, override FPGA specific definitions (JTAG TAP, MEMORY and CLOCK DIVIDER)
 
`define FREQ_NUM_FOR_NS 1000000000
`define FREQ_NUM_FOR_NS 100000000
 
`define FREQ 25000000
`define CLK_PERIOD (`FREQ_NUM_FOR_NS/`FREQ)
24,3 → 24,6
//only use with the memory model.
//If you use the original memory (`define MEMORY_MODEL
//commented out), comment this too.
 
`define TEST_UART
//`define TEST_ETHERNET
/spartan3e_starter_kit/configure
42,8 → 42,7
#NON STANDARD SCRIPT PART
echo "THIS SCRIPT HAS A NON-STANDARD BEGINNING."
echo "__________________________________________________________________________"
echo "Spartan3E Starter Kit requires another configuration for or1200_r3."
echo "or1200_r1 should work fine, roll back this for minsoc release-1.0."
echo "${BOARD} requires another configuration for or1200."
 
echo ""
echo "Copying or1200_defines.v, to or1200 implementation directory..."
65,15 → 64,33
echo ""
echo ""
 
echo "Copying board specific SoC files from $BOARD_DIR to $BACKEND_DIR directory."
echo "__________________________________________________________________________"
echo ""
for file in "${BOARD_FILES[@]}"
do
if [ $file != NONE ]
then
echo "Copying $file, to backend directory..."
cp $BOARD_DIR/$file $BACKEND_DIR
fi
done
echo ""
echo ""
 
echo "Generating project files for simulation and synthesis..."
echo "__________________________________________________________________________"
echo ""
make -C $MINSOC_DIR/prj
echo "Generation complete."
echo "__________________________________________________________________________"
echo ""
echo ""
 
if [ $CONSTRAINT_FILE == 'NONE' ]
then
echo "Skipping synthesis preparation. Standard implementation can only be simulated."
echo ""
echo ""
else
echo "Device part for files under $SYNSRC_DIR will be patched and stored "
echo "temporarily."
97,21 → 114,8
sed "s/$FIND_CONSTRAINT/$CONSTRAINT_FILE/g" TMPFILE > TMPFILE2 && mv TMPFILE2 $SYN_DIR/$MAKEFILE
rm TMPFILE
cp $MAKEFILE_DIR/setup.bat $SYN_DIR/setup.bat
echo ""
echo ""
fi
echo ""
echo ""
 
 
echo "Copying board specific SoC files from $BOARD_DIR to $BACKEND_DIR directory."
echo "__________________________________________________________________________"
echo ""
for file in "${BOARD_FILES[@]}"
do
if [ $file != NONE ]
then
echo "Copying $file, to backend directory..."
cp $BOARD_DIR/$file $BACKEND_DIR
fi
done
echo ""
echo ""
echo "Configuration done."
/spartan3e_starter_kit/minsoc_bench_defines.v
4,7 → 4,7
`define NO_CLOCK_DIVISION //if commented out, generic clock division is implemented (odd divisors are rounded down)
//~set RTL for simulation, override FPGA specific definitions (JTAG TAP, MEMORY and CLOCK DIVIDER)
 
`define FREQ_NUM_FOR_NS 1000000000
`define FREQ_NUM_FOR_NS 100000000
 
`define FREQ 25000000
`define CLK_PERIOD (`FREQ_NUM_FOR_NS/`FREQ)
24,3 → 24,6
//only use with the memory model.
//If you use the original memory (`define MEMORY_MODEL
//commented out), comment this too.
 
`define TEST_UART
//`define TEST_ETHERNET
/spartan3e_starter_kit_eth/configure
42,9 → 42,7
#NON STANDARD SCRIPT PART
echo "THIS SCRIPT HAS A NON-STANDARD BEGINNING."
echo "__________________________________________________________________________"
echo "Ethernet on Spartan3E Starter Kit requires another configuration for or1200."
echo "For minsoc release-1.0 or1200_r1 will be used."
echo "This will need or1200_defines.v of or1200_r1 with same configuration."
echo "${BOARD} requires another configuration for or1200."
 
echo ""
echo "Copying or1200_defines.v, to or1200 implementation directory..."
66,15 → 64,33
echo ""
echo ""
 
echo "Copying board specific SoC files from $BOARD_DIR to $BACKEND_DIR directory."
echo "__________________________________________________________________________"
echo ""
for file in "${BOARD_FILES[@]}"
do
if [ $file != NONE ]
then
echo "Copying $file, to backend directory..."
cp $BOARD_DIR/$file $BACKEND_DIR
fi
done
echo ""
echo ""
 
echo "Generating project files for simulation and synthesis..."
echo "__________________________________________________________________________"
echo ""
make -C $MINSOC_DIR/prj
echo "Generation complete."
echo "__________________________________________________________________________"
echo ""
echo ""
 
if [ $CONSTRAINT_FILE == 'NONE' ]
then
echo "Skipping synthesis preparation. Standard implementation can only be simulated."
echo ""
echo ""
else
echo "Device part for files under $SYNSRC_DIR will be patched and stored "
echo "temporarily."
98,21 → 114,8
sed "s/$FIND_CONSTRAINT/$CONSTRAINT_FILE/g" TMPFILE > TMPFILE2 && mv TMPFILE2 $SYN_DIR/$MAKEFILE
rm TMPFILE
cp $MAKEFILE_DIR/setup.bat $SYN_DIR/setup.bat
echo ""
echo ""
fi
echo ""
echo ""
 
 
echo "Copying board specific SoC files from $BOARD_DIR to $BACKEND_DIR directory."
echo "__________________________________________________________________________"
echo ""
for file in "${BOARD_FILES[@]}"
do
if [ $file != NONE ]
then
echo "Copying $file, to backend directory..."
cp $BOARD_DIR/$file $BACKEND_DIR
fi
done
echo ""
echo ""
echo "Configuration done."
/spartan3e_starter_kit_eth/minsoc_bench_defines.v
4,7 → 4,7
`define NO_CLOCK_DIVISION //if commented out, generic clock division is implemented (odd divisors are rounded down)
//~set RTL for simulation, override FPGA specific definitions (JTAG TAP, MEMORY and CLOCK DIVIDER)
 
`define FREQ_NUM_FOR_NS 1000000000
`define FREQ_NUM_FOR_NS 100000000
 
`define FREQ 10000000
`define CLK_PERIOD (`FREQ_NUM_FOR_NS/`FREQ)
24,3 → 24,6
//only use with the memory model.
//If you use the original memory (`define MEMORY_MODEL
//commented out), comment this too.
 
`define TEST_UART
//`define TEST_ETHERNET

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