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https://opencores.org/ocsvn/minsoc/minsoc/trunk
Subversion Repositories minsoc
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- This comparison shows the changes necessary to convert path
/minsoc/trunk/bench/verilog/sim_lib
- from Rev 27 to Rev 17
- ↔ Reverse comparison
Rev 27 → Rev 17
/fpga_memory_primitives.v
13,11 → 13,7
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parameter lpm_width = 8; |
parameter lpm_widthad = 11; |
parameter lpm_indata = "REGISTERED"; //This 4 parameters are included only to avoid warnings |
parameter lpm_address_control = "REGISTERED"; //they are not accessed inside the module. OR1200 uses this |
parameter lpm_outdata = "UNREGISTERED"; //configuration set on all its instantiations, so this is fine. |
parameter lpm_hint = "USE_EAB=ON"; //It may not be fine, if you are adding this library to your |
//own system, which uses this module with another configuration. |
|
localparam dw = lpm_width; |
localparam aw = lpm_widthad; |
|
34,7 → 30,7
// |
// Data output drivers |
// |
assign q = mem[addr_reg]; |
assign doq = mem[addr_reg]; |
|
// |
// RAM address register |