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URL https://opencores.org/ocsvn/minsoc/minsoc/trunk

Subversion Repositories minsoc

Compare Revisions

  • This comparison shows the changes necessary to convert path
    /minsoc/trunk/bench/verilog
    from Rev 149 to Rev 141
    Reverse comparison

Rev 149 → Rev 141

/minsoc_bench.v
60,7 → 60,6
reg [12*8-1:0] hello;
reg new_line;
reg new_char;
reg flush_line;
`endif
`ifdef ETHERNET
reg [7:0] eth_rx_data [0:1535]; //receive buffer ETH (max packet 1536)
311,7 → 310,7
if ( line[7:0] == "B" )
$display("UART interrupt working.");
else
$display("UART interrupt failed. B was expected, %c was received.", line[7:0]);
$display("UART interrupt failed.");
uart_echo = 1'b1;
 
if ( hello == "Hello World." )
348,9 → 347,9
#((`CLK_PERIOD)/2) clock <= ~clock;
end
 
`ifdef WAVEFORM_OUTPUT
`ifdef VCD_OUTPUT
initial begin
$dumpfile("../results/minsoc_wave.lxt2");
$dumpfile("../results/minsoc_wave.vcd");
$dumpvars();
end
`endif
401,7 → 400,6
begin
new_line = 1'b0;
new_char = 1'b0;
flush_line = 1'b0;
end
 
always @ (posedge clock)
413,7 → 411,6
reg [7:0] tx_byte;
begin
new_char = 1'b0;
new_line = 1'b0;
// Wait for start bit
while (uart_stx == 1'b1)
@(uart_stx);
434,19 → 431,16
//$display("* USER UART returned to idle at time %d",$time);
end
// display the char
new_char = 1'b1;
if ( uart_echo )
$write("%c", tx_byte);
if ( flush_line ) begin
if ( new_line )
line = "";
flush_line = 1'b0;
end
if ( tx_byte == "\n" ) begin
if ( tx_byte == "\n" )
new_line = 1'b1;
flush_line = 1'b1;
end
else begin
line = { line[39*8-1:0], tx_byte};
new_char = 1'b1;
new_line = 1'b0;
end
end
endtask

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