URL
https://opencores.org/ocsvn/minsoc/minsoc/trunk
Subversion Repositories minsoc
Compare Revisions
- This comparison shows the changes necessary to convert path
/minsoc/trunk/bench/verilog
- from Rev 59 to Rev 58
- ↔ Reverse comparison
Rev 59 → Rev 58
/minsoc_bench_defines.v
1,17 → 1,11
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`timescale 1ns/100ps |
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`ifdef POSITIVE_RESET |
`define RESET_LEVEL 1'b1 |
`elsif NEGATIVE_RESET |
`define RESET_LEVEL 1'b0 |
`else |
`define RESET_LEVEL 1'b1 |
`endif |
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//set RTL for simulation, override FPGA specific definitions (JTAG TAP, MEMORY and CLOCK DIVIDER) |
`define GENERIC_FPGA |
`define NO_CLOCK_DIVISION //if commented out, generic clock division is implemented (odd divisors are rounded down) |
`undef NEGATIVE_RESET |
`define POSITIVE_RESET |
//~set RTL for simulation, override FPGA specific definitions (JTAG TAP, MEMORY and CLOCK DIVIDER) |
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`define FREQ_NUM_FOR_NS 1000000000 |
/minsoc_bench.v
60,7 → 60,7
reg load_file; |
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initial begin |
reset = ~`RESET_LEVEL; |
reset = 1'b0; |
clock = 1'b0; |
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`ifndef NO_CLOCK_DIVISION |
120,9 → 120,9
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// Reset controller |
repeat (2) @ (negedge clock); |
reset = `RESET_LEVEL; |
reset = 1'b1; |
repeat (16) @ (negedge clock); |
reset = ~`RESET_LEVEL; |
reset = 1'b0; |
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`ifdef START_UP |
// Pass firmware over spi to or1k_startup |