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Rev 4 → Rev 7

/verilog/minsoc_bench_defines.v
4,6 → 4,7
//set RTL for simulation, override FPGA specific definitions (JTAG TAP, MEMORY and CLOCK DIVIDER)
`define GENERIC_FPGA
`define NO_CLOCK_DIVISION
`define POSITIVE_RESET
//~set RTL for simulation, override FPGA specific definitions (JTAG TAP, MEMORY and CLOCK DIVIDER)
 
`define FREQ 25000000

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