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https://opencores.org/ocsvn/minsoc/minsoc/trunk
Subversion Repositories minsoc
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/minsoc/trunk/bench
- from Rev 58 to Rev 28
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Rev 58 → Rev 28
/verilog/minsoc_bench_defines.v
4,7 → 4,6
//set RTL for simulation, override FPGA specific definitions (JTAG TAP, MEMORY and CLOCK DIVIDER) |
`define GENERIC_FPGA |
`define NO_CLOCK_DIVISION //if commented out, generic clock division is implemented (odd divisors are rounded down) |
`undef NEGATIVE_RESET |
`define POSITIVE_RESET |
//~set RTL for simulation, override FPGA specific definitions (JTAG TAP, MEMORY and CLOCK DIVIDER) |
|