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URL https://opencores.org/ocsvn/minsoc/minsoc/trunk

Subversion Repositories minsoc

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  • This comparison shows the changes necessary to convert path
    /minsoc/trunk/bench
    from Rev 59 to Rev 60
    Reverse comparison

Rev 59 → Rev 60

/verilog/minsoc_memory_model.v
52,7 → 52,7
//
 
 
module minsoc_onchip_ram_top (
module minsoc_memory_model (
wb_clk_i, wb_rst_i,
wb_dat_i, wb_dat_o, wb_adr_i, wb_sel_i, wb_we_i, wb_cyc_i,
/verilog/minsoc_bench_defines.v
1,16 → 1,9
 
`timescale 1ns/100ps
 
`ifdef POSITIVE_RESET
`define RESET_LEVEL 1'b1
`elsif NEGATIVE_RESET
`define RESET_LEVEL 1'b0
`else
`define RESET_LEVEL 1'b1
`endif
 
//set RTL for simulation, override FPGA specific definitions (JTAG TAP, MEMORY and CLOCK DIVIDER)
`define GENERIC_FPGA
`define MEMORY_MODEL //simulation uses a memory model enabling INITIALIZE_MEMORY_MODEL. If you comment this, START_UP might be interesting.
`define NO_CLOCK_DIVISION //if commented out, generic clock division is implemented (odd divisors are rounded down)
//~set RTL for simulation, override FPGA specific definitions (JTAG TAP, MEMORY and CLOCK DIVIDER)
 
/verilog/minsoc_bench.v
4,6 → 4,14
 
module minsoc_bench();
 
`ifdef POSITIVE_RESET
localparam RESET_LEVEL = 1'b1;
`elsif NEGATIVE_RESET
localparam RESET_LEVEL = 1'b0;
`else
localparam RESET_LEVEL = 1'b1;
`endif
 
reg clock, reset;
 
//Debug interface
60,7 → 68,7
reg load_file;
 
initial begin
reset = ~`RESET_LEVEL;
reset = ~RESET_LEVEL;
clock = 1'b0;
 
`ifndef NO_CLOCK_DIVISION
120,9 → 128,9
 
// Reset controller
repeat (2) @ (negedge clock);
reset = `RESET_LEVEL;
reset = RESET_LEVEL;
repeat (16) @ (negedge clock);
reset = ~`RESET_LEVEL;
reset = ~RESET_LEVEL;
 
`ifdef START_UP
// Pass firmware over spi to or1k_startup

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