URL
https://opencores.org/ocsvn/minsoc/minsoc/trunk
Subversion Repositories minsoc
Compare Revisions
- This comparison shows the changes necessary to convert path
/minsoc/trunk/prj
- from Rev 90 to Rev 91
- ↔ Reverse comparison
Rev 90 → Rev 91
/scripts/xilinxprj.sh
34,6 → 34,7
echo -n "$MINSOC_DIR/$dir/$file" >> $SRC_OUTPUT |
echo '"' >> $SRC_OUTPUT |
FOUND=1 |
break |
fi |
done |
|
/scripts/simprj.sh
36,6 → 36,7
then |
echo "$MINSOC_DIR/$dir/$file" >> $OUTPUT |
FOUND=1 |
break |
fi |
done |
|
/sim/minsoc_top.src
7,9 → 7,6
+incdir+/home/raul/or1k/minsoc/prj/../rtl/verilog/uart16550/rtl/verilog |
/home/raul/or1k/minsoc/prj/../backend/minsoc_defines.v |
/home/raul/or1k/minsoc/prj/../rtl/verilog/timescale.v |
/home/raul/or1k/minsoc/prj/../rtl/verilog/or1200/rtl/verilog/timescale.v |
/home/raul/or1k/minsoc/prj/../rtl/verilog/ethmac/rtl/verilog/timescale.v |
/home/raul/or1k/minsoc/prj/../rtl/verilog/uart16550/rtl/verilog/timescale.v |
/home/raul/or1k/minsoc/prj/../rtl/verilog/minsoc_top.v |
/home/raul/or1k/minsoc/prj/../rtl/verilog/minsoc_tc_top.v |
/home/raul/or1k/minsoc/prj/../rtl/verilog/minsoc_onchip_ram.v |
/sim/minsoc.src
18,9 → 18,6
+incdir+/home/raul/or1k/minsoc/prj/../rtl/verilog/uart16550/rtl/verilog |
/home/raul/or1k/minsoc/prj/../backend/minsoc_defines.v |
/home/raul/or1k/minsoc/prj/../rtl/verilog/timescale.v |
/home/raul/or1k/minsoc/prj/../rtl/verilog/or1200/rtl/verilog/timescale.v |
/home/raul/or1k/minsoc/prj/../rtl/verilog/ethmac/rtl/verilog/timescale.v |
/home/raul/or1k/minsoc/prj/../rtl/verilog/uart16550/rtl/verilog/timescale.v |
/home/raul/or1k/minsoc/prj/../rtl/verilog/minsoc_top.v |
/home/raul/or1k/minsoc/prj/../rtl/verilog/minsoc_tc_top.v |
/home/raul/or1k/minsoc/prj/../rtl/verilog/minsoc_onchip_ram.v |
/xilinx/minsoc_top.prj
1,8 → 1,5
`include "/home/raul/or1k/minsoc/prj/../backend/minsoc_defines.v" |
`include "/home/raul/or1k/minsoc/prj/../rtl/verilog/timescale.v" |
`include "/home/raul/or1k/minsoc/prj/../rtl/verilog/or1200/rtl/verilog/timescale.v" |
`include "/home/raul/or1k/minsoc/prj/../rtl/verilog/ethmac/rtl/verilog/timescale.v" |
`include "/home/raul/or1k/minsoc/prj/../rtl/verilog/uart16550/rtl/verilog/timescale.v" |
`include "/home/raul/or1k/minsoc/prj/../rtl/verilog/minsoc_top.v" |
`include "/home/raul/or1k/minsoc/prj/../rtl/verilog/minsoc_tc_top.v" |
`include "/home/raul/or1k/minsoc/prj/../rtl/verilog/minsoc_onchip_ram.v" |