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Tools

URL https://opencores.org/ocsvn/minsoc/minsoc/trunk

Subversion Repositories minsoc

Compare Revisions

This comparison shows the changes necessary to convert path
```
/minsoc/trunk/prj
```
from Rev 97 to Rev 96
↔ Reverse comparison
Compare Path: Rev

With Path: Rev

Rev 97 → Rev 96

/altera/altera_virtual_jtag.prj

0,0 → 1,2

set_global_assignment -name SEARCH_PATH ../../rtl/verilog/adv_debug_sys/Hardware/altera_virtual_jtag/rtl/vhdl/

set_global_assignment -name VHDL_FILE ../../rtl/verilog/adv_debug_sys/Hardware/altera_virtual_jtag/rtl/vhdl/altera_virtual_jtag.vhd

/altera/or1200_top.prj

0,0 → 1,64

+set_global_assignment -name SEARCH_PATH ../../rtl/verilog/or1200/rtl/verilog
+set_global_assignment -name VERILOG_FILE ../../rtl/verilog/or1200/rtl/verilog/or1200_spram_512x20.v
+set_global_assignment -name VERILOG_FILE ../../rtl/verilog/or1200/rtl/verilog/or1200_spram_64x24.v
+set_global_assignment -name VERILOG_FILE ../../rtl/verilog/or1200/rtl/verilog/or1200_du.v
+set_global_assignment -name VERILOG_FILE ../../rtl/verilog/or1200/rtl/verilog/or1200_spram_2048x32_bw.v
+set_global_assignment -name VERILOG_FILE ../../rtl/verilog/or1200/rtl/verilog/or1200_rf.v
+set_global_assignment -name VERILOG_FILE ../../rtl/verilog/or1200/rtl/verilog/or1200_alu.v
+set_global_assignment -name VERILOG_FILE ../../rtl/verilog/or1200/rtl/verilog/or1200_dmmu_top.v
+set_global_assignment -name VERILOG_FILE ../../rtl/verilog/or1200/rtl/verilog/or1200_lsu.v
+set_global_assignment -name VERILOG_FILE ../../rtl/verilog/or1200/rtl/verilog/or1200_spram_1024x32.v
+set_global_assignment -name VERILOG_FILE ../../rtl/verilog/or1200/rtl/verilog/or1200_dc_top.v
+set_global_assignment -name VERILOG_FILE ../../rtl/verilog/or1200/rtl/verilog/or1200_cpu.v
+set_global_assignment -name VERILOG_FILE ../../rtl/verilog/or1200/rtl/verilog/or1200_gmultp2_32x32.v
+set_global_assignment -name VERILOG_FILE ../../rtl/verilog/or1200/rtl/verilog/or1200_immu_top.v
+set_global_assignment -name VERILOG_FILE ../../rtl/verilog/or1200/rtl/verilog/or1200_dpram_256x32.v
+set_global_assignment -name VERILOG_FILE ../../rtl/verilog/or1200/rtl/verilog/or1200_tt.v
+set_global_assignment -name VERILOG_FILE ../../rtl/verilog/or1200/rtl/verilog/or1200_iwb_biu.v
+set_global_assignment -name VERILOG_FILE ../../rtl/verilog/or1200/rtl/verilog/or1200_rfram_generic.v
+set_global_assignment -name VERILOG_FILE ../../rtl/verilog/or1200/rtl/verilog/or1200_dc_tag.v
+set_global_assignment -name VERILOG_FILE ../../rtl/verilog/or1200/rtl/verilog/or1200_spram_2048x8.v
+set_global_assignment -name VERILOG_FILE ../../rtl/verilog/or1200/rtl/verilog/or1200_immu_tlb.v
+set_global_assignment -name VERILOG_FILE ../../rtl/verilog/or1200/rtl/verilog/or1200_ic_tag.v
+set_global_assignment -name VERILOG_FILE ../../rtl/verilog/or1200/rtl/verilog/or1200_spram_64x14.v
+set_global_assignment -name VERILOG_FILE ../../rtl/verilog/or1200/rtl/verilog/or1200_spram_32x24.v
+set_global_assignment -name VERILOG_FILE ../../rtl/verilog/or1200/rtl/verilog/or1200_dpram_32x32.v
+set_global_assignment -name VERILOG_FILE ../../rtl/verilog/or1200/rtl/verilog/or1200_xcv_ram32x8d.v
+set_global_assignment -name VERILOG_FILE ../../rtl/verilog/or1200/rtl/verilog/or1200_spram_1024x8.v
+set_global_assignment -name VERILOG_FILE ../../rtl/verilog/or1200/rtl/verilog/or1200_mem2reg.v
+set_global_assignment -name VERILOG_FILE ../../rtl/verilog/or1200/rtl/verilog/or1200_pm.v
+set_global_assignment -name VERILOG_FILE ../../rtl/verilog/or1200/rtl/verilog/or1200_spram_256x21.v
+set_global_assignment -name VERILOG_FILE ../../rtl/verilog/or1200/rtl/verilog/or1200_operandmuxes.v
+set_global_assignment -name VERILOG_FILE ../../rtl/verilog/or1200/rtl/verilog/or1200_pic.v
+set_global_assignment -name VERILOG_FILE ../../rtl/verilog/or1200/rtl/verilog/or1200_cfgr.v
+set_global_assignment -name VERILOG_FILE ../../rtl/verilog/or1200/rtl/verilog/or1200_if.v
+set_global_assignment -name VERILOG_FILE ../../rtl/verilog/or1200/rtl/verilog/or1200_qmem_top.v
+set_global_assignment -name VERILOG_FILE ../../rtl/verilog/or1200/rtl/verilog/or1200_genpc.v
+set_global_assignment -name VERILOG_FILE ../../rtl/verilog/or1200/rtl/verilog/or1200_defines.v
+set_global_assignment -name VERILOG_FILE ../../rtl/verilog/or1200/rtl/verilog/or1200_wbmux.v
+set_global_assignment -name VERILOG_FILE ../../rtl/verilog/or1200/rtl/verilog/or1200_ic_ram.v
+set_global_assignment -name VERILOG_FILE ../../rtl/verilog/or1200/rtl/verilog/or1200_dmmu_tlb.v
+set_global_assignment -name VERILOG_FILE ../../rtl/verilog/or1200/rtl/verilog/or1200_sb_fifo.v
+set_global_assignment -name VERILOG_FILE ../../rtl/verilog/or1200/rtl/verilog/or1200_sprs.v
+set_global_assignment -name VERILOG_FILE ../../rtl/verilog/or1200/rtl/verilog/or1200_tpram_32x32.v
+set_global_assignment -name VERILOG_FILE ../../rtl/verilog/or1200/rtl/verilog/or1200_ctrl.v
+set_global_assignment -name VERILOG_FILE ../../rtl/verilog/or1200/rtl/verilog/or1200_sb.v
+set_global_assignment -name VERILOG_FILE ../../rtl/verilog/or1200/rtl/verilog/or1200_mult_mac.v
+set_global_assignment -name VERILOG_FILE ../../rtl/verilog/or1200/rtl/verilog/or1200_ic_fsm.v
+set_global_assignment -name VERILOG_FILE ../../rtl/verilog/or1200/rtl/verilog/or1200_amultp2_32x32.v
+set_global_assignment -name VERILOG_FILE ../../rtl/verilog/or1200/rtl/verilog/or1200_reg2mem.v
+set_global_assignment -name VERILOG_FILE ../../rtl/verilog/or1200/rtl/verilog/or1200_spram_2048x32.v
+set_global_assignment -name VERILOG_FILE ../../rtl/verilog/or1200/rtl/verilog/or1200_except.v
+set_global_assignment -name VERILOG_FILE ../../rtl/verilog/or1200/rtl/verilog/or1200_top.v
+set_global_assignment -name VERILOG_FILE ../../rtl/verilog/or1200/rtl/verilog/or1200_ic_top.v
+set_global_assignment -name VERILOG_FILE ../../rtl/verilog/or1200/rtl/verilog/or1200_dc_ram.v
+set_global_assignment -name VERILOG_FILE ../../rtl/verilog/or1200/rtl/verilog/or1200_spram_1024x32_bw.v
+set_global_assignment -name VERILOG_FILE ../../rtl/verilog/or1200/rtl/verilog/or1200_freeze.v
+set_global_assignment -name VERILOG_FILE ../../rtl/verilog/or1200/rtl/verilog/or1200_spram_128x32.v
+set_global_assignment -name VERILOG_FILE ../../rtl/verilog/or1200/rtl/verilog/or1200_dc_fsm.v
+set_global_assignment -name VERILOG_FILE ../../rtl/verilog/or1200/rtl/verilog/or1200_wb_biu.v
+set_global_assignment -name VERILOG_FILE ../../rtl/verilog/or1200/rtl/verilog/or1200_spram_64x22.v
+set_global_assignment -name VERILOG_FILE ../../rtl/verilog/or1200/rtl/verilog/or1200_fpu.v
+set_global_assignment -name VERILOG_FILE ../../rtl/verilog/or1200/rtl/verilog/or1200_spram.v
+set_global_assignment -name VERILOG_FILE ../../rtl/verilog/or1200/rtl/verilog/or1200_spram_32_bw.v
+set_global_assignment -name VERILOG_FILE ../../rtl/verilog/or1200/rtl/verilog/or1200_dpram.v

/altera/jtag_top.prj

0,0 → 1,3

set_global_assignment -name SEARCH_PATH /home/javieralso/repos/personales/Proyectos/svn/opencores/minsoc/setup/minsoc/prj/../rtl/verilog/adv_debug_sys/Hardware/jtag/tap/rtl/verilog

set_global_assignment -name VERILOG_FILE /home/javieralso/repos/personales/Proyectos/svn/opencores/minsoc/setup/minsoc/prj/../rtl/verilog/adv_debug_sys/Hardware/jtag/tap/rtl/verilog/tap_top.v

set_global_assignment -name VERILOG_FILE /home/javieralso/repos/personales/Proyectos/svn/opencores/minsoc/setup/minsoc/prj/../rtl/verilog/adv_debug_sys/Hardware/jtag/tap/rtl/verilog/tap_defines.v

/altera/minsoc_bench.prj

0,0 → 1,11

+set_global_assignment -name SEARCH_PATH ../../backend
+set_global_assignment -name SEARCH_PATH ../../bench/verilog
+set_global_assignment -name SEARCH_PATH ../../bench/verilog/vpi
+set_global_assignment -name SEARCH_PATH ../../bench/verilog/sim_lib
+set_global_assignment -name SEARCH_PATH ../../rtl/verilog
+set_global_assignment -name VERILOG_FILE ../../backend/minsoc_bench_defines.v
+set_global_assignment -name VERILOG_FILE ../../bench/verilog/minsoc_bench.v
+set_global_assignment -name VERILOG_FILE ../../bench/verilog/minsoc_memory_model.v
+set_global_assignment -name VERILOG_FILE ../../bench/verilog/vpi/dbg_comm_vpi.v
+set_global_assignment -name VERILOG_FILE ../../bench/verilog/sim_lib/fpga_memory_primitives.v
+set_global_assignment -name VERILOG_FILE ../../rtl/verilog/timescale.v

/altera/minsoc_top.prj

0,0 → 1,22

+set_global_assignment -name SEARCH_PATH ../../backend
+set_global_assignment -name SEARCH_PATH ../../rtl/verilog
+set_global_assignment -name SEARCH_PATH ../../rtl/verilog/minsoc_startup
+set_global_assignment -name SEARCH_PATH ../../rtl/verilog/or1200/rtl/verilog
+set_global_assignment -name SEARCH_PATH ../../rtl/verilog/adv_debug_sys/Hardware/adv_dbg_if/rtl/verilog
+set_global_assignment -name SEARCH_PATH ../../rtl/verilog/ethmac/rtl/verilog
+set_global_assignment -name SEARCH_PATH ../../rtl/verilog/uart16550/rtl/verilog
+set_global_assignment -name VERILOG_FILE ../../backend/minsoc_defines.v
+set_global_assignment -name VERILOG_FILE ../../rtl/verilog/timescale.v
+set_global_assignment -name VERILOG_FILE ../../rtl/verilog/minsoc_top.v
+set_global_assignment -name VERILOG_FILE ../../rtl/verilog/minsoc_tc_top.v
+set_global_assignment -name VERILOG_FILE ../../rtl/verilog/minsoc_onchip_ram.v
+set_global_assignment -name VERILOG_FILE ../../rtl/verilog/minsoc_onchip_ram_top.v
+set_global_assignment -name VERILOG_FILE ../../rtl/verilog/minsoc_clock_manager.v
+set_global_assignment -name VERILOG_FILE ../../rtl/verilog/altera_pll.v
+set_global_assignment -name VERILOG_FILE ../../rtl/verilog/xilinx_dcm.v
+set_global_assignment -name VERILOG_FILE ../../rtl/verilog/minsoc_xilinx_internal_jtag.v
+set_global_assignment -name VERILOG_FILE ../../rtl/verilog/minsoc_startup/spi_top.v
+set_global_assignment -name VERILOG_FILE ../../rtl/verilog/minsoc_startup/spi_defines.v
+set_global_assignment -name VERILOG_FILE ../../rtl/verilog/minsoc_startup/spi_shift.v
+set_global_assignment -name VERILOG_FILE ../../rtl/verilog/minsoc_startup/spi_clgen.v
+set_global_assignment -name VERILOG_FILE ../../rtl/verilog/minsoc_startup/OR1K_startup_generic.v

/altera/uart_top.prj

0,0 → 1,12

+set_global_assignment -name SEARCH_PATH ../../rtl/verilog/uart16550/rtl/verilog
+set_global_assignment -name VERILOG_FILE ../../rtl/verilog/uart16550/rtl/verilog/uart_top.v
+set_global_assignment -name VERILOG_FILE ../../rtl/verilog/uart16550/rtl/verilog/uart_sync_flops.v
+set_global_assignment -name VERILOG_FILE ../../rtl/verilog/uart16550/rtl/verilog/uart_transmitter.v
+set_global_assignment -name VERILOG_FILE ../../rtl/verilog/uart16550/rtl/verilog/uart_debug_if.v
+set_global_assignment -name VERILOG_FILE ../../rtl/verilog/uart16550/rtl/verilog/uart_wb.v
+set_global_assignment -name VERILOG_FILE ../../rtl/verilog/uart16550/rtl/verilog/uart_receiver.v
+set_global_assignment -name VERILOG_FILE ../../rtl/verilog/uart16550/rtl/verilog/uart_tfifo.v
+set_global_assignment -name VERILOG_FILE ../../rtl/verilog/uart16550/rtl/verilog/uart_regs.v
+set_global_assignment -name VERILOG_FILE ../../rtl/verilog/uart16550/rtl/verilog/uart_rfifo.v
+set_global_assignment -name VERILOG_FILE ../../rtl/verilog/uart16550/rtl/verilog/uart_defines.v
+set_global_assignment -name VERILOG_FILE ../../rtl/verilog/uart16550/rtl/verilog/raminfr.v

/altera/adbg_top.prj

0,0 → 1,11

+set_global_assignment -name SEARCH_PATH ../../rtl/verilog/adv_debug_sys/Hardware/adv_dbg_if/rtl/verilog
+set_global_assignment -name VERILOG_FILE ../../rtl/verilog/adv_debug_sys/Hardware/adv_dbg_if/rtl/verilog/adbg_wb_biu.v
+set_global_assignment -name VERILOG_FILE ../../rtl/verilog/adv_debug_sys/Hardware/adv_dbg_if/rtl/verilog/adbg_wb_module.v
+set_global_assignment -name VERILOG_FILE ../../rtl/verilog/adv_debug_sys/Hardware/adv_dbg_if/rtl/verilog/adbg_or1k_module.v
+set_global_assignment -name VERILOG_FILE ../../rtl/verilog/adv_debug_sys/Hardware/adv_dbg_if/rtl/verilog/adbg_wb_defines.v
+set_global_assignment -name VERILOG_FILE ../../rtl/verilog/adv_debug_sys/Hardware/adv_dbg_if/rtl/verilog/adbg_defines.v
+set_global_assignment -name VERILOG_FILE ../../rtl/verilog/adv_debug_sys/Hardware/adv_dbg_if/rtl/verilog/adbg_crc32.v
+set_global_assignment -name VERILOG_FILE ../../rtl/verilog/adv_debug_sys/Hardware/adv_dbg_if/rtl/verilog/adbg_or1k_biu.v
+set_global_assignment -name VERILOG_FILE ../../rtl/verilog/adv_debug_sys/Hardware/adv_dbg_if/rtl/verilog/adbg_or1k_defines.v
+set_global_assignment -name VERILOG_FILE ../../rtl/verilog/adv_debug_sys/Hardware/adv_dbg_if/rtl/verilog/adbg_or1k_status_reg.v
+set_global_assignment -name VERILOG_FILE ../../rtl/verilog/adv_debug_sys/Hardware/adv_dbg_if/rtl/verilog/adbg_top.v

/altera/ethmac.prj

0,0 → 1,26

+set_global_assignment -name SEARCH_PATH ../../rtl/verilog/ethmac/rtl/verilog
+set_global_assignment -name VERILOG_FILE ../../rtl/verilog/ethmac/rtl/verilog/eth_cop.v
+set_global_assignment -name VERILOG_FILE ../../rtl/verilog/ethmac/rtl/verilog/eth_registers.v
+set_global_assignment -name VERILOG_FILE ../../rtl/verilog/ethmac/rtl/verilog/eth_rxethmac.v
+set_global_assignment -name VERILOG_FILE ../../rtl/verilog/ethmac/rtl/verilog/eth_miim.v
+set_global_assignment -name VERILOG_FILE ../../rtl/verilog/ethmac/rtl/verilog/ethmac.v
+set_global_assignment -name VERILOG_FILE ../../rtl/verilog/ethmac/rtl/verilog/eth_rxaddrcheck.v
+set_global_assignment -name VERILOG_FILE ../../rtl/verilog/ethmac/rtl/verilog/eth_outputcontrol.v
+set_global_assignment -name VERILOG_FILE ../../rtl/verilog/ethmac/rtl/verilog/eth_rxstatem.v
+set_global_assignment -name VERILOG_FILE ../../rtl/verilog/ethmac/rtl/verilog/eth_txethmac.v
+set_global_assignment -name VERILOG_FILE ../../rtl/verilog/ethmac/rtl/verilog/eth_wishbone.v
+set_global_assignment -name VERILOG_FILE ../../rtl/verilog/ethmac/rtl/verilog/eth_maccontrol.v
+set_global_assignment -name VERILOG_FILE ../../rtl/verilog/ethmac/rtl/verilog/eth_txstatem.v
+set_global_assignment -name VERILOG_FILE ../../rtl/verilog/ethmac/rtl/verilog/ethmac_defines.v
+set_global_assignment -name VERILOG_FILE ../../rtl/verilog/ethmac/rtl/verilog/eth_spram_256x32.v
+set_global_assignment -name VERILOG_FILE ../../rtl/verilog/ethmac/rtl/verilog/eth_shiftreg.v
+set_global_assignment -name VERILOG_FILE ../../rtl/verilog/ethmac/rtl/verilog/eth_clockgen.v
+set_global_assignment -name VERILOG_FILE ../../rtl/verilog/ethmac/rtl/verilog/eth_crc.v
+set_global_assignment -name VERILOG_FILE ../../rtl/verilog/ethmac/rtl/verilog/eth_rxcounters.v
+set_global_assignment -name VERILOG_FILE ../../rtl/verilog/ethmac/rtl/verilog/eth_macstatus.v
+set_global_assignment -name VERILOG_FILE ../../rtl/verilog/ethmac/rtl/verilog/eth_random.v
+set_global_assignment -name VERILOG_FILE ../../rtl/verilog/ethmac/rtl/verilog/eth_register.v
+set_global_assignment -name VERILOG_FILE ../../rtl/verilog/ethmac/rtl/verilog/eth_fifo.v
+set_global_assignment -name VERILOG_FILE ../../rtl/verilog/ethmac/rtl/verilog/eth_receivecontrol.v
+set_global_assignment -name VERILOG_FILE ../../rtl/verilog/ethmac/rtl/verilog/eth_transmitcontrol.v
+set_global_assignment -name VERILOG_FILE ../../rtl/verilog/ethmac/rtl/verilog/eth_txcounters.v

/sim/minsoc_top.src

0,0 → 1,22

++incdir+/home/raul/or1k/minsoc/prj/../backend
++incdir+/home/raul/or1k/minsoc/prj/../rtl/verilog
++incdir+/home/raul/or1k/minsoc/prj/../rtl/verilog/minsoc_startup
++incdir+/home/raul/or1k/minsoc/prj/../rtl/verilog/or1200/rtl/verilog
++incdir+/home/raul/or1k/minsoc/prj/../rtl/verilog/adv_debug_sys/Hardware/adv_dbg_if/rtl/verilog
++incdir+/home/raul/or1k/minsoc/prj/../rtl/verilog/ethmac/rtl/verilog
++incdir+/home/raul/or1k/minsoc/prj/../rtl/verilog/uart16550/rtl/verilog
+/home/raul/or1k/minsoc/prj/../backend/minsoc_defines.v
+/home/raul/or1k/minsoc/prj/../rtl/verilog/timescale.v
+/home/raul/or1k/minsoc/prj/../rtl/verilog/minsoc_top.v
+/home/raul/or1k/minsoc/prj/../rtl/verilog/minsoc_tc_top.v
+/home/raul/or1k/minsoc/prj/../rtl/verilog/minsoc_onchip_ram.v
+/home/raul/or1k/minsoc/prj/../rtl/verilog/minsoc_onchip_ram_top.v
+/home/raul/or1k/minsoc/prj/../rtl/verilog/minsoc_clock_manager.v
+/home/raul/or1k/minsoc/prj/../rtl/verilog/altera_pll.v
+/home/raul/or1k/minsoc/prj/../rtl/verilog/xilinx_dcm.v
+/home/raul/or1k/minsoc/prj/../rtl/verilog/minsoc_xilinx_internal_jtag.v
+/home/raul/or1k/minsoc/prj/../rtl/verilog/minsoc_startup/spi_top.v
+/home/raul/or1k/minsoc/prj/../rtl/verilog/minsoc_startup/spi_defines.v
+/home/raul/or1k/minsoc/prj/../rtl/verilog/minsoc_startup/spi_shift.v
+/home/raul/or1k/minsoc/prj/../rtl/verilog/minsoc_startup/spi_clgen.v
+/home/raul/or1k/minsoc/prj/../rtl/verilog/minsoc_startup/OR1K_startup_generic.v

/sim/minsoc.src

0,0 → 1,149

++incdir+/home/raul/or1k/minsoc/prj/../backend
++incdir+/home/raul/or1k/minsoc/prj/../bench/verilog
++incdir+/home/raul/or1k/minsoc/prj/../bench/verilog/vpi
++incdir+/home/raul/or1k/minsoc/prj/../bench/verilog/sim_lib
++incdir+/home/raul/or1k/minsoc/prj/../rtl/verilog
+/home/raul/or1k/minsoc/prj/../backend/minsoc_bench_defines.v
+/home/raul/or1k/minsoc/prj/../bench/verilog/minsoc_bench.v
+/home/raul/or1k/minsoc/prj/../bench/verilog/minsoc_memory_model.v
+/home/raul/or1k/minsoc/prj/../bench/verilog/vpi/dbg_comm_vpi.v
+/home/raul/or1k/minsoc/prj/../bench/verilog/sim_lib/fpga_memory_primitives.v
+/home/raul/or1k/minsoc/prj/../rtl/verilog/timescale.v
++incdir+/home/raul/or1k/minsoc/prj/../backend
++incdir+/home/raul/or1k/minsoc/prj/../rtl/verilog
++incdir+/home/raul/or1k/minsoc/prj/../rtl/verilog/minsoc_startup
++incdir+/home/raul/or1k/minsoc/prj/../rtl/verilog/or1200/rtl/verilog
++incdir+/home/raul/or1k/minsoc/prj/../rtl/verilog/adv_debug_sys/Hardware/adv_dbg_if/rtl/verilog
++incdir+/home/raul/or1k/minsoc/prj/../rtl/verilog/ethmac/rtl/verilog
++incdir+/home/raul/or1k/minsoc/prj/../rtl/verilog/uart16550/rtl/verilog
+/home/raul/or1k/minsoc/prj/../backend/minsoc_defines.v
+/home/raul/or1k/minsoc/prj/../rtl/verilog/timescale.v
+/home/raul/or1k/minsoc/prj/../rtl/verilog/minsoc_top.v
+/home/raul/or1k/minsoc/prj/../rtl/verilog/minsoc_tc_top.v
+/home/raul/or1k/minsoc/prj/../rtl/verilog/minsoc_onchip_ram.v
+/home/raul/or1k/minsoc/prj/../rtl/verilog/minsoc_onchip_ram_top.v
+/home/raul/or1k/minsoc/prj/../rtl/verilog/minsoc_clock_manager.v
+/home/raul/or1k/minsoc/prj/../rtl/verilog/altera_pll.v
+/home/raul/or1k/minsoc/prj/../rtl/verilog/xilinx_dcm.v
+/home/raul/or1k/minsoc/prj/../rtl/verilog/minsoc_xilinx_internal_jtag.v
+/home/raul/or1k/minsoc/prj/../rtl/verilog/minsoc_startup/spi_top.v
+/home/raul/or1k/minsoc/prj/../rtl/verilog/minsoc_startup/spi_defines.v
+/home/raul/or1k/minsoc/prj/../rtl/verilog/minsoc_startup/spi_shift.v
+/home/raul/or1k/minsoc/prj/../rtl/verilog/minsoc_startup/spi_clgen.v
+/home/raul/or1k/minsoc/prj/../rtl/verilog/minsoc_startup/OR1K_startup_generic.v
++incdir+/home/raul/or1k/minsoc/prj/../rtl/verilog/or1200/rtl/verilog
+/home/raul/or1k/minsoc/prj/../rtl/verilog/or1200/rtl/verilog/or1200_spram_512x20.v
+/home/raul/or1k/minsoc/prj/../rtl/verilog/or1200/rtl/verilog/or1200_spram_64x24.v
+/home/raul/or1k/minsoc/prj/../rtl/verilog/or1200/rtl/verilog/or1200_du.v
+/home/raul/or1k/minsoc/prj/../rtl/verilog/or1200/rtl/verilog/or1200_spram_2048x32_bw.v
+/home/raul/or1k/minsoc/prj/../rtl/verilog/or1200/rtl/verilog/or1200_rf.v
+/home/raul/or1k/minsoc/prj/../rtl/verilog/or1200/rtl/verilog/or1200_alu.v
+/home/raul/or1k/minsoc/prj/../rtl/verilog/or1200/rtl/verilog/or1200_dmmu_top.v
+/home/raul/or1k/minsoc/prj/../rtl/verilog/or1200/rtl/verilog/or1200_lsu.v
+/home/raul/or1k/minsoc/prj/../rtl/verilog/or1200/rtl/verilog/or1200_spram_1024x32.v
+/home/raul/or1k/minsoc/prj/../rtl/verilog/or1200/rtl/verilog/or1200_dc_top.v
+/home/raul/or1k/minsoc/prj/../rtl/verilog/or1200/rtl/verilog/or1200_cpu.v
+/home/raul/or1k/minsoc/prj/../rtl/verilog/or1200/rtl/verilog/or1200_gmultp2_32x32.v
+/home/raul/or1k/minsoc/prj/../rtl/verilog/or1200/rtl/verilog/or1200_immu_top.v
+/home/raul/or1k/minsoc/prj/../rtl/verilog/or1200/rtl/verilog/or1200_dpram_256x32.v
+/home/raul/or1k/minsoc/prj/../rtl/verilog/or1200/rtl/verilog/or1200_tt.v
+/home/raul/or1k/minsoc/prj/../rtl/verilog/or1200/rtl/verilog/or1200_iwb_biu.v
+/home/raul/or1k/minsoc/prj/../rtl/verilog/or1200/rtl/verilog/or1200_rfram_generic.v
+/home/raul/or1k/minsoc/prj/../rtl/verilog/or1200/rtl/verilog/or1200_dc_tag.v
+/home/raul/or1k/minsoc/prj/../rtl/verilog/or1200/rtl/verilog/or1200_spram_2048x8.v
+/home/raul/or1k/minsoc/prj/../rtl/verilog/or1200/rtl/verilog/or1200_immu_tlb.v
+/home/raul/or1k/minsoc/prj/../rtl/verilog/or1200/rtl/verilog/or1200_ic_tag.v
+/home/raul/or1k/minsoc/prj/../rtl/verilog/or1200/rtl/verilog/or1200_spram_64x14.v
+/home/raul/or1k/minsoc/prj/../rtl/verilog/or1200/rtl/verilog/or1200_spram_32x24.v
+/home/raul/or1k/minsoc/prj/../rtl/verilog/or1200/rtl/verilog/or1200_dpram_32x32.v
+/home/raul/or1k/minsoc/prj/../rtl/verilog/or1200/rtl/verilog/or1200_xcv_ram32x8d.v
+/home/raul/or1k/minsoc/prj/../rtl/verilog/or1200/rtl/verilog/or1200_spram_1024x8.v
+/home/raul/or1k/minsoc/prj/../rtl/verilog/or1200/rtl/verilog/or1200_mem2reg.v
+/home/raul/or1k/minsoc/prj/../rtl/verilog/or1200/rtl/verilog/or1200_pm.v
+/home/raul/or1k/minsoc/prj/../rtl/verilog/or1200/rtl/verilog/or1200_spram_256x21.v
+/home/raul/or1k/minsoc/prj/../rtl/verilog/or1200/rtl/verilog/or1200_operandmuxes.v
+/home/raul/or1k/minsoc/prj/../rtl/verilog/or1200/rtl/verilog/or1200_pic.v
+/home/raul/or1k/minsoc/prj/../rtl/verilog/or1200/rtl/verilog/or1200_cfgr.v
+/home/raul/or1k/minsoc/prj/../rtl/verilog/or1200/rtl/verilog/or1200_if.v
+/home/raul/or1k/minsoc/prj/../rtl/verilog/or1200/rtl/verilog/or1200_qmem_top.v
+/home/raul/or1k/minsoc/prj/../rtl/verilog/or1200/rtl/verilog/or1200_genpc.v
+/home/raul/or1k/minsoc/prj/../rtl/verilog/or1200/rtl/verilog/or1200_defines.v
+/home/raul/or1k/minsoc/prj/../rtl/verilog/or1200/rtl/verilog/or1200_wbmux.v
+/home/raul/or1k/minsoc/prj/../rtl/verilog/or1200/rtl/verilog/or1200_ic_ram.v
+/home/raul/or1k/minsoc/prj/../rtl/verilog/or1200/rtl/verilog/or1200_dmmu_tlb.v
+/home/raul/or1k/minsoc/prj/../rtl/verilog/or1200/rtl/verilog/or1200_sb_fifo.v
+/home/raul/or1k/minsoc/prj/../rtl/verilog/or1200/rtl/verilog/or1200_sprs.v
+/home/raul/or1k/minsoc/prj/../rtl/verilog/or1200/rtl/verilog/or1200_tpram_32x32.v
+/home/raul/or1k/minsoc/prj/../rtl/verilog/or1200/rtl/verilog/or1200_ctrl.v
+/home/raul/or1k/minsoc/prj/../rtl/verilog/or1200/rtl/verilog/or1200_sb.v
+/home/raul/or1k/minsoc/prj/../rtl/verilog/or1200/rtl/verilog/or1200_mult_mac.v
+/home/raul/or1k/minsoc/prj/../rtl/verilog/or1200/rtl/verilog/or1200_ic_fsm.v
+/home/raul/or1k/minsoc/prj/../rtl/verilog/or1200/rtl/verilog/or1200_amultp2_32x32.v
+/home/raul/or1k/minsoc/prj/../rtl/verilog/or1200/rtl/verilog/or1200_reg2mem.v
+/home/raul/or1k/minsoc/prj/../rtl/verilog/or1200/rtl/verilog/or1200_spram_2048x32.v
+/home/raul/or1k/minsoc/prj/../rtl/verilog/or1200/rtl/verilog/or1200_except.v
+/home/raul/or1k/minsoc/prj/../rtl/verilog/or1200/rtl/verilog/or1200_top.v
+/home/raul/or1k/minsoc/prj/../rtl/verilog/or1200/rtl/verilog/or1200_ic_top.v
+/home/raul/or1k/minsoc/prj/../rtl/verilog/or1200/rtl/verilog/or1200_dc_ram.v
+/home/raul/or1k/minsoc/prj/../rtl/verilog/or1200/rtl/verilog/or1200_spram_1024x32_bw.v
+/home/raul/or1k/minsoc/prj/../rtl/verilog/or1200/rtl/verilog/or1200_freeze.v
+/home/raul/or1k/minsoc/prj/../rtl/verilog/or1200/rtl/verilog/or1200_spram_128x32.v
+/home/raul/or1k/minsoc/prj/../rtl/verilog/or1200/rtl/verilog/or1200_dc_fsm.v
+/home/raul/or1k/minsoc/prj/../rtl/verilog/or1200/rtl/verilog/or1200_wb_biu.v
+/home/raul/or1k/minsoc/prj/../rtl/verilog/or1200/rtl/verilog/or1200_spram_64x22.v
+/home/raul/or1k/minsoc/prj/../rtl/verilog/or1200/rtl/verilog/or1200_fpu.v
+/home/raul/or1k/minsoc/prj/../rtl/verilog/or1200/rtl/verilog/or1200_spram.v
+/home/raul/or1k/minsoc/prj/../rtl/verilog/or1200/rtl/verilog/or1200_spram_32_bw.v
+/home/raul/or1k/minsoc/prj/../rtl/verilog/or1200/rtl/verilog/or1200_dpram.v
++incdir+/home/raul/or1k/minsoc/prj/../rtl/verilog/adv_debug_sys/Hardware/adv_dbg_if/rtl/verilog
+/home/raul/or1k/minsoc/prj/../rtl/verilog/adv_debug_sys/Hardware/adv_dbg_if/rtl/verilog/adbg_wb_biu.v
+/home/raul/or1k/minsoc/prj/../rtl/verilog/adv_debug_sys/Hardware/adv_dbg_if/rtl/verilog/adbg_wb_module.v
+/home/raul/or1k/minsoc/prj/../rtl/verilog/adv_debug_sys/Hardware/adv_dbg_if/rtl/verilog/adbg_or1k_module.v
+/home/raul/or1k/minsoc/prj/../rtl/verilog/adv_debug_sys/Hardware/adv_dbg_if/rtl/verilog/adbg_wb_defines.v
+/home/raul/or1k/minsoc/prj/../rtl/verilog/adv_debug_sys/Hardware/adv_dbg_if/rtl/verilog/adbg_defines.v
+/home/raul/or1k/minsoc/prj/../rtl/verilog/adv_debug_sys/Hardware/adv_dbg_if/rtl/verilog/adbg_crc32.v
+/home/raul/or1k/minsoc/prj/../rtl/verilog/adv_debug_sys/Hardware/adv_dbg_if/rtl/verilog/adbg_or1k_biu.v
+/home/raul/or1k/minsoc/prj/../rtl/verilog/adv_debug_sys/Hardware/adv_dbg_if/rtl/verilog/adbg_or1k_defines.v
+/home/raul/or1k/minsoc/prj/../rtl/verilog/adv_debug_sys/Hardware/adv_dbg_if/rtl/verilog/adbg_or1k_status_reg.v
+/home/raul/or1k/minsoc/prj/../rtl/verilog/adv_debug_sys/Hardware/adv_dbg_if/rtl/verilog/adbg_top.v
++incdir+/home/raul/or1k/minsoc/prj/../rtl/verilog/adv_debug_sys/Hardware/jtag/tap/rtl/verilog
+/home/raul/or1k/minsoc/prj/../rtl/verilog/adv_debug_sys/Hardware/jtag/tap/rtl/verilog/tap_top.v
+/home/raul/or1k/minsoc/prj/../rtl/verilog/adv_debug_sys/Hardware/jtag/tap/rtl/verilog/tap_defines.v
++incdir+/home/raul/or1k/minsoc/prj/../rtl/verilog/uart16550/rtl/verilog
+/home/raul/or1k/minsoc/prj/../rtl/verilog/uart16550/rtl/verilog/uart_top.v
+/home/raul/or1k/minsoc/prj/../rtl/verilog/uart16550/rtl/verilog/uart_sync_flops.v
+/home/raul/or1k/minsoc/prj/../rtl/verilog/uart16550/rtl/verilog/uart_transmitter.v
+/home/raul/or1k/minsoc/prj/../rtl/verilog/uart16550/rtl/verilog/uart_debug_if.v
+/home/raul/or1k/minsoc/prj/../rtl/verilog/uart16550/rtl/verilog/uart_wb.v
+/home/raul/or1k/minsoc/prj/../rtl/verilog/uart16550/rtl/verilog/uart_receiver.v
+/home/raul/or1k/minsoc/prj/../rtl/verilog/uart16550/rtl/verilog/uart_tfifo.v
+/home/raul/or1k/minsoc/prj/../rtl/verilog/uart16550/rtl/verilog/uart_regs.v
+/home/raul/or1k/minsoc/prj/../rtl/verilog/uart16550/rtl/verilog/uart_rfifo.v
+/home/raul/or1k/minsoc/prj/../rtl/verilog/uart16550/rtl/verilog/uart_defines.v
+/home/raul/or1k/minsoc/prj/../rtl/verilog/uart16550/rtl/verilog/raminfr.v
++incdir+/home/raul/or1k/minsoc/prj/../rtl/verilog/ethmac/rtl/verilog
+/home/raul/or1k/minsoc/prj/../rtl/verilog/ethmac/rtl/verilog/eth_cop.v
+/home/raul/or1k/minsoc/prj/../rtl/verilog/ethmac/rtl/verilog/eth_registers.v
+/home/raul/or1k/minsoc/prj/../rtl/verilog/ethmac/rtl/verilog/eth_rxethmac.v
+/home/raul/or1k/minsoc/prj/../rtl/verilog/ethmac/rtl/verilog/eth_miim.v
+/home/raul/or1k/minsoc/prj/../rtl/verilog/ethmac/rtl/verilog/ethmac.v
+/home/raul/or1k/minsoc/prj/../rtl/verilog/ethmac/rtl/verilog/eth_rxaddrcheck.v
+/home/raul/or1k/minsoc/prj/../rtl/verilog/ethmac/rtl/verilog/eth_outputcontrol.v
+/home/raul/or1k/minsoc/prj/../rtl/verilog/ethmac/rtl/verilog/eth_rxstatem.v
+/home/raul/or1k/minsoc/prj/../rtl/verilog/ethmac/rtl/verilog/eth_txethmac.v
+/home/raul/or1k/minsoc/prj/../rtl/verilog/ethmac/rtl/verilog/eth_wishbone.v
+/home/raul/or1k/minsoc/prj/../rtl/verilog/ethmac/rtl/verilog/eth_maccontrol.v
+/home/raul/or1k/minsoc/prj/../rtl/verilog/ethmac/rtl/verilog/eth_txstatem.v
+/home/raul/or1k/minsoc/prj/../rtl/verilog/ethmac/rtl/verilog/ethmac_defines.v
+/home/raul/or1k/minsoc/prj/../rtl/verilog/ethmac/rtl/verilog/eth_spram_256x32.v
+/home/raul/or1k/minsoc/prj/../rtl/verilog/ethmac/rtl/verilog/eth_shiftreg.v
+/home/raul/or1k/minsoc/prj/../rtl/verilog/ethmac/rtl/verilog/eth_clockgen.v
+/home/raul/or1k/minsoc/prj/../rtl/verilog/ethmac/rtl/verilog/eth_crc.v
+/home/raul/or1k/minsoc/prj/../rtl/verilog/ethmac/rtl/verilog/eth_rxcounters.v
+/home/raul/or1k/minsoc/prj/../rtl/verilog/ethmac/rtl/verilog/eth_macstatus.v
+/home/raul/or1k/minsoc/prj/../rtl/verilog/ethmac/rtl/verilog/eth_random.v
+/home/raul/or1k/minsoc/prj/../rtl/verilog/ethmac/rtl/verilog/eth_register.v
+/home/raul/or1k/minsoc/prj/../rtl/verilog/ethmac/rtl/verilog/eth_fifo.v
+/home/raul/or1k/minsoc/prj/../rtl/verilog/ethmac/rtl/verilog/eth_receivecontrol.v
+/home/raul/or1k/minsoc/prj/../rtl/verilog/ethmac/rtl/verilog/eth_transmitcontrol.v
+/home/raul/or1k/minsoc/prj/../rtl/verilog/ethmac/rtl/verilog/eth_txcounters.v

/sim/uart_top.src

0,0 → 1,12

++incdir+/home/raul/or1k/minsoc/prj/../rtl/verilog/uart16550/rtl/verilog
+/home/raul/or1k/minsoc/prj/../rtl/verilog/uart16550/rtl/verilog/uart_top.v
+/home/raul/or1k/minsoc/prj/../rtl/verilog/uart16550/rtl/verilog/uart_sync_flops.v
+/home/raul/or1k/minsoc/prj/../rtl/verilog/uart16550/rtl/verilog/uart_transmitter.v
+/home/raul/or1k/minsoc/prj/../rtl/verilog/uart16550/rtl/verilog/uart_debug_if.v
+/home/raul/or1k/minsoc/prj/../rtl/verilog/uart16550/rtl/verilog/uart_wb.v
+/home/raul/or1k/minsoc/prj/../rtl/verilog/uart16550/rtl/verilog/uart_receiver.v
+/home/raul/or1k/minsoc/prj/../rtl/verilog/uart16550/rtl/verilog/uart_tfifo.v
+/home/raul/or1k/minsoc/prj/../rtl/verilog/uart16550/rtl/verilog/uart_regs.v
+/home/raul/or1k/minsoc/prj/../rtl/verilog/uart16550/rtl/verilog/uart_rfifo.v
+/home/raul/or1k/minsoc/prj/../rtl/verilog/uart16550/rtl/verilog/uart_defines.v
+/home/raul/or1k/minsoc/prj/../rtl/verilog/uart16550/rtl/verilog/raminfr.v

/sim/adbg_top.src

0,0 → 1,11

++incdir+/home/raul/or1k/minsoc/prj/../rtl/verilog/adv_debug_sys/Hardware/adv_dbg_if/rtl/verilog
+/home/raul/or1k/minsoc/prj/../rtl/verilog/adv_debug_sys/Hardware/adv_dbg_if/rtl/verilog/adbg_wb_biu.v
+/home/raul/or1k/minsoc/prj/../rtl/verilog/adv_debug_sys/Hardware/adv_dbg_if/rtl/verilog/adbg_wb_module.v
+/home/raul/or1k/minsoc/prj/../rtl/verilog/adv_debug_sys/Hardware/adv_dbg_if/rtl/verilog/adbg_or1k_module.v
+/home/raul/or1k/minsoc/prj/../rtl/verilog/adv_debug_sys/Hardware/adv_dbg_if/rtl/verilog/adbg_wb_defines.v
+/home/raul/or1k/minsoc/prj/../rtl/verilog/adv_debug_sys/Hardware/adv_dbg_if/rtl/verilog/adbg_defines.v
+/home/raul/or1k/minsoc/prj/../rtl/verilog/adv_debug_sys/Hardware/adv_dbg_if/rtl/verilog/adbg_crc32.v
+/home/raul/or1k/minsoc/prj/../rtl/verilog/adv_debug_sys/Hardware/adv_dbg_if/rtl/verilog/adbg_or1k_biu.v
+/home/raul/or1k/minsoc/prj/../rtl/verilog/adv_debug_sys/Hardware/adv_dbg_if/rtl/verilog/adbg_or1k_defines.v
+/home/raul/or1k/minsoc/prj/../rtl/verilog/adv_debug_sys/Hardware/adv_dbg_if/rtl/verilog/adbg_or1k_status_reg.v
+/home/raul/or1k/minsoc/prj/../rtl/verilog/adv_debug_sys/Hardware/adv_dbg_if/rtl/verilog/adbg_top.v

/sim/ethmac.src

0,0 → 1,26

++incdir+/home/raul/or1k/minsoc/prj/../rtl/verilog/ethmac/rtl/verilog
+/home/raul/or1k/minsoc/prj/../rtl/verilog/ethmac/rtl/verilog/eth_cop.v
+/home/raul/or1k/minsoc/prj/../rtl/verilog/ethmac/rtl/verilog/eth_registers.v
+/home/raul/or1k/minsoc/prj/../rtl/verilog/ethmac/rtl/verilog/eth_rxethmac.v
+/home/raul/or1k/minsoc/prj/../rtl/verilog/ethmac/rtl/verilog/eth_miim.v
+/home/raul/or1k/minsoc/prj/../rtl/verilog/ethmac/rtl/verilog/ethmac.v
+/home/raul/or1k/minsoc/prj/../rtl/verilog/ethmac/rtl/verilog/eth_rxaddrcheck.v
+/home/raul/or1k/minsoc/prj/../rtl/verilog/ethmac/rtl/verilog/eth_outputcontrol.v
+/home/raul/or1k/minsoc/prj/../rtl/verilog/ethmac/rtl/verilog/eth_rxstatem.v
+/home/raul/or1k/minsoc/prj/../rtl/verilog/ethmac/rtl/verilog/eth_txethmac.v
+/home/raul/or1k/minsoc/prj/../rtl/verilog/ethmac/rtl/verilog/eth_wishbone.v
+/home/raul/or1k/minsoc/prj/../rtl/verilog/ethmac/rtl/verilog/eth_maccontrol.v
+/home/raul/or1k/minsoc/prj/../rtl/verilog/ethmac/rtl/verilog/eth_txstatem.v
+/home/raul/or1k/minsoc/prj/../rtl/verilog/ethmac/rtl/verilog/ethmac_defines.v
+/home/raul/or1k/minsoc/prj/../rtl/verilog/ethmac/rtl/verilog/eth_spram_256x32.v
+/home/raul/or1k/minsoc/prj/../rtl/verilog/ethmac/rtl/verilog/eth_shiftreg.v
+/home/raul/or1k/minsoc/prj/../rtl/verilog/ethmac/rtl/verilog/eth_clockgen.v
+/home/raul/or1k/minsoc/prj/../rtl/verilog/ethmac/rtl/verilog/eth_crc.v
+/home/raul/or1k/minsoc/prj/../rtl/verilog/ethmac/rtl/verilog/eth_rxcounters.v
+/home/raul/or1k/minsoc/prj/../rtl/verilog/ethmac/rtl/verilog/eth_macstatus.v
+/home/raul/or1k/minsoc/prj/../rtl/verilog/ethmac/rtl/verilog/eth_random.v
+/home/raul/or1k/minsoc/prj/../rtl/verilog/ethmac/rtl/verilog/eth_register.v
+/home/raul/or1k/minsoc/prj/../rtl/verilog/ethmac/rtl/verilog/eth_fifo.v
+/home/raul/or1k/minsoc/prj/../rtl/verilog/ethmac/rtl/verilog/eth_receivecontrol.v
+/home/raul/or1k/minsoc/prj/../rtl/verilog/ethmac/rtl/verilog/eth_transmitcontrol.v
+/home/raul/or1k/minsoc/prj/../rtl/verilog/ethmac/rtl/verilog/eth_txcounters.v

/sim/or1200_top.src

0,0 → 1,64

++incdir+/home/raul/or1k/minsoc/prj/../rtl/verilog/or1200/rtl/verilog
+/home/raul/or1k/minsoc/prj/../rtl/verilog/or1200/rtl/verilog/or1200_spram_512x20.v
+/home/raul/or1k/minsoc/prj/../rtl/verilog/or1200/rtl/verilog/or1200_spram_64x24.v
+/home/raul/or1k/minsoc/prj/../rtl/verilog/or1200/rtl/verilog/or1200_du.v
+/home/raul/or1k/minsoc/prj/../rtl/verilog/or1200/rtl/verilog/or1200_spram_2048x32_bw.v
+/home/raul/or1k/minsoc/prj/../rtl/verilog/or1200/rtl/verilog/or1200_rf.v
+/home/raul/or1k/minsoc/prj/../rtl/verilog/or1200/rtl/verilog/or1200_alu.v
+/home/raul/or1k/minsoc/prj/../rtl/verilog/or1200/rtl/verilog/or1200_dmmu_top.v
+/home/raul/or1k/minsoc/prj/../rtl/verilog/or1200/rtl/verilog/or1200_lsu.v
+/home/raul/or1k/minsoc/prj/../rtl/verilog/or1200/rtl/verilog/or1200_spram_1024x32.v
+/home/raul/or1k/minsoc/prj/../rtl/verilog/or1200/rtl/verilog/or1200_dc_top.v
+/home/raul/or1k/minsoc/prj/../rtl/verilog/or1200/rtl/verilog/or1200_cpu.v
+/home/raul/or1k/minsoc/prj/../rtl/verilog/or1200/rtl/verilog/or1200_gmultp2_32x32.v
+/home/raul/or1k/minsoc/prj/../rtl/verilog/or1200/rtl/verilog/or1200_immu_top.v
+/home/raul/or1k/minsoc/prj/../rtl/verilog/or1200/rtl/verilog/or1200_dpram_256x32.v
+/home/raul/or1k/minsoc/prj/../rtl/verilog/or1200/rtl/verilog/or1200_tt.v
+/home/raul/or1k/minsoc/prj/../rtl/verilog/or1200/rtl/verilog/or1200_iwb_biu.v
+/home/raul/or1k/minsoc/prj/../rtl/verilog/or1200/rtl/verilog/or1200_rfram_generic.v
+/home/raul/or1k/minsoc/prj/../rtl/verilog/or1200/rtl/verilog/or1200_dc_tag.v
+/home/raul/or1k/minsoc/prj/../rtl/verilog/or1200/rtl/verilog/or1200_spram_2048x8.v
+/home/raul/or1k/minsoc/prj/../rtl/verilog/or1200/rtl/verilog/or1200_immu_tlb.v
+/home/raul/or1k/minsoc/prj/../rtl/verilog/or1200/rtl/verilog/or1200_ic_tag.v
+/home/raul/or1k/minsoc/prj/../rtl/verilog/or1200/rtl/verilog/or1200_spram_64x14.v
+/home/raul/or1k/minsoc/prj/../rtl/verilog/or1200/rtl/verilog/or1200_spram_32x24.v
+/home/raul/or1k/minsoc/prj/../rtl/verilog/or1200/rtl/verilog/or1200_dpram_32x32.v
+/home/raul/or1k/minsoc/prj/../rtl/verilog/or1200/rtl/verilog/or1200_xcv_ram32x8d.v
+/home/raul/or1k/minsoc/prj/../rtl/verilog/or1200/rtl/verilog/or1200_spram_1024x8.v
+/home/raul/or1k/minsoc/prj/../rtl/verilog/or1200/rtl/verilog/or1200_mem2reg.v
+/home/raul/or1k/minsoc/prj/../rtl/verilog/or1200/rtl/verilog/or1200_pm.v
+/home/raul/or1k/minsoc/prj/../rtl/verilog/or1200/rtl/verilog/or1200_spram_256x21.v
+/home/raul/or1k/minsoc/prj/../rtl/verilog/or1200/rtl/verilog/or1200_operandmuxes.v
+/home/raul/or1k/minsoc/prj/../rtl/verilog/or1200/rtl/verilog/or1200_pic.v
+/home/raul/or1k/minsoc/prj/../rtl/verilog/or1200/rtl/verilog/or1200_cfgr.v
+/home/raul/or1k/minsoc/prj/../rtl/verilog/or1200/rtl/verilog/or1200_if.v
+/home/raul/or1k/minsoc/prj/../rtl/verilog/or1200/rtl/verilog/or1200_qmem_top.v
+/home/raul/or1k/minsoc/prj/../rtl/verilog/or1200/rtl/verilog/or1200_genpc.v
+/home/raul/or1k/minsoc/prj/../rtl/verilog/or1200/rtl/verilog/or1200_defines.v
+/home/raul/or1k/minsoc/prj/../rtl/verilog/or1200/rtl/verilog/or1200_wbmux.v
+/home/raul/or1k/minsoc/prj/../rtl/verilog/or1200/rtl/verilog/or1200_ic_ram.v
+/home/raul/or1k/minsoc/prj/../rtl/verilog/or1200/rtl/verilog/or1200_dmmu_tlb.v
+/home/raul/or1k/minsoc/prj/../rtl/verilog/or1200/rtl/verilog/or1200_sb_fifo.v
+/home/raul/or1k/minsoc/prj/../rtl/verilog/or1200/rtl/verilog/or1200_sprs.v
+/home/raul/or1k/minsoc/prj/../rtl/verilog/or1200/rtl/verilog/or1200_tpram_32x32.v
+/home/raul/or1k/minsoc/prj/../rtl/verilog/or1200/rtl/verilog/or1200_ctrl.v
+/home/raul/or1k/minsoc/prj/../rtl/verilog/or1200/rtl/verilog/or1200_sb.v
+/home/raul/or1k/minsoc/prj/../rtl/verilog/or1200/rtl/verilog/or1200_mult_mac.v
+/home/raul/or1k/minsoc/prj/../rtl/verilog/or1200/rtl/verilog/or1200_ic_fsm.v
+/home/raul/or1k/minsoc/prj/../rtl/verilog/or1200/rtl/verilog/or1200_amultp2_32x32.v
+/home/raul/or1k/minsoc/prj/../rtl/verilog/or1200/rtl/verilog/or1200_reg2mem.v
+/home/raul/or1k/minsoc/prj/../rtl/verilog/or1200/rtl/verilog/or1200_spram_2048x32.v
+/home/raul/or1k/minsoc/prj/../rtl/verilog/or1200/rtl/verilog/or1200_except.v
+/home/raul/or1k/minsoc/prj/../rtl/verilog/or1200/rtl/verilog/or1200_top.v
+/home/raul/or1k/minsoc/prj/../rtl/verilog/or1200/rtl/verilog/or1200_ic_top.v
+/home/raul/or1k/minsoc/prj/../rtl/verilog/or1200/rtl/verilog/or1200_dc_ram.v
+/home/raul/or1k/minsoc/prj/../rtl/verilog/or1200/rtl/verilog/or1200_spram_1024x32_bw.v
+/home/raul/or1k/minsoc/prj/../rtl/verilog/or1200/rtl/verilog/or1200_freeze.v
+/home/raul/or1k/minsoc/prj/../rtl/verilog/or1200/rtl/verilog/or1200_spram_128x32.v
+/home/raul/or1k/minsoc/prj/../rtl/verilog/or1200/rtl/verilog/or1200_dc_fsm.v
+/home/raul/or1k/minsoc/prj/../rtl/verilog/or1200/rtl/verilog/or1200_wb_biu.v
+/home/raul/or1k/minsoc/prj/../rtl/verilog/or1200/rtl/verilog/or1200_spram_64x22.v
+/home/raul/or1k/minsoc/prj/../rtl/verilog/or1200/rtl/verilog/or1200_fpu.v
+/home/raul/or1k/minsoc/prj/../rtl/verilog/or1200/rtl/verilog/or1200_spram.v
+/home/raul/or1k/minsoc/prj/../rtl/verilog/or1200/rtl/verilog/or1200_spram_32_bw.v
+/home/raul/or1k/minsoc/prj/../rtl/verilog/or1200/rtl/verilog/or1200_dpram.v

/sim/jtag_top.src

0,0 → 1,3

+incdir+/home/raul/or1k/minsoc/prj/../rtl/verilog/adv_debug_sys/Hardware/jtag/tap/rtl/verilog

/home/raul/or1k/minsoc/prj/../rtl/verilog/adv_debug_sys/Hardware/jtag/tap/rtl/verilog/tap_top.v

/home/raul/or1k/minsoc/prj/../rtl/verilog/adv_debug_sys/Hardware/jtag/tap/rtl/verilog/tap_defines.v

/xilinx/minsoc_top.prj

0,0 → 1,19

+`include "/home/raul/or1k/minsoc/prj/../backend/minsoc_defines.v"
+`include "/home/raul/or1k/minsoc/prj/../rtl/verilog/timescale.v"
+`include "/home/raul/or1k/minsoc/prj/../rtl/verilog/minsoc_top.v"
+`include "/home/raul/or1k/minsoc/prj/../rtl/verilog/minsoc_tc_top.v"
+`include "/home/raul/or1k/minsoc/prj/../rtl/verilog/minsoc_onchip_ram.v"
+`include "/home/raul/or1k/minsoc/prj/../rtl/verilog/minsoc_onchip_ram_top.v"
+`include "/home/raul/or1k/minsoc/prj/../rtl/verilog/minsoc_clock_manager.v"
+`include "/home/raul/or1k/minsoc/prj/../rtl/verilog/altera_pll.v"
+`include "/home/raul/or1k/minsoc/prj/../rtl/verilog/xilinx_dcm.v"
+`include "/home/raul/or1k/minsoc/prj/../rtl/verilog/minsoc_xilinx_internal_jtag.v"
+`include "/home/raul/or1k/minsoc/prj/../rtl/verilog/minsoc_startup/spi_top.v"
+`include "/home/raul/or1k/minsoc/prj/../rtl/verilog/minsoc_startup/spi_defines.v"
+`include "/home/raul/or1k/minsoc/prj/../rtl/verilog/minsoc_startup/spi_shift.v"
+`include "/home/raul/or1k/minsoc/prj/../rtl/verilog/minsoc_startup/spi_clgen.v"
+`include "/home/raul/or1k/minsoc/prj/../rtl/verilog/minsoc_startup/OR1K_startup_generic.v"
+`include "/home/raul/or1k/minsoc/prj/src/blackboxes/adbg_top.v"
+`include "/home/raul/or1k/minsoc/prj/src/blackboxes/ethmac.v"
+`include "/home/raul/or1k/minsoc/prj/src/blackboxes/or1200_top.v"
+`include "/home/raul/or1k/minsoc/prj/src/blackboxes/uart_top.v"

/xilinx/minsoc_top.xst

0,0 → 1,12

+set -tmpdir ./xst
+run
+-vlgincdir { "/home/raul/or1k/minsoc/prj/../backend" "/home/raul/or1k/minsoc/prj/../rtl/verilog" "/home/raul/or1k/minsoc/prj/../rtl/verilog/minsoc_startup" "/home/raul/or1k/minsoc/prj/../rtl/verilog/or1200/rtl/verilog" "/home/raul/or1k/minsoc/prj/../rtl/verilog/adv_debug_sys/Hardware/adv_dbg_if/rtl/verilog" "/home/raul/or1k/minsoc/prj/../rtl/verilog/ethmac/rtl/verilog" "/home/raul/or1k/minsoc/prj/../rtl/verilog/uart16550/rtl/verilog" }
+-ifn /home/raul/or1k/minsoc/prj/../prj/xilinx/minsoc_top.prj
+-ifmt Verilog
+-ofn minsoc_top
+-ofmt NGC
+-p DEVICE_PART
+-top minsoc_top
+-opt_mode Speed
+-opt_level 1
+-iobuf yes

/xilinx/or1200_top.xst

0,0 → 1,12

+set -tmpdir ./xst
+run
+-vlgincdir { "/home/raul/or1k/minsoc/prj/../rtl/verilog/or1200/rtl/verilog" }
+-ifn /home/raul/or1k/minsoc/prj/../prj/xilinx/or1200_top.prj
+-ifmt Verilog
+-ofn or1200_top
+-ofmt NGC
+-p DEVICE_PART
+-top or1200_top
+-opt_mode Speed
+-opt_level 1
+-iobuf no

/xilinx/jtag_top.xst

0,0 → 1,12

+set -tmpdir ./xst
+run
+-vlgincdir { "/home/raul/or1k/minsoc/prj/../rtl/verilog/adv_debug_sys/Hardware/jtag/tap/rtl/verilog" }
+-ifn /home/raul/or1k/minsoc/prj/../prj/xilinx/jtag_top.prj
+-ifmt Verilog
+-ofn jtag_top
+-ofmt NGC
+-p DEVICE_PART
+-top jtag_top
+-opt_mode Speed
+-opt_level 1
+-iobuf no

/xilinx/uart_top.xst

0,0 → 1,12

+set -tmpdir ./xst
+run
+-vlgincdir { "/home/raul/or1k/minsoc/prj/../rtl/verilog/uart16550/rtl/verilog" }
+-ifn /home/raul/or1k/minsoc/prj/../prj/xilinx/uart_top.prj
+-ifmt Verilog
+-ofn uart_top
+-ofmt NGC
+-p DEVICE_PART
+-top uart_top
+-opt_mode Speed
+-opt_level 1
+-iobuf no

/xilinx/adbg_top.xst

0,0 → 1,12

+set -tmpdir ./xst
+run
+-vlgincdir { "/home/raul/or1k/minsoc/prj/../rtl/verilog/adv_debug_sys/Hardware/adv_dbg_if/rtl/verilog" }
+-ifn /home/raul/or1k/minsoc/prj/../prj/xilinx/adbg_top.prj
+-ifmt Verilog
+-ofn adbg_top
+-ofmt NGC
+-p DEVICE_PART
+-top adbg_top
+-opt_mode Speed
+-opt_level 1
+-iobuf no

/xilinx/ethmac.xst

0,0 → 1,12

+set -tmpdir ./xst
+run
+-vlgincdir { "/home/raul/or1k/minsoc/prj/../rtl/verilog/ethmac/rtl/verilog" }
+-ifn /home/raul/or1k/minsoc/prj/../prj/xilinx/ethmac.prj
+-ifmt Verilog
+-ofn ethmac
+-ofmt NGC
+-p DEVICE_PART
+-top ethmac
+-opt_mode Speed
+-opt_level 1
+-iobuf no

/xilinx/or1200_top.prj

0,0 → 1,63

+`include "/home/raul/or1k/minsoc/prj/../rtl/verilog/or1200/rtl/verilog/or1200_spram_512x20.v"
+`include "/home/raul/or1k/minsoc/prj/../rtl/verilog/or1200/rtl/verilog/or1200_spram_64x24.v"
+`include "/home/raul/or1k/minsoc/prj/../rtl/verilog/or1200/rtl/verilog/or1200_du.v"
+`include "/home/raul/or1k/minsoc/prj/../rtl/verilog/or1200/rtl/verilog/or1200_spram_2048x32_bw.v"
+`include "/home/raul/or1k/minsoc/prj/../rtl/verilog/or1200/rtl/verilog/or1200_rf.v"
+`include "/home/raul/or1k/minsoc/prj/../rtl/verilog/or1200/rtl/verilog/or1200_alu.v"
+`include "/home/raul/or1k/minsoc/prj/../rtl/verilog/or1200/rtl/verilog/or1200_dmmu_top.v"
+`include "/home/raul/or1k/minsoc/prj/../rtl/verilog/or1200/rtl/verilog/or1200_lsu.v"
+`include "/home/raul/or1k/minsoc/prj/../rtl/verilog/or1200/rtl/verilog/or1200_spram_1024x32.v"
+`include "/home/raul/or1k/minsoc/prj/../rtl/verilog/or1200/rtl/verilog/or1200_dc_top.v"
+`include "/home/raul/or1k/minsoc/prj/../rtl/verilog/or1200/rtl/verilog/or1200_cpu.v"
+`include "/home/raul/or1k/minsoc/prj/../rtl/verilog/or1200/rtl/verilog/or1200_gmultp2_32x32.v"
+`include "/home/raul/or1k/minsoc/prj/../rtl/verilog/or1200/rtl/verilog/or1200_immu_top.v"
+`include "/home/raul/or1k/minsoc/prj/../rtl/verilog/or1200/rtl/verilog/or1200_dpram_256x32.v"
+`include "/home/raul/or1k/minsoc/prj/../rtl/verilog/or1200/rtl/verilog/or1200_tt.v"
+`include "/home/raul/or1k/minsoc/prj/../rtl/verilog/or1200/rtl/verilog/or1200_iwb_biu.v"
+`include "/home/raul/or1k/minsoc/prj/../rtl/verilog/or1200/rtl/verilog/or1200_rfram_generic.v"
+`include "/home/raul/or1k/minsoc/prj/../rtl/verilog/or1200/rtl/verilog/or1200_dc_tag.v"
+`include "/home/raul/or1k/minsoc/prj/../rtl/verilog/or1200/rtl/verilog/or1200_spram_2048x8.v"
+`include "/home/raul/or1k/minsoc/prj/../rtl/verilog/or1200/rtl/verilog/or1200_immu_tlb.v"
+`include "/home/raul/or1k/minsoc/prj/../rtl/verilog/or1200/rtl/verilog/or1200_ic_tag.v"
+`include "/home/raul/or1k/minsoc/prj/../rtl/verilog/or1200/rtl/verilog/or1200_spram_64x14.v"
+`include "/home/raul/or1k/minsoc/prj/../rtl/verilog/or1200/rtl/verilog/or1200_spram_32x24.v"
+`include "/home/raul/or1k/minsoc/prj/../rtl/verilog/or1200/rtl/verilog/or1200_dpram_32x32.v"
+`include "/home/raul/or1k/minsoc/prj/../rtl/verilog/or1200/rtl/verilog/or1200_xcv_ram32x8d.v"
+`include "/home/raul/or1k/minsoc/prj/../rtl/verilog/or1200/rtl/verilog/or1200_spram_1024x8.v"
+`include "/home/raul/or1k/minsoc/prj/../rtl/verilog/or1200/rtl/verilog/or1200_mem2reg.v"
+`include "/home/raul/or1k/minsoc/prj/../rtl/verilog/or1200/rtl/verilog/or1200_pm.v"
+`include "/home/raul/or1k/minsoc/prj/../rtl/verilog/or1200/rtl/verilog/or1200_spram_256x21.v"
+`include "/home/raul/or1k/minsoc/prj/../rtl/verilog/or1200/rtl/verilog/or1200_operandmuxes.v"
+`include "/home/raul/or1k/minsoc/prj/../rtl/verilog/or1200/rtl/verilog/or1200_pic.v"
+`include "/home/raul/or1k/minsoc/prj/../rtl/verilog/or1200/rtl/verilog/or1200_cfgr.v"
+`include "/home/raul/or1k/minsoc/prj/../rtl/verilog/or1200/rtl/verilog/or1200_if.v"
+`include "/home/raul/or1k/minsoc/prj/../rtl/verilog/or1200/rtl/verilog/or1200_qmem_top.v"
+`include "/home/raul/or1k/minsoc/prj/../rtl/verilog/or1200/rtl/verilog/or1200_genpc.v"
+`include "/home/raul/or1k/minsoc/prj/../rtl/verilog/or1200/rtl/verilog/or1200_defines.v"
+`include "/home/raul/or1k/minsoc/prj/../rtl/verilog/or1200/rtl/verilog/or1200_wbmux.v"
+`include "/home/raul/or1k/minsoc/prj/../rtl/verilog/or1200/rtl/verilog/or1200_ic_ram.v"
+`include "/home/raul/or1k/minsoc/prj/../rtl/verilog/or1200/rtl/verilog/or1200_dmmu_tlb.v"
+`include "/home/raul/or1k/minsoc/prj/../rtl/verilog/or1200/rtl/verilog/or1200_sb_fifo.v"
+`include "/home/raul/or1k/minsoc/prj/../rtl/verilog/or1200/rtl/verilog/or1200_sprs.v"
+`include "/home/raul/or1k/minsoc/prj/../rtl/verilog/or1200/rtl/verilog/or1200_tpram_32x32.v"
+`include "/home/raul/or1k/minsoc/prj/../rtl/verilog/or1200/rtl/verilog/or1200_ctrl.v"
+`include "/home/raul/or1k/minsoc/prj/../rtl/verilog/or1200/rtl/verilog/or1200_sb.v"
+`include "/home/raul/or1k/minsoc/prj/../rtl/verilog/or1200/rtl/verilog/or1200_mult_mac.v"
+`include "/home/raul/or1k/minsoc/prj/../rtl/verilog/or1200/rtl/verilog/or1200_ic_fsm.v"
+`include "/home/raul/or1k/minsoc/prj/../rtl/verilog/or1200/rtl/verilog/or1200_amultp2_32x32.v"
+`include "/home/raul/or1k/minsoc/prj/../rtl/verilog/or1200/rtl/verilog/or1200_reg2mem.v"
+`include "/home/raul/or1k/minsoc/prj/../rtl/verilog/or1200/rtl/verilog/or1200_spram_2048x32.v"
+`include "/home/raul/or1k/minsoc/prj/../rtl/verilog/or1200/rtl/verilog/or1200_except.v"
+`include "/home/raul/or1k/minsoc/prj/../rtl/verilog/or1200/rtl/verilog/or1200_top.v"
+`include "/home/raul/or1k/minsoc/prj/../rtl/verilog/or1200/rtl/verilog/or1200_ic_top.v"
+`include "/home/raul/or1k/minsoc/prj/../rtl/verilog/or1200/rtl/verilog/or1200_dc_ram.v"
+`include "/home/raul/or1k/minsoc/prj/../rtl/verilog/or1200/rtl/verilog/or1200_spram_1024x32_bw.v"
+`include "/home/raul/or1k/minsoc/prj/../rtl/verilog/or1200/rtl/verilog/or1200_freeze.v"
+`include "/home/raul/or1k/minsoc/prj/../rtl/verilog/or1200/rtl/verilog/or1200_spram_128x32.v"
+`include "/home/raul/or1k/minsoc/prj/../rtl/verilog/or1200/rtl/verilog/or1200_dc_fsm.v"
+`include "/home/raul/or1k/minsoc/prj/../rtl/verilog/or1200/rtl/verilog/or1200_wb_biu.v"
+`include "/home/raul/or1k/minsoc/prj/../rtl/verilog/or1200/rtl/verilog/or1200_spram_64x22.v"
+`include "/home/raul/or1k/minsoc/prj/../rtl/verilog/or1200/rtl/verilog/or1200_fpu.v"
+`include "/home/raul/or1k/minsoc/prj/../rtl/verilog/or1200/rtl/verilog/or1200_spram.v"
+`include "/home/raul/or1k/minsoc/prj/../rtl/verilog/or1200/rtl/verilog/or1200_spram_32_bw.v"
+`include "/home/raul/or1k/minsoc/prj/../rtl/verilog/or1200/rtl/verilog/or1200_dpram.v"

/xilinx/jtag_top.prj

0,0 → 1,2

`include "/home/raul/or1k/minsoc/prj/../rtl/verilog/adv_debug_sys/Hardware/jtag/tap/rtl/verilog/tap_top.v"

`include "/home/raul/or1k/minsoc/prj/../rtl/verilog/adv_debug_sys/Hardware/jtag/tap/rtl/verilog/tap_defines.v"

/xilinx/uart_top.prj

0,0 → 1,11

+`include "/home/raul/or1k/minsoc/prj/../rtl/verilog/uart16550/rtl/verilog/uart_top.v"
+`include "/home/raul/or1k/minsoc/prj/../rtl/verilog/uart16550/rtl/verilog/uart_sync_flops.v"
+`include "/home/raul/or1k/minsoc/prj/../rtl/verilog/uart16550/rtl/verilog/uart_transmitter.v"
+`include "/home/raul/or1k/minsoc/prj/../rtl/verilog/uart16550/rtl/verilog/uart_debug_if.v"
+`include "/home/raul/or1k/minsoc/prj/../rtl/verilog/uart16550/rtl/verilog/uart_wb.v"
+`include "/home/raul/or1k/minsoc/prj/../rtl/verilog/uart16550/rtl/verilog/uart_receiver.v"
+`include "/home/raul/or1k/minsoc/prj/../rtl/verilog/uart16550/rtl/verilog/uart_tfifo.v"
+`include "/home/raul/or1k/minsoc/prj/../rtl/verilog/uart16550/rtl/verilog/uart_regs.v"
+`include "/home/raul/or1k/minsoc/prj/../rtl/verilog/uart16550/rtl/verilog/uart_rfifo.v"
+`include "/home/raul/or1k/minsoc/prj/../rtl/verilog/uart16550/rtl/verilog/uart_defines.v"
+`include "/home/raul/or1k/minsoc/prj/../rtl/verilog/uart16550/rtl/verilog/raminfr.v"

/xilinx/adbg_top.prj

0,0 → 1,10

+`include "/home/raul/or1k/minsoc/prj/../rtl/verilog/adv_debug_sys/Hardware/adv_dbg_if/rtl/verilog/adbg_wb_biu.v"
+`include "/home/raul/or1k/minsoc/prj/../rtl/verilog/adv_debug_sys/Hardware/adv_dbg_if/rtl/verilog/adbg_wb_module.v"
+`include "/home/raul/or1k/minsoc/prj/../rtl/verilog/adv_debug_sys/Hardware/adv_dbg_if/rtl/verilog/adbg_or1k_module.v"
+`include "/home/raul/or1k/minsoc/prj/../rtl/verilog/adv_debug_sys/Hardware/adv_dbg_if/rtl/verilog/adbg_wb_defines.v"
+`include "/home/raul/or1k/minsoc/prj/../rtl/verilog/adv_debug_sys/Hardware/adv_dbg_if/rtl/verilog/adbg_defines.v"
+`include "/home/raul/or1k/minsoc/prj/../rtl/verilog/adv_debug_sys/Hardware/adv_dbg_if/rtl/verilog/adbg_crc32.v"
+`include "/home/raul/or1k/minsoc/prj/../rtl/verilog/adv_debug_sys/Hardware/adv_dbg_if/rtl/verilog/adbg_or1k_biu.v"
+`include "/home/raul/or1k/minsoc/prj/../rtl/verilog/adv_debug_sys/Hardware/adv_dbg_if/rtl/verilog/adbg_or1k_defines.v"
+`include "/home/raul/or1k/minsoc/prj/../rtl/verilog/adv_debug_sys/Hardware/adv_dbg_if/rtl/verilog/adbg_or1k_status_reg.v"
+`include "/home/raul/or1k/minsoc/prj/../rtl/verilog/adv_debug_sys/Hardware/adv_dbg_if/rtl/verilog/adbg_top.v"

/xilinx/ethmac.prj

0,0 → 1,25

+`include "/home/raul/or1k/minsoc/prj/../rtl/verilog/ethmac/rtl/verilog/eth_cop.v"
+`include "/home/raul/or1k/minsoc/prj/../rtl/verilog/ethmac/rtl/verilog/eth_registers.v"
+`include "/home/raul/or1k/minsoc/prj/../rtl/verilog/ethmac/rtl/verilog/eth_rxethmac.v"
+`include "/home/raul/or1k/minsoc/prj/../rtl/verilog/ethmac/rtl/verilog/eth_miim.v"
+`include "/home/raul/or1k/minsoc/prj/../rtl/verilog/ethmac/rtl/verilog/ethmac.v"
+`include "/home/raul/or1k/minsoc/prj/../rtl/verilog/ethmac/rtl/verilog/eth_rxaddrcheck.v"
+`include "/home/raul/or1k/minsoc/prj/../rtl/verilog/ethmac/rtl/verilog/eth_outputcontrol.v"
+`include "/home/raul/or1k/minsoc/prj/../rtl/verilog/ethmac/rtl/verilog/eth_rxstatem.v"
+`include "/home/raul/or1k/minsoc/prj/../rtl/verilog/ethmac/rtl/verilog/eth_txethmac.v"
+`include "/home/raul/or1k/minsoc/prj/../rtl/verilog/ethmac/rtl/verilog/eth_wishbone.v"
+`include "/home/raul/or1k/minsoc/prj/../rtl/verilog/ethmac/rtl/verilog/eth_maccontrol.v"
+`include "/home/raul/or1k/minsoc/prj/../rtl/verilog/ethmac/rtl/verilog/eth_txstatem.v"
+`include "/home/raul/or1k/minsoc/prj/../rtl/verilog/ethmac/rtl/verilog/ethmac_defines.v"
+`include "/home/raul/or1k/minsoc/prj/../rtl/verilog/ethmac/rtl/verilog/eth_spram_256x32.v"
+`include "/home/raul/or1k/minsoc/prj/../rtl/verilog/ethmac/rtl/verilog/eth_shiftreg.v"
+`include "/home/raul/or1k/minsoc/prj/../rtl/verilog/ethmac/rtl/verilog/eth_clockgen.v"
+`include "/home/raul/or1k/minsoc/prj/../rtl/verilog/ethmac/rtl/verilog/eth_crc.v"
+`include "/home/raul/or1k/minsoc/prj/../rtl/verilog/ethmac/rtl/verilog/eth_rxcounters.v"
+`include "/home/raul/or1k/minsoc/prj/../rtl/verilog/ethmac/rtl/verilog/eth_macstatus.v"
+`include "/home/raul/or1k/minsoc/prj/../rtl/verilog/ethmac/rtl/verilog/eth_random.v"
+`include "/home/raul/or1k/minsoc/prj/../rtl/verilog/ethmac/rtl/verilog/eth_register.v"
+`include "/home/raul/or1k/minsoc/prj/../rtl/verilog/ethmac/rtl/verilog/eth_fifo.v"
+`include "/home/raul/or1k/minsoc/prj/../rtl/verilog/ethmac/rtl/verilog/eth_receivecontrol.v"
+`include "/home/raul/or1k/minsoc/prj/../rtl/verilog/ethmac/rtl/verilog/eth_transmitcontrol.v"
+`include "/home/raul/or1k/minsoc/prj/../rtl/verilog/ethmac/rtl/verilog/eth_txcounters.v"