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URL https://opencores.org/ocsvn/minsoc/minsoc/trunk

Subversion Repositories minsoc

Compare Revisions

  • This comparison shows the changes necessary to convert path
    /minsoc/trunk/rtl/verilog
    from Rev 156 to Rev 158
    Reverse comparison

Rev 156 → Rev 158

/interconnect_defines.v
0,0 → 1,26
//
// Interrupts
//
`define APP_INT_RES1 1:0
`define APP_INT_UART 2
`define APP_INT_RES2 3
`define APP_INT_ETH 4
`define APP_INT_PS2 5
`define APP_INT_JSP 6
`define APP_INT_RES3 19:7
 
//
// Address map
//
`define APP_ADDR_DEC_W 8
`define APP_ADDR_SRAM `APP_ADDR_DEC_W'h00
`define APP_ADDR_FLASH `APP_ADDR_DEC_W'h04
`define APP_ADDR_DECP_W 4
`define APP_ADDR_PERIP `APP_ADDR_DECP_W'h9
`define APP_ADDR_SPI `APP_ADDR_DEC_W'h97
`define APP_ADDR_ETH `APP_ADDR_DEC_W'h92
`define APP_ADDR_AUDIO `APP_ADDR_DEC_W'h9d
`define APP_ADDR_UART `APP_ADDR_DEC_W'h90
`define APP_ADDR_PS2 `APP_ADDR_DEC_W'h94
`define APP_ADDR_JSP `APP_ADDR_DEC_W'h9e
`define APP_ADDR_RES2 `APP_ADDR_DEC_W'h9f
/minsoc_top.v
1,4 → 1,5
`include "minsoc_defines.v"
`include "interconnect_defines.v"
`include "or1200_defines.v"
 
module minsoc_top (
116,6 → 117,19
wire wb_dm_err_i;
 
//
// Debug core JSP slave i/f wires
//
wire [31:0] wb_jsp_dat_i;
wire [31:0] wb_jsp_dat_o;
wire [31:0] wb_jsp_adr_i;
wire [3:0] wb_jsp_sel_i;
wire wb_jsp_we_i;
wire wb_jsp_cyc_i;
wire wb_jsp_stb_i;
wire wb_jsp_ack_o;
wire wb_jsp_err_o;
 
//
// Debug <-> RISC wires
//
wire [3:0] dbg_lss;
303,13 → 317,6
);
 
//
// Unused WISHBONE signals
//
assign wb_us_err_o = 1'b0;
assign wb_fs_err_o = 1'b0;
assign wb_sp_err_o = 1'b0;
 
//
// Unused interrupts
//
assign pic_ints[`APP_INT_RES1] = 'b0;
445,10 → 452,52
.cpu0_stb_o ( dbg_stb ),
.cpu0_we_o ( dbg_we ),
.cpu0_ack_i ( dbg_ack ),
.cpu0_rst_o ( )
.cpu0_rst_o ( ),
 
// WISHBONE slave interface (JTAG UART)
`ifdef JSP
.wb_jsp_adr_i ( wb_jsp_adr_i[31:0] ),
.wb_jsp_dat_i ( wb_jsp_dat_i[31:0] ),
.wb_jsp_dat_o ( wb_jsp_dat_o[31:0] ),
.wb_jsp_we_i ( wb_jsp_we_i ),
.wb_jsp_stb_i ( wb_jsp_stb_i ),
.wb_jsp_cyc_i ( wb_jsp_cyc_i ),
.wb_jsp_ack_o ( wb_jsp_ack_o ),
.wb_jsp_sel_i ( wb_jsp_sel_i[3:0] ),
.wb_jsp_cab_i ( 1'b0 ),
.wb_jsp_cti_i ( 3'b0 ),
.wb_jsp_bte_i ( 2'b0 ),
 
// Interrupt request
.int_o ( pic_ints[`APP_INT_JSP] )
`else
.wb_jsp_adr_i ( 32'h0000_0000 ),
.wb_jsp_dat_i ( 32'h0000_0000 ),
.wb_jsp_dat_o ( ),
.wb_jsp_we_i ( 1'b0 ),
.wb_jsp_stb_i ( 1'b0 ),
.wb_jsp_cyc_i ( 1'b0 ),
.wb_jsp_ack_o ( ),
.wb_jsp_sel_i ( 4'h0 ),
.wb_jsp_cab_i ( 1'b0 ),
.wb_jsp_cti_i ( 3'b0 ),
.wb_jsp_bte_i ( 2'b0 ),
 
// Interrupt request
.int_o ( )
`endif
);
 
`ifdef JSP
assign wb_jsp_err_o = 1'b0;
`else
assign wb_jsp_dat_o = 32'h0000_0000;
assign wb_jsp_ack_o = 1'b0;
assign wb_jsp_err_o = 1'b1;
assign pic_ints[`APP_INT_JSP] = 1'b0;
`endif
 
 
//
// JTAG TAP controller instantiation
//
631,11 → 680,17
.sclk_pad_o(spi_flash_sclk),
.ss_pad_o(spi_flash_ss)
);
 
assign wb_fs_err_o = 1'b0;
assign wb_sp_err_o = 1'b0;
 
`else
assign wb_fs_dat_o = 32'h0000_0000;
assign wb_fs_ack_o = 1'b0;
assign wb_fs_err_o = 1'b1;
assign wb_sp_dat_o = 32'h0000_0000;
assign wb_sp_ack_o = 1'b0;
assign wb_sp_err_o = 1'b1;
`endif
 
//
703,9 → 758,12
.ri_pad_i ( 1'b0 ),
.dcd_pad_i ( 1'b0 )
);
 
assign wb_us_err_o = 1'b0;
`else
assign wb_us_dat_o = 32'h0000_0000;
assign wb_us_ack_o = 1'b0;
assign wb_us_err_o = 1'b1;
 
assign pic_ints[`APP_INT_UART] = 1'b0;
`endif
768,7 → 826,7
`else
assign wb_es_dat_o = 32'h0000_0000;
assign wb_es_ack_o = 1'b0;
assign wb_es_err_o = 1'b0;
assign wb_es_err_o = 1'b1;
 
assign wb_em_adr_o = 32'h0000_0000;
assign wb_em_sel_o = 4'h0;
793,9 → 851,9
`APP_ADDR_SPI,
`APP_ADDR_ETH,
`APP_ADDR_AUDIO,
`APP_ADDR_UART,
`APP_ADDR_UART,
`APP_ADDR_PS2,
`APP_ADDR_RES1,
`APP_ADDR_JSP,
`APP_ADDR_RES2
) tc_top (
 
955,8 → 1013,8
.t5_wb_dat_o ( wb_us_dat_i ),
.t5_wb_dat_i ( wb_us_dat_o ),
.t5_wb_ack_i ( wb_us_ack_o ),
.t5_wb_err_i ( wb_us_err_o ),
 
.t5_wb_err_i ( wb_us_err_o ),
// WISHBONE Target 6
.t6_wb_cyc_o ( ),
.t6_wb_stb_o ( ),
969,17 → 1027,17
.t6_wb_err_i ( 1'b1 ),
 
// WISHBONE Target 7
.t7_wb_cyc_o ( ),
.t7_wb_stb_o ( ),
.t7_wb_adr_o ( ),
.t7_wb_sel_o ( ),
.t7_wb_we_o ( ),
.t7_wb_dat_o ( ),
.t7_wb_dat_i ( 32'h0000_0000 ),
.t7_wb_ack_i ( 1'b0 ),
.t7_wb_err_i ( 1'b1 ),
.t7_wb_cyc_o ( wb_jsp_cyc_i ),
.t7_wb_stb_o ( wb_jsp_stb_i ),
.t7_wb_adr_o ( wb_jsp_adr_i ),
.t7_wb_sel_o ( wb_jsp_sel_i ),
.t7_wb_we_o ( wb_jsp_we_i ),
.t7_wb_dat_o ( wb_jsp_dat_i ),
.t7_wb_dat_i ( wb_jsp_dat_o ),
.t7_wb_ack_i ( wb_jsp_ack_o ),
.t7_wb_err_i ( wb_jsp_err_o ),
 
// WISHBONE Target 8
// WISHBONE Target 8
.t8_wb_cyc_o ( ),
.t8_wb_stb_o ( ),
.t8_wb_adr_o ( ),

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