OpenCores
URL https://opencores.org/ocsvn/minsoc/minsoc/trunk

Subversion Repositories minsoc

Compare Revisions

  • This comparison shows the changes necessary to convert path
    /minsoc/trunk/rtl/verilog
    from Rev 156 to Rev 88
    Reverse comparison

Rev 156 → Rev 88

/minsoc_top.v
420,7 → 420,6
.debug_select_i( debug_select ),
// WISHBONE common
.wb_clk_i ( wb_clk ),
.wb_rst_i ( wb_rst ),
 
// WISHBONE master interface
.wb_adr_o ( wb_dm_adr_o ),
440,7 → 439,7
.cpu0_addr_o ( dbg_adr ),
.cpu0_data_i ( dbg_dat_risc ),
.cpu0_data_o ( dbg_dat_dbg ),
.cpu0_bp_i ( (dbg_bp | (| dbg_wp[10:0])) ),
.cpu0_bp_i ( dbg_bp ),
.cpu0_stall_o( dbg_stall ),
.cpu0_stb_o ( dbg_stb ),
.cpu0_we_o ( dbg_we ),

powered by: WebSVN 2.1.0

© copyright 1999-2019 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.