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URL https://opencores.org/ocsvn/minsoc/minsoc/trunk

Subversion Repositories minsoc

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  • This comparison shows the changes necessary to convert path
    /minsoc/trunk/rtl/verilog
    from Rev 17 to Rev 20
    Reverse comparison

Rev 17 → Rev 20

/minsoc_defines.v
58,8 → 58,8
//
// Reset polarity
//
//`define NEGATIVE_RESET; //rstn
`define POSITIVE_RESET; //rst
//`define NEGATIVE_RESET //rstn
`define POSITIVE_RESET //rst
 
//
// Start-up circuit (only necessary later to load firmware automatically from SPI memory)
/minsoc_top.v
127,8 → 127,9
wire [31:0] dbg_adr;
wire dbg_ewt;
wire dbg_stall;
wire [2:0] dbg_op; //dbg_op[0] = dbg_we //dbg_op[2] = dbg_stb (didn't change for backward compatibility with DBG_IF_MODEL
wire dbg_ack;
wire dbg_we;
wire dbg_stb;
wire dbg_ack;
 
//
// RISC instruction master i/f wires
437,8 → 438,8
.cpu0_data_o ( dbg_dat_dbg ),
.cpu0_bp_i ( dbg_bp ),
.cpu0_stall_o( dbg_stall ),
.cpu0_stb_o ( dbg_op[2] ),
.cpu0_we_o ( dbg_op[0] ),
.cpu0_stb_o ( dbg_stb ),
.cpu0_we_o ( dbg_we ),
.cpu0_ack_i ( dbg_ack ),
.cpu0_rst_o ( )
 
569,8 → 570,8
.dbg_bp_o ( dbg_bp ),
.dbg_dat_o ( dbg_dat_risc ),
.dbg_ack_o ( dbg_ack ),
.dbg_stb_i ( dbg_op[2] ),
.dbg_we_i ( dbg_op[0] ),
.dbg_stb_i ( dbg_stb ),
.dbg_we_i ( dbg_we ),
 
// Power Management
.pm_clksd_o ( ),

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