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URL https://opencores.org/ocsvn/minsoc/minsoc/trunk

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  • This comparison shows the changes necessary to convert path
    /minsoc/trunk/rtl/verilog
    from Rev 56 to Rev 53
    Reverse comparison

Rev 56 → Rev 53

/minsoc_clock_manager.v
9,8 → 9,9
//
// Parameters
//
parameter divisor = 2;
parameter divisor = 5;
parameter multiplier = 1;
 
input clk_i;
output clk_o;
31,53 → 32,18
assign clk_o = clk_int;
`elsif FPGA_CLOCK_DIVISION
 
`ifdef ALTERA_FPGA
`ifdef ARRIA_GX
defparam systemPll.FAMILY = "Arria GX";
`elsif ARRIA_II_GX
defparam systemPll.FAMILY = "Arria II GX";
`elsif CYCLONE_I
defparam systemPll.FAMILY = "Cyclone I";
`elsif CYCLONE_II
defparam systemPll.FAMILY = "Cyclone II";
`elsif CYCLONE_III
defparam systemPll.FAMILY = "Cyclone III";
`elsif CYCLONE_III_LS
defparam systemPll.FAMILY = "Cyclone III LS";
`elsif CYCLONE_IV_E
defparam systemPll.FAMILY = "Cyclone IV E";
`elsif CYCLONE_IV_GS
defparam systemPll.FAMILY = "Cyclone IV GS";
`elsif MAX_II
defparam systemPll.FAMILY = "MAX II";
`elsif MAX_V
defparam systemPll.FAMILY = "MAX V";
`elsif MAX3000A
defparam systemPll.FAMILY = "MAX3000A";
`elsif MAX7000AE
defparam systemPll.FAMILY = "MAX7000AE";
`elsif MAX7000B
defparam systemPll.FAMILY = "MAX7000B";
`elsif MAX7000S
defparam systemPll.FAMILY = "MAX7000S";
`elsif STRATIX
defparam systemPll.FAMILY = "Stratix";
`elsif STRATIX_II
defapram systemPll.FAMILY = "Stratix II";
`elsif STRATIX_II_GX
defparam systemPll.FAMILY = "Stratix II GX";
`elsif STRATIX_III
defparam systemPll.FAMILY = "Stratix III"
`endif
defparam systemPll.FREQ_DIV = divisor;
`ifdef ALTERA_FPGA
minsoc_pll
#(
multiplier,
divisor
)
systemPll
(
.inclk0(clk_i),
.c0(clk_o)
);
minsoc_pll systemPll
(
.inclk0(clk_i),
.c0(clk_o)
);
`elsif XILINX_FPGA
 
`ifdef SPARTAN2
/minsoc_pll.v
26,7 → 26,6
 
parameter FREQ_MULT = 1;
parameter FREQ_DIV = 1;
parameter FAMILY = "Cyclone III";
 
input inclk0;
output c0;
84,7 → 83,7
altpll_component.clk0_phase_shift = "0",
altpll_component.compensate_clock = "CLK0",
altpll_component.inclk0_input_frequency = 20000,
altpll_component.intended_device_family = FAMILY,
altpll_component.intended_device_family = "Cyclone III",
altpll_component.lpm_hint = "CBX_MODULE_PREFIX=minsocPll",
altpll_component.lpm_type = "altpll",
altpll_component.operation_mode = "NORMAL",
131,6 → 130,8
altpll_component.port_extclk2 = "PORT_UNUSED",
altpll_component.port_extclk3 = "PORT_UNUSED",
altpll_component.width_clock = 5;
 
 
endmodule
 
// ============================================================
/minsoc_defines.v
2,8 → 2,8
// Define FPGA manufacturer
//
//`define GENERIC_FPGA
`define ALTERA_FPGA
//`define XILINX_FPGA
//`define ALTERA_FPGA
`define XILINX_FPGA
 
//
// Define FPGA Model (comment all out for ALTERA)
11,32 → 11,12
//`define SPARTAN2
//`define SPARTAN3
//`define SPARTAN3E
//`define SPARTAN3A
`define SPARTAN3A
//`define VIRTEX
//`define VIRTEX2
//`define VIRTEX4
//`define VIRTEX5
 
//
// Define Altera FPGA Family (comment all out for XILINX)
//`define ARRIA_GX
//`define ARRIA_II_GX
//`define CYCLONE_I
//`define CYCLONE_II
`define CYCLONE_III
//`define CYCLONE_III_LS
//`define CYCLONE_IV_E
//`define CYCLONE_IV_GS
//`define MAX_II
//`define MAX_V
//`define MAX3000A
//`define MAX7000AE
//`define MAX7000B
//`define MAX7000S
//`define STRATIX
//`define STRATIX_II
//`define STRATIX_II_GX
//`define STRATIX_III
 
//
// Memory
66,20 → 46,25
//`define NO_CLOCK_DIVISION
//`define GENERIC_CLOCK_DIVISION
`define FPGA_CLOCK_DIVISION // Altera ALTPLL is yet implemented in Verilog and will be used with this option
// Note that only CYCLONE_III family has been tested.
 
//
// Define division
//
`define CLOCK_DIVISOR 1 //in case of GENERIC_CLOCK_DIVISION the real value will be rounded down to an even value
`define CLOCK_DIVISOR 4 //in case of GENERIC_CLOCK_DIVISION the real value will be rounded down to an even value
//in FPGA case, check minsoc_clock_manager for allowed divisors
//DO NOT USE CLOCK_DIVISOR = 1 COMMENT THE CLOCK DIVISION SELECTION INSTEAD
 
//
// Define multiply
//
`define CLOCK_MULTIPLIER 2 // In case of FPGA_CLOCK_DIVISION for Altera FPGAs, ALTPLL Megafunction will be used
// and this will need a clock multiply factor.
 
//
// Reset polarity
//
`define NEGATIVE_RESET //rstn
//`define POSITIVE_RESET //rst
//`define NEGATIVE_RESET //rstn
`define POSITIVE_RESET //rst
 
//
// Start-up circuit (only necessary later to load firmware automatically from SPI memory)
/minsoc_top.v
295,7 → 295,8
//
minsoc_clock_manager #
(
.divisor(`CLOCK_DIVISOR)
.divisor(`CLOCK_DIVISOR),
.multiplier(`CLOCK_MULTIPLIER)
)
clk_adjust (
.clk_i(clk),

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