URL
https://opencores.org/ocsvn/minsoc/minsoc/trunk
Subversion Repositories minsoc
Compare Revisions
- This comparison shows the changes necessary to convert path
/minsoc/trunk/rtl/verilog
- from Rev 7 to Rev 6
- ↔ Reverse comparison
Rev 7 → Rev 6
/minsoc_onchip_ram.v
436,6 → 436,7
lpm_ram_dq lpm_ram_dq_component ( |
.address(addr), |
.inclock(clk), |
// .outclock(clk), |
.data(di), |
.we(wr), |
.q(doq_internal) |
/minsoc_tc_top.v
86,7 → 86,7
// |
// Width of WB initiator inputs (coming from WB masters) |
// |
// cyc + stb + address bus width + |
// cyc + stb + cab + address bus width + |
// byte select bus width + we + data bus width |
// |
`define TC_IIN_W 1+1+1+`TC_AW+`TC_BSW+1+`TC_DW |
100,6 → 100,7
|
i0_wb_cyc_i, |
i0_wb_stb_i, |
i0_wb_cab_i, |
i0_wb_adr_i, |
i0_wb_sel_i, |
i0_wb_we_i, |
110,6 → 111,7
|
i1_wb_cyc_i, |
i1_wb_stb_i, |
i1_wb_cab_i, |
i1_wb_adr_i, |
i1_wb_sel_i, |
i1_wb_we_i, |
120,6 → 122,7
|
i2_wb_cyc_i, |
i2_wb_stb_i, |
i2_wb_cab_i, |
i2_wb_adr_i, |
i2_wb_sel_i, |
i2_wb_we_i, |
130,6 → 133,7
|
i3_wb_cyc_i, |
i3_wb_stb_i, |
i3_wb_cab_i, |
i3_wb_adr_i, |
i3_wb_sel_i, |
i3_wb_we_i, |
140,6 → 144,7
|
i4_wb_cyc_i, |
i4_wb_stb_i, |
i4_wb_cab_i, |
i4_wb_adr_i, |
i4_wb_sel_i, |
i4_wb_we_i, |
150,6 → 155,7
|
i5_wb_cyc_i, |
i5_wb_stb_i, |
i5_wb_cab_i, |
i5_wb_adr_i, |
i5_wb_sel_i, |
i5_wb_we_i, |
160,6 → 166,7
|
i6_wb_cyc_i, |
i6_wb_stb_i, |
i6_wb_cab_i, |
i6_wb_adr_i, |
i6_wb_sel_i, |
i6_wb_we_i, |
170,6 → 177,7
|
i7_wb_cyc_i, |
i7_wb_stb_i, |
i7_wb_cab_i, |
i7_wb_adr_i, |
i7_wb_sel_i, |
i7_wb_we_i, |
180,6 → 188,7
|
t0_wb_cyc_o, |
t0_wb_stb_o, |
t0_wb_cab_o, |
t0_wb_adr_o, |
t0_wb_sel_o, |
t0_wb_we_o, |
190,6 → 199,7
|
t1_wb_cyc_o, |
t1_wb_stb_o, |
t1_wb_cab_o, |
t1_wb_adr_o, |
t1_wb_sel_o, |
t1_wb_we_o, |
200,6 → 210,7
|
t2_wb_cyc_o, |
t2_wb_stb_o, |
t2_wb_cab_o, |
t2_wb_adr_o, |
t2_wb_sel_o, |
t2_wb_we_o, |
210,6 → 221,7
|
t3_wb_cyc_o, |
t3_wb_stb_o, |
t3_wb_cab_o, |
t3_wb_adr_o, |
t3_wb_sel_o, |
t3_wb_we_o, |
220,6 → 232,7
|
t4_wb_cyc_o, |
t4_wb_stb_o, |
t4_wb_cab_o, |
t4_wb_adr_o, |
t4_wb_sel_o, |
t4_wb_we_o, |
230,6 → 243,7
|
t5_wb_cyc_o, |
t5_wb_stb_o, |
t5_wb_cab_o, |
t5_wb_adr_o, |
t5_wb_sel_o, |
t5_wb_we_o, |
240,6 → 254,7
|
t6_wb_cyc_o, |
t6_wb_stb_o, |
t6_wb_cab_o, |
t6_wb_adr_o, |
t6_wb_sel_o, |
t6_wb_we_o, |
250,6 → 265,7
|
t7_wb_cyc_o, |
t7_wb_stb_o, |
t7_wb_cab_o, |
t7_wb_adr_o, |
t7_wb_sel_o, |
t7_wb_we_o, |
260,6 → 276,7
|
t8_wb_cyc_o, |
t8_wb_stb_o, |
t8_wb_cab_o, |
t8_wb_adr_o, |
t8_wb_sel_o, |
t8_wb_we_o, |
299,6 → 316,7
// |
input i0_wb_cyc_i; |
input i0_wb_stb_i; |
input i0_wb_cab_i; |
input [`TC_AW-1:0] i0_wb_adr_i; |
input [`TC_BSW-1:0] i0_wb_sel_i; |
input i0_wb_we_i; |
312,6 → 330,7
// |
input i1_wb_cyc_i; |
input i1_wb_stb_i; |
input i1_wb_cab_i; |
input [`TC_AW-1:0] i1_wb_adr_i; |
input [`TC_BSW-1:0] i1_wb_sel_i; |
input i1_wb_we_i; |
325,6 → 344,7
// |
input i2_wb_cyc_i; |
input i2_wb_stb_i; |
input i2_wb_cab_i; |
input [`TC_AW-1:0] i2_wb_adr_i; |
input [`TC_BSW-1:0] i2_wb_sel_i; |
input i2_wb_we_i; |
338,6 → 358,7
// |
input i3_wb_cyc_i; |
input i3_wb_stb_i; |
input i3_wb_cab_i; |
input [`TC_AW-1:0] i3_wb_adr_i; |
input [`TC_BSW-1:0] i3_wb_sel_i; |
input i3_wb_we_i; |
351,6 → 372,7
// |
input i4_wb_cyc_i; |
input i4_wb_stb_i; |
input i4_wb_cab_i; |
input [`TC_AW-1:0] i4_wb_adr_i; |
input [`TC_BSW-1:0] i4_wb_sel_i; |
input i4_wb_we_i; |
364,6 → 386,7
// |
input i5_wb_cyc_i; |
input i5_wb_stb_i; |
input i5_wb_cab_i; |
input [`TC_AW-1:0] i5_wb_adr_i; |
input [`TC_BSW-1:0] i5_wb_sel_i; |
input i5_wb_we_i; |
377,6 → 400,7
// |
input i6_wb_cyc_i; |
input i6_wb_stb_i; |
input i6_wb_cab_i; |
input [`TC_AW-1:0] i6_wb_adr_i; |
input [`TC_BSW-1:0] i6_wb_sel_i; |
input i6_wb_we_i; |
390,6 → 414,7
// |
input i7_wb_cyc_i; |
input i7_wb_stb_i; |
input i7_wb_cab_i; |
input [`TC_AW-1:0] i7_wb_adr_i; |
input [`TC_BSW-1:0] i7_wb_sel_i; |
input i7_wb_we_i; |
403,6 → 428,7
// |
output t0_wb_cyc_o; |
output t0_wb_stb_o; |
output t0_wb_cab_o; |
output [`TC_AW-1:0] t0_wb_adr_o; |
output [`TC_BSW-1:0] t0_wb_sel_o; |
output t0_wb_we_o; |
416,6 → 442,7
// |
output t1_wb_cyc_o; |
output t1_wb_stb_o; |
output t1_wb_cab_o; |
output [`TC_AW-1:0] t1_wb_adr_o; |
output [`TC_BSW-1:0] t1_wb_sel_o; |
output t1_wb_we_o; |
429,6 → 456,7
// |
output t2_wb_cyc_o; |
output t2_wb_stb_o; |
output t2_wb_cab_o; |
output [`TC_AW-1:0] t2_wb_adr_o; |
output [`TC_BSW-1:0] t2_wb_sel_o; |
output t2_wb_we_o; |
442,6 → 470,7
// |
output t3_wb_cyc_o; |
output t3_wb_stb_o; |
output t3_wb_cab_o; |
output [`TC_AW-1:0] t3_wb_adr_o; |
output [`TC_BSW-1:0] t3_wb_sel_o; |
output t3_wb_we_o; |
455,6 → 484,7
// |
output t4_wb_cyc_o; |
output t4_wb_stb_o; |
output t4_wb_cab_o; |
output [`TC_AW-1:0] t4_wb_adr_o; |
output [`TC_BSW-1:0] t4_wb_sel_o; |
output t4_wb_we_o; |
468,6 → 498,7
// |
output t5_wb_cyc_o; |
output t5_wb_stb_o; |
output t5_wb_cab_o; |
output [`TC_AW-1:0] t5_wb_adr_o; |
output [`TC_BSW-1:0] t5_wb_sel_o; |
output t5_wb_we_o; |
481,6 → 512,7
// |
output t6_wb_cyc_o; |
output t6_wb_stb_o; |
output t6_wb_cab_o; |
output [`TC_AW-1:0] t6_wb_adr_o; |
output [`TC_BSW-1:0] t6_wb_sel_o; |
output t6_wb_we_o; |
494,6 → 526,7
// |
output t7_wb_cyc_o; |
output t7_wb_stb_o; |
output t7_wb_cab_o; |
output [`TC_AW-1:0] t7_wb_adr_o; |
output [`TC_BSW-1:0] t7_wb_sel_o; |
output t7_wb_we_o; |
507,6 → 540,7
// |
output t8_wb_cyc_o; |
output t8_wb_stb_o; |
output t8_wb_cab_o; |
output [`TC_AW-1:0] t8_wb_adr_o; |
output [`TC_BSW-1:0] t8_wb_sel_o; |
output t8_wb_we_o; |
577,6 → 611,7
// |
wire z_wb_cyc_i; |
wire z_wb_stb_i; |
wire z_wb_cab_i; |
wire [`TC_AW-1:0] z_wb_adr_i; |
wire [`TC_BSW-1:0] z_wb_sel_i; |
wire z_wb_we_i; |
623,6 → 658,7
|
.i0_wb_cyc_i(i0_wb_cyc_i), |
.i0_wb_stb_i(i0_wb_stb_i), |
.i0_wb_cab_i(i0_wb_cab_i), |
.i0_wb_adr_i(i0_wb_adr_i), |
.i0_wb_sel_i(i0_wb_sel_i), |
.i0_wb_we_i(i0_wb_we_i), |
633,6 → 669,7
|
.i1_wb_cyc_i(i1_wb_cyc_i), |
.i1_wb_stb_i(i1_wb_stb_i), |
.i1_wb_cab_i(i1_wb_cab_i), |
.i1_wb_adr_i(i1_wb_adr_i), |
.i1_wb_sel_i(i1_wb_sel_i), |
.i1_wb_we_i(i1_wb_we_i), |
643,6 → 680,7
|
.i2_wb_cyc_i(i2_wb_cyc_i), |
.i2_wb_stb_i(i2_wb_stb_i), |
.i2_wb_cab_i(i2_wb_cab_i), |
.i2_wb_adr_i(i2_wb_adr_i), |
.i2_wb_sel_i(i2_wb_sel_i), |
.i2_wb_we_i(i2_wb_we_i), |
653,6 → 691,7
|
.i3_wb_cyc_i(i3_wb_cyc_i), |
.i3_wb_stb_i(i3_wb_stb_i), |
.i3_wb_cab_i(i3_wb_cab_i), |
.i3_wb_adr_i(i3_wb_adr_i), |
.i3_wb_sel_i(i3_wb_sel_i), |
.i3_wb_we_i(i3_wb_we_i), |
663,6 → 702,7
|
.i4_wb_cyc_i(i4_wb_cyc_i), |
.i4_wb_stb_i(i4_wb_stb_i), |
.i4_wb_cab_i(i4_wb_cab_i), |
.i4_wb_adr_i(i4_wb_adr_i), |
.i4_wb_sel_i(i4_wb_sel_i), |
.i4_wb_we_i(i4_wb_we_i), |
673,6 → 713,7
|
.i5_wb_cyc_i(i5_wb_cyc_i), |
.i5_wb_stb_i(i5_wb_stb_i), |
.i5_wb_cab_i(i5_wb_cab_i), |
.i5_wb_adr_i(i5_wb_adr_i), |
.i5_wb_sel_i(i5_wb_sel_i), |
.i5_wb_we_i(i5_wb_we_i), |
683,6 → 724,7
|
.i6_wb_cyc_i(i6_wb_cyc_i), |
.i6_wb_stb_i(i6_wb_stb_i), |
.i6_wb_cab_i(i6_wb_cab_i), |
.i6_wb_adr_i(i6_wb_adr_i), |
.i6_wb_sel_i(i6_wb_sel_i), |
.i6_wb_we_i(i6_wb_we_i), |
693,6 → 735,7
|
.i7_wb_cyc_i(i7_wb_cyc_i), |
.i7_wb_stb_i(i7_wb_stb_i), |
.i7_wb_cab_i(i7_wb_cab_i), |
.i7_wb_adr_i(i7_wb_adr_i), |
.i7_wb_sel_i(i7_wb_sel_i), |
.i7_wb_we_i(i7_wb_we_i), |
703,6 → 746,7
|
.t0_wb_cyc_o(t0_wb_cyc_o), |
.t0_wb_stb_o(t0_wb_stb_o), |
.t0_wb_cab_o(t0_wb_cab_o), |
.t0_wb_adr_o(t0_wb_adr_o), |
.t0_wb_sel_o(t0_wb_sel_o), |
.t0_wb_we_o(t0_wb_we_o), |
723,6 → 767,7
|
.i0_wb_cyc_i(i0_wb_cyc_i), |
.i0_wb_stb_i(i0_wb_stb_i), |
.i0_wb_cab_i(i0_wb_cab_i), |
.i0_wb_adr_i(i0_wb_adr_i), |
.i0_wb_sel_i(i0_wb_sel_i), |
.i0_wb_we_i(i0_wb_we_i), |
733,6 → 778,7
|
.i1_wb_cyc_i(i1_wb_cyc_i), |
.i1_wb_stb_i(i1_wb_stb_i), |
.i1_wb_cab_i(i1_wb_cab_i), |
.i1_wb_adr_i(i1_wb_adr_i), |
.i1_wb_sel_i(i1_wb_sel_i), |
.i1_wb_we_i(i1_wb_we_i), |
743,6 → 789,7
|
.i2_wb_cyc_i(i2_wb_cyc_i), |
.i2_wb_stb_i(i2_wb_stb_i), |
.i2_wb_cab_i(i2_wb_cab_i), |
.i2_wb_adr_i(i2_wb_adr_i), |
.i2_wb_sel_i(i2_wb_sel_i), |
.i2_wb_we_i(i2_wb_we_i), |
753,6 → 800,7
|
.i3_wb_cyc_i(i3_wb_cyc_i), |
.i3_wb_stb_i(i3_wb_stb_i), |
.i3_wb_cab_i(i3_wb_cab_i), |
.i3_wb_adr_i(i3_wb_adr_i), |
.i3_wb_sel_i(i3_wb_sel_i), |
.i3_wb_we_i(i3_wb_we_i), |
763,6 → 811,7
|
.i4_wb_cyc_i(i4_wb_cyc_i), |
.i4_wb_stb_i(i4_wb_stb_i), |
.i4_wb_cab_i(i4_wb_cab_i), |
.i4_wb_adr_i(i4_wb_adr_i), |
.i4_wb_sel_i(i4_wb_sel_i), |
.i4_wb_we_i(i4_wb_we_i), |
773,6 → 822,7
|
.i5_wb_cyc_i(i5_wb_cyc_i), |
.i5_wb_stb_i(i5_wb_stb_i), |
.i5_wb_cab_i(i5_wb_cab_i), |
.i5_wb_adr_i(i5_wb_adr_i), |
.i5_wb_sel_i(i5_wb_sel_i), |
.i5_wb_we_i(i5_wb_we_i), |
783,6 → 833,7
|
.i6_wb_cyc_i(i6_wb_cyc_i), |
.i6_wb_stb_i(i6_wb_stb_i), |
.i6_wb_cab_i(i6_wb_cab_i), |
.i6_wb_adr_i(i6_wb_adr_i), |
.i6_wb_sel_i(i6_wb_sel_i), |
.i6_wb_we_i(i6_wb_we_i), |
793,6 → 844,7
|
.i7_wb_cyc_i(i7_wb_cyc_i), |
.i7_wb_stb_i(i7_wb_stb_i), |
.i7_wb_cab_i(i7_wb_cab_i), |
.i7_wb_adr_i(i7_wb_adr_i), |
.i7_wb_sel_i(i7_wb_sel_i), |
.i7_wb_we_i(i7_wb_we_i), |
803,6 → 855,7
|
.t0_wb_cyc_o(z_wb_cyc_i), |
.t0_wb_stb_o(z_wb_stb_i), |
.t0_wb_cab_o(z_wb_cab_i), |
.t0_wb_adr_o(z_wb_adr_i), |
.t0_wb_sel_o(z_wb_sel_i), |
.t0_wb_we_o(z_wb_we_i), |
821,6 → 874,7
|
.i0_wb_cyc_i(z_wb_cyc_i), |
.i0_wb_stb_i(z_wb_stb_i), |
.i0_wb_cab_i(z_wb_cab_i), |
.i0_wb_adr_i(z_wb_adr_i), |
.i0_wb_sel_i(z_wb_sel_i), |
.i0_wb_we_i(z_wb_we_i), |
831,6 → 885,7
|
.t0_wb_cyc_o(t1_wb_cyc_o), |
.t0_wb_stb_o(t1_wb_stb_o), |
.t0_wb_cab_o(t1_wb_cab_o), |
.t0_wb_adr_o(t1_wb_adr_o), |
.t0_wb_sel_o(t1_wb_sel_o), |
.t0_wb_we_o(t1_wb_we_o), |
841,6 → 896,7
|
.t1_wb_cyc_o(t2_wb_cyc_o), |
.t1_wb_stb_o(t2_wb_stb_o), |
.t1_wb_cab_o(t2_wb_cab_o), |
.t1_wb_adr_o(t2_wb_adr_o), |
.t1_wb_sel_o(t2_wb_sel_o), |
.t1_wb_we_o(t2_wb_we_o), |
851,6 → 907,7
|
.t2_wb_cyc_o(t3_wb_cyc_o), |
.t2_wb_stb_o(t3_wb_stb_o), |
.t2_wb_cab_o(t3_wb_cab_o), |
.t2_wb_adr_o(t3_wb_adr_o), |
.t2_wb_sel_o(t3_wb_sel_o), |
.t2_wb_we_o(t3_wb_we_o), |
861,6 → 918,7
|
.t3_wb_cyc_o(t4_wb_cyc_o), |
.t3_wb_stb_o(t4_wb_stb_o), |
.t3_wb_cab_o(t4_wb_cab_o), |
.t3_wb_adr_o(t4_wb_adr_o), |
.t3_wb_sel_o(t4_wb_sel_o), |
.t3_wb_we_o(t4_wb_we_o), |
871,6 → 929,7
|
.t4_wb_cyc_o(t5_wb_cyc_o), |
.t4_wb_stb_o(t5_wb_stb_o), |
.t4_wb_cab_o(t5_wb_cab_o), |
.t4_wb_adr_o(t5_wb_adr_o), |
.t4_wb_sel_o(t5_wb_sel_o), |
.t4_wb_we_o(t5_wb_we_o), |
881,6 → 940,7
|
.t5_wb_cyc_o(t6_wb_cyc_o), |
.t5_wb_stb_o(t6_wb_stb_o), |
.t5_wb_cab_o(t6_wb_cab_o), |
.t5_wb_adr_o(t6_wb_adr_o), |
.t5_wb_sel_o(t6_wb_sel_o), |
.t5_wb_we_o(t6_wb_we_o), |
891,6 → 951,7
|
.t6_wb_cyc_o(t7_wb_cyc_o), |
.t6_wb_stb_o(t7_wb_stb_o), |
.t6_wb_cab_o(t7_wb_cab_o), |
.t6_wb_adr_o(t7_wb_adr_o), |
.t6_wb_sel_o(t7_wb_sel_o), |
.t6_wb_we_o(t7_wb_we_o), |
901,6 → 962,7
|
.t7_wb_cyc_o(t8_wb_cyc_o), |
.t7_wb_stb_o(t8_wb_stb_o), |
.t7_wb_cab_o(t8_wb_cab_o), |
.t7_wb_adr_o(t8_wb_adr_o), |
.t7_wb_sel_o(t8_wb_sel_o), |
.t7_wb_we_o(t8_wb_we_o), |
922,6 → 984,7
|
i0_wb_cyc_i, |
i0_wb_stb_i, |
i0_wb_cab_i, |
i0_wb_adr_i, |
i0_wb_sel_i, |
i0_wb_we_i, |
932,6 → 995,7
|
i1_wb_cyc_i, |
i1_wb_stb_i, |
i1_wb_cab_i, |
i1_wb_adr_i, |
i1_wb_sel_i, |
i1_wb_we_i, |
942,6 → 1006,7
|
i2_wb_cyc_i, |
i2_wb_stb_i, |
i2_wb_cab_i, |
i2_wb_adr_i, |
i2_wb_sel_i, |
i2_wb_we_i, |
952,6 → 1017,7
|
i3_wb_cyc_i, |
i3_wb_stb_i, |
i3_wb_cab_i, |
i3_wb_adr_i, |
i3_wb_sel_i, |
i3_wb_we_i, |
962,6 → 1028,7
|
i4_wb_cyc_i, |
i4_wb_stb_i, |
i4_wb_cab_i, |
i4_wb_adr_i, |
i4_wb_sel_i, |
i4_wb_we_i, |
972,6 → 1039,7
|
i5_wb_cyc_i, |
i5_wb_stb_i, |
i5_wb_cab_i, |
i5_wb_adr_i, |
i5_wb_sel_i, |
i5_wb_we_i, |
982,6 → 1050,7
|
i6_wb_cyc_i, |
i6_wb_stb_i, |
i6_wb_cab_i, |
i6_wb_adr_i, |
i6_wb_sel_i, |
i6_wb_we_i, |
992,6 → 1061,7
|
i7_wb_cyc_i, |
i7_wb_stb_i, |
i7_wb_cab_i, |
i7_wb_adr_i, |
i7_wb_sel_i, |
i7_wb_we_i, |
1002,6 → 1072,7
|
t0_wb_cyc_o, |
t0_wb_stb_o, |
t0_wb_cab_o, |
t0_wb_adr_o, |
t0_wb_sel_o, |
t0_wb_we_o, |
1032,6 → 1103,7
// |
input i0_wb_cyc_i; |
input i0_wb_stb_i; |
input i0_wb_cab_i; |
input [`TC_AW-1:0] i0_wb_adr_i; |
input [`TC_BSW-1:0] i0_wb_sel_i; |
input i0_wb_we_i; |
1045,6 → 1117,7
// |
input i1_wb_cyc_i; |
input i1_wb_stb_i; |
input i1_wb_cab_i; |
input [`TC_AW-1:0] i1_wb_adr_i; |
input [`TC_BSW-1:0] i1_wb_sel_i; |
input i1_wb_we_i; |
1058,6 → 1131,7
// |
input i2_wb_cyc_i; |
input i2_wb_stb_i; |
input i2_wb_cab_i; |
input [`TC_AW-1:0] i2_wb_adr_i; |
input [`TC_BSW-1:0] i2_wb_sel_i; |
input i2_wb_we_i; |
1071,6 → 1145,7
// |
input i3_wb_cyc_i; |
input i3_wb_stb_i; |
input i3_wb_cab_i; |
input [`TC_AW-1:0] i3_wb_adr_i; |
input [`TC_BSW-1:0] i3_wb_sel_i; |
input i3_wb_we_i; |
1084,6 → 1159,7
// |
input i4_wb_cyc_i; |
input i4_wb_stb_i; |
input i4_wb_cab_i; |
input [`TC_AW-1:0] i4_wb_adr_i; |
input [`TC_BSW-1:0] i4_wb_sel_i; |
input i4_wb_we_i; |
1097,6 → 1173,7
// |
input i5_wb_cyc_i; |
input i5_wb_stb_i; |
input i5_wb_cab_i; |
input [`TC_AW-1:0] i5_wb_adr_i; |
input [`TC_BSW-1:0] i5_wb_sel_i; |
input i5_wb_we_i; |
1110,6 → 1187,7
// |
input i6_wb_cyc_i; |
input i6_wb_stb_i; |
input i6_wb_cab_i; |
input [`TC_AW-1:0] i6_wb_adr_i; |
input [`TC_BSW-1:0] i6_wb_sel_i; |
input i6_wb_we_i; |
1123,6 → 1201,7
// |
input i7_wb_cyc_i; |
input i7_wb_stb_i; |
input i7_wb_cab_i; |
input [`TC_AW-1:0] i7_wb_adr_i; |
input [`TC_BSW-1:0] i7_wb_sel_i; |
input i7_wb_we_i; |
1136,6 → 1215,7
// |
output t0_wb_cyc_o; |
output t0_wb_stb_o; |
output t0_wb_cab_o; |
output [`TC_AW-1:0] t0_wb_adr_o; |
output [`TC_BSW-1:0] t0_wb_sel_o; |
output t0_wb_we_o; |
1165,7 → 1245,7
// |
// Group WB initiator 0 i/f inputs and outputs |
// |
assign i0_in = {i0_wb_cyc_i, i0_wb_stb_i, i0_wb_adr_i, |
assign i0_in = {i0_wb_cyc_i, i0_wb_stb_i, i0_wb_cab_i, i0_wb_adr_i, |
i0_wb_sel_i, i0_wb_we_i, i0_wb_dat_i}; |
assign {i0_wb_dat_o, i0_wb_ack_o, i0_wb_err_o} = i0_out; |
|
1172,7 → 1252,7
// |
// Group WB initiator 1 i/f inputs and outputs |
// |
assign i1_in = {i1_wb_cyc_i, i1_wb_stb_i, i1_wb_adr_i, |
assign i1_in = {i1_wb_cyc_i, i1_wb_stb_i, i1_wb_cab_i, i1_wb_adr_i, |
i1_wb_sel_i, i1_wb_we_i, i1_wb_dat_i}; |
assign {i1_wb_dat_o, i1_wb_ack_o, i1_wb_err_o} = i1_out; |
|
1179,7 → 1259,7
// |
// Group WB initiator 2 i/f inputs and outputs |
// |
assign i2_in = {i2_wb_cyc_i, i2_wb_stb_i, i2_wb_adr_i, |
assign i2_in = {i2_wb_cyc_i, i2_wb_stb_i, i2_wb_cab_i, i2_wb_adr_i, |
i2_wb_sel_i, i2_wb_we_i, i2_wb_dat_i}; |
assign {i2_wb_dat_o, i2_wb_ack_o, i2_wb_err_o} = i2_out; |
|
1186,7 → 1266,7
// |
// Group WB initiator 3 i/f inputs and outputs |
// |
assign i3_in = {i3_wb_cyc_i, i3_wb_stb_i, i3_wb_adr_i, |
assign i3_in = {i3_wb_cyc_i, i3_wb_stb_i, i3_wb_cab_i, i3_wb_adr_i, |
i3_wb_sel_i, i3_wb_we_i, i3_wb_dat_i}; |
assign {i3_wb_dat_o, i3_wb_ack_o, i3_wb_err_o} = i3_out; |
|
1193,7 → 1273,7
// |
// Group WB initiator 4 i/f inputs and outputs |
// |
assign i4_in = {i4_wb_cyc_i, i4_wb_stb_i, i4_wb_adr_i, |
assign i4_in = {i4_wb_cyc_i, i4_wb_stb_i, i4_wb_cab_i, i4_wb_adr_i, |
i4_wb_sel_i, i4_wb_we_i, i4_wb_dat_i}; |
assign {i4_wb_dat_o, i4_wb_ack_o, i4_wb_err_o} = i4_out; |
|
1200,7 → 1280,7
// |
// Group WB initiator 5 i/f inputs and outputs |
// |
assign i5_in = {i5_wb_cyc_i, i5_wb_stb_i, i5_wb_adr_i, |
assign i5_in = {i5_wb_cyc_i, i5_wb_stb_i, i5_wb_cab_i, i5_wb_adr_i, |
i5_wb_sel_i, i5_wb_we_i, i5_wb_dat_i}; |
assign {i5_wb_dat_o, i5_wb_ack_o, i5_wb_err_o} = i5_out; |
|
1207,7 → 1287,7
// |
// Group WB initiator 6 i/f inputs and outputs |
// |
assign i6_in = {i6_wb_cyc_i, i6_wb_stb_i, i6_wb_adr_i, |
assign i6_in = {i6_wb_cyc_i, i6_wb_stb_i, i6_wb_cab_i, i6_wb_adr_i, |
i6_wb_sel_i, i6_wb_we_i, i6_wb_dat_i}; |
assign {i6_wb_dat_o, i6_wb_ack_o, i6_wb_err_o} = i6_out; |
|
1214,7 → 1294,7
// |
// Group WB initiator 7 i/f inputs and outputs |
// |
assign i7_in = {i7_wb_cyc_i, i7_wb_stb_i, i7_wb_adr_i, |
assign i7_in = {i7_wb_cyc_i, i7_wb_stb_i, i7_wb_cab_i, i7_wb_adr_i, |
i7_wb_sel_i, i7_wb_we_i, i7_wb_dat_i}; |
assign {i7_wb_dat_o, i7_wb_ack_o, i7_wb_err_o} = i7_out; |
|
1221,7 → 1301,7
// |
// Group WB target 0 i/f inputs and outputs |
// |
assign {t0_wb_cyc_o, t0_wb_stb_o, t0_wb_adr_o, |
assign {t0_wb_cyc_o, t0_wb_stb_o, t0_wb_cab_o, t0_wb_adr_o, |
t0_wb_sel_o, t0_wb_we_o, t0_wb_dat_o} = t0_out; |
assign t0_in = {t0_wb_dat_i, t0_wb_ack_i, t0_wb_err_i}; |
|
1336,6 → 1416,7
|
i0_wb_cyc_i, |
i0_wb_stb_i, |
i0_wb_cab_i, |
i0_wb_adr_i, |
i0_wb_sel_i, |
i0_wb_we_i, |
1346,6 → 1427,7
|
t0_wb_cyc_o, |
t0_wb_stb_o, |
t0_wb_cab_o, |
t0_wb_adr_o, |
t0_wb_sel_o, |
t0_wb_we_o, |
1356,6 → 1438,7
|
t1_wb_cyc_o, |
t1_wb_stb_o, |
t1_wb_cab_o, |
t1_wb_adr_o, |
t1_wb_sel_o, |
t1_wb_we_o, |
1366,6 → 1449,7
|
t2_wb_cyc_o, |
t2_wb_stb_o, |
t2_wb_cab_o, |
t2_wb_adr_o, |
t2_wb_sel_o, |
t2_wb_we_o, |
1376,6 → 1460,7
|
t3_wb_cyc_o, |
t3_wb_stb_o, |
t3_wb_cab_o, |
t3_wb_adr_o, |
t3_wb_sel_o, |
t3_wb_we_o, |
1386,6 → 1471,7
|
t4_wb_cyc_o, |
t4_wb_stb_o, |
t4_wb_cab_o, |
t4_wb_adr_o, |
t4_wb_sel_o, |
t4_wb_we_o, |
1396,6 → 1482,7
|
t5_wb_cyc_o, |
t5_wb_stb_o, |
t5_wb_cab_o, |
t5_wb_adr_o, |
t5_wb_sel_o, |
t5_wb_we_o, |
1406,6 → 1493,7
|
t6_wb_cyc_o, |
t6_wb_stb_o, |
t6_wb_cab_o, |
t6_wb_adr_o, |
t6_wb_sel_o, |
t6_wb_we_o, |
1416,6 → 1504,7
|
t7_wb_cyc_o, |
t7_wb_stb_o, |
t7_wb_cab_o, |
t7_wb_adr_o, |
t7_wb_sel_o, |
t7_wb_we_o, |
1449,6 → 1538,7
// |
input i0_wb_cyc_i; |
input i0_wb_stb_i; |
input i0_wb_cab_i; |
input [`TC_AW-1:0] i0_wb_adr_i; |
input [`TC_BSW-1:0] i0_wb_sel_i; |
input i0_wb_we_i; |
1462,6 → 1552,7
// |
output t0_wb_cyc_o; |
output t0_wb_stb_o; |
output t0_wb_cab_o; |
output [`TC_AW-1:0] t0_wb_adr_o; |
output [`TC_BSW-1:0] t0_wb_sel_o; |
output t0_wb_we_o; |
1475,6 → 1566,7
// |
output t1_wb_cyc_o; |
output t1_wb_stb_o; |
output t1_wb_cab_o; |
output [`TC_AW-1:0] t1_wb_adr_o; |
output [`TC_BSW-1:0] t1_wb_sel_o; |
output t1_wb_we_o; |
1488,6 → 1580,7
// |
output t2_wb_cyc_o; |
output t2_wb_stb_o; |
output t2_wb_cab_o; |
output [`TC_AW-1:0] t2_wb_adr_o; |
output [`TC_BSW-1:0] t2_wb_sel_o; |
output t2_wb_we_o; |
1501,6 → 1594,7
// |
output t3_wb_cyc_o; |
output t3_wb_stb_o; |
output t3_wb_cab_o; |
output [`TC_AW-1:0] t3_wb_adr_o; |
output [`TC_BSW-1:0] t3_wb_sel_o; |
output t3_wb_we_o; |
1514,6 → 1608,7
// |
output t4_wb_cyc_o; |
output t4_wb_stb_o; |
output t4_wb_cab_o; |
output [`TC_AW-1:0] t4_wb_adr_o; |
output [`TC_BSW-1:0] t4_wb_sel_o; |
output t4_wb_we_o; |
1527,6 → 1622,7
// |
output t5_wb_cyc_o; |
output t5_wb_stb_o; |
output t5_wb_cab_o; |
output [`TC_AW-1:0] t5_wb_adr_o; |
output [`TC_BSW-1:0] t5_wb_sel_o; |
output t5_wb_we_o; |
1540,6 → 1636,7
// |
output t6_wb_cyc_o; |
output t6_wb_stb_o; |
output t6_wb_cab_o; |
output [`TC_AW-1:0] t6_wb_adr_o; |
output [`TC_BSW-1:0] t6_wb_sel_o; |
output t6_wb_we_o; |
1553,6 → 1650,7
// |
output t7_wb_cyc_o; |
output t7_wb_stb_o; |
output t7_wb_cab_o; |
output [`TC_AW-1:0] t7_wb_adr_o; |
output [`TC_BSW-1:0] t7_wb_sel_o; |
output t7_wb_we_o; |
1579,7 → 1677,7
// |
// Group WB initiator 0 i/f inputs and outputs |
// |
assign i0_in = {i0_wb_cyc_i, i0_wb_stb_i, i0_wb_adr_i, |
assign i0_in = {i0_wb_cyc_i, i0_wb_stb_i, i0_wb_cab_i, i0_wb_adr_i, |
i0_wb_sel_i, i0_wb_we_i, i0_wb_dat_i}; |
assign {i0_wb_dat_o, i0_wb_ack_o, i0_wb_err_o} = i0_out; |
|
1586,7 → 1684,7
// |
// Group WB target 0 i/f inputs and outputs |
// |
assign {t0_wb_cyc_o, t0_wb_stb_o, t0_wb_adr_o, |
assign {t0_wb_cyc_o, t0_wb_stb_o, t0_wb_cab_o, t0_wb_adr_o, |
t0_wb_sel_o, t0_wb_we_o, t0_wb_dat_o} = t0_out; |
assign t0_in = {t0_wb_dat_i, t0_wb_ack_i, t0_wb_err_i}; |
|
1593,7 → 1691,7
// |
// Group WB target 1 i/f inputs and outputs |
// |
assign {t1_wb_cyc_o, t1_wb_stb_o, t1_wb_adr_o, |
assign {t1_wb_cyc_o, t1_wb_stb_o, t1_wb_cab_o, t1_wb_adr_o, |
t1_wb_sel_o, t1_wb_we_o, t1_wb_dat_o} = t1_out; |
assign t1_in = {t1_wb_dat_i, t1_wb_ack_i, t1_wb_err_i}; |
|
1600,7 → 1698,7
// |
// Group WB target 2 i/f inputs and outputs |
// |
assign {t2_wb_cyc_o, t2_wb_stb_o, t2_wb_adr_o, |
assign {t2_wb_cyc_o, t2_wb_stb_o, t2_wb_cab_o, t2_wb_adr_o, |
t2_wb_sel_o, t2_wb_we_o, t2_wb_dat_o} = t2_out; |
assign t2_in = {t2_wb_dat_i, t2_wb_ack_i, t2_wb_err_i}; |
|
1607,7 → 1705,7
// |
// Group WB target 3 i/f inputs and outputs |
// |
assign {t3_wb_cyc_o, t3_wb_stb_o, t3_wb_adr_o, |
assign {t3_wb_cyc_o, t3_wb_stb_o, t3_wb_cab_o, t3_wb_adr_o, |
t3_wb_sel_o, t3_wb_we_o, t3_wb_dat_o} = t3_out; |
assign t3_in = {t3_wb_dat_i, t3_wb_ack_i, t3_wb_err_i}; |
|
1614,7 → 1712,7
// |
// Group WB target 4 i/f inputs and outputs |
// |
assign {t4_wb_cyc_o, t4_wb_stb_o, t4_wb_adr_o, |
assign {t4_wb_cyc_o, t4_wb_stb_o, t4_wb_cab_o, t4_wb_adr_o, |
t4_wb_sel_o, t4_wb_we_o, t4_wb_dat_o} = t4_out; |
assign t4_in = {t4_wb_dat_i, t4_wb_ack_i, t4_wb_err_i}; |
|
1621,7 → 1719,7
// |
// Group WB target 5 i/f inputs and outputs |
// |
assign {t5_wb_cyc_o, t5_wb_stb_o, t5_wb_adr_o, |
assign {t5_wb_cyc_o, t5_wb_stb_o, t5_wb_cab_o, t5_wb_adr_o, |
t5_wb_sel_o, t5_wb_we_o, t5_wb_dat_o} = t5_out; |
assign t5_in = {t5_wb_dat_i, t5_wb_ack_i, t5_wb_err_i}; |
|
1628,7 → 1726,7
// |
// Group WB target 6 i/f inputs and outputs |
// |
assign {t6_wb_cyc_o, t6_wb_stb_o, t6_wb_adr_o, |
assign {t6_wb_cyc_o, t6_wb_stb_o, t6_wb_cab_o, t6_wb_adr_o, |
t6_wb_sel_o, t6_wb_we_o, t6_wb_dat_o} = t6_out; |
assign t6_in = {t6_wb_dat_i, t6_wb_ack_i, t6_wb_err_i}; |
|
1635,7 → 1733,7
// |
// Group WB target 7 i/f inputs and outputs |
// |
assign {t7_wb_cyc_o, t7_wb_stb_o, t7_wb_adr_o, |
assign {t7_wb_cyc_o, t7_wb_stb_o, t7_wb_cab_o, t7_wb_adr_o, |
t7_wb_sel_o, t7_wb_we_o, t7_wb_dat_o} = t7_out; |
assign t7_in = {t7_wb_dat_i, t7_wb_ack_i, t7_wb_err_i}; |
|
/minsoc_defines.v
1,4 → 1,64
////////////////////////////////////////////////////////////////////// |
//// //// |
//// OR1K test app definitions //// |
//// //// |
//// This file is part of the OR1K test application //// |
//// http://www.opencores.org/cores/or1k/xess/ //// |
//// //// |
//// Description //// |
//// DEfine target technology etc. Right now FIFOs are available //// |
//// only for Xilinx Virtex FPGAs. (TARGET_VIRTEX) //// |
//// //// |
//// To Do: //// |
//// - nothing really //// |
//// //// |
//// Author(s): //// |
//// - Damjan Lampret, damjan.lampret@opencores.org //// |
//// //// |
////////////////////////////////////////////////////////////////////// |
//// //// |
//// Copyright (C) 2001 Authors //// |
//// //// |
//// This source file may be used and distributed without //// |
//// restriction provided that this copyright statement is not //// |
//// removed from the file and that any derivative work contains //// |
//// the original copyright notice and the associated disclaimer. //// |
//// //// |
//// This source file is free software; you can redistribute it //// |
//// and/or modify it under the terms of the GNU Lesser General //// |
//// Public License as published by the Free Software Foundation; //// |
//// either version 2.1 of the License, or (at your option) any //// |
//// later version. //// |
//// //// |
//// This source is distributed in the hope that it will be //// |
//// useful, but WITHOUT ANY WARRANTY; without even the implied //// |
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR //// |
//// PURPOSE. See the GNU Lesser General Public License for more //// |
//// details. //// |
//// //// |
//// You should have received a copy of the GNU Lesser General //// |
//// Public License along with this source; if not, download it //// |
//// from http://www.opencores.org/lgpl.shtml //// |
//// //// |
////////////////////////////////////////////////////////////////////// |
// |
// CVS Revision History |
// |
// $Log: xsv_fpga_defines.v,v $ |
// Revision 1.4 2004/04/05 08:44:35 lampret |
// Merged branch_qmem into main tree. |
// |
// Revision 1.2 2002/03/29 20:58:51 lampret |
// Changed hardcoded address for fake MC to use a define. |
// |
// Revision 1.1.1.1 2002/03/21 16:55:44 lampret |
// First import of the "new" XESS XSV environment. |
// |
// |
// |
|
|
// |
// Define FPGA manufacturer |
// |
//`define GENERIC_FPGA |
26,7 → 86,7
//the memory data width is 32 bit, memory amount in Bytes = 4*memory depth |
|
// |
// Memory type (uncomment something if ASIC or generic memory) |
// Memory type (uncomment something if ASIC or if you want generic memory) |
// |
//`define GENERIC_MEMORY |
//`define AVANT_ATP |
56,12 → 116,6
//DO NOT USE CLOCK_DIVISOR = 1 COMMENT THE CLOCK DIVISION SELECTION INSTEAD |
|
// |
// Reset polarity |
// |
//`define NEGATIVE_RESET; //rstn |
`define POSITIVE_RESET; //rst |
|
// |
// Start-up circuit (only necessary later to load firmware automatically from SPI memory) |
// |
//`define START_UP |
/minsoc_onchip_ram_top.v
46,12 → 46,7
// |
// Revision History |
// |
// Revision 1.1 2009/10/02 16:49 fajardo |
// Not using the oe signal (output enable) from |
// memories, instead multiplexing the outputs |
// between the different instantiated blocks |
// |
// |
// Revision 1.0 2009/08/18 15:15:00 fajardo |
// Created interface and tested |
// |
67,9 → 62,9
// |
// Parameters |
// |
parameter aw_int = 11; //11 = 2048 |
parameter adr_width = 13; //Memory address width, is composed by blocks of aw_int, is not allowed to be less than 12 |
localparam aw_int = 11; //11 = 2048 |
localparam blocks = (1<<(adr_width-aw_int)); //generated memory contains "blocks" memory blocks of 2048x32 2048 depth x32 bit data |
parameter blocks = (1<<(adr_width-aw_int)); //generated memory contains "blocks" memory blocks of 2048x32 2048 depth x32 bit data |
|
// |
// I/O Ports |
134,53 → 129,6
ack_re <= #1 1'b0; |
end |
|
//Generic (multiple inputs x 1 output) MUX |
localparam mux_in_nr = blocks; |
localparam slices = adr_width-aw_int; |
localparam mux_out_nr = blocks-1; |
|
wire [31:0] int_dat_o[0:mux_in_nr-1]; |
wire [31:0] mux_out[0:mux_out_nr-1]; |
|
generate |
genvar j, k; |
for (j=0; j<slices; j=j+1) begin : SLICES |
for (k=0; k<(mux_in_nr>>(j+1)); k=k+1) begin : MUX |
if (j==0) begin |
mux2 # |
( |
.dw(32) |
) |
mux_int( |
.sel( wb_adr_i[aw_int+2+j] ), |
.in1( int_dat_o[k*2] ), |
.in2( int_dat_o[k*2+1] ), |
.out( mux_out[k] ) |
); |
end |
else begin |
mux2 # |
( |
.dw(32) |
) |
mux_int( |
.sel( wb_adr_i[aw_int+2+j] ), |
.in1( mux_out[(mux_in_nr-(mux_in_nr>>(j-1)))+k*2] ), |
.in2( mux_out[(mux_in_nr-(mux_in_nr>>(j-1)))+k*2+1] ), |
.out( mux_out[(mux_in_nr-(mux_in_nr>>j))+k] ) |
); |
end |
end |
end |
endgenerate |
|
//last output = total output |
assign wb_dat_o = mux_out[mux_out_nr-1]; |
|
//(mux_in_nr-(mux_in_nr>>j)): |
//-Given sum of 2^i | i = x -> y series can be resumed to 2^(y+1)-2^x |
//so, with this expression I'm evaluating how many times the internal loop has been run |
|
wire [blocks-1:0] bank; |
|
generate |
195,11 → 143,10
.rst(wb_rst_i), |
.addr(wb_adr_i[aw_int+1:2]), |
.di(wb_dat_i[7:0]), |
.doq(int_dat_o[i][7:0]), |
.doq(wb_dat_o[7:0]), |
.we(we & bank[i]), |
.oe(1'b1), |
.ce(be_i[0]) |
); |
.oe(bank[i]), |
.ce(be_i[0])); |
|
|
minsoc_onchip_ram block_ram_1 ( |
207,11 → 154,10
.rst(wb_rst_i), |
.addr(wb_adr_i[aw_int+1:2]), |
.di(wb_dat_i[15:8]), |
.doq(int_dat_o[i][15:8]), |
.doq(wb_dat_o[15:8]), |
.we(we & bank[i]), |
.oe(1'b1), |
.ce(be_i[1]) |
); |
.oe(bank[i]), |
.ce(be_i[1])); |
|
minsoc_onchip_ram block_ram_2 ( |
.clk(wb_clk_i), |
218,11 → 164,10
.rst(wb_rst_i), |
.addr(wb_adr_i[aw_int+1:2]), |
.di(wb_dat_i[23:16]), |
.doq(int_dat_o[i][23:16]), |
.doq(wb_dat_o[23:16]), |
.we(we & bank[i]), |
.oe(1'b1), |
.ce(be_i[2]) |
); |
.oe(bank[i]), |
.ce(be_i[2])); |
|
minsoc_onchip_ram block_ram_3 ( |
.clk(wb_clk_i), |
229,11 → 174,10
.rst(wb_rst_i), |
.addr(wb_adr_i[aw_int+1:2]), |
.di(wb_dat_i[31:24]), |
.doq(int_dat_o[i][31:24]), |
.doq(wb_dat_o[31:24]), |
.we(we & bank[i]), |
.oe(1'b1), |
.ce(be_i[3]) |
); |
.oe(bank[i]), |
.ce(be_i[3])); |
|
end |
endgenerate |
240,20 → 184,3
|
endmodule |
|
module mux2(sel,in1,in2,out); |
|
parameter dw = 32; |
|
input sel; |
input [dw-1:0] in1, in2; |
output reg [dw-1:0] out; |
|
always @ (sel or in1 or in2) |
begin |
case (sel) |
1'b0: out = in1; |
1'b1: out = in2; |
endcase |
end |
|
endmodule |
/minsoc_top.v
1,3 → 1,75
////////////////////////////////////////////////////////////////////// |
//// //// |
//// OR1K test application for XESS XSV board, Top Level //// |
//// //// |
//// This file is part of the OR1K test application //// |
//// http://www.opencores.org/cores/or1k/ //// |
//// //// |
//// Description //// |
//// Top level instantiating all the blocks. //// |
//// //// |
//// To Do: //// |
//// - nothing really //// |
//// //// |
//// Author(s): //// |
//// - Damjan Lampret, lampret@opencores.org //// |
//// //// |
////////////////////////////////////////////////////////////////////// |
//// //// |
//// Copyright (C) 2001 Authors //// |
//// //// |
//// This source file may be used and distributed without //// |
//// restriction provided that this copyright statement is not //// |
//// removed from the file and that any derivative work contains //// |
//// the original copyright notice and the associated disclaimer. //// |
//// //// |
//// This source file is free software; you can redistribute it //// |
//// and/or modify it under the terms of the GNU Lesser General //// |
//// Public License as published by the Free Software Foundation; //// |
//// either version 2.1 of the License, or (at your option) any //// |
//// later version. //// |
//// //// |
//// This source is distributed in the hope that it will be //// |
//// useful, but WITHOUT ANY WARRANTY; without even the implied //// |
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR //// |
//// PURPOSE. See the GNU Lesser General Public License for more //// |
//// details. //// |
//// //// |
//// You should have received a copy of the GNU Lesser General //// |
//// Public License along with this source; if not, download it //// |
//// from http://www.opencores.org/lgpl.shtml //// |
//// //// |
////////////////////////////////////////////////////////////////////// |
// |
// CVS Revision History |
// |
// $Log: xsv_fpga_top.v,v $ |
// Revision 1.10 2004/04/05 08:44:35 lampret |
// Merged branch_qmem into main tree. |
// |
// Revision 1.8 2003/04/07 21:05:58 lampret |
// WB = 1/2 RISC clock test code enabled. |
// |
// Revision 1.7 2003/04/07 01:28:17 lampret |
// Adding OR1200_CLMODE_1TO2 test code. |
// |
// Revision 1.6 2002/08/12 05:35:12 lampret |
// rty_i are unused - tied to zero. |
// |
// Revision 1.5 2002/03/29 20:58:51 lampret |
// Changed hardcoded address for fake MC to use a define. |
// |
// Revision 1.4 2002/03/29 16:30:47 lampret |
// Fixed port names that changed. |
// |
// Revision 1.3 2002/03/29 15:50:03 lampret |
// Added response from memory controller (addr 0x60000000) |
// |
// Revision 1.2 2002/03/21 17:39:16 lampret |
// Fixed some typos |
// |
// |
|
`include "minsoc_defines.v" |
`include "or1200_defines.v" |
|
92,11 → 164,7
|
wire rstn; |
|
`ifdef POSITIVE_RESET |
assign rstn = ~reset; |
`elsif NEGATIVE_RESET |
assign rstn = reset; |
`endif |
|
// |
// Internal wires |
112,6 → 180,7
wire wb_dm_we_o; |
wire wb_dm_stb_o; |
wire wb_dm_cyc_o; |
wire wb_dm_cab_o; |
wire wb_dm_ack_i; |
wire wb_dm_err_i; |
|
143,6 → 212,7
wire wb_rim_rty_i = 1'b0; |
wire wb_rim_we_o; |
wire wb_rim_stb_o; |
wire wb_rim_cab_o; |
wire [31:0] wb_rif_dat_i; |
wire wb_rif_ack_i; |
|
159,6 → 229,7
wire wb_rdm_rty_i = 1'b0; |
wire wb_rdm_we_o; |
wire wb_rdm_stb_o; |
wire wb_rdm_cab_o; |
|
// |
// RISC misc |
222,6 → 293,7
wire wb_em_we_o; |
wire wb_em_stb_o; |
wire wb_em_cyc_o; |
wire wb_em_cab_o; |
wire wb_em_ack_i; |
wire wb_em_err_i; |
|
272,7 → 344,11
// |
// Global clock |
// |
`ifdef OR1200_CLMODE_1TO2 |
reg wb_clk; |
`else |
wire wb_clk; |
`endif |
|
// |
// Reset debounce |
290,8 → 366,15
wb_rst <= #1 rst_r; |
|
// |
// Clock Divider |
// This is purely for testing 1/2 WB clock |
// This should never be used when implementing in |
// an FPGA. It is used only for simulation regressions. |
// |
`ifdef OR1200_CLMODE_1TO2 |
initial wb_clk = 0; |
always @(posedge clk) |
wb_clk = ~wb_clk; |
`else |
minsoc_clock_manager # |
( |
.divisor(`CLOCK_DIVISOR) |
300,11 → 383,13
.clk_i(clk), |
.clk_o(wb_clk) |
); |
`endif // OR1200_CLMODE_1TO2 |
|
// |
// Unused WISHBONE signals |
// |
assign wb_us_err_o = 1'b0; |
assign wb_em_cab_o = 1'b0; |
assign wb_fs_err_o = 1'b0; |
assign wb_sp_err_o = 1'b0; |
|
425,6 → 510,7
.wb_we_o ( wb_dm_we_o ), |
.wb_stb_o ( wb_dm_stb_o ), |
.wb_cyc_o ( wb_dm_cyc_o ), |
.wb_cab_o ( wb_dm_cab_o ), |
.wb_ack_i ( wb_dm_ack_i ), |
.wb_err_i ( wb_dm_err_i ), |
.wb_cti_o ( ), |
543,6 → 629,7
.iwb_rty_i ( wb_rim_rty_i ), |
.iwb_we_o ( wb_rim_we_o ), |
.iwb_stb_o ( wb_rim_stb_o ), |
.iwb_cab_o ( wb_rim_cab_o ), |
|
// WISHBONE Data Master |
.dwb_clk_i ( wb_clk ), |
557,6 → 644,7
.dwb_rty_i ( wb_rdm_rty_i ), |
.dwb_we_o ( wb_rdm_we_o ), |
.dwb_stb_o ( wb_rdm_stb_o ), |
.dwb_cab_o ( wb_rdm_cab_o ), |
|
// Debug |
.dbg_stall_i ( dbg_stall ), |
792,6 → 880,7
// WISHBONE Initiator 0 |
.i0_wb_cyc_i ( 1'b0 ), |
.i0_wb_stb_i ( 1'b0 ), |
.i0_wb_cab_i ( 1'b0 ), |
.i0_wb_adr_i ( 32'h0000_0000 ), |
.i0_wb_sel_i ( 4'b0000 ), |
.i0_wb_we_i ( 1'b0 ), |
803,6 → 892,7
// WISHBONE Initiator 1 |
.i1_wb_cyc_i ( wb_em_cyc_o ), |
.i1_wb_stb_i ( wb_em_stb_o ), |
.i1_wb_cab_i ( wb_em_cab_o ), |
.i1_wb_adr_i ( wb_em_adr_o ), |
.i1_wb_sel_i ( wb_em_sel_o ), |
.i1_wb_we_i ( wb_em_we_o ), |
814,6 → 904,7
// WISHBONE Initiator 2 |
.i2_wb_cyc_i ( 1'b0 ), |
.i2_wb_stb_i ( 1'b0 ), |
.i2_wb_cab_i ( 1'b0 ), |
.i2_wb_adr_i ( 32'h0000_0000 ), |
.i2_wb_sel_i ( 4'b0000 ), |
.i2_wb_we_i ( 1'b0 ), |
825,6 → 916,7
// WISHBONE Initiator 3 |
.i3_wb_cyc_i ( wb_dm_cyc_o ), |
.i3_wb_stb_i ( wb_dm_stb_o ), |
.i3_wb_cab_i ( wb_dm_cab_o ), |
.i3_wb_adr_i ( wb_dm_adr_o ), |
.i3_wb_sel_i ( wb_dm_sel_o ), |
.i3_wb_we_i ( wb_dm_we_o ), |
836,6 → 928,7
// WISHBONE Initiator 4 |
.i4_wb_cyc_i ( wb_rdm_cyc_o ), |
.i4_wb_stb_i ( wb_rdm_stb_o ), |
.i4_wb_cab_i ( wb_rdm_cab_o ), |
.i4_wb_adr_i ( wb_rdm_adr_o ), |
.i4_wb_sel_i ( wb_rdm_sel_o ), |
.i4_wb_we_i ( wb_rdm_we_o ), |
847,6 → 940,7
// WISHBONE Initiator 5 |
.i5_wb_cyc_i ( wb_rim_cyc_o ), |
.i5_wb_stb_i ( wb_rim_stb_o ), |
.i5_wb_cab_i ( wb_rim_cab_o ), |
.i5_wb_adr_i ( wb_rim_adr_o ), |
.i5_wb_sel_i ( wb_rim_sel_o ), |
.i5_wb_we_i ( wb_rim_we_o ), |
858,6 → 952,7
// WISHBONE Initiator 6 |
.i6_wb_cyc_i ( 1'b0 ), |
.i6_wb_stb_i ( 1'b0 ), |
.i6_wb_cab_i ( 1'b0 ), |
.i6_wb_adr_i ( 32'h0000_0000 ), |
.i6_wb_sel_i ( 4'b0000 ), |
.i6_wb_we_i ( 1'b0 ), |
869,6 → 964,7
// WISHBONE Initiator 7 |
.i7_wb_cyc_i ( 1'b0 ), |
.i7_wb_stb_i ( 1'b0 ), |
.i7_wb_cab_i ( 1'b0 ), |
.i7_wb_adr_i ( 32'h0000_0000 ), |
.i7_wb_sel_i ( 4'b0000 ), |
.i7_wb_we_i ( 1'b0 ), |
880,6 → 976,7
// WISHBONE Target 0 |
.t0_wb_cyc_o ( wb_ss_cyc_i ), |
.t0_wb_stb_o ( wb_ss_stb_i ), |
.t0_wb_cab_o ( wb_ss_cab_i ), |
.t0_wb_adr_o ( wb_ss_adr_i ), |
.t0_wb_sel_o ( wb_ss_sel_i ), |
.t0_wb_we_o ( wb_ss_we_i ), |
891,6 → 988,7
// WISHBONE Target 1 |
.t1_wb_cyc_o ( wb_fs_cyc_i ), |
.t1_wb_stb_o ( wb_fs_stb_i ), |
.t1_wb_cab_o ( wb_fs_cab_i ), |
.t1_wb_adr_o ( wb_fs_adr_i ), |
.t1_wb_sel_o ( wb_fs_sel_i ), |
.t1_wb_we_o ( wb_fs_we_i ), |
902,6 → 1000,7
// WISHBONE Target 2 |
.t2_wb_cyc_o ( wb_sp_cyc_i ), |
.t2_wb_stb_o ( wb_sp_stb_i ), |
.t2_wb_cab_o ( wb_sp_cab_i ), |
.t2_wb_adr_o ( wb_sp_adr_i ), |
.t2_wb_sel_o ( wb_sp_sel_i ), |
.t2_wb_we_o ( wb_sp_we_i ), |
913,6 → 1012,7
// WISHBONE Target 3 |
.t3_wb_cyc_o ( wb_es_cyc_i ), |
.t3_wb_stb_o ( wb_es_stb_i ), |
.t3_wb_cab_o ( wb_es_cab_i ), |
.t3_wb_adr_o ( wb_es_adr_i ), |
.t3_wb_sel_o ( wb_es_sel_i ), |
.t3_wb_we_o ( wb_es_we_i ), |
924,6 → 1024,7
// WISHBONE Target 4 |
.t4_wb_cyc_o ( ), |
.t4_wb_stb_o ( ), |
.t4_wb_cab_o ( ), |
.t4_wb_adr_o ( ), |
.t4_wb_sel_o ( ), |
.t4_wb_we_o ( ), |
935,6 → 1036,7
// WISHBONE Target 5 |
.t5_wb_cyc_o ( wb_us_cyc_i ), |
.t5_wb_stb_o ( wb_us_stb_i ), |
.t5_wb_cab_o ( wb_us_cab_i ), |
.t5_wb_adr_o ( wb_us_adr_i ), |
.t5_wb_sel_o ( wb_us_sel_i ), |
.t5_wb_we_o ( wb_us_we_i ), |
946,6 → 1048,7
// WISHBONE Target 6 |
.t6_wb_cyc_o ( ), |
.t6_wb_stb_o ( ), |
.t6_wb_cab_o ( ), |
.t6_wb_adr_o ( ), |
.t6_wb_sel_o ( ), |
.t6_wb_we_o ( ), |
957,6 → 1060,7
// WISHBONE Target 7 |
.t7_wb_cyc_o ( ), |
.t7_wb_stb_o ( ), |
.t7_wb_cab_o ( ), |
.t7_wb_adr_o ( ), |
.t7_wb_sel_o ( ), |
.t7_wb_we_o ( ), |
968,6 → 1072,7
// WISHBONE Target 8 |
.t8_wb_cyc_o ( ), |
.t8_wb_stb_o ( ), |
.t8_wb_cab_o ( ), |
.t8_wb_adr_o ( ), |
.t8_wb_sel_o ( ), |
.t8_wb_we_o ( ), |