OpenCores
URL https://opencores.org/ocsvn/minsoc/minsoc/trunk

Subversion Repositories minsoc

Compare Revisions

  • This comparison shows the changes necessary to convert path 
    /minsoc/trunk/rtl
    from Rev 6 to Rev 7
    ↔ Reverse comparison
  •

Rev 6 → Rev 7

/verilog/minsoc_tc_top.v
86,7 → 86,7
//
// Width of WB initiator inputs (coming from WB masters)
//
// cyc + stb + cab + address bus width +
// cyc + stb + address bus width +
// byte select bus width + we + data bus width
//
`define TC_IIN_W 1+1+1+`TC_AW+`TC_BSW+1+`TC_DW
100,7 → 100,6
 
i0_wb_cyc_i,
i0_wb_stb_i,
i0_wb_cab_i,
i0_wb_adr_i,
i0_wb_sel_i,
i0_wb_we_i,
111,7 → 110,6
 
i1_wb_cyc_i,
i1_wb_stb_i,
i1_wb_cab_i,
i1_wb_adr_i,
i1_wb_sel_i,
i1_wb_we_i,
122,7 → 120,6
 
i2_wb_cyc_i,
i2_wb_stb_i,
i2_wb_cab_i,
i2_wb_adr_i,
i2_wb_sel_i,
i2_wb_we_i,
133,7 → 130,6
 
i3_wb_cyc_i,
i3_wb_stb_i,
i3_wb_cab_i,
i3_wb_adr_i,
i3_wb_sel_i,
i3_wb_we_i,
144,7 → 140,6
 
i4_wb_cyc_i,
i4_wb_stb_i,
i4_wb_cab_i,
i4_wb_adr_i,
i4_wb_sel_i,
i4_wb_we_i,
155,7 → 150,6
 
i5_wb_cyc_i,
i5_wb_stb_i,
i5_wb_cab_i,
i5_wb_adr_i,
i5_wb_sel_i,
i5_wb_we_i,
166,7 → 160,6
 
i6_wb_cyc_i,
i6_wb_stb_i,
i6_wb_cab_i,
i6_wb_adr_i,
i6_wb_sel_i,
i6_wb_we_i,
177,7 → 170,6
 
i7_wb_cyc_i,
i7_wb_stb_i,
i7_wb_cab_i,
i7_wb_adr_i,
i7_wb_sel_i,
i7_wb_we_i,
188,7 → 180,6
 
t0_wb_cyc_o,
t0_wb_stb_o,
t0_wb_cab_o,
t0_wb_adr_o,
t0_wb_sel_o,
t0_wb_we_o,
199,7 → 190,6
 
t1_wb_cyc_o,
t1_wb_stb_o,
t1_wb_cab_o,
t1_wb_adr_o,
t1_wb_sel_o,
t1_wb_we_o,
210,7 → 200,6
 
t2_wb_cyc_o,
t2_wb_stb_o,
t2_wb_cab_o,
t2_wb_adr_o,
t2_wb_sel_o,
t2_wb_we_o,
221,7 → 210,6
 
t3_wb_cyc_o,
t3_wb_stb_o,
t3_wb_cab_o,
t3_wb_adr_o,
t3_wb_sel_o,
t3_wb_we_o,
232,7 → 220,6
 
t4_wb_cyc_o,
t4_wb_stb_o,
t4_wb_cab_o,
t4_wb_adr_o,
t4_wb_sel_o,
t4_wb_we_o,
243,7 → 230,6
 
t5_wb_cyc_o,
t5_wb_stb_o,
t5_wb_cab_o,
t5_wb_adr_o,
t5_wb_sel_o,
t5_wb_we_o,
254,7 → 240,6
 
t6_wb_cyc_o,
t6_wb_stb_o,
t6_wb_cab_o,
t6_wb_adr_o,
t6_wb_sel_o,
t6_wb_we_o,
265,7 → 250,6
 
t7_wb_cyc_o,
t7_wb_stb_o,
t7_wb_cab_o,
t7_wb_adr_o,
t7_wb_sel_o,
t7_wb_we_o,
276,7 → 260,6
 
t8_wb_cyc_o,
t8_wb_stb_o,
t8_wb_cab_o,
t8_wb_adr_o,
t8_wb_sel_o,
t8_wb_we_o,
316,7 → 299,6
//
input i0_wb_cyc_i;
input i0_wb_stb_i;
input i0_wb_cab_i;
input [`TC_AW-1:0] i0_wb_adr_i;
input [`TC_BSW-1:0] i0_wb_sel_i;
input i0_wb_we_i;
330,7 → 312,6
//
input i1_wb_cyc_i;
input i1_wb_stb_i;
input i1_wb_cab_i;
input [`TC_AW-1:0] i1_wb_adr_i;
input [`TC_BSW-1:0] i1_wb_sel_i;
input i1_wb_we_i;
344,7 → 325,6
//
input i2_wb_cyc_i;
input i2_wb_stb_i;
input i2_wb_cab_i;
input [`TC_AW-1:0] i2_wb_adr_i;
input [`TC_BSW-1:0] i2_wb_sel_i;
input i2_wb_we_i;
358,7 → 338,6
//
input i3_wb_cyc_i;
input i3_wb_stb_i;
input i3_wb_cab_i;
input [`TC_AW-1:0] i3_wb_adr_i;
input [`TC_BSW-1:0] i3_wb_sel_i;
input i3_wb_we_i;
372,7 → 351,6
//
input i4_wb_cyc_i;
input i4_wb_stb_i;
input i4_wb_cab_i;
input [`TC_AW-1:0] i4_wb_adr_i;
input [`TC_BSW-1:0] i4_wb_sel_i;
input i4_wb_we_i;
386,7 → 364,6
//
input i5_wb_cyc_i;
input i5_wb_stb_i;
input i5_wb_cab_i;
input [`TC_AW-1:0] i5_wb_adr_i;
input [`TC_BSW-1:0] i5_wb_sel_i;
input i5_wb_we_i;
400,7 → 377,6
//
input i6_wb_cyc_i;
input i6_wb_stb_i;
input i6_wb_cab_i;
input [`TC_AW-1:0] i6_wb_adr_i;
input [`TC_BSW-1:0] i6_wb_sel_i;
input i6_wb_we_i;
414,7 → 390,6
//
input i7_wb_cyc_i;
input i7_wb_stb_i;
input i7_wb_cab_i;
input [`TC_AW-1:0] i7_wb_adr_i;
input [`TC_BSW-1:0] i7_wb_sel_i;
input i7_wb_we_i;
428,7 → 403,6
//
output t0_wb_cyc_o;
output t0_wb_stb_o;
output t0_wb_cab_o;
output [`TC_AW-1:0] t0_wb_adr_o;
output [`TC_BSW-1:0] t0_wb_sel_o;
output t0_wb_we_o;
442,7 → 416,6
//
output t1_wb_cyc_o;
output t1_wb_stb_o;
output t1_wb_cab_o;
output [`TC_AW-1:0] t1_wb_adr_o;
output [`TC_BSW-1:0] t1_wb_sel_o;
output t1_wb_we_o;
456,7 → 429,6
//
output t2_wb_cyc_o;
output t2_wb_stb_o;
output t2_wb_cab_o;
output [`TC_AW-1:0] t2_wb_adr_o;
output [`TC_BSW-1:0] t2_wb_sel_o;
output t2_wb_we_o;
470,7 → 442,6
//
output t3_wb_cyc_o;
output t3_wb_stb_o;
output t3_wb_cab_o;
output [`TC_AW-1:0] t3_wb_adr_o;
output [`TC_BSW-1:0] t3_wb_sel_o;
output t3_wb_we_o;
484,7 → 455,6
//
output t4_wb_cyc_o;
output t4_wb_stb_o;
output t4_wb_cab_o;
output [`TC_AW-1:0] t4_wb_adr_o;
output [`TC_BSW-1:0] t4_wb_sel_o;
output t4_wb_we_o;
498,7 → 468,6
//
output t5_wb_cyc_o;
output t5_wb_stb_o;
output t5_wb_cab_o;
output [`TC_AW-1:0] t5_wb_adr_o;
output [`TC_BSW-1:0] t5_wb_sel_o;
output t5_wb_we_o;
512,7 → 481,6
//
output t6_wb_cyc_o;
output t6_wb_stb_o;
output t6_wb_cab_o;
output [`TC_AW-1:0] t6_wb_adr_o;
output [`TC_BSW-1:0] t6_wb_sel_o;
output t6_wb_we_o;
526,7 → 494,6
//
output t7_wb_cyc_o;
output t7_wb_stb_o;
output t7_wb_cab_o;
output [`TC_AW-1:0] t7_wb_adr_o;
output [`TC_BSW-1:0] t7_wb_sel_o;
output t7_wb_we_o;
540,7 → 507,6
//
output t8_wb_cyc_o;
output t8_wb_stb_o;
output t8_wb_cab_o;
output [`TC_AW-1:0] t8_wb_adr_o;
output [`TC_BSW-1:0] t8_wb_sel_o;
output t8_wb_we_o;
611,7 → 577,6
//
wire z_wb_cyc_i;
wire z_wb_stb_i;
wire z_wb_cab_i;
wire [`TC_AW-1:0] z_wb_adr_i;
wire [`TC_BSW-1:0] z_wb_sel_i;
wire z_wb_we_i;
658,7 → 623,6
 
.i0_wb_cyc_i(i0_wb_cyc_i),
.i0_wb_stb_i(i0_wb_stb_i),
.i0_wb_cab_i(i0_wb_cab_i),
.i0_wb_adr_i(i0_wb_adr_i),
.i0_wb_sel_i(i0_wb_sel_i),
.i0_wb_we_i(i0_wb_we_i),
669,7 → 633,6
 
.i1_wb_cyc_i(i1_wb_cyc_i),
.i1_wb_stb_i(i1_wb_stb_i),
.i1_wb_cab_i(i1_wb_cab_i),
.i1_wb_adr_i(i1_wb_adr_i),
.i1_wb_sel_i(i1_wb_sel_i),
.i1_wb_we_i(i1_wb_we_i),
680,7 → 643,6
 
.i2_wb_cyc_i(i2_wb_cyc_i),
.i2_wb_stb_i(i2_wb_stb_i),
.i2_wb_cab_i(i2_wb_cab_i),
.i2_wb_adr_i(i2_wb_adr_i),
.i2_wb_sel_i(i2_wb_sel_i),
.i2_wb_we_i(i2_wb_we_i),
691,7 → 653,6
 
.i3_wb_cyc_i(i3_wb_cyc_i),
.i3_wb_stb_i(i3_wb_stb_i),
.i3_wb_cab_i(i3_wb_cab_i),
.i3_wb_adr_i(i3_wb_adr_i),
.i3_wb_sel_i(i3_wb_sel_i),
.i3_wb_we_i(i3_wb_we_i),
702,7 → 663,6
 
.i4_wb_cyc_i(i4_wb_cyc_i),
.i4_wb_stb_i(i4_wb_stb_i),
.i4_wb_cab_i(i4_wb_cab_i),
.i4_wb_adr_i(i4_wb_adr_i),
.i4_wb_sel_i(i4_wb_sel_i),
.i4_wb_we_i(i4_wb_we_i),
713,7 → 673,6
 
.i5_wb_cyc_i(i5_wb_cyc_i),
.i5_wb_stb_i(i5_wb_stb_i),
.i5_wb_cab_i(i5_wb_cab_i),
.i5_wb_adr_i(i5_wb_adr_i),
.i5_wb_sel_i(i5_wb_sel_i),
.i5_wb_we_i(i5_wb_we_i),
724,7 → 683,6
 
.i6_wb_cyc_i(i6_wb_cyc_i),
.i6_wb_stb_i(i6_wb_stb_i),
.i6_wb_cab_i(i6_wb_cab_i),
.i6_wb_adr_i(i6_wb_adr_i),
.i6_wb_sel_i(i6_wb_sel_i),
.i6_wb_we_i(i6_wb_we_i),
735,7 → 693,6
 
.i7_wb_cyc_i(i7_wb_cyc_i),
.i7_wb_stb_i(i7_wb_stb_i),
.i7_wb_cab_i(i7_wb_cab_i),
.i7_wb_adr_i(i7_wb_adr_i),
.i7_wb_sel_i(i7_wb_sel_i),
.i7_wb_we_i(i7_wb_we_i),
746,7 → 703,6
 
.t0_wb_cyc_o(t0_wb_cyc_o),
.t0_wb_stb_o(t0_wb_stb_o),
.t0_wb_cab_o(t0_wb_cab_o),
.t0_wb_adr_o(t0_wb_adr_o),
.t0_wb_sel_o(t0_wb_sel_o),
.t0_wb_we_o(t0_wb_we_o),
767,7 → 723,6
 
.i0_wb_cyc_i(i0_wb_cyc_i),
.i0_wb_stb_i(i0_wb_stb_i),
.i0_wb_cab_i(i0_wb_cab_i),
.i0_wb_adr_i(i0_wb_adr_i),
.i0_wb_sel_i(i0_wb_sel_i),
.i0_wb_we_i(i0_wb_we_i),
778,7 → 733,6
 
.i1_wb_cyc_i(i1_wb_cyc_i),
.i1_wb_stb_i(i1_wb_stb_i),
.i1_wb_cab_i(i1_wb_cab_i),
.i1_wb_adr_i(i1_wb_adr_i),
.i1_wb_sel_i(i1_wb_sel_i),
.i1_wb_we_i(i1_wb_we_i),
789,7 → 743,6
 
.i2_wb_cyc_i(i2_wb_cyc_i),
.i2_wb_stb_i(i2_wb_stb_i),
.i2_wb_cab_i(i2_wb_cab_i),
.i2_wb_adr_i(i2_wb_adr_i),
.i2_wb_sel_i(i2_wb_sel_i),
.i2_wb_we_i(i2_wb_we_i),
800,7 → 753,6
 
.i3_wb_cyc_i(i3_wb_cyc_i),
.i3_wb_stb_i(i3_wb_stb_i),
.i3_wb_cab_i(i3_wb_cab_i),
.i3_wb_adr_i(i3_wb_adr_i),
.i3_wb_sel_i(i3_wb_sel_i),
.i3_wb_we_i(i3_wb_we_i),
811,7 → 763,6
 
.i4_wb_cyc_i(i4_wb_cyc_i),
.i4_wb_stb_i(i4_wb_stb_i),
.i4_wb_cab_i(i4_wb_cab_i),
.i4_wb_adr_i(i4_wb_adr_i),
.i4_wb_sel_i(i4_wb_sel_i),
.i4_wb_we_i(i4_wb_we_i),
822,7 → 773,6
 
.i5_wb_cyc_i(i5_wb_cyc_i),
.i5_wb_stb_i(i5_wb_stb_i),
.i5_wb_cab_i(i5_wb_cab_i),
.i5_wb_adr_i(i5_wb_adr_i),
.i5_wb_sel_i(i5_wb_sel_i),
.i5_wb_we_i(i5_wb_we_i),
833,7 → 783,6
 
.i6_wb_cyc_i(i6_wb_cyc_i),
.i6_wb_stb_i(i6_wb_stb_i),
.i6_wb_cab_i(i6_wb_cab_i),
.i6_wb_adr_i(i6_wb_adr_i),
.i6_wb_sel_i(i6_wb_sel_i),
.i6_wb_we_i(i6_wb_we_i),
844,7 → 793,6
 
.i7_wb_cyc_i(i7_wb_cyc_i),
.i7_wb_stb_i(i7_wb_stb_i),
.i7_wb_cab_i(i7_wb_cab_i),
.i7_wb_adr_i(i7_wb_adr_i),
.i7_wb_sel_i(i7_wb_sel_i),
.i7_wb_we_i(i7_wb_we_i),
855,7 → 803,6
 
.t0_wb_cyc_o(z_wb_cyc_i),
.t0_wb_stb_o(z_wb_stb_i),
.t0_wb_cab_o(z_wb_cab_i),
.t0_wb_adr_o(z_wb_adr_i),
.t0_wb_sel_o(z_wb_sel_i),
.t0_wb_we_o(z_wb_we_i),
874,7 → 821,6
 
.i0_wb_cyc_i(z_wb_cyc_i),
.i0_wb_stb_i(z_wb_stb_i),
.i0_wb_cab_i(z_wb_cab_i),
.i0_wb_adr_i(z_wb_adr_i),
.i0_wb_sel_i(z_wb_sel_i),
.i0_wb_we_i(z_wb_we_i),
885,7 → 831,6
 
.t0_wb_cyc_o(t1_wb_cyc_o),
.t0_wb_stb_o(t1_wb_stb_o),
.t0_wb_cab_o(t1_wb_cab_o),
.t0_wb_adr_o(t1_wb_adr_o),
.t0_wb_sel_o(t1_wb_sel_o),
.t0_wb_we_o(t1_wb_we_o),
896,7 → 841,6
 
.t1_wb_cyc_o(t2_wb_cyc_o),
.t1_wb_stb_o(t2_wb_stb_o),
.t1_wb_cab_o(t2_wb_cab_o),
.t1_wb_adr_o(t2_wb_adr_o),
.t1_wb_sel_o(t2_wb_sel_o),
.t1_wb_we_o(t2_wb_we_o),
907,7 → 851,6
 
.t2_wb_cyc_o(t3_wb_cyc_o),
.t2_wb_stb_o(t3_wb_stb_o),
.t2_wb_cab_o(t3_wb_cab_o),
.t2_wb_adr_o(t3_wb_adr_o),
.t2_wb_sel_o(t3_wb_sel_o),
.t2_wb_we_o(t3_wb_we_o),
918,7 → 861,6
 
.t3_wb_cyc_o(t4_wb_cyc_o),
.t3_wb_stb_o(t4_wb_stb_o),
.t3_wb_cab_o(t4_wb_cab_o),
.t3_wb_adr_o(t4_wb_adr_o),
.t3_wb_sel_o(t4_wb_sel_o),
.t3_wb_we_o(t4_wb_we_o),
929,7 → 871,6
 
.t4_wb_cyc_o(t5_wb_cyc_o),
.t4_wb_stb_o(t5_wb_stb_o),
.t4_wb_cab_o(t5_wb_cab_o),
.t4_wb_adr_o(t5_wb_adr_o),
.t4_wb_sel_o(t5_wb_sel_o),
.t4_wb_we_o(t5_wb_we_o),
940,7 → 881,6
 
.t5_wb_cyc_o(t6_wb_cyc_o),
.t5_wb_stb_o(t6_wb_stb_o),
.t5_wb_cab_o(t6_wb_cab_o),
.t5_wb_adr_o(t6_wb_adr_o),
.t5_wb_sel_o(t6_wb_sel_o),
.t5_wb_we_o(t6_wb_we_o),
951,7 → 891,6
 
.t6_wb_cyc_o(t7_wb_cyc_o),
.t6_wb_stb_o(t7_wb_stb_o),
.t6_wb_cab_o(t7_wb_cab_o),
.t6_wb_adr_o(t7_wb_adr_o),
.t6_wb_sel_o(t7_wb_sel_o),
.t6_wb_we_o(t7_wb_we_o),
962,7 → 901,6
 
.t7_wb_cyc_o(t8_wb_cyc_o),
.t7_wb_stb_o(t8_wb_stb_o),
.t7_wb_cab_o(t8_wb_cab_o),
.t7_wb_adr_o(t8_wb_adr_o),
.t7_wb_sel_o(t8_wb_sel_o),
.t7_wb_we_o(t8_wb_we_o),
984,7 → 922,6
 
i0_wb_cyc_i,
i0_wb_stb_i,
i0_wb_cab_i,
i0_wb_adr_i,
i0_wb_sel_i,
i0_wb_we_i,
995,7 → 932,6
 
i1_wb_cyc_i,
i1_wb_stb_i,
i1_wb_cab_i,
i1_wb_adr_i,
i1_wb_sel_i,
i1_wb_we_i,
1006,7 → 942,6
 
i2_wb_cyc_i,
i2_wb_stb_i,
i2_wb_cab_i,
i2_wb_adr_i,
i2_wb_sel_i,
i2_wb_we_i,
1017,7 → 952,6
 
i3_wb_cyc_i,
i3_wb_stb_i,
i3_wb_cab_i,
i3_wb_adr_i,
i3_wb_sel_i,
i3_wb_we_i,
1028,7 → 962,6
 
i4_wb_cyc_i,
i4_wb_stb_i,
i4_wb_cab_i,
i4_wb_adr_i,
i4_wb_sel_i,
i4_wb_we_i,
1039,7 → 972,6
 
i5_wb_cyc_i,
i5_wb_stb_i,
i5_wb_cab_i,
i5_wb_adr_i,
i5_wb_sel_i,
i5_wb_we_i,
1050,7 → 982,6
 
i6_wb_cyc_i,
i6_wb_stb_i,
i6_wb_cab_i,
i6_wb_adr_i,
i6_wb_sel_i,
i6_wb_we_i,
1061,7 → 992,6
 
i7_wb_cyc_i,
i7_wb_stb_i,
i7_wb_cab_i,
i7_wb_adr_i,
i7_wb_sel_i,
i7_wb_we_i,
1072,7 → 1002,6
 
t0_wb_cyc_o,
t0_wb_stb_o,
t0_wb_cab_o,
t0_wb_adr_o,
t0_wb_sel_o,
t0_wb_we_o,
1103,7 → 1032,6
//
input i0_wb_cyc_i;
input i0_wb_stb_i;
input i0_wb_cab_i;
input [`TC_AW-1:0] i0_wb_adr_i;
input [`TC_BSW-1:0] i0_wb_sel_i;
input i0_wb_we_i;
1117,7 → 1045,6
//
input i1_wb_cyc_i;
input i1_wb_stb_i;
input i1_wb_cab_i;
input [`TC_AW-1:0] i1_wb_adr_i;
input [`TC_BSW-1:0] i1_wb_sel_i;
input i1_wb_we_i;
1131,7 → 1058,6
//
input i2_wb_cyc_i;
input i2_wb_stb_i;
input i2_wb_cab_i;
input [`TC_AW-1:0] i2_wb_adr_i;
input [`TC_BSW-1:0] i2_wb_sel_i;
input i2_wb_we_i;
1145,7 → 1071,6
//
input i3_wb_cyc_i;
input i3_wb_stb_i;
input i3_wb_cab_i;
input [`TC_AW-1:0] i3_wb_adr_i;
input [`TC_BSW-1:0] i3_wb_sel_i;
input i3_wb_we_i;
1159,7 → 1084,6
//
input i4_wb_cyc_i;
input i4_wb_stb_i;
input i4_wb_cab_i;
input [`TC_AW-1:0] i4_wb_adr_i;
input [`TC_BSW-1:0] i4_wb_sel_i;
input i4_wb_we_i;
1173,7 → 1097,6
//
input i5_wb_cyc_i;
input i5_wb_stb_i;
input i5_wb_cab_i;
input [`TC_AW-1:0] i5_wb_adr_i;
input [`TC_BSW-1:0] i5_wb_sel_i;
input i5_wb_we_i;
1187,7 → 1110,6
//
input i6_wb_cyc_i;
input i6_wb_stb_i;
input i6_wb_cab_i;
input [`TC_AW-1:0] i6_wb_adr_i;
input [`TC_BSW-1:0] i6_wb_sel_i;
input i6_wb_we_i;
1201,7 → 1123,6
//
input i7_wb_cyc_i;
input i7_wb_stb_i;
input i7_wb_cab_i;
input [`TC_AW-1:0] i7_wb_adr_i;
input [`TC_BSW-1:0] i7_wb_sel_i;
input i7_wb_we_i;
1215,7 → 1136,6
//
output t0_wb_cyc_o;
output t0_wb_stb_o;
output t0_wb_cab_o;
output [`TC_AW-1:0] t0_wb_adr_o;
output [`TC_BSW-1:0] t0_wb_sel_o;
output t0_wb_we_o;
1245,7 → 1165,7
//
// Group WB initiator 0 i/f inputs and outputs
//
assign i0_in = {i0_wb_cyc_i, i0_wb_stb_i, i0_wb_cab_i, i0_wb_adr_i,
assign i0_in = {i0_wb_cyc_i, i0_wb_stb_i, i0_wb_adr_i,
i0_wb_sel_i, i0_wb_we_i, i0_wb_dat_i};
assign {i0_wb_dat_o, i0_wb_ack_o, i0_wb_err_o} = i0_out;
 
1252,7 → 1172,7
//
// Group WB initiator 1 i/f inputs and outputs
//
assign i1_in = {i1_wb_cyc_i, i1_wb_stb_i, i1_wb_cab_i, i1_wb_adr_i,
assign i1_in = {i1_wb_cyc_i, i1_wb_stb_i, i1_wb_adr_i,
i1_wb_sel_i, i1_wb_we_i, i1_wb_dat_i};
assign {i1_wb_dat_o, i1_wb_ack_o, i1_wb_err_o} = i1_out;
 
1259,7 → 1179,7
//
// Group WB initiator 2 i/f inputs and outputs
//
assign i2_in = {i2_wb_cyc_i, i2_wb_stb_i, i2_wb_cab_i, i2_wb_adr_i,
assign i2_in = {i2_wb_cyc_i, i2_wb_stb_i, i2_wb_adr_i,
i2_wb_sel_i, i2_wb_we_i, i2_wb_dat_i};
assign {i2_wb_dat_o, i2_wb_ack_o, i2_wb_err_o} = i2_out;
 
1266,7 → 1186,7
//
// Group WB initiator 3 i/f inputs and outputs
//
assign i3_in = {i3_wb_cyc_i, i3_wb_stb_i, i3_wb_cab_i, i3_wb_adr_i,
assign i3_in = {i3_wb_cyc_i, i3_wb_stb_i, i3_wb_adr_i,
i3_wb_sel_i, i3_wb_we_i, i3_wb_dat_i};
assign {i3_wb_dat_o, i3_wb_ack_o, i3_wb_err_o} = i3_out;
 
1273,7 → 1193,7
//
// Group WB initiator 4 i/f inputs and outputs
//
assign i4_in = {i4_wb_cyc_i, i4_wb_stb_i, i4_wb_cab_i, i4_wb_adr_i,
assign i4_in = {i4_wb_cyc_i, i4_wb_stb_i, i4_wb_adr_i,
i4_wb_sel_i, i4_wb_we_i, i4_wb_dat_i};
assign {i4_wb_dat_o, i4_wb_ack_o, i4_wb_err_o} = i4_out;
 
1280,7 → 1200,7
//
// Group WB initiator 5 i/f inputs and outputs
//
assign i5_in = {i5_wb_cyc_i, i5_wb_stb_i, i5_wb_cab_i, i5_wb_adr_i,
assign i5_in = {i5_wb_cyc_i, i5_wb_stb_i, i5_wb_adr_i,
i5_wb_sel_i, i5_wb_we_i, i5_wb_dat_i};
assign {i5_wb_dat_o, i5_wb_ack_o, i5_wb_err_o} = i5_out;
 
1287,7 → 1207,7
//
// Group WB initiator 6 i/f inputs and outputs
//
assign i6_in = {i6_wb_cyc_i, i6_wb_stb_i, i6_wb_cab_i, i6_wb_adr_i,
assign i6_in = {i6_wb_cyc_i, i6_wb_stb_i, i6_wb_adr_i,
i6_wb_sel_i, i6_wb_we_i, i6_wb_dat_i};
assign {i6_wb_dat_o, i6_wb_ack_o, i6_wb_err_o} = i6_out;
 
1294,7 → 1214,7
//
// Group WB initiator 7 i/f inputs and outputs
//
assign i7_in = {i7_wb_cyc_i, i7_wb_stb_i, i7_wb_cab_i, i7_wb_adr_i,
assign i7_in = {i7_wb_cyc_i, i7_wb_stb_i, i7_wb_adr_i,
i7_wb_sel_i, i7_wb_we_i, i7_wb_dat_i};
assign {i7_wb_dat_o, i7_wb_ack_o, i7_wb_err_o} = i7_out;
 
1301,7 → 1221,7
//
// Group WB target 0 i/f inputs and outputs
//
assign {t0_wb_cyc_o, t0_wb_stb_o, t0_wb_cab_o, t0_wb_adr_o,
assign {t0_wb_cyc_o, t0_wb_stb_o, t0_wb_adr_o,
t0_wb_sel_o, t0_wb_we_o, t0_wb_dat_o} = t0_out;
assign t0_in = {t0_wb_dat_i, t0_wb_ack_i, t0_wb_err_i};
 
1416,7 → 1336,6
 
i0_wb_cyc_i,
i0_wb_stb_i,
i0_wb_cab_i,
i0_wb_adr_i,
i0_wb_sel_i,
i0_wb_we_i,
1427,7 → 1346,6
 
t0_wb_cyc_o,
t0_wb_stb_o,
t0_wb_cab_o,
t0_wb_adr_o,
t0_wb_sel_o,
t0_wb_we_o,
1438,7 → 1356,6
 
t1_wb_cyc_o,
t1_wb_stb_o,
t1_wb_cab_o,
t1_wb_adr_o,
t1_wb_sel_o,
t1_wb_we_o,
1449,7 → 1366,6
 
t2_wb_cyc_o,
t2_wb_stb_o,
t2_wb_cab_o,
t2_wb_adr_o,
t2_wb_sel_o,
t2_wb_we_o,
1460,7 → 1376,6
 
t3_wb_cyc_o,
t3_wb_stb_o,
t3_wb_cab_o,
t3_wb_adr_o,
t3_wb_sel_o,
t3_wb_we_o,
1471,7 → 1386,6
 
t4_wb_cyc_o,
t4_wb_stb_o,
t4_wb_cab_o,
t4_wb_adr_o,
t4_wb_sel_o,
t4_wb_we_o,
1482,7 → 1396,6
 
t5_wb_cyc_o,
t5_wb_stb_o,
t5_wb_cab_o,
t5_wb_adr_o,
t5_wb_sel_o,
t5_wb_we_o,
1493,7 → 1406,6
 
t6_wb_cyc_o,
t6_wb_stb_o,
t6_wb_cab_o,
t6_wb_adr_o,
t6_wb_sel_o,
t6_wb_we_o,
1504,7 → 1416,6
 
t7_wb_cyc_o,
t7_wb_stb_o,
t7_wb_cab_o,
t7_wb_adr_o,
t7_wb_sel_o,
t7_wb_we_o,
1538,7 → 1449,6
//
input i0_wb_cyc_i;
input i0_wb_stb_i;
input i0_wb_cab_i;
input [`TC_AW-1:0] i0_wb_adr_i;
input [`TC_BSW-1:0] i0_wb_sel_i;
input i0_wb_we_i;
1552,7 → 1462,6
//
output t0_wb_cyc_o;
output t0_wb_stb_o;
output t0_wb_cab_o;
output [`TC_AW-1:0] t0_wb_adr_o;
output [`TC_BSW-1:0] t0_wb_sel_o;
output t0_wb_we_o;
1566,7 → 1475,6
//
output t1_wb_cyc_o;
output t1_wb_stb_o;
output t1_wb_cab_o;
output [`TC_AW-1:0] t1_wb_adr_o;
output [`TC_BSW-1:0] t1_wb_sel_o;
output t1_wb_we_o;
1580,7 → 1488,6
//
output t2_wb_cyc_o;
output t2_wb_stb_o;
output t2_wb_cab_o;
output [`TC_AW-1:0] t2_wb_adr_o;
output [`TC_BSW-1:0] t2_wb_sel_o;
output t2_wb_we_o;
1594,7 → 1501,6
//
output t3_wb_cyc_o;
output t3_wb_stb_o;
output t3_wb_cab_o;
output [`TC_AW-1:0] t3_wb_adr_o;
output [`TC_BSW-1:0] t3_wb_sel_o;
output t3_wb_we_o;
1608,7 → 1514,6
//
output t4_wb_cyc_o;
output t4_wb_stb_o;
output t4_wb_cab_o;
output [`TC_AW-1:0] t4_wb_adr_o;
output [`TC_BSW-1:0] t4_wb_sel_o;
output t4_wb_we_o;
1622,7 → 1527,6
//
output t5_wb_cyc_o;
output t5_wb_stb_o;
output t5_wb_cab_o;
output [`TC_AW-1:0] t5_wb_adr_o;
output [`TC_BSW-1:0] t5_wb_sel_o;
output t5_wb_we_o;
1636,7 → 1540,6
//
output t6_wb_cyc_o;
output t6_wb_stb_o;
output t6_wb_cab_o;
output [`TC_AW-1:0] t6_wb_adr_o;
output [`TC_BSW-1:0] t6_wb_sel_o;
output t6_wb_we_o;
1650,7 → 1553,6
//
output t7_wb_cyc_o;
output t7_wb_stb_o;
output t7_wb_cab_o;
output [`TC_AW-1:0] t7_wb_adr_o;
output [`TC_BSW-1:0] t7_wb_sel_o;
output t7_wb_we_o;
1677,7 → 1579,7
//
// Group WB initiator 0 i/f inputs and outputs
//
assign i0_in = {i0_wb_cyc_i, i0_wb_stb_i, i0_wb_cab_i, i0_wb_adr_i,
assign i0_in = {i0_wb_cyc_i, i0_wb_stb_i, i0_wb_adr_i,
i0_wb_sel_i, i0_wb_we_i, i0_wb_dat_i};
assign {i0_wb_dat_o, i0_wb_ack_o, i0_wb_err_o} = i0_out;
 
1684,7 → 1586,7
//
// Group WB target 0 i/f inputs and outputs
//
assign {t0_wb_cyc_o, t0_wb_stb_o, t0_wb_cab_o, t0_wb_adr_o,
assign {t0_wb_cyc_o, t0_wb_stb_o, t0_wb_adr_o,
t0_wb_sel_o, t0_wb_we_o, t0_wb_dat_o} = t0_out;
assign t0_in = {t0_wb_dat_i, t0_wb_ack_i, t0_wb_err_i};
 
1691,7 → 1593,7
//
// Group WB target 1 i/f inputs and outputs
//
assign {t1_wb_cyc_o, t1_wb_stb_o, t1_wb_cab_o, t1_wb_adr_o,
assign {t1_wb_cyc_o, t1_wb_stb_o, t1_wb_adr_o,
t1_wb_sel_o, t1_wb_we_o, t1_wb_dat_o} = t1_out;
assign t1_in = {t1_wb_dat_i, t1_wb_ack_i, t1_wb_err_i};
 
1698,7 → 1600,7
//
// Group WB target 2 i/f inputs and outputs
//
assign {t2_wb_cyc_o, t2_wb_stb_o, t2_wb_cab_o, t2_wb_adr_o,
assign {t2_wb_cyc_o, t2_wb_stb_o, t2_wb_adr_o,
t2_wb_sel_o, t2_wb_we_o, t2_wb_dat_o} = t2_out;
assign t2_in = {t2_wb_dat_i, t2_wb_ack_i, t2_wb_err_i};
 
1705,7 → 1607,7
//
// Group WB target 3 i/f inputs and outputs
//
assign {t3_wb_cyc_o, t3_wb_stb_o, t3_wb_cab_o, t3_wb_adr_o,
assign {t3_wb_cyc_o, t3_wb_stb_o, t3_wb_adr_o,
t3_wb_sel_o, t3_wb_we_o, t3_wb_dat_o} = t3_out;
assign t3_in = {t3_wb_dat_i, t3_wb_ack_i, t3_wb_err_i};
 
1712,7 → 1614,7
//
// Group WB target 4 i/f inputs and outputs
//
assign {t4_wb_cyc_o, t4_wb_stb_o, t4_wb_cab_o, t4_wb_adr_o,
assign {t4_wb_cyc_o, t4_wb_stb_o, t4_wb_adr_o,
t4_wb_sel_o, t4_wb_we_o, t4_wb_dat_o} = t4_out;
assign t4_in = {t4_wb_dat_i, t4_wb_ack_i, t4_wb_err_i};
 
1719,7 → 1621,7
//
// Group WB target 5 i/f inputs and outputs
//
assign {t5_wb_cyc_o, t5_wb_stb_o, t5_wb_cab_o, t5_wb_adr_o,
assign {t5_wb_cyc_o, t5_wb_stb_o, t5_wb_adr_o,
t5_wb_sel_o, t5_wb_we_o, t5_wb_dat_o} = t5_out;
assign t5_in = {t5_wb_dat_i, t5_wb_ack_i, t5_wb_err_i};
 
1726,7 → 1628,7
//
// Group WB target 6 i/f inputs and outputs
//
assign {t6_wb_cyc_o, t6_wb_stb_o, t6_wb_cab_o, t6_wb_adr_o,
assign {t6_wb_cyc_o, t6_wb_stb_o, t6_wb_adr_o,
t6_wb_sel_o, t6_wb_we_o, t6_wb_dat_o} = t6_out;
assign t6_in = {t6_wb_dat_i, t6_wb_ack_i, t6_wb_err_i};
 
1733,7 → 1635,7
//
// Group WB target 7 i/f inputs and outputs
//
assign {t7_wb_cyc_o, t7_wb_stb_o, t7_wb_cab_o, t7_wb_adr_o,
assign {t7_wb_cyc_o, t7_wb_stb_o, t7_wb_adr_o,
t7_wb_sel_o, t7_wb_we_o, t7_wb_dat_o} = t7_out;
assign t7_in = {t7_wb_dat_i, t7_wb_ack_i, t7_wb_err_i};
 
/verilog/minsoc_defines.v
1,64 → 1,4
//////////////////////////////////////////////////////////////////////
//// ////
//// OR1K test app definitions ////
//// ////
//// This file is part of the OR1K test application ////
//// http://www.opencores.org/cores/or1k/xess/ ////
//// ////
//// Description ////
//// DEfine target technology etc. Right now FIFOs are available ////
//// only for Xilinx Virtex FPGAs. (TARGET_VIRTEX) ////
//// ////
//// To Do: ////
//// - nothing really ////
//// ////
//// Author(s): ////
//// - Damjan Lampret, damjan.lampret@opencores.org ////
//// ////
//////////////////////////////////////////////////////////////////////
//// ////
//// Copyright (C) 2001 Authors ////
//// ////
//// This source file may be used and distributed without ////
//// restriction provided that this copyright statement is not ////
//// removed from the file and that any derivative work contains ////
//// the original copyright notice and the associated disclaimer. ////
//// ////
//// This source file is free software; you can redistribute it ////
//// and/or modify it under the terms of the GNU Lesser General ////
//// Public License as published by the Free Software Foundation; ////
//// either version 2.1 of the License, or (at your option) any ////
//// later version. ////
//// ////
//// This source is distributed in the hope that it will be ////
//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
//// PURPOSE. See the GNU Lesser General Public License for more ////
//// details. ////
//// ////
//// You should have received a copy of the GNU Lesser General ////
//// Public License along with this source; if not, download it ////
//// from http://www.opencores.org/lgpl.shtml ////
//// ////
//////////////////////////////////////////////////////////////////////
//
// CVS Revision History
//
// $Log: xsv_fpga_defines.v,v $
// Revision 1.4 2004/04/05 08:44:35 lampret
// Merged branch_qmem into main tree.
//
// Revision 1.2 2002/03/29 20:58:51 lampret
// Changed hardcoded address for fake MC to use a define.
//
// Revision 1.1.1.1 2002/03/21 16:55:44 lampret
// First import of the "new" XESS XSV environment.
//
//
//
 
 
//
// Define FPGA manufacturer
//
//`define GENERIC_FPGA
86,7 → 26,7
//the memory data width is 32 bit, memory amount in Bytes = 4*memory depth
 
//
// Memory type (uncomment something if ASIC or if you want generic memory)
// Memory type (uncomment something if ASIC or generic memory)
//
//`define GENERIC_MEMORY
//`define AVANT_ATP
116,6 → 56,12
//DO NOT USE CLOCK_DIVISOR = 1 COMMENT THE CLOCK DIVISION SELECTION INSTEAD
 
//
// Reset polarity
//
//`define NEGATIVE_RESET; //rstn
`define POSITIVE_RESET; //rst
 
//
// Start-up circuit (only necessary later to load firmware automatically from SPI memory)
//
//`define START_UP
/verilog/minsoc_onchip_ram.v
436,7 → 436,6
lpm_ram_dq lpm_ram_dq_component (
.address(addr),
.inclock(clk),
// .outclock(clk),
.data(di),
.we(wr),
.q(doq_internal)
/verilog/minsoc_onchip_ram_top.v
46,7 → 46,12
//
// Revision History
//
// Revision 1.1 2009/10/02 16:49 fajardo
// Not using the oe signal (output enable) from
// memories, instead multiplexing the outputs
// between the different instantiated blocks
//
//
// Revision 1.0 2009/08/18 15:15:00 fajardo
// Created interface and tested
//
62,9 → 67,9
//
// Parameters
//
parameter aw_int = 11; //11 = 2048
parameter adr_width = 13; //Memory address width, is composed by blocks of aw_int, is not allowed to be less than 12
parameter blocks = (1<<(adr_width-aw_int)); //generated memory contains "blocks" memory blocks of 2048x32 2048 depth x32 bit data
localparam aw_int = 11; //11 = 2048
localparam blocks = (1<<(adr_width-aw_int)); //generated memory contains "blocks" memory blocks of 2048x32 2048 depth x32 bit data
 
//
// I/O Ports
129,6 → 134,53
ack_re <= #1 1'b0;
end
 
//Generic (multiple inputs x 1 output) MUX
localparam mux_in_nr = blocks;
localparam slices = adr_width-aw_int;
localparam mux_out_nr = blocks-1;
 
wire [31:0] int_dat_o[0:mux_in_nr-1];
wire [31:0] mux_out[0:mux_out_nr-1];
 
generate
genvar j, k;
for (j=0; j<slices; j=j+1) begin : SLICES
for (k=0; k<(mux_in_nr>>(j+1)); k=k+1) begin : MUX
if (j==0) begin
mux2 #
(
.dw(32)
)
mux_int(
.sel( wb_adr_i[aw_int+2+j] ),
.in1( int_dat_o[k*2] ),
.in2( int_dat_o[k*2+1] ),
.out( mux_out[k] )
);
end
else begin
mux2 #
(
.dw(32)
)
mux_int(
.sel( wb_adr_i[aw_int+2+j] ),
.in1( mux_out[(mux_in_nr-(mux_in_nr>>(j-1)))+k*2] ),
.in2( mux_out[(mux_in_nr-(mux_in_nr>>(j-1)))+k*2+1] ),
.out( mux_out[(mux_in_nr-(mux_in_nr>>j))+k] )
);
end
end
end
endgenerate
 
//last output = total output
assign wb_dat_o = mux_out[mux_out_nr-1];
 
//(mux_in_nr-(mux_in_nr>>j)):
//-Given sum of 2^i | i = x -> y series can be resumed to 2^(y+1)-2^x
//so, with this expression I'm evaluating how many times the internal loop has been run
 
wire [blocks-1:0] bank;
generate
143,10 → 195,11
.rst(wb_rst_i),
.addr(wb_adr_i[aw_int+1:2]),
.di(wb_dat_i[7:0]),
.doq(wb_dat_o[7:0]),
.doq(int_dat_o[i][7:0]),
.we(we & bank[i]),
.oe(bank[i]),
.ce(be_i[0]));
.oe(1'b1),
.ce(be_i[0])
);
 
 
minsoc_onchip_ram block_ram_1 (
154,10 → 207,11
.rst(wb_rst_i),
.addr(wb_adr_i[aw_int+1:2]),
.di(wb_dat_i[15:8]),
.doq(wb_dat_o[15:8]),
.doq(int_dat_o[i][15:8]),
.we(we & bank[i]),
.oe(bank[i]),
.ce(be_i[1]));
.oe(1'b1),
.ce(be_i[1])
);
 
minsoc_onchip_ram block_ram_2 (
.clk(wb_clk_i),
164,10 → 218,11
.rst(wb_rst_i),
.addr(wb_adr_i[aw_int+1:2]),
.di(wb_dat_i[23:16]),
.doq(wb_dat_o[23:16]),
.doq(int_dat_o[i][23:16]),
.we(we & bank[i]),
.oe(bank[i]),
.ce(be_i[2]));
.oe(1'b1),
.ce(be_i[2])
);
 
minsoc_onchip_ram block_ram_3 (
.clk(wb_clk_i),
174,10 → 229,11
.rst(wb_rst_i),
.addr(wb_adr_i[aw_int+1:2]),
.di(wb_dat_i[31:24]),
.doq(wb_dat_o[31:24]),
.doq(int_dat_o[i][31:24]),
.we(we & bank[i]),
.oe(bank[i]),
.ce(be_i[3]));
.oe(1'b1),
.ce(be_i[3])
);
 
end
endgenerate
184,3 → 240,20
 
endmodule
 
module mux2(sel,in1,in2,out);
 
parameter dw = 32;
 
input sel;
input [dw-1:0] in1, in2;
output reg [dw-1:0] out;
 
always @ (sel or in1 or in2)
begin
case (sel)
1'b0: out = in1;
1'b1: out = in2;
endcase
end
 
endmodule
/verilog/minsoc_top.v
1,75 → 1,3
//////////////////////////////////////////////////////////////////////
//// ////
//// OR1K test application for XESS XSV board, Top Level ////
//// ////
//// This file is part of the OR1K test application ////
//// http://www.opencores.org/cores/or1k/ ////
//// ////
//// Description ////
//// Top level instantiating all the blocks. ////
//// ////
//// To Do: ////
//// - nothing really ////
//// ////
//// Author(s): ////
//// - Damjan Lampret, lampret@opencores.org ////
//// ////
//////////////////////////////////////////////////////////////////////
//// ////
//// Copyright (C) 2001 Authors ////
//// ////
//// This source file may be used and distributed without ////
//// restriction provided that this copyright statement is not ////
//// removed from the file and that any derivative work contains ////
//// the original copyright notice and the associated disclaimer. ////
//// ////
//// This source file is free software; you can redistribute it ////
//// and/or modify it under the terms of the GNU Lesser General ////
//// Public License as published by the Free Software Foundation; ////
//// either version 2.1 of the License, or (at your option) any ////
//// later version. ////
//// ////
//// This source is distributed in the hope that it will be ////
//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
//// PURPOSE. See the GNU Lesser General Public License for more ////
//// details. ////
//// ////
//// You should have received a copy of the GNU Lesser General ////
//// Public License along with this source; if not, download it ////
//// from http://www.opencores.org/lgpl.shtml ////
//// ////
//////////////////////////////////////////////////////////////////////
//
// CVS Revision History
//
// $Log: xsv_fpga_top.v,v $
// Revision 1.10 2004/04/05 08:44:35 lampret
// Merged branch_qmem into main tree.
//
// Revision 1.8 2003/04/07 21:05:58 lampret
// WB = 1/2 RISC clock test code enabled.
//
// Revision 1.7 2003/04/07 01:28:17 lampret
// Adding OR1200_CLMODE_1TO2 test code.
//
// Revision 1.6 2002/08/12 05:35:12 lampret
// rty_i are unused - tied to zero.
//
// Revision 1.5 2002/03/29 20:58:51 lampret
// Changed hardcoded address for fake MC to use a define.
//
// Revision 1.4 2002/03/29 16:30:47 lampret
// Fixed port names that changed.
//
// Revision 1.3 2002/03/29 15:50:03 lampret
// Added response from memory controller (addr 0x60000000)
//
// Revision 1.2 2002/03/21 17:39:16 lampret
// Fixed some typos
//
//
 
`include "minsoc_defines.v"
`include "or1200_defines.v"
 
164,7 → 92,11
 
wire rstn;
 
`ifdef POSITIVE_RESET
assign rstn = ~reset;
`elsif NEGATIVE_RESET
assign rstn = reset;
`endif
 
//
// Internal wires
180,7 → 112,6
wire wb_dm_we_o;
wire wb_dm_stb_o;
wire wb_dm_cyc_o;
wire wb_dm_cab_o;
wire wb_dm_ack_i;
wire wb_dm_err_i;
 
212,7 → 143,6
wire wb_rim_rty_i = 1'b0;
wire wb_rim_we_o;
wire wb_rim_stb_o;
wire wb_rim_cab_o;
wire [31:0] wb_rif_dat_i;
wire wb_rif_ack_i;
 
229,7 → 159,6
wire wb_rdm_rty_i = 1'b0;
wire wb_rdm_we_o;
wire wb_rdm_stb_o;
wire wb_rdm_cab_o;
 
//
// RISC misc
293,7 → 222,6
wire wb_em_we_o;
wire wb_em_stb_o;
wire wb_em_cyc_o;
wire wb_em_cab_o;
wire wb_em_ack_i;
wire wb_em_err_i;
 
344,11 → 272,7
//
// Global clock
//
`ifdef OR1200_CLMODE_1TO2
reg wb_clk;
`else
wire wb_clk;
`endif
 
//
// Reset debounce
366,15 → 290,8
wb_rst <= #1 rst_r;
 
//
// This is purely for testing 1/2 WB clock
// This should never be used when implementing in
// an FPGA. It is used only for simulation regressions.
// Clock Divider
//
`ifdef OR1200_CLMODE_1TO2
initial wb_clk = 0;
always @(posedge clk)
wb_clk = ~wb_clk;
`else
minsoc_clock_manager #
(
.divisor(`CLOCK_DIVISOR)
383,13 → 300,11
.clk_i(clk),
.clk_o(wb_clk)
);
`endif // OR1200_CLMODE_1TO2
 
//
// Unused WISHBONE signals
//
assign wb_us_err_o = 1'b0;
assign wb_em_cab_o = 1'b0;
assign wb_fs_err_o = 1'b0;
assign wb_sp_err_o = 1'b0;
 
510,7 → 425,6
.wb_we_o ( wb_dm_we_o ),
.wb_stb_o ( wb_dm_stb_o ),
.wb_cyc_o ( wb_dm_cyc_o ),
.wb_cab_o ( wb_dm_cab_o ),
.wb_ack_i ( wb_dm_ack_i ),
.wb_err_i ( wb_dm_err_i ),
.wb_cti_o ( ),
629,7 → 543,6
.iwb_rty_i ( wb_rim_rty_i ),
.iwb_we_o ( wb_rim_we_o ),
.iwb_stb_o ( wb_rim_stb_o ),
.iwb_cab_o ( wb_rim_cab_o ),
 
// WISHBONE Data Master
.dwb_clk_i ( wb_clk ),
644,7 → 557,6
.dwb_rty_i ( wb_rdm_rty_i ),
.dwb_we_o ( wb_rdm_we_o ),
.dwb_stb_o ( wb_rdm_stb_o ),
.dwb_cab_o ( wb_rdm_cab_o ),
 
// Debug
.dbg_stall_i ( dbg_stall ),
880,7 → 792,6
// WISHBONE Initiator 0
.i0_wb_cyc_i ( 1'b0 ),
.i0_wb_stb_i ( 1'b0 ),
.i0_wb_cab_i ( 1'b0 ),
.i0_wb_adr_i ( 32'h0000_0000 ),
.i0_wb_sel_i ( 4'b0000 ),
.i0_wb_we_i ( 1'b0 ),
892,7 → 803,6
// WISHBONE Initiator 1
.i1_wb_cyc_i ( wb_em_cyc_o ),
.i1_wb_stb_i ( wb_em_stb_o ),
.i1_wb_cab_i ( wb_em_cab_o ),
.i1_wb_adr_i ( wb_em_adr_o ),
.i1_wb_sel_i ( wb_em_sel_o ),
.i1_wb_we_i ( wb_em_we_o ),
904,7 → 814,6
// WISHBONE Initiator 2
.i2_wb_cyc_i ( 1'b0 ),
.i2_wb_stb_i ( 1'b0 ),
.i2_wb_cab_i ( 1'b0 ),
.i2_wb_adr_i ( 32'h0000_0000 ),
.i2_wb_sel_i ( 4'b0000 ),
.i2_wb_we_i ( 1'b0 ),
916,7 → 825,6
// WISHBONE Initiator 3
.i3_wb_cyc_i ( wb_dm_cyc_o ),
.i3_wb_stb_i ( wb_dm_stb_o ),
.i3_wb_cab_i ( wb_dm_cab_o ),
.i3_wb_adr_i ( wb_dm_adr_o ),
.i3_wb_sel_i ( wb_dm_sel_o ),
.i3_wb_we_i ( wb_dm_we_o ),
928,7 → 836,6
// WISHBONE Initiator 4
.i4_wb_cyc_i ( wb_rdm_cyc_o ),
.i4_wb_stb_i ( wb_rdm_stb_o ),
.i4_wb_cab_i ( wb_rdm_cab_o ),
.i4_wb_adr_i ( wb_rdm_adr_o ),
.i4_wb_sel_i ( wb_rdm_sel_o ),
.i4_wb_we_i ( wb_rdm_we_o ),
940,7 → 847,6
// WISHBONE Initiator 5
.i5_wb_cyc_i ( wb_rim_cyc_o ),
.i5_wb_stb_i ( wb_rim_stb_o ),
.i5_wb_cab_i ( wb_rim_cab_o ),
.i5_wb_adr_i ( wb_rim_adr_o ),
.i5_wb_sel_i ( wb_rim_sel_o ),
.i5_wb_we_i ( wb_rim_we_o ),
952,7 → 858,6
// WISHBONE Initiator 6
.i6_wb_cyc_i ( 1'b0 ),
.i6_wb_stb_i ( 1'b0 ),
.i6_wb_cab_i ( 1'b0 ),
.i6_wb_adr_i ( 32'h0000_0000 ),
.i6_wb_sel_i ( 4'b0000 ),
.i6_wb_we_i ( 1'b0 ),
964,7 → 869,6
// WISHBONE Initiator 7
.i7_wb_cyc_i ( 1'b0 ),
.i7_wb_stb_i ( 1'b0 ),
.i7_wb_cab_i ( 1'b0 ),
.i7_wb_adr_i ( 32'h0000_0000 ),
.i7_wb_sel_i ( 4'b0000 ),
.i7_wb_we_i ( 1'b0 ),
976,7 → 880,6
// WISHBONE Target 0
.t0_wb_cyc_o ( wb_ss_cyc_i ),
.t0_wb_stb_o ( wb_ss_stb_i ),
.t0_wb_cab_o ( wb_ss_cab_i ),
.t0_wb_adr_o ( wb_ss_adr_i ),
.t0_wb_sel_o ( wb_ss_sel_i ),
.t0_wb_we_o ( wb_ss_we_i ),
988,7 → 891,6
// WISHBONE Target 1
.t1_wb_cyc_o ( wb_fs_cyc_i ),
.t1_wb_stb_o ( wb_fs_stb_i ),
.t1_wb_cab_o ( wb_fs_cab_i ),
.t1_wb_adr_o ( wb_fs_adr_i ),
.t1_wb_sel_o ( wb_fs_sel_i ),
.t1_wb_we_o ( wb_fs_we_i ),
1000,7 → 902,6
// WISHBONE Target 2
.t2_wb_cyc_o ( wb_sp_cyc_i ),
.t2_wb_stb_o ( wb_sp_stb_i ),
.t2_wb_cab_o ( wb_sp_cab_i ),
.t2_wb_adr_o ( wb_sp_adr_i ),
.t2_wb_sel_o ( wb_sp_sel_i ),
.t2_wb_we_o ( wb_sp_we_i ),
1012,7 → 913,6
// WISHBONE Target 3
.t3_wb_cyc_o ( wb_es_cyc_i ),
.t3_wb_stb_o ( wb_es_stb_i ),
.t3_wb_cab_o ( wb_es_cab_i ),
.t3_wb_adr_o ( wb_es_adr_i ),
.t3_wb_sel_o ( wb_es_sel_i ),
.t3_wb_we_o ( wb_es_we_i ),
1024,7 → 924,6
// WISHBONE Target 4
.t4_wb_cyc_o ( ),
.t4_wb_stb_o ( ),
.t4_wb_cab_o ( ),
.t4_wb_adr_o ( ),
.t4_wb_sel_o ( ),
.t4_wb_we_o ( ),
1036,7 → 935,6
// WISHBONE Target 5
.t5_wb_cyc_o ( wb_us_cyc_i ),
.t5_wb_stb_o ( wb_us_stb_i ),
.t5_wb_cab_o ( wb_us_cab_i ),
.t5_wb_adr_o ( wb_us_adr_i ),
.t5_wb_sel_o ( wb_us_sel_i ),
.t5_wb_we_o ( wb_us_we_i ),
1048,7 → 946,6
// WISHBONE Target 6
.t6_wb_cyc_o ( ),
.t6_wb_stb_o ( ),
.t6_wb_cab_o ( ),
.t6_wb_adr_o ( ),
.t6_wb_sel_o ( ),
.t6_wb_we_o ( ),
1060,7 → 957,6
// WISHBONE Target 7
.t7_wb_cyc_o ( ),
.t7_wb_stb_o ( ),
.t7_wb_cab_o ( ),
.t7_wb_adr_o ( ),
.t7_wb_sel_o ( ),
.t7_wb_we_o ( ),
1072,7 → 968,6
// WISHBONE Target 8
.t8_wb_cyc_o ( ),
.t8_wb_stb_o ( ),
.t8_wb_cab_o ( ),
.t8_wb_adr_o ( ),
.t8_wb_sel_o ( ),
.t8_wb_we_o ( ),

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