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URL https://opencores.org/ocsvn/minsoc/minsoc/trunk

Subversion Repositories minsoc

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    /minsoc/trunk/rtl
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Rev 60 → Rev 62

/verilog/minsoc_pll.v File deleted
/verilog/minsoc_clock_manager.v
29,259 → 29,30
end
end
assign clk_o = clk_int;
 
`elsif FPGA_CLOCK_DIVISION
 
`ifdef ALTERA_FPGA
`ifdef ARRIA_GX
defparam systemPll.FAMILY = "Arria GX";
`elsif ARRIA_II_GX
defparam systemPll.FAMILY = "Arria II GX";
`elsif CYCLONE_I
defparam systemPll.FAMILY = "Cyclone I";
`elsif CYCLONE_II
defparam systemPll.FAMILY = "Cyclone II";
`elsif CYCLONE_III
defparam systemPll.FAMILY = "Cyclone III";
`elsif CYCLONE_III_LS
defparam systemPll.FAMILY = "Cyclone III LS";
`elsif CYCLONE_IV_E
defparam systemPll.FAMILY = "Cyclone IV E";
`elsif CYCLONE_IV_GS
defparam systemPll.FAMILY = "Cyclone IV GS";
`elsif MAX_II
defparam systemPll.FAMILY = "MAX II";
`elsif MAX_V
defparam systemPll.FAMILY = "MAX V";
`elsif MAX3000A
defparam systemPll.FAMILY = "MAX3000A";
`elsif MAX7000AE
defparam systemPll.FAMILY = "MAX7000AE";
`elsif MAX7000B
defparam systemPll.FAMILY = "MAX7000B";
`elsif MAX7000S
defparam systemPll.FAMILY = "MAX7000S";
`elsif STRATIX
defparam systemPll.FAMILY = "Stratix";
`elsif STRATIX_II
defapram systemPll.FAMILY = "Stratix II";
`elsif STRATIX_II_GX
defparam systemPll.FAMILY = "Stratix II GX";
`elsif STRATIX_III
defparam systemPll.FAMILY = "Stratix III"
`endif
defparam systemPll.FREQ_DIV = divisor;
`ifdef ALTERA_FPGA
altera_pll #
(
.FREQ_DIV(divisor)
)
minsoc_altera_pll
(
.inclk0(clk_i),
.c0(clk_o)
);
minsoc_pll systemPll
(
.inclk0(clk_i),
.c0(clk_o)
);
`elsif XILINX_FPGA
 
`ifdef SPARTAN2
`define MINSOC_DLL
`elsif VIRTEX
`define MINSOC_DLL
`endif // !SPARTAN2/VIRTEX
 
`ifdef SPARTAN3
`define MINSOC_DCM
`elsif VIRTEX2
`define MINSOC_DCM
`endif // !SPARTAN3/VIRTEX2
 
`ifdef SPARTAN3E
`define MINSOC_DCM_SP
`elsif SPARTAN3A
`define MINSOC_DCM_SP
`endif // !SPARTAN3E/SPARTAN3A
 
`ifdef VIRTEX4
`define MINSOC_DCM_ADV
`define MINSOC_DCM_COMPONENT "VIRTEX4"
`elsif VIRTEX5
`define MINSOC_DCM_ADV
`define MINSOC_DCM_COMPONENT "VIRTEX5"
`endif // !VIRTEX4/VIRTEX5
 
wire CLKIN_IN;
wire CLKDV_OUT;
 
assign CLKIN_IN = clk_i;
assign clk_o = CLKDV_OUT;
 
wire CLKIN_IBUFG;
wire CLK0_BUF;
wire CLKFB_IN;
wire CLKDV_BUF;
 
IBUFG CLKIN_IBUFG_INST (
.I(CLKIN_IN),
.O(CLKIN_IBUFG)
xilinx_dcm #
(
.divisor(divisor)
)
minsoc_xilinx_dcm
(
.clk_i(clk_i),
.clk_o(clk_o)
);
 
BUFG CLK0_BUFG_INST (
.I(CLK0_BUF),
.O(CLKFB_IN)
);
 
BUFG CLKDV_BUFG_INST (
.I(CLKDV_BUF),
.O(CLKDV_OUT)
);
 
`ifdef MINSOC_DLL
 
CLKDLL #(
.CLKDV_DIVIDE(divisor), // Divide by: 1.5,2.0,2.5,3.0,4.0,5.0,8.0 or 16.0
.DUTY_CYCLE_CORRECTION("TRUE"), // Duty cycle correction, TRUE or FALSE
.FACTORY_JF(16'hC080), // FACTORY JF Values
.STARTUP_WAIT("FALSE") // Delay config DONE until DLL LOCK, TRUE/FALSE
) CLKDLL_inst (
.CLK0(CLK0_BUF), // 0 degree DLL CLK output
.CLK180(), // 180 degree DLL CLK output
.CLK270(), // 270 degree DLL CLK output
.CLK2X(), // 2X DLL CLK output
.CLK90(), // 90 degree DLL CLK output
.CLKDV(CLKDV_BUF), // Divided DLL CLK out (CLKDV_DIVIDE)
.LOCKED(), // DLL LOCK status output
.CLKFB(CLKFB_IN), // DLL clock feedback
.CLKIN(CLKIN_IBUFG), // Clock input (from IBUFG, BUFG or DLL)
.RST(1'b0) // DLL asynchronous reset input
);
 
`elsif MINSOC_DCM
 
DCM #(
.SIM_MODE("SAFE"), // Simulation: "SAFE" vs. "FAST", see "Synthesis and Simulation Design Guide" for details
.CLKDV_DIVIDE(divisor), // Divide by: 1.5,2.0,2.5,3.0,3.5,4.0,4.5,5.0,5.5,6.0,6.5
// 7.0,7.5,8.0,9.0,10.0,11.0,12.0,13.0,14.0,15.0 or 16.0
.CLKFX_DIVIDE(1), // Can be any integer from 1 to 32
.CLKFX_MULTIPLY(4), // Can be any integer from 2 to 32
.CLKIN_DIVIDE_BY_2("FALSE"), // TRUE/FALSE to enable CLKIN divide by two feature
.CLKIN_PERIOD(0.0), // Specify period of input clock
.CLKOUT_PHASE_SHIFT("NONE"), // Specify phase shift of NONE, FIXED or VARIABLE
.CLK_FEEDBACK("1X"), // Specify clock feedback of NONE, 1X or 2X
.DESKEW_ADJUST("SYSTEM_SYNCHRONOUS"), // SOURCE_SYNCHRONOUS, SYSTEM_SYNCHRONOUS or
// an integer from 0 to 15
.DFS_FREQUENCY_MODE("LOW"), // HIGH or LOW frequency mode for frequency synthesis
.DLL_FREQUENCY_MODE("LOW"), // HIGH or LOW frequency mode for DLL
.DUTY_CYCLE_CORRECTION("TRUE"), // Duty cycle correction, TRUE or FALSE
.FACTORY_JF(16'hC080), // FACTORY JF values
.PHASE_SHIFT(0), // Amount of fixed phase shift from -255 to 255
.STARTUP_WAIT("FALSE") // Delay configuration DONE until DCM LOCK, TRUE/FALSE
) DCM_inst (
.CLK0(CLK0_BUF), // 0 degree DCM CLK output
.CLK180(), // 180 degree DCM CLK output
.CLK270(), // 270 degree DCM CLK output
.CLK2X(), // 2X DCM CLK output
.CLK2X180(), // 2X, 180 degree DCM CLK out
.CLK90(), // 90 degree DCM CLK output
.CLKDV(CLKDV_BUF), // Divided DCM CLK out (CLKDV_DIVIDE)
.CLKFX(), // DCM CLK synthesis out (M/D)
.CLKFX180(), // 180 degree CLK synthesis out
.LOCKED(), // DCM LOCK status output
.PSDONE(), // Dynamic phase adjust done output
.STATUS(), // 8-bit DCM status bits output
.CLKFB(CLKFB_IN), // DCM clock feedback
.CLKIN(CLKIN_IBUFG), // Clock input (from IBUFG, BUFG or DCM)
.PSCLK(1'b0), // Dynamic phase adjust clock input
.PSEN(1'b0), // Dynamic phase adjust enable input
.PSINCDEC(1'b0), // Dynamic phase adjust increment/decrement
.RST(1'b0) // DCM asynchronous reset input
);
 
`elsif MINSOC_DCM_SP
 
DCM_SP #(
.CLKDV_DIVIDE(divisor), // Divide by: 1.5,2.0,2.5,3.0,3.5,4.0,4.5,5.0,5.5,6.0,6.5
// 7.0,7.5,8.0,9.0,10.0,11.0,12.0,13.0,14.0,15.0 or 16.0
.CLKFX_DIVIDE(1), // Can be any integer from 1 to 32
.CLKFX_MULTIPLY(4), // Can be any integer from 2 to 32
.CLKIN_DIVIDE_BY_2("FALSE"), // TRUE/FALSE to enable CLKIN divide by two feature
.CLKIN_PERIOD(0.0), // Specify period of input clock
.CLKOUT_PHASE_SHIFT("NONE"), // Specify phase shift of NONE, FIXED or VARIABLE
.CLK_FEEDBACK("1X"), // Specify clock feedback of NONE, 1X or 2X
.DESKEW_ADJUST("SYSTEM_SYNCHRONOUS"), // SOURCE_SYNCHRONOUS, SYSTEM_SYNCHRONOUS or
// an integer from 0 to 15
.DLL_FREQUENCY_MODE("LOW"), // HIGH or LOW frequency mode for DLL
.DUTY_CYCLE_CORRECTION("TRUE"), // Duty cycle correction, TRUE or FALSE
.PHASE_SHIFT(0), // Amount of fixed phase shift from -255 to 255
.STARTUP_WAIT("FALSE") // Delay configuration DONE until DCM LOCK, TRUE/FALSE
) DCM_SP_inst (
.CLK0(CLK0_BUF), // 0 degree DCM CLK output
.CLK180(), // 180 degree DCM CLK output
.CLK270(), // 270 degree DCM CLK output
.CLK2X(), // 2X DCM CLK output
.CLK2X180(), // 2X, 180 degree DCM CLK out
.CLK90(), // 90 degree DCM CLK output
.CLKDV(CLKDV_BUF), // Divided DCM CLK out (CLKDV_DIVIDE)
.CLKFX(), // DCM CLK synthesis out (M/D)
.CLKFX180(), // 180 degree CLK synthesis out
.LOCKED(), // DCM LOCK status output
.PSDONE(), // Dynamic phase adjust done output
.STATUS(), // 8-bit DCM status bits output
.CLKFB(CLKFB_IN), // DCM clock feedback
.CLKIN(CLKIN_IBUFG), // Clock input (from IBUFG, BUFG or DCM)
.PSCLK(1'b0), // Dynamic phase adjust clock input
.PSEN(1'b0), // Dynamic phase adjust enable input
.PSINCDEC(1'b0), // Dynamic phase adjust increment/decrement
.RST(1'b0) // DCM asynchronous reset input
);
 
`elsif MINSOC_DCM_ADV
 
DCM_ADV #(
.CLKDV_DIVIDE(divisor), // Divide by: 1.5,2.0,2.5,3.0,3.5,4.0,4.5,5.0,5.5,6.0,6.5
// 7.0,7.5,8.0,9.0,10.0,11.0,12.0,13.0,14.0,15.0 or 16.0
.CLKFX_DIVIDE(1), // Can be any integer from 1 to 32
.CLKFX_MULTIPLY(4), // Can be any integer from 2 to 32
.CLKIN_DIVIDE_BY_2("FALSE"), // TRUE/FALSE to enable CLKIN divide by two feature
.CLKIN_PERIOD(10.0), // Specify period of input clock in ns from 1.25 to 1000.00
.CLKOUT_PHASE_SHIFT("NONE"), // Specify phase shift mode of NONE, FIXED,
// VARIABLE_POSITIVE, VARIABLE_CENTER or DIRECT
.CLK_FEEDBACK("1X"), // Specify clock feedback of NONE, 1X or 2X
.DCM_AUTOCALIBRATION("TRUE"), // DCM calibration circuitry "TRUE"/"FALSE"
.DCM_PERFORMANCE_MODE("MAX_SPEED"), // Can be MAX_SPEED or MAX_RANGE
.DESKEW_ADJUST("SYSTEM_SYNCHRONOUS"), // SOURCE_SYNCHRONOUS, SYSTEM_SYNCHRONOUS or
// an integer from 0 to 15
.DFS_FREQUENCY_MODE("LOW"), // HIGH or LOW frequency mode for frequency synthesis
.DLL_FREQUENCY_MODE("LOW"), // LOW, HIGH, or HIGH_SER frequency mode for DLL
.DUTY_CYCLE_CORRECTION("TRUE"), // Duty cycle correction, "TRUE"/"FALSE"
.FACTORY_JF(16'hf0f0), // FACTORY JF value suggested to be set to 16’hf0f0
.PHASE_SHIFT(0), // Amount of fixed phase shift from -255 to 1023
.SIM_DEVICE(`MINSOC_DCM_COMPONENT), // Set target device, "VIRTEX4" or "VIRTEX5"
.STARTUP_WAIT("FALSE") // Delay configuration DONE until DCM LOCK, "TRUE"/"FALSE"
) DCM_ADV_inst (
.CLK0(CLK0_BUF), // 0 degree DCM CLK output
.CLK180(), // 180 degree DCM CLK output
.CLK270(), // 270 degree DCM CLK output
.CLK2X(), // 2X DCM CLK output
.CLK2X180(), // 2X, 180 degree DCM CLK out
.CLK90(), // 90 degree DCM CLK output
.CLKDV(CLKDV_BUF), // Divided DCM CLK out (CLKDV_DIVIDE)
.CLKFX(), // DCM CLK synthesis out (M/D)
.CLKFX180(), // 180 degree CLK synthesis out
.DO(), // 16-bit data output for Dynamic Reconfiguration Port (DRP)
.DRDY(), // Ready output signal from the DRP
.LOCKED(), // DCM LOCK status output
.PSDONE(), // Dynamic phase adjust done output
.CLKFB(CLKFB_IN), // DCM clock feedback
.CLKIN(CLKIN_IBUFG), // Clock input (from IBUFG, BUFG or DCM)
.DADDR(7'h00), // 7-bit address for the DRP
.DCLK(1'b0), // Clock for the DRP
.DEN(1'b0), // Enable input for the DRP
.DI(16'h0000), // 16-bit data input for the DRP
.DWE(1'b0), // Active high allows for writing configuration memory
.PSCLK(1'b0), // Dynamic phase adjust clock input
.PSEN(1'b0), // Dynamic phase adjust enable input
.PSINCDEC(1'b0), // Dynamic phase adjust increment/decrement
.RST(1'b0) // DCM asynchronous reset input
);
 
`endif // !MINSOC_DLL/MINSOC_DCM/MINSOC_DCM_SP/MINSOC_DCM_ADV
`endif // !ALTERA_FPGA/XILINX_FPGA
`endif // !NO_CLOCK_DIVISION/GENERIC_CLOCK_DIVISION/FPGA_CLOCK_DIVISION
 
/verilog/xilinx_dcm.v
0,0 → 1,223
 
`include "minsoc_defines.v"
 
module xilinx_dcm(
clk_i,
clk_o
);
 
//
// Parameters
//
parameter divisor = 2;
input clk_i;
output clk_o;
 
 
`ifdef SPARTAN2
`define XILINX_DLL
`elsif VIRTEX
`define XILINX_DLL
`endif // !SPARTAN2/VIRTEX
 
`ifdef SPARTAN3
`define XILINX_DCM
`elsif VIRTEX2
`define XILINX_DCM
`endif // !SPARTAN3/VIRTEX2
 
`ifdef SPARTAN3E
`define XILINX_DCM_SP
`elsif SPARTAN3A
`define XILINX_DCM_SP
`endif // !SPARTAN3E/SPARTAN3A
 
`ifdef VIRTEX4
`define XILINX_DCM_ADV
`define XILINX_DCM_COMPONENT "VIRTEX4"
`elsif VIRTEX5
`define XILINX_DCM_ADV
`define XILINX_DCM_COMPONENT "VIRTEX5"
`endif // !VIRTEX4/VIRTEX5
 
 
wire CLKIN_IN;
wire CLKDV_OUT;
 
assign CLKIN_IN = clk_i;
assign clk_o = CLKDV_OUT;
 
wire CLKIN_IBUFG;
wire CLK0_BUF;
wire CLKFB_IN;
wire CLKDV_BUF;
 
IBUFG CLKIN_IBUFG_INST (
.I(CLKIN_IN),
.O(CLKIN_IBUFG)
);
 
BUFG CLK0_BUFG_INST (
.I(CLK0_BUF),
.O(CLKFB_IN)
);
 
BUFG CLKDV_BUFG_INST (
.I(CLKDV_BUF),
.O(CLKDV_OUT)
);
 
`ifdef XILINX_DLL
 
CLKDLL #(
.CLKDV_DIVIDE(divisor), // Divide by: 1.5,2.0,2.5,3.0,4.0,5.0,8.0 or 16.0
.DUTY_CYCLE_CORRECTION("TRUE"), // Duty cycle correction, TRUE or FALSE
.FACTORY_JF(16'hC080), // FACTORY JF Values
.STARTUP_WAIT("FALSE") // Delay config DONE until DLL LOCK, TRUE/FALSE
) CLKDLL_inst (
.CLK0(CLK0_BUF), // 0 degree DLL CLK output
.CLK180(), // 180 degree DLL CLK output
.CLK270(), // 270 degree DLL CLK output
.CLK2X(), // 2X DLL CLK output
.CLK90(), // 90 degree DLL CLK output
.CLKDV(CLKDV_BUF), // Divided DLL CLK out (CLKDV_DIVIDE)
.LOCKED(), // DLL LOCK status output
.CLKFB(CLKFB_IN), // DLL clock feedback
.CLKIN(CLKIN_IBUFG), // Clock input (from IBUFG, BUFG or DLL)
.RST(1'b0) // DLL asynchronous reset input
);
 
`elsif XILINX_DCM
 
DCM #(
.SIM_MODE("SAFE"), // Simulation: "SAFE" vs. "FAST", see "Synthesis and Simulation Design Guide" for details
.CLKDV_DIVIDE(divisor), // Divide by: 1.5,2.0,2.5,3.0,3.5,4.0,4.5,5.0,5.5,6.0,6.5
// 7.0,7.5,8.0,9.0,10.0,11.0,12.0,13.0,14.0,15.0 or 16.0
.CLKFX_DIVIDE(1), // Can be any integer from 1 to 32
.CLKFX_MULTIPLY(4), // Can be any integer from 2 to 32
.CLKIN_DIVIDE_BY_2("FALSE"), // TRUE/FALSE to enable CLKIN divide by two feature
.CLKIN_PERIOD(0.0), // Specify period of input clock
.CLKOUT_PHASE_SHIFT("NONE"), // Specify phase shift of NONE, FIXED or VARIABLE
.CLK_FEEDBACK("1X"), // Specify clock feedback of NONE, 1X or 2X
.DESKEW_ADJUST("SYSTEM_SYNCHRONOUS"), // SOURCE_SYNCHRONOUS, SYSTEM_SYNCHRONOUS or
// an integer from 0 to 15
.DFS_FREQUENCY_MODE("LOW"), // HIGH or LOW frequency mode for frequency synthesis
.DLL_FREQUENCY_MODE("LOW"), // HIGH or LOW frequency mode for DLL
.DUTY_CYCLE_CORRECTION("TRUE"), // Duty cycle correction, TRUE or FALSE
.FACTORY_JF(16'hC080), // FACTORY JF values
.PHASE_SHIFT(0), // Amount of fixed phase shift from -255 to 255
.STARTUP_WAIT("FALSE") // Delay configuration DONE until DCM LOCK, TRUE/FALSE
) DCM_inst (
.CLK0(CLK0_BUF), // 0 degree DCM CLK output
.CLK180(), // 180 degree DCM CLK output
.CLK270(), // 270 degree DCM CLK output
.CLK2X(), // 2X DCM CLK output
.CLK2X180(), // 2X, 180 degree DCM CLK out
.CLK90(), // 90 degree DCM CLK output
.CLKDV(CLKDV_BUF), // Divided DCM CLK out (CLKDV_DIVIDE)
.CLKFX(), // DCM CLK synthesis out (M/D)
.CLKFX180(), // 180 degree CLK synthesis out
.LOCKED(), // DCM LOCK status output
.PSDONE(), // Dynamic phase adjust done output
.STATUS(), // 8-bit DCM status bits output
.CLKFB(CLKFB_IN), // DCM clock feedback
.CLKIN(CLKIN_IBUFG), // Clock input (from IBUFG, BUFG or DCM)
.PSCLK(1'b0), // Dynamic phase adjust clock input
.PSEN(1'b0), // Dynamic phase adjust enable input
.PSINCDEC(1'b0), // Dynamic phase adjust increment/decrement
.RST(1'b0) // DCM asynchronous reset input
);
 
`elsif XILINX_DCM_SP
 
DCM_SP #(
.CLKDV_DIVIDE(divisor), // Divide by: 1.5,2.0,2.5,3.0,3.5,4.0,4.5,5.0,5.5,6.0,6.5
// 7.0,7.5,8.0,9.0,10.0,11.0,12.0,13.0,14.0,15.0 or 16.0
.CLKFX_DIVIDE(1), // Can be any integer from 1 to 32
.CLKFX_MULTIPLY(4), // Can be any integer from 2 to 32
.CLKIN_DIVIDE_BY_2("FALSE"), // TRUE/FALSE to enable CLKIN divide by two feature
.CLKIN_PERIOD(0.0), // Specify period of input clock
.CLKOUT_PHASE_SHIFT("NONE"), // Specify phase shift of NONE, FIXED or VARIABLE
.CLK_FEEDBACK("1X"), // Specify clock feedback of NONE, 1X or 2X
.DESKEW_ADJUST("SYSTEM_SYNCHRONOUS"), // SOURCE_SYNCHRONOUS, SYSTEM_SYNCHRONOUS or
// an integer from 0 to 15
.DLL_FREQUENCY_MODE("LOW"), // HIGH or LOW frequency mode for DLL
.DUTY_CYCLE_CORRECTION("TRUE"), // Duty cycle correction, TRUE or FALSE
.PHASE_SHIFT(0), // Amount of fixed phase shift from -255 to 255
.STARTUP_WAIT("FALSE") // Delay configuration DONE until DCM LOCK, TRUE/FALSE
) DCM_SP_inst (
.CLK0(CLK0_BUF), // 0 degree DCM CLK output
.CLK180(), // 180 degree DCM CLK output
.CLK270(), // 270 degree DCM CLK output
.CLK2X(), // 2X DCM CLK output
.CLK2X180(), // 2X, 180 degree DCM CLK out
.CLK90(), // 90 degree DCM CLK output
.CLKDV(CLKDV_BUF), // Divided DCM CLK out (CLKDV_DIVIDE)
.CLKFX(), // DCM CLK synthesis out (M/D)
.CLKFX180(), // 180 degree CLK synthesis out
.LOCKED(), // DCM LOCK status output
.PSDONE(), // Dynamic phase adjust done output
.STATUS(), // 8-bit DCM status bits output
.CLKFB(CLKFB_IN), // DCM clock feedback
.CLKIN(CLKIN_IBUFG), // Clock input (from IBUFG, BUFG or DCM)
.PSCLK(1'b0), // Dynamic phase adjust clock input
.PSEN(1'b0), // Dynamic phase adjust enable input
.PSINCDEC(1'b0), // Dynamic phase adjust increment/decrement
.RST(1'b0) // DCM asynchronous reset input
);
 
`elsif XILINX_DCM_ADV
 
DCM_ADV #(
.CLKDV_DIVIDE(divisor), // Divide by: 1.5,2.0,2.5,3.0,3.5,4.0,4.5,5.0,5.5,6.0,6.5
// 7.0,7.5,8.0,9.0,10.0,11.0,12.0,13.0,14.0,15.0 or 16.0
.CLKFX_DIVIDE(1), // Can be any integer from 1 to 32
.CLKFX_MULTIPLY(4), // Can be any integer from 2 to 32
.CLKIN_DIVIDE_BY_2("FALSE"), // TRUE/FALSE to enable CLKIN divide by two feature
.CLKIN_PERIOD(10.0), // Specify period of input clock in ns from 1.25 to 1000.00
.CLKOUT_PHASE_SHIFT("NONE"), // Specify phase shift mode of NONE, FIXED,
// VARIABLE_POSITIVE, VARIABLE_CENTER or DIRECT
.CLK_FEEDBACK("1X"), // Specify clock feedback of NONE, 1X or 2X
.DCM_AUTOCALIBRATION("TRUE"), // DCM calibration circuitry "TRUE"/"FALSE"
.DCM_PERFORMANCE_MODE("MAX_SPEED"), // Can be MAX_SPEED or MAX_RANGE
.DESKEW_ADJUST("SYSTEM_SYNCHRONOUS"), // SOURCE_SYNCHRONOUS, SYSTEM_SYNCHRONOUS or
// an integer from 0 to 15
.DFS_FREQUENCY_MODE("LOW"), // HIGH or LOW frequency mode for frequency synthesis
.DLL_FREQUENCY_MODE("LOW"), // LOW, HIGH, or HIGH_SER frequency mode for DLL
.DUTY_CYCLE_CORRECTION("TRUE"), // Duty cycle correction, "TRUE"/"FALSE"
.FACTORY_JF(16'hf0f0), // FACTORY JF value suggested to be set to 16’hf0f0
.PHASE_SHIFT(0), // Amount of fixed phase shift from -255 to 1023
.SIM_DEVICE(`XILINX_DCM_COMPONENT), // Set target device, "VIRTEX4" or "VIRTEX5"
.STARTUP_WAIT("FALSE") // Delay configuration DONE until DCM LOCK, "TRUE"/"FALSE"
) DCM_ADV_inst (
.CLK0(CLK0_BUF), // 0 degree DCM CLK output
.CLK180(), // 180 degree DCM CLK output
.CLK270(), // 270 degree DCM CLK output
.CLK2X(), // 2X DCM CLK output
.CLK2X180(), // 2X, 180 degree DCM CLK out
.CLK90(), // 90 degree DCM CLK output
.CLKDV(CLKDV_BUF), // Divided DCM CLK out (CLKDV_DIVIDE)
.CLKFX(), // DCM CLK synthesis out (M/D)
.CLKFX180(), // 180 degree CLK synthesis out
.DO(), // 16-bit data output for Dynamic Reconfiguration Port (DRP)
.DRDY(), // Ready output signal from the DRP
.LOCKED(), // DCM LOCK status output
.PSDONE(), // Dynamic phase adjust done output
.CLKFB(CLKFB_IN), // DCM clock feedback
.CLKIN(CLKIN_IBUFG), // Clock input (from IBUFG, BUFG or DCM)
.DADDR(7'h00), // 7-bit address for the DRP
.DCLK(1'b0), // Clock for the DRP
.DEN(1'b0), // Enable input for the DRP
.DI(16'h0000), // 16-bit data input for the DRP
.DWE(1'b0), // Active high allows for writing configuration memory
.PSCLK(1'b0), // Dynamic phase adjust clock input
.PSEN(1'b0), // Dynamic phase adjust enable input
.PSINCDEC(1'b0), // Dynamic phase adjust increment/decrement
.RST(1'b0) // DCM asynchronous reset input
);
 
`endif // !XILINX_DLL/XILINX_DCM/XILINX_DCM_SP/XILINX_DCM_ADV
 
 
endmodule
/verilog/altera_pll.v
0,0 → 1,155
 
`include "minsoc_defines.v"
 
module altera_pll (
inclk0,
c0);
 
parameter FREQ_MULT = 1;
parameter FREQ_DIV = 1;
 
input inclk0;
output c0;
 
 
`ifdef ARRIA_GX
localparam FAMILY = "Arria GX";
`elsif ARRIA_II_GX
localparam FAMILY = "Arria II GX";
`elsif CYCLONE_I
localparam FAMILY = "Cyclone I";
`elsif CYCLONE_II
localparam FAMILY = "Cyclone II";
`elsif CYCLONE_III
localparam FAMILY = "Cyclone III";
`elsif CYCLONE_III_LS
localparam FAMILY = "Cyclone III LS";
`elsif CYCLONE_IV_E
localparam FAMILY = "Cyclone IV E";
`elsif CYCLONE_IV_GS
localparam FAMILY = "Cyclone IV GS";
`elsif MAX_II
localparam FAMILY = "MAX II";
`elsif MAX_V
localparam FAMILY = "MAX V";
`elsif MAX3000A
localparam FAMILY = "MAX3000A";
`elsif MAX7000AE
localparam FAMILY = "MAX7000AE";
`elsif MAX7000B
localparam FAMILY = "MAX7000B";
`elsif MAX7000S
localparam FAMILY = "MAX7000S";
`elsif STRATIX
localparam FAMILY = "Stratix";
`elsif STRATIX_II
defapram systemPll.FAMILY = "Stratix II";
`elsif STRATIX_II_GX
localparam FAMILY = "Stratix II GX";
`elsif STRATIX_III
localparam FAMILY = "Stratix III"
`endif
 
 
wire [4:0] sub_wire0;
wire [0:0] sub_wire4 = 1'h0;
wire [0:0] sub_wire1 = sub_wire0[0:0];
wire c0 = sub_wire1;
wire sub_wire2 = inclk0;
wire [1:0] sub_wire3 = {sub_wire4, sub_wire2};
 
altpll altpll_component (
.inclk (sub_wire3),
.clk (sub_wire0),
.activeclock (),
.areset (1'b0),
.clkbad (),
.clkena ({6{1'b1}}),
.clkloss (),
.clkswitch (1'b0),
.configupdate (1'b0),
.enable0 (),
.enable1 (),
.extclk (),
.extclkena ({4{1'b1}}),
.fbin (1'b1),
.fbmimicbidir (),
.fbout (),
.fref (),
.icdrclk (),
.locked (),
.pfdena (1'b1),
.phasecounterselect ({4{1'b1}}),
.phasedone (),
.phasestep (1'b1),
.phaseupdown (1'b1),
.pllena (1'b1),
.scanaclr (1'b0),
.scanclk (1'b0),
.scanclkena (1'b1),
.scandata (1'b0),
.scandataout (),
.scandone (),
.scanread (1'b0),
.scanwrite (1'b0),
.sclkout0 (),
.sclkout1 (),
.vcooverrange (),
.vcounderrange ());
defparam
altpll_component.bandwidth_type = "AUTO",
altpll_component.clk0_divide_by = FREQ_DIV,
altpll_component.clk0_duty_cycle = 50,
altpll_component.clk0_multiply_by = FREQ_MULT,
altpll_component.clk0_phase_shift = "0",
altpll_component.compensate_clock = "CLK0",
altpll_component.inclk0_input_frequency = 20000,
altpll_component.intended_device_family = FAMILY,
altpll_component.lpm_hint = "CBX_MODULE_PREFIX=minsocPll",
altpll_component.lpm_type = "altpll",
altpll_component.operation_mode = "NORMAL",
altpll_component.pll_type = "AUTO",
altpll_component.port_activeclock = "PORT_UNUSED",
altpll_component.port_areset = "PORT_UNUSED",
altpll_component.port_clkbad0 = "PORT_UNUSED",
altpll_component.port_clkbad1 = "PORT_UNUSED",
altpll_component.port_clkloss = "PORT_UNUSED",
altpll_component.port_clkswitch = "PORT_UNUSED",
altpll_component.port_configupdate = "PORT_UNUSED",
altpll_component.port_fbin = "PORT_UNUSED",
altpll_component.port_inclk0 = "PORT_USED",
altpll_component.port_inclk1 = "PORT_UNUSED",
altpll_component.port_locked = "PORT_UNUSED",
altpll_component.port_pfdena = "PORT_UNUSED",
altpll_component.port_phasecounterselect = "PORT_UNUSED",
altpll_component.port_phasedone = "PORT_UNUSED",
altpll_component.port_phasestep = "PORT_UNUSED",
altpll_component.port_phaseupdown = "PORT_UNUSED",
altpll_component.port_pllena = "PORT_UNUSED",
altpll_component.port_scanaclr = "PORT_UNUSED",
altpll_component.port_scanclk = "PORT_UNUSED",
altpll_component.port_scanclkena = "PORT_UNUSED",
altpll_component.port_scandata = "PORT_UNUSED",
altpll_component.port_scandataout = "PORT_UNUSED",
altpll_component.port_scandone = "PORT_UNUSED",
altpll_component.port_scanread = "PORT_UNUSED",
altpll_component.port_scanwrite = "PORT_UNUSED",
altpll_component.port_clk0 = "PORT_USED",
altpll_component.port_clk1 = "PORT_UNUSED",
altpll_component.port_clk2 = "PORT_UNUSED",
altpll_component.port_clk3 = "PORT_UNUSED",
altpll_component.port_clk4 = "PORT_UNUSED",
altpll_component.port_clk5 = "PORT_UNUSED",
altpll_component.port_clkena0 = "PORT_UNUSED",
altpll_component.port_clkena1 = "PORT_UNUSED",
altpll_component.port_clkena2 = "PORT_UNUSED",
altpll_component.port_clkena3 = "PORT_UNUSED",
altpll_component.port_clkena4 = "PORT_UNUSED",
altpll_component.port_clkena5 = "PORT_UNUSED",
altpll_component.port_extclk0 = "PORT_UNUSED",
altpll_component.port_extclk1 = "PORT_UNUSED",
altpll_component.port_extclk2 = "PORT_UNUSED",
altpll_component.port_extclk3 = "PORT_UNUSED",
altpll_component.width_clock = 5;
endmodule
 

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