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URL https://opencores.org/ocsvn/minsoc/minsoc/trunk

Subversion Repositories minsoc

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  • This comparison shows the changes necessary to convert path
    /minsoc/trunk/rtl
    from Rev 62 to Rev 63
    Reverse comparison

Rev 62 → Rev 63

/verilog/altera_pll.v
58,6 → 58,7
wire sub_wire2 = inclk0;
wire [1:0] sub_wire3 = {sub_wire4, sub_wire2};
 
`ifdef ALTERA_FPGA
altpll altpll_component (
.inclk (sub_wire3),
.clk (sub_wire0),
151,5 → 152,7
altpll_component.port_extclk2 = "PORT_UNUSED",
altpll_component.port_extclk3 = "PORT_UNUSED",
altpll_component.width_clock = 5;
`endif
 
endmodule
 
/verilog/minsoc_defines.v
81,8 → 81,8
//
// Reset polarity
//
`define NEGATIVE_RESET //rstn
//`define POSITIVE_RESET //rst
//`define NEGATIVE_RESET //rstn
`define POSITIVE_RESET //rst
 
//
// Start-up circuit (only necessary later to load firmware automatically from SPI memory)

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