OpenCores
URL https://opencores.org/ocsvn/minsoc/minsoc/trunk

Subversion Repositories minsoc

Compare Revisions

  • This comparison shows the changes necessary to convert path
    /minsoc/trunk/sim
    from Rev 60 to Rev 64
    Reverse comparison

Rev 60 → Rev 64

/bin/minsoc_verilog_files.txt
1,3 → 1,4
+incdir+../../backend
+incdir+../../bench/verilog
+incdir+../../bench/verilog/vpi
+incdir+../../bench/verilog/sim_lib
9,6 → 10,7
+incdir+../../rtl/verilog/adv_debug_sys/Software/adv_jtag_bridge/sim_rtl
+incdir+../../rtl/verilog/uart16550/rtl/verilog
+incdir+../../rtl/verilog/ethmac/rtl/verilog
../../backend/minsoc_defines.v
../../bench/verilog/minsoc_bench_defines.v
../../bench/verilog/minsoc_bench.v
../../bench/verilog/minsoc_memory_model.v
24,7 → 26,6
../../rtl/verilog/minsoc_onchip_ram.v
../../rtl/verilog/minsoc_clock_manager.v
../../rtl/verilog/minsoc_onchip_ram_top.v
../../rtl/verilog/minsoc_defines.v
../../rtl/verilog/or1200/rtl/verilog/or1200_spram_512x20.v
../../rtl/verilog/or1200/rtl/verilog/or1200_spram_64x24.v
../../rtl/verilog/or1200/rtl/verilog/or1200_du.v

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