URL
https://opencores.org/ocsvn/minsoc/minsoc/trunk
Subversion Repositories minsoc
Compare Revisions
- This comparison shows the changes necessary to convert path
/minsoc/trunk/sim
- from Rev 70 to Rev 69
- ↔ Reverse comparison
Rev 70 → Rev 69
/modelsim/compile_design.sh
File deleted
\ No newline at end of file
modelsim/compile_design.sh
Property changes :
Deleted: svn:executable
## -1 +0,0 ##
-*
\ No newline at end of property
Index: modelsim/prepare_modelsim.sh
===================================================================
--- modelsim/prepare_modelsim.sh (revision 70)
+++ modelsim/prepare_modelsim.sh (nonexistent)
@@ -1,4 +0,0 @@
-#!/bin/bash
-
-vlib minsoc
-vmap minsoc ./minsoc
modelsim/prepare_modelsim.sh
Property changes :
Deleted: svn:executable
## -1 +0,0 ##
-*
\ No newline at end of property
Index: modelsim/run_sim.sh
===================================================================
--- modelsim/run_sim.sh (revision 70)
+++ modelsim/run_sim.sh (nonexistent)
@@ -1,3 +0,0 @@
-#!/bin/bash
-
-vsim -lib minsoc minsoc_bench -pli ../../bench/verilog/vpi/jp-io-vpi.so +file_name=$1
modelsim/run_sim.sh
Property changes :
Deleted: svn:executable
## -1 +0,0 ##
-*
\ No newline at end of property
Index: bin/minsoc_verilog_files.txt
===================================================================
--- bin/minsoc_verilog_files.txt (revision 70)
+++ bin/minsoc_verilog_files.txt (revision 69)
@@ -16,7 +16,6 @@
../../bench/verilog/minsoc_memory_model.v
../../bench/verilog/vpi/dbg_comm_vpi.v
../../bench/verilog/sim_lib/fpga_memory_primitives.v
-../../rtl/verilog/timescale.v
../../rtl/verilog/minsoc_top.v
../../rtl/verilog/minsoc_startup/spi_top.v
../../rtl/verilog/minsoc_startup/spi_defines.v