URL
https://opencores.org/ocsvn/minsoc/minsoc/trunk
Subversion Repositories minsoc
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- This comparison shows the changes necessary to convert path
/minsoc/trunk
- from Rev 11 to Rev 12
- ↔ Reverse comparison
Rev 11 → Rev 12
/rtl/verilog/minsoc_startup/spi_top.v
165,7 → 165,7
`ifdef SPI_CTRL_TX_NEGEDGE |
assign tx_negedge = 1'b1; |
`else |
assign tx_negedge = 1'b1; |
assign tx_negedge = 1'b0; |
`endif |
|
assign ctrl = {ass,1'b0,lsb,tx_negedge,rx_negedge,go,1'b0,1'b0,char_len}; |
/doc/minsoc.pdf
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/doc/minsoc.odt
Cannot display: file marked as a binary type.
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/backend/spartan3e_starter_kit.ucf
1,50 → 1,50
# |
# Soldered 50MHz clock. |
# |
NET "clk" LOC = "C9" | IOSTANDARD = LVTTL; |
NET "clk" LOC = "C9"; |
|
# |
# Use button "south" as reset. |
# |
NET "reset" LOC = "K17" | IOSTANDARD = LVTTL | PULLDOWN ; |
NET "reset" LOC = "K17" | PULLDOWN ; |
|
# |
# UART serial port (RS232 DCE) - connector DB9 female. |
# |
NET "uart_srx" LOC = "R7" | IOSTANDARD = LVTTL ; |
NET "uart_stx" LOC = "M14" | IOSTANDARD = LVTTL | DRIVE = 8 | SLEW = SLOW ; |
#NET "uart_srx" LOC = "R7" | IOSTANDARD = LVTTL ; |
#NET "uart_stx" LOC = "M14" | IOSTANDARD = LVTTL | DRIVE = 8 | SLEW = SLOW ; |
|
########################### |
## |
## ETH |
## |
#NET "eth_txd(3)" LOC = "t5"; |
#NET "eth_txd(2)" LOC = "r5"; |
#NET "eth_txd(1)" LOC = "t15"; |
#NET "eth_txd(0)" LOC = "r11"; |
# |
#NET "eth_tx_en" LOC = "p15"; |
#NET "eth_tx_clk" LOC = "t7"; |
#NET "eth_tx_er" LOC = "r6"; |
# |
#NET "eth_rxd(3)" LOC = "v14"; |
#NET "eth_rxd(2)" LOC = "u11"; |
#NET "eth_rxd(1)" LOC = "t11"; |
#NET "eth_rxd(0)" LOC = "v8"; |
# |
#NET "eth_rx_er" LOC = "u14"; |
#NET "eth_rx_dv" LOC = "v2"; |
# |
#NET "eth_rx_clk" LOC = "v3"; |
# |
#NET "eth_mdio" LOC = "u5" | PULLUP; |
#NET "eth_crs" LOC = "u13"; |
#NET "eth_col" LOC = "u6"; |
#NET "eth_mdc" LOC = "p9"; |
# |
#NET "eth_trste" LOC = "n2"; #put it to a non connected FPGA pin (starter kit schematic BANK3) |
# |
#NET "eth_fds_mdint" LOC = "n1" | PULLUP; #put it to a non connected FPGA pin (starter kit schematic BANK3)(pullup not to generate interrupts) |
NET "eth_txd(3)" LOC = "t5"; |
NET "eth_txd(2)" LOC = "r5"; |
NET "eth_txd(1)" LOC = "t15"; |
NET "eth_txd(0)" LOC = "r11"; |
|
NET "eth_tx_en" LOC = "p15"; |
NET "eth_tx_clk" LOC = "t7" | CLOCK_DEDICATED_ROUTE = FALSE; |
NET "eth_tx_er" LOC = "r6"; |
|
NET "eth_rxd(3)" LOC = "v14"; |
NET "eth_rxd(2)" LOC = "u11"; |
NET "eth_rxd(1)" LOC = "t11"; |
NET "eth_rxd(0)" LOC = "v8"; |
|
NET "eth_rx_er" LOC = "u14"; |
NET "eth_rx_dv" LOC = "v2"; |
|
NET "eth_rx_clk" LOC = "v3" | CLOCK_DEDICATED_ROUTE = FALSE; |
|
NET "eth_mdio" LOC = "u5" | PULLUP; |
NET "eth_crs" LOC = "u13"; |
NET "eth_col" LOC = "u6"; |
NET "eth_mdc" LOC = "p9"; |
|
NET "eth_trste" LOC = "p13"; #put it to a non connected FPGA pin (starter kit schematic BANK3) |
|
NET "eth_fds_mdint" LOC = "r13" | PULLUP; #put it to a non connected FPGA pin (starter kit schematic BANK3)(pullup not to generate interrupts) |
########################### |
|
# |