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    /minsoc/trunk
    from Rev 26 to Rev 27
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Rev 26 → Rev 27

/bench/verilog/sim_lib/fpga_memory_primitives.v
13,7 → 13,11
 
parameter lpm_width = 8;
parameter lpm_widthad = 11;
 
parameter lpm_indata = "REGISTERED"; //This 4 parameters are included only to avoid warnings
parameter lpm_address_control = "REGISTERED"; //they are not accessed inside the module. OR1200 uses this
parameter lpm_outdata = "UNREGISTERED"; //configuration set on all its instantiations, so this is fine.
parameter lpm_hint = "USE_EAB=ON"; //It may not be fine, if you are adding this library to your
//own system, which uses this module with another configuration.
localparam dw = lpm_width;
localparam aw = lpm_widthad;
 
30,7 → 34,7
//
// Data output drivers
//
assign doq = mem[addr_reg];
assign q = mem[addr_reg];
 
//
// RAM address register

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