URL
https://opencores.org/ocsvn/minsoc/minsoc/trunk
Subversion Repositories minsoc
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- This comparison shows the changes necessary to convert path
/minsoc/trunk
- from Rev 50 to Rev 49
- ↔ Reverse comparison
Rev 50 → Rev 49
/sw/support/reset.S
1,6 → 1,7
/* Support file for c based tests */ |
#include "spr_defs.h" |
#include "board.h" |
#include "mc.h" |
|
.section .stack |
.space STACK_SIZE |
/sw/support/except.S
11,79 → 11,217
l.j _reset_except |
l.nop |
*/ |
.org 0x000 |
|
_except_200: |
l.nop |
l.addi r1,r1,-244 //free 29 words (29 x 4 = 112) + 4 because stack points to contained data (stack is r1) |
//plus 128 bytes not to mess with the previous frame pointer (32 register x 4 bytes = 128 bytes ) (required by C++ multiple threading) |
l.sw 0x18(r1),r9 //save register r9(return addr) to stack |
l.jal store_regs //save registers r3-r31 (except r9) to stack (r9 is changed here) |
l.nop |
|
/* This cannot be a regular function because it would waste the return register r9 of the interrupted procedure. */ |
/* Furthermore, if this would be a function and l.j handler would be outside of this, the return register set here would be use upon return of this function. */ |
/* However, the desired behavior is to finish the handler and let the return of the service routine simply restore the registers and return to the interrupted procedure. */ |
#define intr_handler(handler) \ |
l.nop ;\ |
l.addi r1,r1,-244 /*free 29 words (29 x 4 = 112) + 4 because stack points to contained data (stack is r1)*/;\ |
/*plus 128 bytes not to mess with the previous frame pointer (32 register x 4 bytes = 128 bytes ) (required by C++ multiple threading) */;\ |
l.sw 0x18(r1),r9 /*save register r9(return addr) to stack*/;\ |
l.jal store_regs /*save registers r3-r31 (except r9) to stack (r9 is changed here)*/;\ |
l.nop ;\ |
;\ |
l.movhi r9,hi(end_except) /*set return addr to end_except instruction*/;\ |
l.ori r9,r9,lo(end_except)/*set return addr to end_except instruction*/;\ |
l.j handler ;\ |
l.movhi r9,hi(end_except) //set return addr to end_except instruction |
l.ori r9,r9,lo(end_except) //set return addr to end_except instruction |
l.j buserr_except |
l.nop |
|
.org 0x000 |
_except_200: |
intr_handler(buserr_except) |
|
.org 0x100 |
|
_except_300: |
intr_handler(dpf_except) |
l.nop |
l.addi r1,r1,-244 //free 29 words (29 x 4 = 112) + 4 because stack points to contained data (stack is r1) |
//plus 128 bytes not to mess with the previous frame pointer (32 register x 4 bytes = 128 bytes ) (required by C++ multiple threading) |
l.sw 0x18(r1),r9 //save register r9(return addr) to stack |
l.jal store_regs //save registers r3-r31 (except r9) to stack (r9 is changed here) |
l.nop |
|
l.movhi r9,hi(end_except) //set return addr to end_except instruction |
l.ori r9,r9,lo(end_except) //set return addr to end_except instruction |
l.j dpf_except |
l.nop |
|
.org 0x200 |
|
_except_400: |
intr_handler(ipf_except) |
l.nop |
l.addi r1,r1,-244 //free 29 words (29 x 4 = 112) + 4 because stack points to contained data (stack is r1) |
//plus 128 bytes not to mess with the previous frame pointer (32 register x 4 bytes = 128 bytes ) (required by C++ multiple threading) |
l.sw 0x18(r1),r9 //save register r9(return addr) to stack |
l.jal store_regs //save registers r3-r31 (except r9) to stack (r9 is changed here) |
l.nop |
|
l.movhi r9,hi(end_except) //set return addr to end_except instruction |
l.ori r9,r9,lo(end_except) //set return addr to end_except instruction |
l.j ipf_except |
l.nop |
|
.org 0x300 |
|
_except_500: |
intr_handler(tick_except) |
l.nop |
l.addi r1,r1,-244 //free 29 words (29 x 4 = 112) + 4 because stack points to contained data (stack is r1) |
//plus 128 bytes not to mess with the previous frame pointer (32 register x 4 bytes = 128 bytes ) (required by C++ multiple threading) |
l.sw 0x18(r1),r9 //save register r9(return addr) to stack |
l.jal store_regs //save registers r3-r31 (except r9) to stack (r9 is changed here) |
l.nop |
|
l.movhi r9,hi(end_except) //set return addr to end_except instruction |
l.ori r9,r9,lo(end_except) //set return addr to end_except instruction |
l.j tick_except |
l.nop |
|
.org 0x400 |
|
_except_600: |
intr_handler(align_except) |
l.nop |
l.addi r1,r1,-244 //free 29 words (29 x 4 = 112) + 4 because stack points to contained data (stack is r1) |
//plus 128 bytes not to mess with the previous frame pointer (32 register x 4 bytes = 128 bytes ) (required by C++ multiple threading) |
l.sw 0x18(r1),r9 //save register r9(return addr) to stack |
l.jal store_regs //save registers r3-r31 (except r9) to stack (r9 is changed here) |
l.nop |
|
l.movhi r9,hi(end_except) //set return addr to end_except instruction |
l.ori r9,r9,lo(end_except) //set return addr to end_except instruction |
l.j align_except |
l.nop |
|
.org 0x500 |
|
_except_700: |
intr_handler(illegal_except) |
l.nop |
l.addi r1,r1,-244 //free 29 words (29 x 4 = 112) + 4 because stack points to contained data (stack is r1) |
//plus 128 bytes not to mess with the previous frame pointer (32 register x 4 bytes = 128 bytes ) (required by C++ multiple threading) |
l.sw 0x18(r1),r9 //save register r9(return addr) to stack |
l.jal store_regs //save registers r3-r31 (except r9) to stack (r9 is changed here) |
l.nop |
|
l.movhi r9,hi(end_except) //set return addr to end_except instruction |
l.ori r9,r9,lo(end_except) //set return addr to end_except instruction |
l.j illegal_except |
l.nop |
|
.org 0x600 |
|
_except_800: |
intr_handler(ext_except) |
l.nop |
l.addi r1,r1,-244 //free 29 words (29 x 4 = 112) + 4 because stack points to contained data (stack is r1) |
//plus 128 bytes not to mess with the previous frame pointer (32 register x 4 bytes = 128 bytes ) (required by C++ multiple threading) |
l.sw 0x18(r1),r9 //save register r9(return addr) to stack |
l.jal store_regs //save registers r3-r31 (except r9) to stack (r9 is changed here) |
l.nop |
|
l.movhi r9,hi(end_except) //set return addr to end_except instruction |
l.ori r9,r9,lo(end_except) //set return addr to end_except instruction |
l.j ext_except //jmp to C interrupt handler (returns later to end_except) |
l.nop |
|
|
.org 0x700 |
|
_except_900: |
intr_handler(dtlbmiss_except) |
l.nop |
l.addi r1,r1,-244 //free 29 words (29 x 4 = 112) + 4 because stack points to contained data (stack is r1) |
//plus 128 bytes not to mess with the previous frame pointer (32 register x 4 bytes = 128 bytes ) (required by C++ multiple threading) |
l.sw 0x18(r1),r9 //save register r9(return addr) to stack |
l.jal store_regs //save registers r3-r31 (except r9) to stack (r9 is changed here) |
l.nop |
|
l.movhi r9,hi(end_except) //set return addr to end_except instruction |
l.ori r9,r9,lo(end_except) //set return addr to end_except instruction |
l.j dtlbmiss_except |
l.nop |
|
.org 0x800 |
|
_except_a00: |
intr_handler(itlbmiss_except) |
l.nop |
l.addi r1,r1,-244 //free 29 words (29 x 4 = 112) + 4 because stack points to contained data (stack is r1) |
//plus 128 bytes not to mess with the previous frame pointer (32 register x 4 bytes = 128 bytes ) (required by C++ multiple threading) |
l.sw 0x18(r1),r9 //save register r9(return addr) to stack |
l.jal store_regs //save registers r3-r31 (except r9) to stack (r9 is changed here) |
l.nop |
|
l.movhi r9,hi(end_except) //set return addr to end_except instruction |
l.ori r9,r9,lo(end_except) //set return addr to end_except instruction |
l.j itlbmiss_except |
l.nop |
|
.org 0x900 |
|
_except_b00: |
intr_handler(range_except) |
l.nop |
l.addi r1,r1,-244 //free 29 words (29 x 4 = 112) + 4 because stack points to contained data (stack is r1) |
//plus 128 bytes not to mess with the previous frame pointer (32 register x 4 bytes = 128 bytes ) (required by C++ multiple threading) |
l.sw 0x18(r1),r9 //save register r9(return addr) to stack |
l.jal store_regs //save registers r3-r31 (except r9) to stack (r9 is changed here) |
l.nop |
|
l.movhi r9,hi(end_except) //set return addr to end_except instruction |
l.ori r9,r9,lo(end_except) //set return addr to end_except instruction |
l.j range_except |
l.nop |
|
.org 0xa00 |
|
_except_c00: |
intr_handler(syscall_except) |
l.nop |
l.addi r1,r1,-244 //free 29 words (29 x 4 = 112) + 4 because stack points to contained data (stack is r1) |
//plus 128 bytes not to mess with the previous frame pointer (32 register x 4 bytes = 128 bytes ) (required by C++ multiple threading) |
l.sw 0x18(r1),r9 //save register r9(return addr) to stack |
l.jal store_regs //save registers r3-r31 (except r9) to stack (r9 is changed here) |
l.nop |
|
l.movhi r9,hi(end_except) //set return addr to end_except instruction |
l.ori r9,r9,lo(end_except) //set return addr to end_except instruction |
l.j syscall_except |
l.nop |
|
.org 0xb00 |
|
_except_d00: |
intr_handler(res1_except) |
l.nop |
l.addi r1,r1,-244 //free 29 words (29 x 4 = 112) + 4 because stack points to contained data (stack is r1) |
//plus 128 bytes not to mess with the previous frame pointer (32 register x 4 bytes = 128 bytes ) (required by C++ multiple threading) |
l.sw 0x18(r1),r9 //save register r9(return addr) to stack |
l.jal store_regs //save registers r3-r31 (except r9) to stack (r9 is changed here) |
l.nop |
|
l.movhi r9,hi(end_except) //set return addr to end_except instruction |
l.ori r9,r9,lo(end_except) //set return addr to end_except instruction |
l.j res1_except |
l.nop |
|
.org 0xc00 |
|
_except_e00: |
intr_handler(trap_except) |
l.nop |
l.addi r1,r1,-244 //free 29 words (29 x 4 = 112) + 4 because stack points to contained data (stack is r1) |
//plus 128 bytes not to mess with the previous frame pointer (32 register x 4 bytes = 128 bytes ) (required by C++ multiple threading) |
l.sw 0x18(r1),r9 //save register r9(return addr) to stack |
l.jal store_regs //save registers r3-r31 (except r9) to stack (r9 is changed here) |
l.nop |
|
l.movhi r9,hi(end_except) //set return addr to end_except instruction |
l.ori r9,r9,lo(end_except) //set return addr to end_except instruction |
l.j trap_except |
l.nop |
|
.org 0xd00 |
|
_except_f00: |
intr_handler(res2_except) |
l.nop |
l.addi r1,r1,-244 //free 29 words (29 x 4 = 112) + 4 because stack points to contained data (stack is r1) |
//plus 128 bytes not to mess with the previous frame pointer (32 register x 4 bytes = 128 bytes ) (required by C++ multiple threading) |
l.sw 0x18(r1),r9 //save register r9(return addr) to stack |
l.jal store_regs //save registers r3-r31 (except r9) to stack (r9 is changed here) |
l.nop |
|
l.movhi r9,hi(end_except) //set return addr to end_except instruction |
l.ori r9,r9,lo(end_except) //set return addr to end_except instruction |
l.j res2_except |
l.nop |
|
store_regs: //save registers r3-r31 (except r9) to stack |
l.sw 0x00(r1),r3 |
l.sw 0x04(r1),r4 |
/sw/support/mc.h
0,0 → 1,111
/* mc.h -- Simulation of Memory Controller |
Copyright (C) 2001 by Marko Mlinar, markom@opencores.org |
|
This file is part of OpenRISC 1000 Architectural Simulator. |
|
This program is free software; you can redistribute it and/or modify |
it under the terms of the GNU General Public License as published by |
the Free Software Foundation; either version 2 of the License, or |
(at your option) any later version. |
|
This program is distributed in the hope that it will be useful, |
but WITHOUT ANY WARRANTY; without even the implied warranty of |
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
GNU General Public License for more details. |
|
You should have received a copy of the GNU General Public License |
along with this program; if not, write to the Free Software |
Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. |
*/ |
|
/* Prototypes */ |
#ifndef __MC_H |
#define __MC_H |
|
#define N_CE (8) |
|
#define MC_CSR (0x00) |
#define MC_POC (0x04) |
#define MC_BA_MASK (0x08) |
#define MC_CSC(i) (0x10 + (i) * 8) |
#define MC_TMS(i) (0x14 + (i) * 8) |
|
#define MC_ADDR_SPACE (MC_CSC(N_CE)) |
|
/* POC register field definition */ |
#define MC_POC_EN_BW_OFFSET 0 |
#define MC_POC_EN_BW_WIDTH 2 |
#define MC_POC_EN_MEMTYPE_OFFSET 2 |
#define MC_POC_EN_MEMTYPE_WIDTH 2 |
|
/* CSC register field definition */ |
#define MC_CSC_EN_OFFSET 0 |
#define MC_CSC_MEMTYPE_OFFSET 1 |
#define MC_CSC_MEMTYPE_WIDTH 2 |
#define MC_CSC_BW_OFFSET 4 |
#define MC_CSC_BW_WIDTH 2 |
#define MC_CSC_MS_OFFSET 6 |
#define MC_CSC_MS_WIDTH 2 |
#define MC_CSC_WP_OFFSET 8 |
#define MC_CSC_BAS_OFFSET 9 |
#define MC_CSC_KRO_OFFSET 10 |
#define MC_CSC_PEN_OFFSET 11 |
#define MC_CSC_SEL_OFFSET 16 |
#define MC_CSC_SEL_WIDTH 8 |
|
#define MC_CSC_MEMTYPE_SDRAM 0 |
#define MC_CSC_MEMTYPE_SSRAM 1 |
#define MC_CSC_MEMTYPE_ASYNC 2 |
#define MC_CSC_MEMTYPE_SYNC 3 |
|
#define MC_CSR_VALID 0xFF000703LU |
#define MC_POC_VALID 0x0000000FLU |
#define MC_BA_MASK_VALID 0x000000FFLU |
#define MC_CSC_VALID 0x00FF0FFFLU |
#define MC_TMS_SDRAM_VALID 0x0FFF83FFLU |
#define MC_TMS_SSRAM_VALID 0x00000000LU |
#define MC_TMS_ASYNC_VALID 0x03FFFFFFLU |
#define MC_TMS_SYNC_VALID 0x01FFFFFFLU |
#define MC_TMS_VALID 0xFFFFFFFFLU /* reg test compat. */ |
|
/* TMS register field definition SDRAM */ |
#define MC_TMS_SDRAM_TRFC_OFFSET 24 |
#define MC_TMS_SDRAM_TRFC_WIDTH 4 |
#define MC_TMS_SDRAM_TRP_OFFSET 20 |
#define MC_TMS_SDRAM_TRP_WIDTH 4 |
#define MC_TMS_SDRAM_TRCD_OFFSET 17 |
#define MC_TMS_SDRAM_TRCD_WIDTH 4 |
#define MC_TMS_SDRAM_TWR_OFFSET 15 |
#define MC_TMS_SDRAM_TWR_WIDTH 2 |
#define MC_TMS_SDRAM_WBL_OFFSET 9 |
#define MC_TMS_SDRAM_OM_OFFSET 7 |
#define MC_TMS_SDRAM_OM_WIDTH 2 |
#define MC_TMS_SDRAM_CL_OFFSET 4 |
#define MC_TMS_SDRAM_CL_WIDTH 3 |
#define MC_TMS_SDRAM_BT_OFFSET 3 |
#define MC_TMS_SDRAM_BL_OFFSET 0 |
#define MC_TMS_SDRAM_BL_WIDTH 3 |
|
/* TMS register field definition ASYNC */ |
#define MC_TMS_ASYNC_TWWD_OFFSET 20 |
#define MC_TMS_ASYNC_TWWD_WIDTH 6 |
#define MC_TMS_ASYNC_TWD_OFFSET 16 |
#define MC_TMS_ASYNC_TWD_WIDTH 4 |
#define MC_TMS_ASYNC_TWPW_OFFSET 12 |
#define MC_TMS_ASYNC_TWPW_WIDTH 4 |
#define MC_TMS_ASYNC_TRDZ_OFFSET 8 |
#define MC_TMS_ASYNC_TRDZ_WIDTH 4 |
#define MC_TMS_ASYNC_TRDV_OFFSET 0 |
#define MC_TMS_ASYNC_TRDV_WIDTH 8 |
|
/* TMS register field definition SYNC */ |
#define MC_TMS_SYNC_TTO_OFFSET 16 |
#define MC_TMS_SYNC_TTO_WIDTH 9 |
#define MC_TMS_SYNC_TWR_OFFSET 12 |
#define MC_TMS_SYNC_TWR_WIDTH 4 |
#define MC_TMS_SYNC_TRDZ_OFFSET 8 |
#define MC_TMS_SYNC_TRDZ_WIDTH 4 |
#define MC_TMS_SYNC_TRDV_OFFSET 0 |
#define MC_TMS_SYNC_TRDV_WIDTH 8 |
|
#endif |
sw/support/mc.h
Property changes :
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Index: sw/support/orp.cfg
===================================================================
--- sw/support/orp.cfg (nonexistent)
+++ sw/support/orp.cfg (revision 49)
@@ -0,0 +1,901 @@
+/* sim.cfg -- Simulator configuration script file
+ Copyright (C) 2001-2002, Marko Mlinar, markom@opencores.org
+
+This file is part of OpenRISC 1000 Architectural Simulator.
+It contains the default configuration and help about configuring
+the simulator.
+
+This program is free software; you can redistribute it and/or modify
+it under the terms of the GNU General Public License as published by
+the Free Software Foundation; either version 2 of the License, or
+(at your option) any later version.
+
+This program is distributed in the hope that it will be useful,
+but WITHOUT ANY WARRANTY; without even the implied warranty of
+MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+GNU General Public License for more details.
+
+You should have received a copy of the GNU General Public License
+along with this program; if not, write to the Free Software
+Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. */
+
+
+/* INTRODUCTION
+
+ The ork1sim has various parameters, that are set in configuration files
+ like this one. The user can switch between configurations at startup by
+ specifying the required configuration file with the -f option.
+ If no configuration file is specified or1ksim searches for the default
+ configuration file sim.cfg. First it searches for './sim.cfg'. If this
+ file is not found, it searches for '~/or1k/sim.cfg'. If this file is
+ not found too, it reverts to the built-in default configuration.
+
+ NOTE: Users should not rely on the built-in configuration, since the
+ default configuration may differ between version.
+ Rather create a configuration file that sets all critical values.
+
+ This file may contain (standard C) comments only - no // support.
+
+ Configure files may be be included, using:
+ include "file_name_to_include"
+
+ Like normal configuration files, the included file is divided into
+ sections. Each section is described in detail also.
+
+ Some section have subsections. One example of such a subsection is:
+
+ device
+ instance specific parameters...
+ enddevice
+
+ which creates a device instance.
+*/
+
+
+/* MEMORY SECTION
+
+ This section specifies how the memory is generated and the blocks
+ it consists of.
+
+ type = random/unknown/pattern
+ Specifies the initial memory values.
+ 'random' generates random memory using seed 'random_seed'.
+ 'pattern' fills memory with 'pattern'.
+ 'unknown' does not specify how memory should be generated,
+ leaving the memory in a undefined state. This is the fastest
+ option.
+
+ random_seed =
+ random seed for randomizer, used if type = 'random'.
+
+ pattern =
+ pattern to fill memory, used if type = 'pattern'.
+
+ nmemories =
+ number of memory instances connected
+
+ baseaddr =
+ memory start address
+
+ size =
+ memory size
+
+ name = ""
+ memory block name
+
+ ce =
+ chip enable index of the memory instance
+
+ mc =
+ memory controller this memory is connected to
+
+ delayr =
+ cycles, required for read access, -1 if instance does not support reading
+
+ delayw =
+ cycles, required for write access, -1 if instance does not support writing
+
+ log = ""
+ filename, where to log memory accesses to, no log, if log command is not specified
+*/
+
+
+section memory
+ /*random_seed = 12345
+ type = random*/
+ pattern = 0x00
+ type = unknown /* Fastest */
+
+ name = "FLASH"
+ ce = 0
+ mc = 0
+ baseaddr = 0x04000000
+ size = 0x00200000
+ delayr = 1
+ delayw = -1
+end
+
+section memory
+ /*random_seed = 12345
+ type = random*/
+ pattern = 0x00
+ type = unknown /* Fastest */
+
+ name = "RAM"
+ ce = 1
+ mc = 0
+ baseaddr = 0x00000000
+ size = 0x00200000
+ delayr = 1
+ delayw = 5
+end
+
+section memory
+ /*random_seed = 12345
+ type = random*/
+ pattern = 0x00
+ type = unknown /* Fastest */
+
+ name = "ICM"
+ mc = 0
+ ce = 2
+ baseaddr = 0x00800000
+ size = 0x00004000
+ delayr = 1
+ delayw = 1
+end
+
+
+/* IMMU SECTION
+
+ This section configures the Instruction Memory Manangement Unit
+
+ enabled = 0/1
+ '0': disabled
+ '1': enabled
+ (NOTE: UPR bit is set)
+
+ nsets =
+ number of ITLB sets; must be power of two
+
+ nways =
+ number of ITLB ways
+
+ pagesize =
+ instruction page size; must be power of two
+
+ entrysize =
+ instruction entry size in bytes
+
+ ustates =
+ number of ITLB usage states (2, 3, 4 etc., max is 4)
+
+ hitdelay =
+ number of cycles immu hit costs
+
+ missdelay =
+ number of cycles immu miss costs
+*/
+
+section immu
+
+ enabled = 1
+ nsets = 32
+ nways = 1
+ pagesize = 8192
+
+end
+
+
+/* DMMU SECTION
+
+ This section configures the Data Memory Manangement Unit
+
+ enabled = 0/1
+ '0': disabled
+ '1': enabled
+ (NOTE: UPR bit is set)
+
+ nsets =
+ number of DTLB sets; must be power of two
+
+ nways =
+ number of DTLB ways
+
+ pagesize =
+ data page size; must be power of two
+
+ entrysize =
+ data entry size in bytes
+
+ ustates =
+ number of DTLB usage states (2, 3, 4 etc., max is 4)
+
+ hitdelay =
+ number of cycles dmmu hit costs
+
+ missdelay =
+ number of cycles dmmu miss costs
+*/
+
+section dmmu
+ enabled = 1
+ nsets = 32
+ nways = 1
+ pagesize = 8192
+end
+
+
+/* IC SECTION
+
+ This section configures the Instruction Cache
+
+ enabled = 0/1
+ '0': disabled
+ '1': enabled
+ (NOTE: UPR bit is set)
+
+ nsets =
+ number of IC sets; must be power of two
+
+ nways =
+ number of IC ways
+
+ blocksize =
+ IC block size in bytes; must be power of two
+
+ ustates =
+ number of IC usage states (2, 3, 4 etc., max is 4)
+
+ hitdelay =
+ number of cycles ic hit costs
+
+ missdelay =
+ number of cycles ic miss costs
+*/
+
+section ic
+ enabled = 1
+ nsets = 512
+ nways = 1
+ blocksize = 16
+end
+
+
+/* DC SECTION
+
+ This section configures the Data Cache
+
+ enabled = 0/1
+ '0': disabled
+ '1': enabled
+ (NOTE: UPR bit is set)
+
+ nsets =
+ number of DC sets; must be power of two
+
+ nways =
+ number of DC ways
+
+ blocksize =
+ DC block size in bytes; must be power of two
+
+ ustates =
+ number of DC usage states (2, 3, 4 etc., max is 4)
+
+ load_hitdelay =
+ number of cycles dc load hit costs
+
+ load_missdelay =
+ number of cycles dc load miss costs
+
+ store_hitdelay =
+ number of cycles dc load hit costs
+
+ store_missdelay =
+ number of cycles dc load miss costs
+*/
+
+section dc
+ enabled = 1
+ nsets = 512
+ nways = 1
+ blocksize = 16
+end
+
+
+/* SIM SECTION
+
+ This section specifies how or1ksim should behave.
+
+ verbose = 0/1
+ '0': don't print extra messages
+ '1': print extra messages
+
+ debug = 0-9
+ 0 : no debug messages
+ 1-9: debug message level.
+ higher numbers produce more messages
+
+ profile = 0/1
+ '0': don't generate profiling file 'sim.profile'
+ '1': don't generate profiling file 'sim.profile'
+
+ prof_fn = ""
+ optional filename for the profiling file.
+ valid only if 'profile' is set
+
+ mprofile = 0/1
+ '0': don't generate memory profiling file 'sim.mprofile'
+ '1': generate memory profiling file 'sim.mprofile'
+
+ mprof_fn = ""
+ optional filename for the memory profiling file.
+ valid only if 'mprofile' is set
+
+ history = 0/1
+ '0': don't track execution flow
+ '1': track execution flow
+ Execution flow can be tracked for the simulator's
+ 'hist' command. Useful for back-trace debugging.
+
+ iprompt = 0/1
+ '0': start in (so what do we start in ???)
+ '1': start in interactive prompt.
+
+ exe_log = 0/1
+ '0': don't generate execution log.
+ '1': generate execution log.
+
+ exe_log = default/hardware/simple/software
+ type of execution log, default is used when not specified
+
+ exe_log_start =
+ index of first instruction to start logging, default = 0
+
+ exe_log_end =
+ index of last instruction to end logging; not limited, if omitted
+
+ exe_log_marker =
+ specifies number of instructions before horizontal marker is
+ printed; if zero, markers are disabled (default)
+
+ exe_log_fn = ""
+ filename for the exection log file.
+ valid only if 'exe_log' is set
+
+ clkcycle = [ps|ns|us|ms]
+ specifies time measurement for one cycle
+*/
+
+section sim
+ verbose = 1
+ debug = 0
+ profile = 0
+ prof_fn = "sim.profile"
+
+ history = 1
+ /* iprompt = 0 */
+ exe_log = 1
+ exe_log_type = hardware
+/* exe_log_start = 0 */
+/* exe_log_end = 2000000 */
+/* exe_log_marker = 50 */
+ exe_log_fn = "executed.log"
+
+/* clkcycle = 10000ns */
+
+end
+
+
+/* SECTION VAPI
+
+ This section configures the Verification API, used for Advanced
+ Core Verification.
+
+ enabled = 0/1
+ '0': disbable VAPI server
+ '1': enable/start VAPI server
+
+ server_port =
+ TCP/IP port to start VAPI server on
+
+ log_enabled = 0/1
+ '0': disable VAPI requests logging
+ '1': enable VAPI requests logging
+
+ hide_device_id = 0/1
+ '0': don't log device id (for compatability with old version)
+ '1': log device id
+
+
+ vapi_fn =
+ filename for the log file.
+ valid only if log_enabled is set
+*/
+
+section VAPI
+ enabled = 0
+ server_port = 9998
+ log_enabled = 0
+ vapi_log_fn = "vapi.log"
+end
+
+
+/* CPU SECTION
+
+ This section specifies various CPU parameters.
+
+ ver =
+ rev =
+ specifies version and revision of the CPU used
+
+ upr =
+ changes the upr register
+
+ sr =
+ sets the initial Supervision Register value
+
+ superscalar = 0/1
+ '0': CPU is scalar
+ '1': CPU is superscalar
+ (modify cpu/or32/execute.c to tune superscalar model)
+
+ hazards = 0/1
+ '0': don't track data hazards in superscalar CPU
+ '1': track data hazards in superscalar CPU
+ If tracked, data hazards can be displayed using the
+ simulator's 'r' command.
+
+ dependstats = 0/1
+ '0': don't calculate inter-instruction dependencies.
+ '1': calculate inter-instruction dependencies.
+ If calculated, inter-instruction dependencies can be
+ displayed using the simulator's 'stat' command.
+
+ sbuf_len =
+ length of store buffer (<= 256), 0 = disabled
+*/
+
+section cpu
+ ver = 0x1200
+ rev = 0x0001
+ /* upr = */
+ superscalar = 0
+ hazards = 1
+ dependstats = 1
+ sbuf_len = 1
+end
+
+
+/* PM SECTION
+
+ This section specifies Power Management parameters
+
+ enabled = 0/1
+ '0': disable power management
+ '1': enable power management
+*/
+
+section pm
+ enabled = 0
+end
+
+
+/* BPB SECTION
+
+ This section specifies how branch prediction should behave.
+
+ enabled = 0/1
+ '0': disable branch prediction
+ '1': enable branch prediction
+
+ btic = 0/1
+ '0': disable branch target instruction cache model
+ '1': enable branch target instruction cache model
+
+ sbp_bf_fwd = 0/1
+ Static branch prediction for 'l.bf'
+ '0': don't use forward prediction
+ '1': use forward prediction
+
+ sbp_bnf_fwd = 0/1
+ Static branch prediction for 'l.bnf'
+ '0': don't use forward prediction
+ '1': use forward prediction
+
+ hitdelay =
+ number of cycles bpb hit costs
+
+ missdelay =
+ number of cycles bpb miss costs
+*/
+
+section bpb
+ enabled = 1
+ btic = 1
+ sbp_bf_fwd = 0
+ sbp_bnf_fwd = 0
+ hitdelay = 0
+ missdelay = 0
+end
+
+
+/* DEBUG SECTION
+
+ This sections specifies how the debug unit should behave.
+
+ enabled = 0/1
+ '0': disable debug unit
+ '1': enable debug unit
+
+ gdb_enabled = 0/1
+ '0': don't start gdb server
+ '1': start gdb server at port 'server_port'
+
+ server_port =
+ TCP/IP port to start gdb server on
+ valid only if gdb_enabled is set
+
+ vapi_id =
+ Used to create "fake" vapi log file containing the JTAG proxy messages.
+*/
+/*
+section debug
+ enabled = 1
+ gdb_enabled = 1
+ server_port = 12345
+end
+*/
+
+/* MC SECTION
+
+ This section configures the memory controller
+
+ enabled = 0/1
+ '0': disable memory controller
+ '1': enable memory controller
+
+ baseaddr =
+ address of first MC register
+
+ POC =
+ Power On Configuration register
+
+ index =
+ Index of this memory controller amongst all the memory controllers
+*/
+
+section mc
+ enabled = 1
+ baseaddr = 0x60000000
+ POC = 0x00000008 /* Power on configuration register */
+ index = 0
+end
+
+
+/* UART SECTION
+
+ This section configures the UARTs
+
+ enabled = <0|1>
+ Enable/disable the peripheral. By default if it is enabled.
+
+ baseaddr =
+ address of first UART register for this device
+
+
+ channel = :
+
+ The channel parameter indicates the source of received UART characters
+ and the sink for transmitted UART characters.
+
+ The can be either "file", "xterm", "tcp", "fd", or "tty"
+ (without quotes).
+
+ A) To send/receive characters from a pair of files, use a file
+ channel:
+
+ channel=file:,
+
+ B) To create an interactive terminal window, use an xterm channel:
+
+ channel=xterm:[]*
+
+ C) To create a bidirectional tcp socket which one could, for example,
+ access via telnet, use a tcp channel:
+
+ channel=tcp:
+
+ D) To cause the UART to read/write from existing numeric file
+ descriptors, use an fd channel:
+
+ channel=fd:,
+
+ E) To connect the UART to a physical serial port, create a tty
+ channel:
+
+ channel=tty:device=/dev/ttyS0,baud=9600
+
+ irq =
+ irq number for this device
+
+ 16550 = 0/1
+ '0': this device is a UART16450
+ '1': this device is a UART16550
+
+ jitter =
+ in msecs... time to block, -1 to disable it
+
+ vapi_id =
+ VAPI id of this instance
+*/
+
+section uart
+ enabled = 1
+ baseaddr = 0x90000000
+ irq = 2
+ /*channel = "file:uart0.rx,uart0.tx"*/
+ channel = "tcp:10084"
+ jitter = -1 /* async behaviour */
+ 16550 = 1
+end
+
+
+/* DMA SECTION
+
+ This section configures the DMAs
+
+ enabled = <0|1>
+ Enable/disable the peripheral. By default if it is enabled.
+
+ baseaddr =
+ address of first DMA register for this device
+
+ irq =
+ irq number for this device
+
+ vapi_id =
+ VAPI id of this instance
+*/
+
+section dma
+ enabled = 1
+ baseaddr = 0x9a000000
+ irq = 11
+end
+
+
+/* ETHERNET SECTION
+
+ This section configures the ETHERNETs
+
+ enabled = <0|1>
+ Enable/disable the peripheral. By default if it is enabled.
+
+ baseaddr =
+ address of first ethernet register for this device
+
+ dma =
+ which controller is this ethernet "connected" to
+
+ irq =
+ ethernet mac IRQ level
+
+ rtx_type =
+ use 0 - file interface, 1 - socket interface
+
+ rx_channel =
+ DMA channel used for RX
+
+ tx_channel =
+ DMA channel used for TX
+
+ rxfile = ""
+ filename, where to read data from
+
+ txfile = ""
+ filename, where to write data to
+
+ sockif = ""
+ interface name of ethernet socket
+
+ vapi_id =
+ VAPI id of this instance
+*/
+
+section ethernet
+ enabled = 1
+ baseaddr = 0x92000000
+ dma = 0
+ irq = 4
+ rtx_type = 0
+ tx_channel = 0
+ rx_channel = 1
+ rxfile = "eth0.rx"
+ txfile = "eth0.tx"
+ sockif = "eth0"
+end
+
+
+/* GPIO SECTION
+
+ This section configures the GPIOs
+
+ enabled = <0|1>
+ Enable/disable the peripheral. By default if it is enabled.
+
+ baseaddr =
+ address of first GPIO register for this device
+
+ irq =
+ irq number for this device
+
+ base_vapi_id =
+ first VAPI id of this instance
+ GPIO uses 8 consecutive VAPI IDs
+*/
+
+section gpio
+ enabled = 0
+ baseaddr = 0x91000000
+ irq = 3
+ base_vapi_id = 0x0200
+end
+
+/* VGA SECTION
+
+ This section configures the VGA/LCD controller
+
+ enabled = <0|1>
+ Enable/disable the peripheral. By default if it is enabled.
+
+ baseaddr =
+ address of first VGA register
+
+ irq =
+ irq number for this device
+
+ refresh_rate =
+ number of cycles between screen dumps
+
+ filename = ""
+ template name for generated names (e.g. "primary" produces "primary0023.bmp")
+*/
+
+section vga
+ enabled = 1
+ baseaddr = 0x97100000
+ irq = 8
+ refresh_rate = 100000
+ filename = "primary"
+end
+
+
+/* TICK TIMER SECTION
+
+ This section configures tick timer
+
+ enabled = 0/1
+ whether tick timer is enabled
+*/
+/*
+section tick
+ enabled = 1
+ irq = 3
+end
+*/
+/*
+section pic
+ enabled = 1
+ edge_trigger = 1
+end
+*/
+
+/* FB SECTION
+
+ This section configures the frame buffer
+
+ enabled = <0|1>
+ Enable/disable the peripheral. By default if it is enabled.
+
+ baseaddr =
+ base address of frame buffer
+
+ paladdr =
+ base address of first palette entry
+
+ refresh_rate =
+ number of cycles between screen dumps
+
+ filename = ""
+ template name for generated names (e.g. "primary" produces "primary0023.bmp")
+*/
+/*
+section fb
+ enabled = 1
+ baseaddr = 0x97000000
+ refresh_rate = 1000000
+ filename = "primary"
+end
+*/
+
+/* KBD SECTION
+
+ This section configures the PS/2 compatible keyboard
+
+ baseaddr =
+ base address of the keyboard device
+
+ rxfile = ""
+ filename, where to read data from
+*/
+/*
+section kbd
+ enabled = 1
+ irq = 5
+ baseaddr = 0x94000000
+ rxfile = "kbd.rx"
+end
+*/
+
+/* ATA SECTION
+
+ This section configures the ATA/ATAPI host controller
+
+ baseaddr =
+ address of first ATA register
+
+ enabled = <0|1>
+ Enable/disable the peripheral. By default if it is enabled.
+
+ irq =
+ irq number for this device
+
+ debug =
+ debug level for ata models.
+ 0: no debug messages
+ 1: verbose messages
+ 3: normal messages (more messages than verbose)
+ 5: debug messages (normal debug messages)
+ 7: flow control messages (debug statemachine flows)
+ 9: low priority message (display everything the code does)
+
+ dev_type0/1 =
+ ata device 0 type
+ 0: NO_CONNeCT: none (not connected)
+ 1: FILE : simulated harddisk
+ 2: LOCAL : local system harddisk
+
+ dev_file0/1 = ""
+ filename for simulated ATA device
+ valid only if dev_type0 == 1
+
+ dev_size0/1 =
+ size of simulated hard-disk (in MBytes)
+ valid only if dev_type0 == 1
+
+ dev_packet0/1 =
+ 0: simulated ATA device does NOT implement PACKET command feature set
+ 1: simulated ATA device does implement PACKET command feature set
+
+ FIXME: irq number
+*/
+/*
+section ata
+ enabled = 0
+ baseaddr = 0x9e000000
+ irq = 15
+
+ dev_type0 = 1
+ dev_file0 = "/tmp/sim_atadev0"
+ dev_size0 = 1
+ dev_packet0 = 0
+
+ dev_type1 = 0
+ dev_file1 = ""
+ dev_size1 = 0
+ dev_packet1 = 0
+end
+*/
+
sw/support/orp.cfg
Property changes :
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property