URL
https://opencores.org/ocsvn/minsoc/minsoc/trunk
Subversion Repositories minsoc
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- This comparison shows the changes necessary to convert path
/minsoc/trunk
- from Rev 52 to Rev 51
- ↔ Reverse comparison
Rev 52 → Rev 51
/rtl/verilog/minsoc_pll.v
File deleted
/rtl/verilog/minsoc_top.v
295,8 → 295,7
// |
minsoc_clock_manager # |
( |
.divisor(`CLOCK_DIVISOR), |
.multiplier(`CLOCK_MULTIPLIER) |
.divisor(`CLOCK_DIVISOR) |
) |
clk_adjust ( |
.clk_i(clk), |
/rtl/verilog/minsoc_defines.v
45,22 → 45,17
// |
//`define NO_CLOCK_DIVISION |
//`define GENERIC_CLOCK_DIVISION |
`define FPGA_CLOCK_DIVISION // Altera ALTPLL is yet implemented in Verilog and will be used with this option |
`define FPGA_CLOCK_DIVISION //Altera ALTPLL is not implemented, didn't find the code for its verilog instantiation |
//if you selected altera and this, the GENERIC_CLOCK_DIVISION will be automatically taken |
|
// |
// Define division |
// |
`define CLOCK_DIVISOR 4 //in case of GENERIC_CLOCK_DIVISION the real value will be rounded down to an even value |
//in FPGA case, check minsoc_clock_manager for allowed divisors |
//DO NOT USE CLOCK_DIVISOR = 1 COMMENT THE CLOCK DIVISION SELECTION INSTEAD |
`define CLOCK_DIVISOR 5 //in case of GENERIC_CLOCK_DIVISION the real value will be rounded down to an even value |
//in FPGA case, check minsoc_clock_manager for allowed divisors |
//DO NOT USE CLOCK_DIVISOR = 1 COMMENT THE CLOCK DIVISION SELECTION INSTEAD |
|
// |
// Define multiply |
// |
`define CLOCK_MULTIPLIER 2 // In case of FPGA_CLOCK_DIVISION for Altera FPGAs, ALTPLL Megafunction will be used |
// and this will need a clock multiply factor. |
|
// |
// Reset polarity |
// |
//`define NEGATIVE_RESET //rstn |
/rtl/verilog/minsoc_clock_manager.v
10,7 → 10,6
// Parameters |
// |
parameter divisor = 5; |
parameter multiplier = 1; |
|
input clk_i; |
output clk_o; |
33,17 → 32,18
`elsif FPGA_CLOCK_DIVISION |
|
`ifdef ALTERA_FPGA |
minsoc_pll |
#( |
multiplier, |
divisor |
) |
systemPll |
( |
.inclk0(clk_i), |
.c0(clk_o) |
); |
|
reg [31:0] clock_divisor; |
reg clk_int; |
always @ (posedge clk_i) |
begin |
clock_divisor <= clock_divisor + 1'b1; |
if ( clock_divisor >= divisor/2 - 1 ) begin |
clk_int <= ~clk_int; |
clock_divisor <= 32'h0000_0000; |
end |
end |
assign clk_o = clk_int; |
|
`elsif XILINX_FPGA |
|
`ifdef SPARTAN2 |