OpenCores
URL https://opencores.org/ocsvn/minsoc/minsoc/trunk

Subversion Repositories minsoc

Compare Revisions

  • This comparison shows the changes necessary to convert path
    /minsoc/trunk
    from Rev 74 to Rev 75
    Reverse comparison

Rev 74 → Rev 75

/rtl/verilog/minsoc_top.v
713,7 → 713,7
// Instantiation of the Ethernet 10/100 MAC
//
`ifdef ETHERNET
eth_top eth_top (
ethmac ethmac (
 
// WISHBONE common
.wb_clk_i ( wb_clk ),
/sim/bin/minsoc_verilog_files.txt
117,7 → 117,7
../../rtl/verilog/ethmac/rtl/verilog/eth_registers.v
../../rtl/verilog/ethmac/rtl/verilog/eth_rxethmac.v
../../rtl/verilog/ethmac/rtl/verilog/eth_miim.v
../../rtl/verilog/ethmac/rtl/verilog/eth_top.v
../../rtl/verilog/ethmac/rtl/verilog/ethmac.v
../../rtl/verilog/ethmac/rtl/verilog/eth_rxaddrcheck.v
../../rtl/verilog/ethmac/rtl/verilog/eth_outputcontrol.v
../../rtl/verilog/ethmac/rtl/verilog/eth_rxstatem.v
125,7 → 125,7
../../rtl/verilog/ethmac/rtl/verilog/eth_wishbone.v
../../rtl/verilog/ethmac/rtl/verilog/eth_maccontrol.v
../../rtl/verilog/ethmac/rtl/verilog/eth_txstatem.v
../../rtl/verilog/ethmac/rtl/verilog/eth_defines.v
../../rtl/verilog/ethmac/rtl/verilog/ethmac_defines.v
../../rtl/verilog/ethmac/rtl/verilog/eth_spram_256x32.v
../../rtl/verilog/ethmac/rtl/verilog/eth_shiftreg.v
../../rtl/verilog/ethmac/rtl/verilog/eth_clockgen.v

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