Subversion Repositories minsoc

/backend/altera_3c25_board/configure

backend/altera_3c25_board/configure Property changes : Added: svn:executable ## -0,0 +1 ## +* \ No newline at end of property Index: backend/altera_3c25_board/gcc-opt.mk =================================================================== --- backend/altera_3c25_board/gcc-opt.mk (nonexistent) +++ backend/altera_3c25_board/gcc-opt.mk (revision 93) @@ -0,0 +1 @@ +GCC_OPT=-mhard-mul -mhard-div -nostdlib Index: backend/altera_3c25_board/altera_3c25_board.ucf =================================================================== --- backend/altera_3c25_board/altera_3c25_board.ucf (nonexistent) +++ backend/altera_3c25_board/altera_3c25_board.ucf (revision 93) @@ -0,0 +1,16 @@ +# Altera 3c25 board based pinout and definitions. +# This file uses quartus qsf file format for compose final config file. + +# RS232 Port +set_location_assignment PIN_12 -to uart_srx +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to uart_srx +set_location_assignment PIN_14 -to uart_stx +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to uart_stx + +# 50 Mhz Pin +set_location_assignment PIN_152 -to clk +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to clk + +# Reset pin. +set_location_assignment PIN_200 -to reset +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to reset Index: backend/altera_3c25_board/minsoc_bench_defines.v =================================================================== --- backend/altera_3c25_board/minsoc_bench_defines.v (nonexistent) +++ backend/altera_3c25_board/minsoc_bench_defines.v (revision 93) @@ -0,0 +1,26 @@ +//set RTL for simulation, override FPGA specific definitions (JTAG TAP, MEMORY and CLOCK DIVIDER) +`define GENERIC_FPGA +`define MEMORY_MODEL //simulation uses a memory model enabling INITIALIZE_MEMORY_MODEL. If you comment this, START_UP might be interesting. +`define NO_CLOCK_DIVISION //if commented out, generic clock division is implemented (odd divisors are rounded down) +//~set RTL for simulation, override FPGA specific definitions (JTAG TAP, MEMORY and CLOCK DIVIDER) + +`define FREQ_NUM_FOR_NS 1000000000 + +`define FREQ 25000000 +`define CLK_PERIOD (`FREQ_NUM_FOR_NS/`FREQ) + +`define ETH_PHY_FREQ 25000000 +`define ETH_PHY_PERIOD (`FREQ_NUM_FOR_NS/`ETH_PHY_FREQ) //40ns + +`define UART_BAUDRATE 115200 + +`define VPI_DEBUG + +//`define VCD_OUTPUT + +//`define START_UP //pass firmware over spi to or1k_startup + +`define INITIALIZE_MEMORY_MODEL //instantaneously initialize memory model with firmware + //only use with the memory model. + //If you use the original memory (`define MEMORY_MODEL + //commented out), comment this too.

backend/altera_3c25_board/minsoc_bench_defines.v Property changes : Added: svn:executable ## -0,0 +1 ## +* \ No newline at end of property Index: backend/altera_3c25_board/minsoc_defines.v =================================================================== --- backend/altera_3c25_board/minsoc_defines.v (nonexistent) +++ backend/altera_3c25_board/minsoc_defines.v (revision 93) @@ -0,0 +1,150 @@ +// +// Define FPGA manufacturer +// +//`define GENERIC_FPGA +`define ALTERA_FPGA +//`define XILINX_FPGA + +// +// Define Xilinx FPGA family +// +`ifdef XILINX_FPGA +//`define SPARTAN2 +//`define SPARTAN3 +//`define SPARTAN3E +`define SPARTAN3A +//`define VIRTEX +//`define VIRTEX2 +//`define VIRTEX4 +//`define VIRTEX5 + +// +// Define Altera FPGA family +// +`elsif ALTERA_FPGA +//`define ARRIA_GX +//`define ARRIA_II_GX +//`define CYCLONE_I +//`define CYCLONE_II +`define CYCLONE_III +//`define CYCLONE_III_LS +//`define CYCLONE_IV_E +//`define CYCLONE_IV_GS +//`define MAX_II +//`define MAX_V +//`define MAX3000A +//`define MAX7000AE +//`define MAX7000B +//`define MAX7000S +//`define STRATIX +//`define STRATIX_II +//`define STRATIX_II_GX +//`define STRATIX_III +`endif + +// +// Memory +// +`define MEMORY_ADR_WIDTH 13 //MEMORY_ADR_WIDTH IS NOT ALLOWED TO BE LESS THAN 12, + //memory is composed by blocks of address width 11 + //Address width of memory -> select memory depth, + //2 powers MEMORY_ADR_WIDTH defines the memory depth + //the memory data width is 32 bit, + //memory amount in Bytes = 4*memory depth + +// +// Memory type (uncomment something if ASIC or generic memory) +// +//`define GENERIC_MEMORY +//`define AVANT_ATP +//`define VIRAGE_SSP +//`define VIRTUALSILICON_SSP + + +// +// TAP selection +// +//`define GENERIC_TAP +`define FPGA_TAP + +// +// Clock Division selection +// +//`define NO_CLOCK_DIVISION +//`define GENERIC_CLOCK_DIVISION +`define FPGA_CLOCK_DIVISION // For Altera ALTPLL, only CYCLONE_III family has been tested. + +// +// Define division +// +`define CLOCK_DIVISOR 5 //in case of GENERIC_CLOCK_DIVISION the real value will be rounded + //down to an even value in FPGA case, check minsoc_clock_manager + //for allowed divisors. + //DO NOT USE CLOCK_DIVISOR = 1 COMMENT THE CLOCK DIVISION SELECTION + //INSTEAD. + +// +// Reset polarity +// +//`define NEGATIVE_RESET //rstn +`define POSITIVE_RESET //rst + +// +// Start-up circuit (only necessary later to load firmware automatically from SPI memory) +// +//`define START_UP + +// +// Connected modules +// +`define UART +`define ETHERNET + +// +// Ethernet reset +// +//`define ETH_RESET 1'b0 +`define ETH_RESET 1'b1 + +// +// Interrupts +// +`define APP_INT_RES1 1:0 +`define APP_INT_UART 2 +`define APP_INT_RES2 3 +`define APP_INT_ETH 4 +`define APP_INT_PS2 5 +`define APP_INT_RES3 19:6 + +// +// Address map +// +`define APP_ADDR_DEC_W 8 +`define APP_ADDR_SRAM `APP_ADDR_DEC_W'h00 +`define APP_ADDR_FLASH `APP_ADDR_DEC_W'h04 +`define APP_ADDR_DECP_W 4 +`define APP_ADDR_PERIP `APP_ADDR_DECP_W'h9 +`define APP_ADDR_SPI `APP_ADDR_DEC_W'h97 +`define APP_ADDR_ETH `APP_ADDR_DEC_W'h92 +`define APP_ADDR_AUDIO `APP_ADDR_DEC_W'h9d +`define APP_ADDR_UART `APP_ADDR_DEC_W'h90 +`define APP_ADDR_PS2 `APP_ADDR_DEC_W'h94 +`define APP_ADDR_RES1 `APP_ADDR_DEC_W'h9e +`define APP_ADDR_RES2 `APP_ADDR_DEC_W'h9f + +// +// Set-up GENERIC_TAP, GENERIC_MEMORY if GENERIC_FPGA was chosen +// and GENERIC_CLOCK_DIVISION if NO_CLOCK_DIVISION was not set +// +`ifdef GENERIC_FPGA + `undef FPGA_TAP + `undef FPGA_CLOCK_DIVISION + `undef XILINX_FPGA + `undef SPARTAN3A + + `define GENERIC_TAP + `define GENERIC_MEMORY + `ifndef NO_CLOCK_DIVISION + `define GENERIC_CLOCK_DIVISION + `endif +`endif Index: backend/altera_3c25_board/board.h =================================================================== --- backend/altera_3c25_board/board.h (nonexistent) +++ backend/altera_3c25_board/board.h (revision 93) @@ -0,0 +1,40 @@ +#ifndef _BOARD_H_ +#define _BOARD_H_ + +#define MC_ENABLED 0 + +#define IC_ENABLE 0 +#define IC_SIZE 8192 +#define DC_ENABLE 0 +#define DC_SIZE 8192 + + +#define IN_CLK 25000000 + + +#define STACK_SIZE 0x01000 + +#define UART_BAUD_RATE 115200 + +#define UART_BASE 0x90000000 +#define UART_IRQ 2 +#define ETH_BASE 0x92000000 +#define ETH_IRQ 4 +#define I2C_BASE 0x9D000000 +#define I2C_IRQ 3 +#define CAN_BASE 0x94000000 +#define CAN_IRQ 5 + +#define MC_BASE_ADDR 0x60000000 +#define SPI_BASE 0xa0000000 + +#define ETH_DATA_BASE 0xa8000000 /* Address for ETH_DATA */ + +#define ETH_MACADDR0 0x00 +#define ETH_MACADDR1 0x12 +#define ETH_MACADDR2 0x34 +#define ETH_MACADDR3 0x56 +#define ETH_MACADDR4 0x78 +#define ETH_MACADDR5 0x9a + +#endif

backend/altera_3c25_board/board.h Property changes : Added: svn:executable ## -0,0 +1 ## +* \ No newline at end of property Index: backend/altera_3c25_board/orp.ld =================================================================== --- backend/altera_3c25_board/orp.ld (nonexistent) +++ backend/altera_3c25_board/orp.ld (revision 93) @@ -0,0 +1,60 @@ +MEMORY + { + reset : ORIGIN = 0x00000000, LENGTH = 0x00000200 + vectors : ORIGIN = 0x00000200, LENGTH = 0x00001000 + ram : ORIGIN = 0x00001200, LENGTH = 0x0001EE00 /*0x20000 total*/ + } + +SECTIONS +{ + .reset : + { + *(.reset) + } > reset + + + + .vectors : + { + _vec_start = .; + *(.vectors) + _vec_end = .; + } > vectors + + .text : + { + *(.text) + } > ram + + .rodata : + { + *(.rodata) + *(.rodata.*) + } > ram + + .icm : + { + _icm_start = .; + *(.icm) + _icm_end = .; + } > ram + + .data : + { + _dst_beg = .; + *(.data) + _dst_end = .; + } > ram + + .bss : + { + *(.bss) + } > ram + + .stack (NOLOAD) : + { + *(.stack) + _src_addr = .; + } > ram + +}

backend/altera_3c25_board/orp.ld Property changes : Added: svn:executable ## -0,0 +1 ## +* \ No newline at end of property Index: syn/altera/Makefile =================================================================== --- syn/altera/Makefile (nonexistent) +++ syn/altera/Makefile (revision 93) @@ -0,0 +1,55 @@ +MINSOC = .. +MINSOC_DEFINES = ${MINSOC}/backend +MINSOC_RTL = ${MINSOC}/rtl/verilog +MINSOC_STARTUP_RTL = ${MINSOC_RTL}/minsoc_startup +UART_RTL = ${MINSOC_RTL}/uart16550/rtl/verilog +ADV_DEBUG_ROOT = ${MINSOC_RTL}/adv_debug_sys/Hardware +DEBUG_RTL = ${ADV_DEBUG_ROOT}/adv_dbg_if/rtl/verilog +OR1200_RTL = ${MINSOC_RTL}/or1200/rtl/verilog +ETH_RTL = ${MINSOC_RTL}/ethmac/rtl/verilog +BUILD_SUPPORT = $(MINSOC)/syn/buildSupport +PROJECT_DIR = $(MINSOC)/prj/altera + +help: + @echo " all: Synthesize and implement the SoC, then generate a bit stream" + @echo "" + @echo " bitgen: Generate a programming file for the target FPGA" + @echo " map: Express the SoC netlist in the target hardware" + @echo " fit: Place the target hardware, then route the wires" + @echo " sta: Perfom a timming analysis" + @echo " eda: Generate a netlist of the hardware" + @echo "" + @echo " clean: Delete all superfluous files generated by Altera tools" + @echo " distclean: Delete all generated files" + +all: bitgen eda sta +map: minsoc_top.map.summary +fit: minsoc_top.fit.summary +bitgen: minsoc_top.sof +eda: minsoc_top.eda.summary +sta: minsoc_top.sta.summary + +#minsoc_top.map.summary: ${MINSOC_RTL}/*.v $(UART_RTL)/*.v $(ADV_DEBUG_ROOT)/*.v $(DEBUG_RTL)/*.v $(OR1200_RTL)/*.v $(ETH_RTL)/*.v ${MINSOC_DEFINES}/minsoc_defines.v minsoc_top.qsf +minsoc_top.map.summary: ${MINSOC_DEFINES}/minsoc_defines.v minsoc_top.qsf + + quartus_map minsoc_top --write_settings_files=off + +minsoc_top.fit.summary: minsoc_top.map.summary + quartus_fit minsoc_top --write_Settings_files=off --pack_register=minimize_area + +minsoc_top.sof: minsoc_top.fit.summary + quartus_asm minsoc_top + +minsoc_top.sta.summary: minsoc_top.fit.summary + quartus_sta minsoc_top + +minsoc_top.eda.summary: minsoc_top.fit.summary + quartus_eda minsoc_top --write_settings_files=off + +distclean: + $(RM) *.sof + make clean + +clean: + $(RM) *.rpt *.summary *.jdi *.smsg *.pin *.qpf + rm -fr db incremental_db Index: prj/altera/adv_dbg.prj =================================================================== --- prj/altera/adv_dbg.prj (nonexistent) +++ prj/altera/adv_dbg.prj (revision 93) @@ -0,0 +1 @@ +set_global_assignment -name SEARCH_PATH ../rtl/verilog/adv_debug_sys/Hardware/adv_dbg_if/rtl/verilog Index: prj/altera/minsoc_top.qsf =================================================================== --- prj/altera/minsoc_top.qsf (nonexistent) +++ prj/altera/minsoc_top.qsf (revision 93) @@ -0,0 +1,37 @@ +set_global_assignment -name FAMILY "FAMILY_PART" +set_global_assignment -name DEVICE DEVICE_PART +set_global_assignment -name TOP_LEVEL_ENTITY minsoc_top +#set_global_assignment -name ORIGINAL_QUARTUS_VERSION SW_VERSION +#set_global_assignment -name LAST_QUARTUS_VERSION SW_VERSION +set_global_assignment -name MIN_CORE_JUNCTION_TEMP 0 +set_global_assignment -name MAX_CORE_JUNCTION_TEMP 85 +set_global_assignment -name DEVICE_FILTER_PIN_COUNT 240 +set_global_assignment -name ERROR_CHECK_FREQUENCY_DIVISOR 2 +set_global_assignment -name PARTITION_NETLIST_TYPE SOURCE -section_id Top +set_global_assignment -name PARTITION_FITTER_PRESERVATION_LEVEL PLACEMENT_AND_ROUTING -section_id Top +set_global_assignment -name PARTITION_COLOR 16764057 -section_id Top +set_global_assignment -name STRATIX_DEVICE_IO_STANDARD "2.5 V" +#set_global_assignment -name MISC_FILE ./minsoc_top.dpf +set_global_assignment -name USE_CONFIGURATION_DEVICE OFF +set_global_assignment -name CRC_ERROR_OPEN_DRAIN OFF +set_global_assignment -name FORCE_CONFIGURATION_VCCIO ON +set_global_assignment -name OUTPUT_IO_TIMING_NEAR_END_VMEAS "HALF VCCIO" -rise +set_global_assignment -name OUTPUT_IO_TIMING_NEAR_END_VMEAS "HALF VCCIO" -fall +set_global_assignment -name OUTPUT_IO_TIMING_FAR_END_VMEAS "HALF SIGNAL SWING" -rise +set_global_assignment -name OUTPUT_IO_TIMING_FAR_END_VMEAS "HALF SIGNAL SWING" -fall +set_global_assignment -name RESERVE_DATA1_AFTER_CONFIGURATION "USE AS REGULAR IO" +set_global_assignment -name RESERVE_FLASH_NCE_AFTER_CONFIGURATION "USE AS REGULAR IO" +set_global_assignment -name EDA_BOARD_DESIGN_BOUNDARY_SCAN_TOOL "BSDL (Boundary Scan)" +set_global_assignment -name EDA_OUTPUT_DATA_FORMAT BSDL -section_id eda_board_design_boundary_scan +set_global_assignment -name EDA_BOARD_BOUNDARY_SCAN_OPERATION POST_CONFIG -section_id eda_board_design_boundary_scan +set_global_assignment -name POWER_PRESET_COOLING_SOLUTION "23 MM HEAT SINK WITH 200 LFPM AIRFLOW" +set_global_assignment -name POWER_BOARD_THERMAL_MODEL "NONE (CONSERVATIVE)" +set_global_assignment -name EDA_TIMING_ANALYSIS_TOOL "" +set_global_assignment -name EDA_TIME_SCALE "1 ps" -section_id eda_timing_analysis +set_global_assignment -name EDA_RUN_TOOL_AUTOMATICALLY OFF -section_id eda_timing_analysis +set_global_assignment -name EDA_OUTPUT_DATA_FORMAT NONE -section_id eda_timing_analysis +set_global_assignment -name EDA_LAUNCH_CMD_LINE_TOOL OFF -section_id eda_timing_analysis + +set_global_assignment -name SDC_FILE minsoc_top.sdc +set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -section_id Top + Index: prj/altera/minsoc_top.prj =================================================================== --- prj/altera/minsoc_top.prj (nonexistent) +++ prj/altera/minsoc_top.prj (revision 93) @@ -0,0 +1,8 @@ +set_global_assignment -name VERILOG_FILE ../rtl/verilog/timescale.v +set_global_assignment -name VERILOG_FILE ../rtl/verilog/minsoc_top.v +set_global_assignment -name VERILOG_FILE ../rtl/verilog/minsoc_tc_top.v +set_global_assignment -name VERILOG_FILE ../rtl/verilog/minsoc_onchip_ram_top.v +set_global_assignment -name VERILOG_FILE ../rtl/verilog/minsoc_onchip_ram.v +set_global_assignment -name VERILOG_FILE ../rtl/verilog/minsoc_defines.v +set_global_assignment -name VERILOG_FILE ../rtl/verilog/minsoc_clock_manager.v +set_global_assignment -name VERILOG_FILE ../rtl/verilog/altera_pll.v Index: prj/altera/or1k.prj =================================================================== --- prj/altera/or1k.prj (nonexistent) +++ prj/altera/or1k.prj (revision 93) @@ -0,0 +1 @@ +set_global_assignment -name SEARCH_PATH ../rtl/verilog/or1200/rtl/verilog Index: prj/altera/uart16550.prj =================================================================== --- prj/altera/uart16550.prj (nonexistent) +++ prj/altera/uart16550.prj (revision 93) @@ -0,0 +1 @@ +set_global_assignment -name SEARCH_PATH ../rtl/verilog/uart16550/rtl/verilog Index: prj/altera/altera_jtag.prj =================================================================== --- prj/altera/altera_jtag.prj (nonexistent) +++ prj/altera/altera_jtag.prj (revision 93) @@ -0,0 +1 @@ +set_global_assignment -name SEARCH_PATH ../rtl/verilog/adv_debug_sys/Hardware/altera_virtual_jtag/rtl/vhdl Index: prj/altera/ethmac.prj =================================================================== --- prj/altera/ethmac.prj (nonexistent) +++ prj/altera/ethmac.prj (revision 93) @@ -0,0 +1 @@ +set_global_assignment -name SEARCH_PATH ../rtl/verilog/ethmac/rtl/verilog