OpenCores
URL https://opencores.org/ocsvn/minsoc/minsoc/trunk

Subversion Repositories minsoc

Compare Revisions

  • This comparison shows the changes necessary to convert path
    /minsoc/trunk
    from Rev 94 to Rev 95
    Reverse comparison

Rev 94 → Rev 95

/backend/altera_3c25_board/configure
17,7 → 17,7
SYNSUPPORT_DIR=$SYN_DIR/buildSupport
MAKEFILE_DIR=$SYN_DIR/altera
 
SYN_FILES=(adv_dbg.prj altera_jtag.prj ethmac.prj or1k.prj uart16550.prj minsoc_top.prj)
SYN_FILES=(adbg_top.prj jtag_top.prj or1200_top.prj uart_top.prj minsoc_top.prj)
MAKEFILE=Makefile
 
FIND_PART='DEVICE_PART'
54,30 → 54,29
then
echo "Skipping synthesis preparation. Standard implementation can only be simulated."
else
echo "Device part for files under minsoc/prj/altera will be patched and stored "
echo "Device part and family for qsf file under $MAKEFILE_DIR will patched and stored "
echo "temporarily."
echo "Afterwards, they are copied to minsoc/syn/buildSupport."
echo "__________________________________________________________________________"
echo ""
echo "Generating quartus settings file from templates..."
sed "s/$FIND_PART/$DEVICE_PART/g" $SYNSRC_DIR/$PROJECT_FILE > TMPFILE
sed "s/$FIND_PART/$DEVICE_PART/g" $MAKEFILE_DIR/$PROJECT_FILE > TMPFILE
sed "s/$FIND_FAMILY/$FAMILY_PART/g" TMPFILE > TMPFILE2
#sed "s/$FIND_VERSION/$SW_VERSION/g" TMPFILE> TMPFILE
echo "Adding settings from constraint file..."
cat $CONSTRAINT_FILE >> TMPFILE2
 
echo "Generating quartus settings from prj files in $SYNSRC_DIR"
for file in "${SYN_FILES[@]}"
do
echo "Adding settings from file $file..."
cat $SYNSRC_DIR/$file >> TMPFILE2
done
mv TMPFILE2 $SYN_DIR/$PROJECT_FILE
mv TMPFILE2 $SYNSUPPORT_DIR/$PROJECT_FILE
rm TMPFILE
echo ""
echo "Generated quartus settings file in $SYN_DIR/$PROJECT_FILE"
echo "Generated quartus settings file in $SYNSUPPORT_DIR/$PROJECT_FILE"
echo ""
 
echo "Updating Makefile file..."
echo "Copying Makefile to synthesis directory..."
cp $MAKEFILE_DIR/$MAKEFILE $SYN_DIR/$MAKEFILE
echo ""
95,6 → 94,6
done
echo ""
echo "Configuration done."
echo "For synthesis go to $SYN_DIR and type \"make\"."
echo "For synthesis help go to $SYN_DIR and type \"make\"."
fi
 
/backend/altera_3c25_board/minsoc_defines.v
77,7 → 77,7
//
// Define division
//
`define CLOCK_DIVISOR 5 //in case of GENERIC_CLOCK_DIVISION the real value will be rounded
`define CLOCK_DIVISOR 2 //in case of GENERIC_CLOCK_DIVISION the real value will be rounded
//down to an even value in FPGA case, check minsoc_clock_manager
//for allowed divisors.
//DO NOT USE CLOCK_DIVISOR = 1 COMMENT THE CLOCK DIVISION SELECTION
86,8 → 86,8
//
// Reset polarity
//
//`define NEGATIVE_RESET //rstn
`define POSITIVE_RESET //rst
`define NEGATIVE_RESET //rstn
//`define POSITIVE_RESET //rst
 
//
// Start-up circuit (only necessary later to load firmware automatically from SPI memory)
98,7 → 98,7
// Connected modules
//
`define UART
`define ETHERNET
//`define ETHERNET
 
//
// Ethernet reset
/syn/altera/minsoc_top.qsf
0,0 → 1,37
set_global_assignment -name FAMILY "FAMILY_PART"
set_global_assignment -name DEVICE DEVICE_PART
set_global_assignment -name TOP_LEVEL_ENTITY minsoc_top
#set_global_assignment -name ORIGINAL_QUARTUS_VERSION SW_VERSION
#set_global_assignment -name LAST_QUARTUS_VERSION SW_VERSION
set_global_assignment -name MIN_CORE_JUNCTION_TEMP 0
set_global_assignment -name MAX_CORE_JUNCTION_TEMP 85
set_global_assignment -name DEVICE_FILTER_PIN_COUNT 240
set_global_assignment -name ERROR_CHECK_FREQUENCY_DIVISOR 2
set_global_assignment -name PARTITION_NETLIST_TYPE SOURCE -section_id Top
set_global_assignment -name PARTITION_FITTER_PRESERVATION_LEVEL PLACEMENT_AND_ROUTING -section_id Top
set_global_assignment -name PARTITION_COLOR 16764057 -section_id Top
set_global_assignment -name STRATIX_DEVICE_IO_STANDARD "2.5 V"
#set_global_assignment -name MISC_FILE ./minsoc_top.dpf
set_global_assignment -name USE_CONFIGURATION_DEVICE OFF
set_global_assignment -name CRC_ERROR_OPEN_DRAIN OFF
set_global_assignment -name FORCE_CONFIGURATION_VCCIO ON
set_global_assignment -name OUTPUT_IO_TIMING_NEAR_END_VMEAS "HALF VCCIO" -rise
set_global_assignment -name OUTPUT_IO_TIMING_NEAR_END_VMEAS "HALF VCCIO" -fall
set_global_assignment -name OUTPUT_IO_TIMING_FAR_END_VMEAS "HALF SIGNAL SWING" -rise
set_global_assignment -name OUTPUT_IO_TIMING_FAR_END_VMEAS "HALF SIGNAL SWING" -fall
set_global_assignment -name RESERVE_DATA1_AFTER_CONFIGURATION "USE AS REGULAR IO"
set_global_assignment -name RESERVE_FLASH_NCE_AFTER_CONFIGURATION "USE AS REGULAR IO"
set_global_assignment -name EDA_BOARD_DESIGN_BOUNDARY_SCAN_TOOL "BSDL (Boundary Scan)"
set_global_assignment -name EDA_OUTPUT_DATA_FORMAT BSDL -section_id eda_board_design_boundary_scan
set_global_assignment -name EDA_BOARD_BOUNDARY_SCAN_OPERATION POST_CONFIG -section_id eda_board_design_boundary_scan
set_global_assignment -name POWER_PRESET_COOLING_SOLUTION "23 MM HEAT SINK WITH 200 LFPM AIRFLOW"
set_global_assignment -name POWER_BOARD_THERMAL_MODEL "NONE (CONSERVATIVE)"
set_global_assignment -name EDA_TIMING_ANALYSIS_TOOL "<None>"
set_global_assignment -name EDA_TIME_SCALE "1 ps" -section_id eda_timing_analysis
set_global_assignment -name EDA_RUN_TOOL_AUTOMATICALLY OFF -section_id eda_timing_analysis
set_global_assignment -name EDA_OUTPUT_DATA_FORMAT NONE -section_id eda_timing_analysis
set_global_assignment -name EDA_LAUNCH_CMD_LINE_TOOL OFF -section_id eda_timing_analysis
 
set_global_assignment -name SDC_FILE minsoc_top.sdc
set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -section_id Top
 
/syn/altera/Makefile
9,7 → 9,7
ETH_RTL = ${MINSOC_RTL}/ethmac/rtl/verilog
BUILD_SUPPORT = $(MINSOC)/syn/buildSupport
PROJECT_DIR = $(MINSOC)/prj/altera
 
QSF_FILE = $(BUILD_SUPPORT)/minsoc_top
help:
@echo " all: Synthesize and implement the SoC, then generate a bit stream"
@echo ""
18,38 → 18,43
@echo " fit: Place the target hardware, then route the wires"
@echo " sta: Perfom a timming analysis"
@echo " eda: Generate a netlist of the hardware"
@echo " config: Load the bitstream into the device using ALTERA USB Blaster and JTAG configuration"
@echo ""
@echo " clean: Delete all superfluous files generated by Altera tools"
@echo " distclean: Delete all generated files"
 
all: bitgen eda sta
map: minsoc_top.map.summary
fit: minsoc_top.fit.summary
map: $(BUILD_SUPPORT)/minsoc_top.map.summary
fit: $(BUILD_SUPPORT)/minsoc_top.fit.summary
bitgen: minsoc_top.sof
eda: minsoc_top.eda.summary
sta: minsoc_top.sta.summary
eda: $(BUILD_SUPPORT)/minsoc_top.eda.summary
sta: $(BUILD_SUPPORT)/minsoc_top.sta.summary
 
#minsoc_top.map.summary: ${MINSOC_RTL}/*.v $(UART_RTL)/*.v $(ADV_DEBUG_ROOT)/*.v $(DEBUG_RTL)/*.v $(OR1200_RTL)/*.v $(ETH_RTL)/*.v ${MINSOC_DEFINES}/minsoc_defines.v minsoc_top.qsf
minsoc_top.map.summary: ${MINSOC_DEFINES}/minsoc_defines.v minsoc_top.qsf
$(BUILD_SUPPORT)/minsoc_top.map.summary: ${MINSOC_DEFINES}/minsoc_defines.v $(BUILD_SUPPORT)/minsoc_top.qsf
 
quartus_map minsoc_top --write_settings_files=off
quartus_map $(QSF_FILE) --write_settings_files=off
 
minsoc_top.fit.summary: minsoc_top.map.summary
quartus_fit minsoc_top --write_Settings_files=off --pack_register=minimize_area
$(BUILD_SUPPORT)/minsoc_top.fit.summary: $(BUILD_SUPPORT)/minsoc_top.map.summary
quartus_fit $(QSF_FILE) --write_Settings_files=off --pack_register=minimize_area
 
minsoc_top.sof: minsoc_top.fit.summary
quartus_asm minsoc_top
minsoc_top.sof: $(BUILD_SUPPORT)/minsoc_top.fit.summary
quartus_asm $(QSF_FILE)
mv $(BUILD_SUPPORT)/*.sof .
 
minsoc_top.sta.summary: minsoc_top.fit.summary
quartus_sta minsoc_top
$(BUILD_SUPPORT)/minsoc_top.sta.summary: $(BUILD_SUPPORT)/minsoc_top.fit.summary
quartus_sta $(QSF_FILE)
 
minsoc_top.eda.summary: minsoc_top.fit.summary
quartus_eda minsoc_top --write_settings_files=off
$(BUILD_SUPPORT)/minsoc_top.eda.summary: $(BUILD_SUPPORT)/minsoc_top.fit.summary
quartus_eda $(QSF_FILE) --write_settings_files=off
 
config: minsoc_top.sof
quartus_pgm -c USB-Blaster -m jtag -o "p;minsoc_top.sof"
 
distclean:
$(RM) *.sof
make clean
 
clean:
$(RM) *.rpt *.summary *.jdi *.smsg *.pin *.qpf
rm -fr db incremental_db
$(RM) $(BUILD_SUPPORT)/*.rpt $(BUILD_SUPPORT)/*.summary $(BUILD_SUPPORT)/*.jdi $(BUILD_SUPPORT)/*.smsg $(BUILD_SUPPORT)/*.pin $(BUILD_SUPPORT)/*.qpf
$(RM) -r $(BUILD_SUPPORT)/db $(BUILD_SUPPORT)/incremental_db
/prj/altera/or1k.prj File deleted
/prj/altera/or1200_top.prj
0,0 → 1,64
set_global_assignment -name SEARCH_PATH ../../rtl/verilog/or1200/rtl/verilog
set_global_assignment -name VERILOG_FILE ../../rtl/verilog/or1200/rtl/verilog/or1200_spram_512x20.v
set_global_assignment -name VERILOG_FILE ../../rtl/verilog/or1200/rtl/verilog/or1200_spram_64x24.v
set_global_assignment -name VERILOG_FILE ../../rtl/verilog/or1200/rtl/verilog/or1200_du.v
set_global_assignment -name VERILOG_FILE ../../rtl/verilog/or1200/rtl/verilog/or1200_spram_2048x32_bw.v
set_global_assignment -name VERILOG_FILE ../../rtl/verilog/or1200/rtl/verilog/or1200_rf.v
set_global_assignment -name VERILOG_FILE ../../rtl/verilog/or1200/rtl/verilog/or1200_alu.v
set_global_assignment -name VERILOG_FILE ../../rtl/verilog/or1200/rtl/verilog/or1200_dmmu_top.v
set_global_assignment -name VERILOG_FILE ../../rtl/verilog/or1200/rtl/verilog/or1200_lsu.v
set_global_assignment -name VERILOG_FILE ../../rtl/verilog/or1200/rtl/verilog/or1200_spram_1024x32.v
set_global_assignment -name VERILOG_FILE ../../rtl/verilog/or1200/rtl/verilog/or1200_dc_top.v
set_global_assignment -name VERILOG_FILE ../../rtl/verilog/or1200/rtl/verilog/or1200_cpu.v
set_global_assignment -name VERILOG_FILE ../../rtl/verilog/or1200/rtl/verilog/or1200_gmultp2_32x32.v
set_global_assignment -name VERILOG_FILE ../../rtl/verilog/or1200/rtl/verilog/or1200_immu_top.v
set_global_assignment -name VERILOG_FILE ../../rtl/verilog/or1200/rtl/verilog/or1200_dpram_256x32.v
set_global_assignment -name VERILOG_FILE ../../rtl/verilog/or1200/rtl/verilog/or1200_tt.v
set_global_assignment -name VERILOG_FILE ../../rtl/verilog/or1200/rtl/verilog/or1200_iwb_biu.v
set_global_assignment -name VERILOG_FILE ../../rtl/verilog/or1200/rtl/verilog/or1200_rfram_generic.v
set_global_assignment -name VERILOG_FILE ../../rtl/verilog/or1200/rtl/verilog/or1200_dc_tag.v
set_global_assignment -name VERILOG_FILE ../../rtl/verilog/or1200/rtl/verilog/or1200_spram_2048x8.v
set_global_assignment -name VERILOG_FILE ../../rtl/verilog/or1200/rtl/verilog/or1200_immu_tlb.v
set_global_assignment -name VERILOG_FILE ../../rtl/verilog/or1200/rtl/verilog/or1200_ic_tag.v
set_global_assignment -name VERILOG_FILE ../../rtl/verilog/or1200/rtl/verilog/or1200_spram_64x14.v
set_global_assignment -name VERILOG_FILE ../../rtl/verilog/or1200/rtl/verilog/or1200_spram_32x24.v
set_global_assignment -name VERILOG_FILE ../../rtl/verilog/or1200/rtl/verilog/or1200_dpram_32x32.v
set_global_assignment -name VERILOG_FILE ../../rtl/verilog/or1200/rtl/verilog/or1200_xcv_ram32x8d.v
set_global_assignment -name VERILOG_FILE ../../rtl/verilog/or1200/rtl/verilog/or1200_spram_1024x8.v
set_global_assignment -name VERILOG_FILE ../../rtl/verilog/or1200/rtl/verilog/or1200_mem2reg.v
set_global_assignment -name VERILOG_FILE ../../rtl/verilog/or1200/rtl/verilog/or1200_pm.v
set_global_assignment -name VERILOG_FILE ../../rtl/verilog/or1200/rtl/verilog/or1200_spram_256x21.v
set_global_assignment -name VERILOG_FILE ../../rtl/verilog/or1200/rtl/verilog/or1200_operandmuxes.v
set_global_assignment -name VERILOG_FILE ../../rtl/verilog/or1200/rtl/verilog/or1200_pic.v
set_global_assignment -name VERILOG_FILE ../../rtl/verilog/or1200/rtl/verilog/or1200_cfgr.v
set_global_assignment -name VERILOG_FILE ../../rtl/verilog/or1200/rtl/verilog/or1200_if.v
set_global_assignment -name VERILOG_FILE ../../rtl/verilog/or1200/rtl/verilog/or1200_qmem_top.v
set_global_assignment -name VERILOG_FILE ../../rtl/verilog/or1200/rtl/verilog/or1200_genpc.v
set_global_assignment -name VERILOG_FILE ../../rtl/verilog/or1200/rtl/verilog/or1200_defines.v
set_global_assignment -name VERILOG_FILE ../../rtl/verilog/or1200/rtl/verilog/or1200_wbmux.v
set_global_assignment -name VERILOG_FILE ../../rtl/verilog/or1200/rtl/verilog/or1200_ic_ram.v
set_global_assignment -name VERILOG_FILE ../../rtl/verilog/or1200/rtl/verilog/or1200_dmmu_tlb.v
set_global_assignment -name VERILOG_FILE ../../rtl/verilog/or1200/rtl/verilog/or1200_sb_fifo.v
set_global_assignment -name VERILOG_FILE ../../rtl/verilog/or1200/rtl/verilog/or1200_sprs.v
set_global_assignment -name VERILOG_FILE ../../rtl/verilog/or1200/rtl/verilog/or1200_tpram_32x32.v
set_global_assignment -name VERILOG_FILE ../../rtl/verilog/or1200/rtl/verilog/or1200_ctrl.v
set_global_assignment -name VERILOG_FILE ../../rtl/verilog/or1200/rtl/verilog/or1200_sb.v
set_global_assignment -name VERILOG_FILE ../../rtl/verilog/or1200/rtl/verilog/or1200_mult_mac.v
set_global_assignment -name VERILOG_FILE ../../rtl/verilog/or1200/rtl/verilog/or1200_ic_fsm.v
set_global_assignment -name VERILOG_FILE ../../rtl/verilog/or1200/rtl/verilog/or1200_amultp2_32x32.v
set_global_assignment -name VERILOG_FILE ../../rtl/verilog/or1200/rtl/verilog/or1200_reg2mem.v
set_global_assignment -name VERILOG_FILE ../../rtl/verilog/or1200/rtl/verilog/or1200_spram_2048x32.v
set_global_assignment -name VERILOG_FILE ../../rtl/verilog/or1200/rtl/verilog/or1200_except.v
set_global_assignment -name VERILOG_FILE ../../rtl/verilog/or1200/rtl/verilog/or1200_top.v
set_global_assignment -name VERILOG_FILE ../../rtl/verilog/or1200/rtl/verilog/or1200_ic_top.v
set_global_assignment -name VERILOG_FILE ../../rtl/verilog/or1200/rtl/verilog/or1200_dc_ram.v
set_global_assignment -name VERILOG_FILE ../../rtl/verilog/or1200/rtl/verilog/or1200_spram_1024x32_bw.v
set_global_assignment -name VERILOG_FILE ../../rtl/verilog/or1200/rtl/verilog/or1200_freeze.v
set_global_assignment -name VERILOG_FILE ../../rtl/verilog/or1200/rtl/verilog/or1200_spram_128x32.v
set_global_assignment -name VERILOG_FILE ../../rtl/verilog/or1200/rtl/verilog/or1200_dc_fsm.v
set_global_assignment -name VERILOG_FILE ../../rtl/verilog/or1200/rtl/verilog/or1200_wb_biu.v
set_global_assignment -name VERILOG_FILE ../../rtl/verilog/or1200/rtl/verilog/or1200_spram_64x22.v
set_global_assignment -name VERILOG_FILE ../../rtl/verilog/or1200/rtl/verilog/or1200_fpu.v
set_global_assignment -name VERILOG_FILE ../../rtl/verilog/or1200/rtl/verilog/or1200_spram.v
set_global_assignment -name VERILOG_FILE ../../rtl/verilog/or1200/rtl/verilog/or1200_spram_32_bw.v
set_global_assignment -name VERILOG_FILE ../../rtl/verilog/or1200/rtl/verilog/or1200_dpram.v
/prj/altera/jtag_top.prj
0,0 → 1,3
set_global_assignment -name SEARCH_PATH /home/javieralso/repos/personales/Proyectos/svn/opencores/minsoc/setup/minsoc/prj/../rtl/verilog/adv_debug_sys/Hardware/jtag/tap/rtl/verilog
set_global_assignment -name VERILOG_FILE /home/javieralso/repos/personales/Proyectos/svn/opencores/minsoc/setup/minsoc/prj/../rtl/verilog/adv_debug_sys/Hardware/jtag/tap/rtl/verilog/tap_top.v
set_global_assignment -name VERILOG_FILE /home/javieralso/repos/personales/Proyectos/svn/opencores/minsoc/setup/minsoc/prj/../rtl/verilog/adv_debug_sys/Hardware/jtag/tap/rtl/verilog/tap_defines.v
/prj/altera/minsoc_bench.prj
0,0 → 1,11
set_global_assignment -name SEARCH_PATH ../../backend
set_global_assignment -name SEARCH_PATH ../../bench/verilog
set_global_assignment -name SEARCH_PATH ../../bench/verilog/vpi
set_global_assignment -name SEARCH_PATH ../../bench/verilog/sim_lib
set_global_assignment -name SEARCH_PATH ../../rtl/verilog
set_global_assignment -name VERILOG_FILE ../../backend/minsoc_bench_defines.v
set_global_assignment -name VERILOG_FILE ../../bench/verilog/minsoc_bench.v
set_global_assignment -name VERILOG_FILE ../../bench/verilog/minsoc_memory_model.v
set_global_assignment -name VERILOG_FILE ../../bench/verilog/vpi/dbg_comm_vpi.v
set_global_assignment -name VERILOG_FILE ../../bench/verilog/sim_lib/fpga_memory_primitives.v
set_global_assignment -name VERILOG_FILE ../../rtl/verilog/timescale.v
/prj/altera/minsoc_top.prj
1,8 → 1,22
set_global_assignment -name VERILOG_FILE ../rtl/verilog/timescale.v
set_global_assignment -name VERILOG_FILE ../rtl/verilog/minsoc_top.v
set_global_assignment -name VERILOG_FILE ../rtl/verilog/minsoc_tc_top.v
set_global_assignment -name VERILOG_FILE ../rtl/verilog/minsoc_onchip_ram_top.v
set_global_assignment -name VERILOG_FILE ../rtl/verilog/minsoc_onchip_ram.v
set_global_assignment -name VERILOG_FILE ../rtl/verilog/minsoc_clock_manager.v
set_global_assignment -name VERILOG_FILE ../rtl/verilog/altera_pll.v
set_global_assignment -name SEARCH_PATH ../backend/
set_global_assignment -name SEARCH_PATH ../../backend
set_global_assignment -name SEARCH_PATH ../../rtl/verilog
set_global_assignment -name SEARCH_PATH ../../rtl/verilog/minsoc_startup
set_global_assignment -name SEARCH_PATH ../../rtl/verilog/or1200/rtl/verilog
set_global_assignment -name SEARCH_PATH ../../rtl/verilog/adv_debug_sys/Hardware/adv_dbg_if/rtl/verilog
set_global_assignment -name SEARCH_PATH ../../rtl/verilog/ethmac/rtl/verilog
set_global_assignment -name SEARCH_PATH ../../rtl/verilog/uart16550/rtl/verilog
set_global_assignment -name VERILOG_FILE ../../backend/minsoc_defines.v
set_global_assignment -name VERILOG_FILE ../../rtl/verilog/timescale.v
set_global_assignment -name VERILOG_FILE ../../rtl/verilog/minsoc_top.v
set_global_assignment -name VERILOG_FILE ../../rtl/verilog/minsoc_tc_top.v
set_global_assignment -name VERILOG_FILE ../../rtl/verilog/minsoc_onchip_ram.v
set_global_assignment -name VERILOG_FILE ../../rtl/verilog/minsoc_onchip_ram_top.v
set_global_assignment -name VERILOG_FILE ../../rtl/verilog/minsoc_clock_manager.v
set_global_assignment -name VERILOG_FILE ../../rtl/verilog/altera_pll.v
set_global_assignment -name VERILOG_FILE ../../rtl/verilog/xilinx_dcm.v
set_global_assignment -name VERILOG_FILE ../../rtl/verilog/minsoc_xilinx_internal_jtag.v
set_global_assignment -name VERILOG_FILE ../../rtl/verilog/minsoc_startup/spi_top.v
set_global_assignment -name VERILOG_FILE ../../rtl/verilog/minsoc_startup/spi_defines.v
set_global_assignment -name VERILOG_FILE ../../rtl/verilog/minsoc_startup/spi_shift.v
set_global_assignment -name VERILOG_FILE ../../rtl/verilog/minsoc_startup/spi_clgen.v
set_global_assignment -name VERILOG_FILE ../../rtl/verilog/minsoc_startup/OR1K_startup_generic.v
/prj/altera/uart_top.prj
0,0 → 1,12
set_global_assignment -name SEARCH_PATH ../../rtl/verilog/uart16550/rtl/verilog
set_global_assignment -name VERILOG_FILE ../../rtl/verilog/uart16550/rtl/verilog/uart_top.v
set_global_assignment -name VERILOG_FILE ../../rtl/verilog/uart16550/rtl/verilog/uart_sync_flops.v
set_global_assignment -name VERILOG_FILE ../../rtl/verilog/uart16550/rtl/verilog/uart_transmitter.v
set_global_assignment -name VERILOG_FILE ../../rtl/verilog/uart16550/rtl/verilog/uart_debug_if.v
set_global_assignment -name VERILOG_FILE ../../rtl/verilog/uart16550/rtl/verilog/uart_wb.v
set_global_assignment -name VERILOG_FILE ../../rtl/verilog/uart16550/rtl/verilog/uart_receiver.v
set_global_assignment -name VERILOG_FILE ../../rtl/verilog/uart16550/rtl/verilog/uart_tfifo.v
set_global_assignment -name VERILOG_FILE ../../rtl/verilog/uart16550/rtl/verilog/uart_regs.v
set_global_assignment -name VERILOG_FILE ../../rtl/verilog/uart16550/rtl/verilog/uart_rfifo.v
set_global_assignment -name VERILOG_FILE ../../rtl/verilog/uart16550/rtl/verilog/uart_defines.v
set_global_assignment -name VERILOG_FILE ../../rtl/verilog/uart16550/rtl/verilog/raminfr.v
/prj/altera/adbg_top.prj
0,0 → 1,11
set_global_assignment -name SEARCH_PATH ../../rtl/verilog/adv_debug_sys/Hardware/adv_dbg_if/rtl/verilog
set_global_assignment -name VERILOG_FILE ../../rtl/verilog/adv_debug_sys/Hardware/adv_dbg_if/rtl/verilog/adbg_wb_biu.v
set_global_assignment -name VERILOG_FILE ../../rtl/verilog/adv_debug_sys/Hardware/adv_dbg_if/rtl/verilog/adbg_wb_module.v
set_global_assignment -name VERILOG_FILE ../../rtl/verilog/adv_debug_sys/Hardware/adv_dbg_if/rtl/verilog/adbg_or1k_module.v
set_global_assignment -name VERILOG_FILE ../../rtl/verilog/adv_debug_sys/Hardware/adv_dbg_if/rtl/verilog/adbg_wb_defines.v
set_global_assignment -name VERILOG_FILE ../../rtl/verilog/adv_debug_sys/Hardware/adv_dbg_if/rtl/verilog/adbg_defines.v
set_global_assignment -name VERILOG_FILE ../../rtl/verilog/adv_debug_sys/Hardware/adv_dbg_if/rtl/verilog/adbg_crc32.v
set_global_assignment -name VERILOG_FILE ../../rtl/verilog/adv_debug_sys/Hardware/adv_dbg_if/rtl/verilog/adbg_or1k_biu.v
set_global_assignment -name VERILOG_FILE ../../rtl/verilog/adv_debug_sys/Hardware/adv_dbg_if/rtl/verilog/adbg_or1k_defines.v
set_global_assignment -name VERILOG_FILE ../../rtl/verilog/adv_debug_sys/Hardware/adv_dbg_if/rtl/verilog/adbg_or1k_status_reg.v
set_global_assignment -name VERILOG_FILE ../../rtl/verilog/adv_debug_sys/Hardware/adv_dbg_if/rtl/verilog/adbg_top.v
/prj/altera/ethmac.prj
1,0 → 26,11
set_global_assignment -name SEARCH_PATH ../rtl/verilog/ethmac/rtl/verilog
set_global_assignment -name SEARCH_PATH ../../rtl/verilog/ethmac/rtl/verilog
set_global_assignment -name VERILOG_FILE ../../rtl/verilog/ethmac/rtl/verilog/eth_cop.v
set_global_assignment -name VERILOG_FILE ../../rtl/verilog/ethmac/rtl/verilog/eth_registers.v
set_global_assignment -name VERILOG_FILE ../../rtl/verilog/ethmac/rtl/verilog/eth_rxethmac.v
set_global_assignment -name VERILOG_FILE ../../rtl/verilog/ethmac/rtl/verilog/eth_miim.v
set_global_assignment -name VERILOG_FILE ../../rtl/verilog/ethmac/rtl/verilog/ethmac.v
set_global_assignment -name VERILOG_FILE ../../rtl/verilog/ethmac/rtl/verilog/eth_rxaddrcheck.v
set_global_assignment -name VERILOG_FILE ../../rtl/verilog/ethmac/rtl/verilog/eth_outputcontrol.v
set_global_assignment -name VERILOG_FILE ../../rtl/verilog/ethmac/rtl/verilog/eth_rxstatem.v
set_global_assignment -name VERILOG_FILE ../../rtl/verilog/ethmac/rtl/verilog/eth_txethmac.v
set_global_assignment -name VERILOG_FILE ../../rtl/verilog/ethmac/rtl/verilog/eth_wishbone.v
set_global_assignment -name VERILOG_FILE ../../rtl/verilog/ethmac/rtl/verilog/eth_maccontrol.v
set_global_assignment -name VERILOG_FILE ../../rtl/verilog/ethmac/rtl/verilog/eth_txstatem.v
set_global_assignment -name VERILOG_FILE ../../rtl/verilog/ethmac/rtl/verilog/ethmac_defines.v
set_global_assignment -name VERILOG_FILE ../../rtl/verilog/ethmac/rtl/verilog/eth_spram_256x32.v
set_global_assignment -name VERILOG_FILE ../../rtl/verilog/ethmac/rtl/verilog/eth_shiftreg.v
set_global_assignment -name VERILOG_FILE ../../rtl/verilog/ethmac/rtl/verilog/eth_clockgen.v
set_global_assignment -name VERILOG_FILE ../../rtl/verilog/ethmac/rtl/verilog/eth_crc.v
set_global_assignment -name VERILOG_FILE ../../rtl/verilog/ethmac/rtl/verilog/eth_rxcounters.v
set_global_assignment -name VERILOG_FILE ../../rtl/verilog/ethmac/rtl/verilog/eth_macstatus.v
set_global_assignment -name VERILOG_FILE ../../rtl/verilog/ethmac/rtl/verilog/eth_random.v
set_global_assignment -name VERILOG_FILE ../../rtl/verilog/ethmac/rtl/verilog/eth_register.v
set_global_assignment -name VERILOG_FILE ../../rtl/verilog/ethmac/rtl/verilog/eth_fifo.v
set_global_assignment -name VERILOG_FILE ../../rtl/verilog/ethmac/rtl/verilog/eth_receivecontrol.v
set_global_assignment -name VERILOG_FILE ../../rtl/verilog/ethmac/rtl/verilog/eth_transmitcontrol.v
set_global_assignment -name VERILOG_FILE ../../rtl/verilog/ethmac/rtl/verilog/eth_txcounters.v
/prj/Makefile
10,11 → 10,12
SIMULATION_FILES = $(addprefix $(SIMULATION_DIR)/, $(addsuffix .src, $(basename $(PROJECTS))))
XILINX_PRJ_FILES = $(addprefix $(XILINX_DIR)/, $(addsuffix .prj, $(basename $(PROJECTS))))
XILINX_XST_FILES = $(addprefix $(XILINX_DIR)/, $(addsuffix .xst, $(basename $(PROJECTS))))
ALTERA_PRJ_FILES = $(addprefix $(ALTERA_DIR)/, $(addsuffix .prj, $(basename $(PROJECTS))))
 
all: $(SIMULATION_DIR)/minsoc.src $(XILINX_PRJ_FILES) $(XILINX_XST_FILES)
all: $(SIMULATION_DIR)/minsoc.src $(XILINX_PRJ_FILES) $(XILINX_XST_FILES) $(ALTERA_PRJ_FILES)
 
clean:
rm -rf $(SIMULATION_DIR)/*.src $(XILINX_DIR)/*.prj $(XILINX_DIR)/*.xst
rm -rf $(SIMULATION_DIR)/*.src $(XILINX_DIR)/*.prj $(XILINX_DIR)/*.xst $(ALTERA_DIR)/*.prj
 
$(XILINX_DIR)/minsoc_top.xst: $(SRC_DIR)/minsoc_top.prj
bash $(SCRIPTS_DIR)/xilinxxst.sh $^ $@ minsoc_top.prj minsoc_top topmodule
28,6 → 29,9
$(XILINX_DIR)/%.prj: $(SRC_DIR)/%.prj
bash $(SCRIPTS_DIR)/xilinxprj.sh $^ $@
 
$(ALTERA_DIR)/%.prj: $(SRC_DIR)/%.prj
bash $(SCRIPTS_DIR)/altprj.sh $^ $@
 
$(SIMULATION_DIR)/minsoc.src: $(SIMULATION_FILES)
cat $(SIMULATION_FILES) > $(SIMULATION_DIR)/minsoc.src
 

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