URL
https://opencores.org/ocsvn/minsoc/minsoc/trunk
Subversion Repositories minsoc
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- This comparison shows the changes necessary to convert path
/minsoc
- from Rev 58 to Rev 57
- ↔ Reverse comparison
Rev 58 → Rev 57
/trunk/rtl/verilog/minsoc_defines.v
132,9 → 132,6
// and GENERIC_CLOCK_DIVISION if NO_CLOCK_DIVISION was not set |
// |
`ifdef GENERIC_FPGA |
`undef FPGA_TAP |
`undef FPGA_CLOCK_DIVISION |
|
`define GENERIC_TAP |
`define GENERIC_MEMORY |
`ifndef NO_CLOCK_DIVISION |
/trunk/bench/verilog/minsoc_bench_defines.v
4,7 → 4,6
//set RTL for simulation, override FPGA specific definitions (JTAG TAP, MEMORY and CLOCK DIVIDER) |
`define GENERIC_FPGA |
`define NO_CLOCK_DIVISION //if commented out, generic clock division is implemented (odd divisors are rounded down) |
`undef NEGATIVE_RESET |
`define POSITIVE_RESET |
//~set RTL for simulation, override FPGA specific definitions (JTAG TAP, MEMORY and CLOCK DIVIDER) |
|