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URL https://opencores.org/ocsvn/minsoc/minsoc/trunk

Subversion Repositories minsoc

Compare Revisions

  • This comparison shows the changes necessary to convert path
    /minsoc
    from Rev 69 to Rev 70
    Reverse comparison

Rev 69 → Rev 70

/trunk/rtl/verilog/timescale.v
0,0 → 1,?rev2len?
`timescale 10ns/1ns
/trunk/backend/spartan3a_dsp_kit/minsoc_bench_defines.v
1,6 → 1,3
 
`timescale 1ns/100ps
 
//set RTL for simulation, override FPGA specific definitions (JTAG TAP, MEMORY and CLOCK DIVIDER)
`define GENERIC_FPGA
`define MEMORY_MODEL //simulation uses a memory model enabling INITIALIZE_MEMORY_MODEL. If you comment this, START_UP might be interesting.
/trunk/backend/std/minsoc_bench_defines.v
1,6 → 1,3
 
`timescale 1ns/100ps
 
//set RTL for simulation, override FPGA specific definitions (JTAG TAP, MEMORY and CLOCK DIVIDER)
`define GENERIC_FPGA
`define MEMORY_MODEL //simulation uses a memory model enabling INITIALIZE_MEMORY_MODEL. If you comment this, START_UP might be interesting.
/trunk/backend/spartan3e_starter_kit/minsoc_bench_defines.v
1,6 → 1,3
 
`timescale 1ns/100ps
 
//set RTL for simulation, override FPGA specific definitions (JTAG TAP, MEMORY and CLOCK DIVIDER)
`define GENERIC_FPGA
`define MEMORY_MODEL //simulation uses a memory model enabling INITIALIZE_MEMORY_MODEL. If you comment this, START_UP might be interesting.
/trunk/backend/spartan3e_starter_kit_eth/minsoc_bench_defines.v
1,6 → 1,3
 
`timescale 1ns/100ps
 
//set RTL for simulation, override FPGA specific definitions (JTAG TAP, MEMORY and CLOCK DIVIDER)
`define GENERIC_FPGA
`define MEMORY_MODEL //simulation uses a memory model enabling INITIALIZE_MEMORY_MODEL. If you comment this, START_UP might be interesting.
/trunk/sim/bin/minsoc_verilog_files.txt
16,6 → 16,7
../../bench/verilog/minsoc_memory_model.v
../../bench/verilog/vpi/dbg_comm_vpi.v
../../bench/verilog/sim_lib/fpga_memory_primitives.v
../../rtl/verilog/timescale.v
../../rtl/verilog/minsoc_top.v
../../rtl/verilog/minsoc_startup/spi_top.v
../../rtl/verilog/minsoc_startup/spi_defines.v
/trunk/sim/modelsim/prepare_modelsim.sh
0,0 → 1,4
#!/bin/bash
 
vlib minsoc
vmap minsoc ./minsoc
trunk/sim/modelsim/prepare_modelsim.sh Property changes : Added: svn:executable ## -0,0 +1 ## +* \ No newline at end of property Index: trunk/sim/modelsim/run_sim.sh =================================================================== --- trunk/sim/modelsim/run_sim.sh (nonexistent) +++ trunk/sim/modelsim/run_sim.sh (revision 70) @@ -0,0 +1,3 @@ +#!/bin/bash + +vsim -lib minsoc minsoc_bench -pli ../../bench/verilog/vpi/jp-io-vpi.so +file_name=$1
trunk/sim/modelsim/run_sim.sh Property changes : Added: svn:executable ## -0,0 +1 ## +* \ No newline at end of property Index: trunk/sim/modelsim/compile_design.sh =================================================================== --- trunk/sim/modelsim/compile_design.sh (nonexistent) +++ trunk/sim/modelsim/compile_design.sh (revision 70) @@ -0,0 +1,3 @@ +#!/bin/bash + +vlog -incr -work minsoc -f ../bin/minsoc_verilog_files.txt \ No newline at end of file
trunk/sim/modelsim/compile_design.sh Property changes : Added: svn:executable ## -0,0 +1 ## +* \ No newline at end of property

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