OpenCores
URL https://opencores.org/ocsvn/minsoc/minsoc/trunk

Subversion Repositories minsoc

Compare Revisions

  • This comparison shows the changes necessary to convert path
    /minsoc
    from Rev 89 to Rev 90
    Reverse comparison

Rev 89 → Rev 90

/trunk/prj/sim/minsoc_top.src
1,7 → 1,4
+incdir+/home/raul/or1k/minsoc/prj/../backend
+incdir+/home/raul/or1k/minsoc/prj/../bench/verilog
+incdir+/home/raul/or1k/minsoc/prj/../bench/verilog/vpi
+incdir+/home/raul/or1k/minsoc/prj/../bench/verilog/sim_lib
+incdir+/home/raul/or1k/minsoc/prj/../rtl/verilog
+incdir+/home/raul/or1k/minsoc/prj/../rtl/verilog/minsoc_startup
+incdir+/home/raul/or1k/minsoc/prj/../rtl/verilog/or1200/rtl/verilog
/trunk/prj/sim/minsoc.src
10,9 → 10,6
/home/raul/or1k/minsoc/prj/../bench/verilog/sim_lib/fpga_memory_primitives.v
/home/raul/or1k/minsoc/prj/../rtl/verilog/timescale.v
+incdir+/home/raul/or1k/minsoc/prj/../backend
+incdir+/home/raul/or1k/minsoc/prj/../bench/verilog
+incdir+/home/raul/or1k/minsoc/prj/../bench/verilog/vpi
+incdir+/home/raul/or1k/minsoc/prj/../bench/verilog/sim_lib
+incdir+/home/raul/or1k/minsoc/prj/../rtl/verilog
+incdir+/home/raul/or1k/minsoc/prj/../rtl/verilog/minsoc_startup
+incdir+/home/raul/or1k/minsoc/prj/../rtl/verilog/or1200/rtl/verilog
/trunk/prj/xilinx/minsoc_top.xst
1,6 → 1,6
set -tmpdir ./xst
run
-vlgincdir { "/home/raul/or1k/minsoc/prj/../backend" "/home/raul/or1k/minsoc/prj/../bench/verilog" "/home/raul/or1k/minsoc/prj/../bench/verilog/vpi" "/home/raul/or1k/minsoc/prj/../bench/verilog/sim_lib" "/home/raul/or1k/minsoc/prj/../rtl/verilog" "/home/raul/or1k/minsoc/prj/../rtl/verilog/minsoc_startup" "/home/raul/or1k/minsoc/prj/../rtl/verilog/or1200/rtl/verilog" "/home/raul/or1k/minsoc/prj/../rtl/verilog/adv_debug_sys/Hardware/adv_dbg_if/rtl/verilog" "/home/raul/or1k/minsoc/prj/../rtl/verilog/ethmac/rtl/verilog" "/home/raul/or1k/minsoc/prj/../rtl/verilog/uart16550/rtl/verilog" }
-vlgincdir { "/home/raul/or1k/minsoc/prj/../backend" "/home/raul/or1k/minsoc/prj/../rtl/verilog" "/home/raul/or1k/minsoc/prj/../rtl/verilog/minsoc_startup" "/home/raul/or1k/minsoc/prj/../rtl/verilog/or1200/rtl/verilog" "/home/raul/or1k/minsoc/prj/../rtl/verilog/adv_debug_sys/Hardware/adv_dbg_if/rtl/verilog" "/home/raul/or1k/minsoc/prj/../rtl/verilog/ethmac/rtl/verilog" "/home/raul/or1k/minsoc/prj/../rtl/verilog/uart16550/rtl/verilog" }
-ifn /home/raul/or1k/minsoc/prj/../prj/xilinx/minsoc_top.prj
-ifmt Verilog
-ofn minsoc_top

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