URL
https://opencores.org/ocsvn/minsoc/minsoc/trunk
Subversion Repositories minsoc
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- from Rev 12 to Rev 13
- ↔ Reverse comparison
Rev 12 → Rev 13
/minsoc/trunk/backend/spartan3e_starter_kit.ucf
11,40 → 11,40
# |
# UART serial port (RS232 DCE) - connector DB9 female. |
# |
#NET "uart_srx" LOC = "R7" | IOSTANDARD = LVTTL ; |
#NET "uart_stx" LOC = "M14" | IOSTANDARD = LVTTL | DRIVE = 8 | SLEW = SLOW ; |
NET "uart_srx" LOC = "R7"; |
NET "uart_stx" LOC = "M14" | DRIVE = 8 | SLEW = SLOW ; |
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########################### |
## |
## ETH |
## |
NET "eth_txd(3)" LOC = "t5"; |
NET "eth_txd(2)" LOC = "r5"; |
NET "eth_txd(1)" LOC = "t15"; |
NET "eth_txd(0)" LOC = "r11"; |
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NET "eth_tx_en" LOC = "p15"; |
NET "eth_tx_clk" LOC = "t7" | CLOCK_DEDICATED_ROUTE = FALSE; |
NET "eth_tx_er" LOC = "r6"; |
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NET "eth_rxd(3)" LOC = "v14"; |
NET "eth_rxd(2)" LOC = "u11"; |
NET "eth_rxd(1)" LOC = "t11"; |
NET "eth_rxd(0)" LOC = "v8"; |
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NET "eth_rx_er" LOC = "u14"; |
NET "eth_rx_dv" LOC = "v2"; |
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NET "eth_rx_clk" LOC = "v3" | CLOCK_DEDICATED_ROUTE = FALSE; |
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NET "eth_mdio" LOC = "u5" | PULLUP; |
NET "eth_crs" LOC = "u13"; |
NET "eth_col" LOC = "u6"; |
NET "eth_mdc" LOC = "p9"; |
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NET "eth_trste" LOC = "p13"; #put it to a non connected FPGA pin (starter kit schematic BANK3) |
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NET "eth_fds_mdint" LOC = "r13" | PULLUP; #put it to a non connected FPGA pin (starter kit schematic BANK3)(pullup not to generate interrupts) |
#NET "eth_txd(3)" LOC = "t5"; |
#NET "eth_txd(2)" LOC = "r5"; |
#NET "eth_txd(1)" LOC = "t15"; |
#NET "eth_txd(0)" LOC = "r11"; |
# |
#NET "eth_tx_en" LOC = "p15"; |
#NET "eth_tx_clk" LOC = "t7" | CLOCK_DEDICATED_ROUTE = FALSE; |
#NET "eth_tx_er" LOC = "r6"; |
# |
#NET "eth_rxd(3)" LOC = "v14"; |
#NET "eth_rxd(2)" LOC = "u11"; |
#NET "eth_rxd(1)" LOC = "t11"; |
#NET "eth_rxd(0)" LOC = "v8"; |
# |
#NET "eth_rx_er" LOC = "u14"; |
#NET "eth_rx_dv" LOC = "v2"; |
# |
#NET "eth_rx_clk" LOC = "v3" | CLOCK_DEDICATED_ROUTE = FALSE; |
# |
#NET "eth_mdio" LOC = "u5" | PULLUP; |
#NET "eth_crs" LOC = "u13"; |
#NET "eth_col" LOC = "u6"; |
#NET "eth_mdc" LOC = "p9"; |
# |
#NET "eth_trste" LOC = "p13"; #put it to a non connected FPGA pin (starter kit schematic BANK3) |
# |
#NET "eth_fds_mdint" LOC = "r13" | PULLUP; #put it to a non connected FPGA pin (starter kit schematic BANK3)(pullup not to generate interrupts) |
########################### |
|
# |
51,10 → 51,10
# JTAG signals - on J4 6-pin accessory header. |
# |
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#NET "jtag_tms" LOC = "D7" | IOSTANDARD = LVCMOS33 | PULLDOWN ; |
#NET "jtag_tdi" LOC = "C7" | IOSTANDARD = LVCMOS33 | PULLDOWN ; |
#NET "jtag_tdo" LOC = "F8" | IOSTANDARD = LVCMOS33 | SLEW = FAST | DRIVE = 8 ; |
#NET "jtag_tck" LOC = "E8" | IOSTANDARD = LVCMOS33 | PULLDOWN ; |
#NET "jtag_tms" LOC = "D7" | PULLDOWN ; |
#NET "jtag_tdi" LOC = "C7" | PULLDOWN ; |
#NET "jtag_tdo" LOC = "F8" | SLEW = FAST | DRIVE = 8 ; |
#NET "jtag_tck" LOC = "E8" | PULLDOWN ; |
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#net "jtag_gnd" loc = "k2"; #put it to a non connected FPGA pin (starter kit schematic BANK3) |
#net "jtag_vref" loc = "k7"; #put it to a non connected FPGA pin (starter kit schematic BANK3) |