OpenCores
URL https://opencores.org/ocsvn/minsoc/minsoc/trunk

Subversion Repositories minsoc

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  • This comparison shows the changes necessary to convert path 
    /
    from Rev 87 to Rev 88
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  •

Rev 87 → Rev 88

/minsoc/trunk/rtl/verilog/xilinx_dcm.v
53,6 → 53,8
wire CLKFB_IN;
wire CLKDV_BUF;
 
`ifdef XILINX_FPGA
 
IBUFG CLKIN_IBUFG_INST (
.I(CLKIN_IN),
.O(CLKIN_IBUFG)
218,6 → 220,7
);
 
`endif // !XILINX_DLL/XILINX_DCM/XILINX_DCM_SP/XILINX_DCM_ADV
`endif // !XILINX_FPGA
 
 
endmodule
/minsoc/trunk/backend/spartan3a_dsp_kit/minsoc_defines.v
139,6 → 139,8
`ifdef GENERIC_FPGA
`undef FPGA_TAP
`undef FPGA_CLOCK_DIVISION
`undef XILINX_FPGA
`undef SPARTAN3A
 
`define GENERIC_TAP
`define GENERIC_MEMORY
/minsoc/trunk/backend/spartan3e_starter_kit/minsoc_defines.v
139,6 → 139,8
`ifdef GENERIC_FPGA
`undef FPGA_TAP
`undef FPGA_CLOCK_DIVISION
`undef XILINX_FPGA
`undef SPARTAN3E
 
`define GENERIC_TAP
`define GENERIC_MEMORY
/minsoc/trunk/backend/spartan3e_starter_kit_eth/minsoc_defines.v
139,6 → 139,8
`ifdef GENERIC_FPGA
`undef FPGA_TAP
`undef FPGA_CLOCK_DIVISION
`undef XILINX_FPGA
`undef SPARTAN3E
 
`define GENERIC_TAP
`define GENERIC_MEMORY
/minsoc/trunk/syn/xilinx/Makefile
8,6 → 8,7
OR1200_RTL = ${MINSOC_RTL}/or1200/rtl/verilog
ETH_RTL = ${MINSOC_RTL}/ethmac/rtl/verilog
BUILD_SUPPORT = $(MINSOC)/syn/buildSupport
PROJECT_DIR = $(MINSOC)/prj/xilinx
 
help:
@echo " all: Synthesize and implement the SoC, then generate a bit stream"
46,27 → 47,27
rm -rf *.ngc *.ncd *.ngd *.bit
make clean
 
minsoc_top.ngc: ${MINSOC_RTL}/*.v ${MINSOC_DEFINES}/minsoc_defines.v $(BUILD_SUPPORT)/minsoc_top.xst $(BUILD_SUPPORT)/minsoc_top.prj
minsoc_top.ngc: ${MINSOC_RTL}/*.v ${MINSOC_DEFINES}/minsoc_defines.v $(BUILD_SUPPORT)/minsoc_top.xst $(PROJECT_DIR)/minsoc_top.prj
make prepare
xst -ifn "$(BUILD_SUPPORT)/minsoc_top.xst"
 
uart: uart_top.ngc
uart_top.ngc: ${UART_RTL}/*.v $(BUILD_SUPPORT)/uart_top.xst $(BUILD_SUPPORT)/uart_top.prj
uart_top.ngc: ${UART_RTL}/*.v $(BUILD_SUPPORT)/uart_top.xst $(PROJECT_DIR)/uart_top.prj
make prepare
xst -ifn "$(BUILD_SUPPORT)/uart_top.xst"
 
eth: ethmac.ngc
ethmac.ngc: ${ETH_RTL}/*.v $(BUILD_SUPPORT)/ethmac.xst $(BUILD_SUPPORT)/ethmac.prj
ethmac.ngc: ${ETH_RTL}/*.v $(BUILD_SUPPORT)/ethmac.xst $(PROJECT_DIR)/ethmac.prj
make prepare
xst -ifn "$(BUILD_SUPPORT)/ethmac.xst"
 
debug: adbg_top.ngc
adbg_top.ngc: ${DEBUG_RTL}/*.v $(BUILD_SUPPORT)/adbg_top.xst $(BUILD_SUPPORT)/adbg_top.prj
adbg_top.ngc: ${DEBUG_RTL}/*.v $(BUILD_SUPPORT)/adbg_top.xst $(PROJECT_DIR)/adbg_top.prj
make prepare
xst -ifn "$(BUILD_SUPPORT)/adbg_top.xst"
 
or1200: or1200_top.ngc
or1200_top.ngc: ${OR1200_RTL}/*.v $(BUILD_SUPPORT)/or1200_top.xst $(BUILD_SUPPORT)/or1200_top.prj
or1200_top.ngc: ${OR1200_RTL}/*.v $(BUILD_SUPPORT)/or1200_top.xst $(PROJECT_DIR)/or1200_top.prj
make prepare
xst -ifn "$(BUILD_SUPPORT)/or1200_top.xst"
 
/minsoc/trunk/prj/scripts/xilinxprj.sh
18,6 → 18,7
echo "Third argument should be the destintion file for the source inclusions."
exit 1
fi
echo -n "" > $SRC_OUTPUT
 
source $PROJECT
 
/minsoc/trunk/prj/scripts/xilinxxst.sh
20,6 → 20,7
echo "Second argument should be the destintion file for the directory inclusions."
exit 1
fi
echo -n "" > $DIR_OUTPUT
 
source $PROJECT
 
36,7 → 37,7
DIR_PATH="$DIR_PATH }"
echo $DIR_PATH >> $DIR_OUTPUT
 
echo "-ifn $MINSOC_DIR/prj/${PROJECT_FILE}" >> $DIR_OUTPUT
echo "-ifn $MINSOC_DIR/prj/xilinx/${PROJECT_FILE}" >> $DIR_OUTPUT
echo "-ifmt Verilog" >> $DIR_OUTPUT
echo "-ofn ${TOP_MODULE_NAME}" >> $DIR_OUTPUT
echo "-ofmt NGC" >> $DIR_OUTPUT
/minsoc/trunk/prj/scripts/simprj.sh
17,6 → 17,7
echo "Second argument should be the destintion file for the file and directory inclusions."
exit 1
fi
echo -n "" > $OUTPUT
 
source $PROJECT
 
/minsoc/trunk/prj/src/minsoc_bench.prj
0,0 → 1,8
PROJECT_DIR=(backend bench/verilog bench/verilog/vpi bench/verilog/sim_lib rtl/verilog)
PROJECT_SRC=(minsoc_bench_defines.v
minsoc_bench.v
minsoc_memory_model.v
dbg_comm_vpi.v
fpga_memory_primitives.v
timescale.v)
 
/minsoc/trunk/prj/src/minsoc_top.prj
1,18 → 1,17
PROJECT_DIR=(backend bench/verilog bench/verilog/vpi bench/verilog/sim_lib rtl/verilog rtl/verilog/minsoc_startup)
PROJECT_DIR=(backend bench/verilog bench/verilog/vpi bench/verilog/sim_lib rtl/verilog rtl/verilog/minsoc_startup rtl/verilog/or1200/rtl/verilog rtl/verilog/adv_debug_sys/Hardware/adv_dbg_if/rtl/verilog rtl/verilog/ethmac/rtl/verilog rtl/verilog/uart16550/rtl/verilog)
PROJECT_SRC=(minsoc_defines.v
minsoc_bench_defines.v
minsoc_bench.v
minsoc_memory_model.v
dbg_comm_vpi.v
fpga_memory_primitives.v
timescale.v
minsoc_top.v
minsoc_tc_top.v
minsoc_onchip_ram.v
minsoc_onchip_ram_top.v
minsoc_clock_manager.v
altera_pll.v
xilinx_dcm.v
minsoc_xilinx_internal_jtag.v
spi_top.v
spi_defines.v
spi_shift.v
spi_clgen.v
OR1K_startup_generic.v
minsoc_tc_top.v
minsoc_onchip_ram.v
minsoc_clock_manager.v
minsoc_onchip_ram_top.v)
OR1K_startup_generic.v)
 
/minsoc/trunk/prj/sim/minsoc_top.src
4,20 → 4,25
+incdir+/home/raul/or1k/minsoc/prj/../bench/verilog/sim_lib
+incdir+/home/raul/or1k/minsoc/prj/../rtl/verilog
+incdir+/home/raul/or1k/minsoc/prj/../rtl/verilog/minsoc_startup
+incdir+/home/raul/or1k/minsoc/prj/../rtl/verilog/or1200/rtl/verilog
+incdir+/home/raul/or1k/minsoc/prj/../rtl/verilog/adv_debug_sys/Hardware/adv_dbg_if/rtl/verilog
+incdir+/home/raul/or1k/minsoc/prj/../rtl/verilog/ethmac/rtl/verilog
+incdir+/home/raul/or1k/minsoc/prj/../rtl/verilog/uart16550/rtl/verilog
/home/raul/or1k/minsoc/prj/../backend/minsoc_defines.v
/home/raul/or1k/minsoc/prj/../backend/minsoc_bench_defines.v
/home/raul/or1k/minsoc/prj/../bench/verilog/minsoc_bench.v
/home/raul/or1k/minsoc/prj/../bench/verilog/minsoc_memory_model.v
/home/raul/or1k/minsoc/prj/../bench/verilog/vpi/dbg_comm_vpi.v
/home/raul/or1k/minsoc/prj/../bench/verilog/sim_lib/fpga_memory_primitives.v
/home/raul/or1k/minsoc/prj/../rtl/verilog/timescale.v
/home/raul/or1k/minsoc/prj/../rtl/verilog/or1200/rtl/verilog/timescale.v
/home/raul/or1k/minsoc/prj/../rtl/verilog/ethmac/rtl/verilog/timescale.v
/home/raul/or1k/minsoc/prj/../rtl/verilog/uart16550/rtl/verilog/timescale.v
/home/raul/or1k/minsoc/prj/../rtl/verilog/minsoc_top.v
/home/raul/or1k/minsoc/prj/../rtl/verilog/minsoc_tc_top.v
/home/raul/or1k/minsoc/prj/../rtl/verilog/minsoc_onchip_ram.v
/home/raul/or1k/minsoc/prj/../rtl/verilog/minsoc_onchip_ram_top.v
/home/raul/or1k/minsoc/prj/../rtl/verilog/minsoc_clock_manager.v
/home/raul/or1k/minsoc/prj/../rtl/verilog/altera_pll.v
/home/raul/or1k/minsoc/prj/../rtl/verilog/xilinx_dcm.v
/home/raul/or1k/minsoc/prj/../rtl/verilog/minsoc_xilinx_internal_jtag.v
/home/raul/or1k/minsoc/prj/../rtl/verilog/minsoc_startup/spi_top.v
/home/raul/or1k/minsoc/prj/../rtl/verilog/minsoc_startup/spi_defines.v
/home/raul/or1k/minsoc/prj/../rtl/verilog/minsoc_startup/spi_shift.v
/home/raul/or1k/minsoc/prj/../rtl/verilog/minsoc_startup/spi_clgen.v
/home/raul/or1k/minsoc/prj/../rtl/verilog/minsoc_startup/OR1K_startup_generic.v
/home/raul/or1k/minsoc/prj/../rtl/verilog/minsoc_tc_top.v
/home/raul/or1k/minsoc/prj/../rtl/verilog/minsoc_onchip_ram.v
/home/raul/or1k/minsoc/prj/../rtl/verilog/minsoc_clock_manager.v
/home/raul/or1k/minsoc/prj/../rtl/verilog/minsoc_onchip_ram_top.v
/minsoc/trunk/prj/sim/minsoc.src
3,8 → 3,6
+incdir+/home/raul/or1k/minsoc/prj/../bench/verilog/vpi
+incdir+/home/raul/or1k/minsoc/prj/../bench/verilog/sim_lib
+incdir+/home/raul/or1k/minsoc/prj/../rtl/verilog
+incdir+/home/raul/or1k/minsoc/prj/../rtl/verilog/minsoc_startup
/home/raul/or1k/minsoc/prj/../backend/minsoc_defines.v
/home/raul/or1k/minsoc/prj/../backend/minsoc_bench_defines.v
/home/raul/or1k/minsoc/prj/../bench/verilog/minsoc_bench.v
/home/raul/or1k/minsoc/prj/../bench/verilog/minsoc_memory_model.v
11,16 → 9,34
/home/raul/or1k/minsoc/prj/../bench/verilog/vpi/dbg_comm_vpi.v
/home/raul/or1k/minsoc/prj/../bench/verilog/sim_lib/fpga_memory_primitives.v
/home/raul/or1k/minsoc/prj/../rtl/verilog/timescale.v
+incdir+/home/raul/or1k/minsoc/prj/../backend
+incdir+/home/raul/or1k/minsoc/prj/../bench/verilog
+incdir+/home/raul/or1k/minsoc/prj/../bench/verilog/vpi
+incdir+/home/raul/or1k/minsoc/prj/../bench/verilog/sim_lib
+incdir+/home/raul/or1k/minsoc/prj/../rtl/verilog
+incdir+/home/raul/or1k/minsoc/prj/../rtl/verilog/minsoc_startup
+incdir+/home/raul/or1k/minsoc/prj/../rtl/verilog/or1200/rtl/verilog
+incdir+/home/raul/or1k/minsoc/prj/../rtl/verilog/adv_debug_sys/Hardware/adv_dbg_if/rtl/verilog
+incdir+/home/raul/or1k/minsoc/prj/../rtl/verilog/ethmac/rtl/verilog
+incdir+/home/raul/or1k/minsoc/prj/../rtl/verilog/uart16550/rtl/verilog
/home/raul/or1k/minsoc/prj/../backend/minsoc_defines.v
/home/raul/or1k/minsoc/prj/../rtl/verilog/timescale.v
/home/raul/or1k/minsoc/prj/../rtl/verilog/or1200/rtl/verilog/timescale.v
/home/raul/or1k/minsoc/prj/../rtl/verilog/ethmac/rtl/verilog/timescale.v
/home/raul/or1k/minsoc/prj/../rtl/verilog/uart16550/rtl/verilog/timescale.v
/home/raul/or1k/minsoc/prj/../rtl/verilog/minsoc_top.v
/home/raul/or1k/minsoc/prj/../rtl/verilog/minsoc_tc_top.v
/home/raul/or1k/minsoc/prj/../rtl/verilog/minsoc_onchip_ram.v
/home/raul/or1k/minsoc/prj/../rtl/verilog/minsoc_onchip_ram_top.v
/home/raul/or1k/minsoc/prj/../rtl/verilog/minsoc_clock_manager.v
/home/raul/or1k/minsoc/prj/../rtl/verilog/altera_pll.v
/home/raul/or1k/minsoc/prj/../rtl/verilog/xilinx_dcm.v
/home/raul/or1k/minsoc/prj/../rtl/verilog/minsoc_xilinx_internal_jtag.v
/home/raul/or1k/minsoc/prj/../rtl/verilog/minsoc_startup/spi_top.v
/home/raul/or1k/minsoc/prj/../rtl/verilog/minsoc_startup/spi_defines.v
/home/raul/or1k/minsoc/prj/../rtl/verilog/minsoc_startup/spi_shift.v
/home/raul/or1k/minsoc/prj/../rtl/verilog/minsoc_startup/spi_clgen.v
/home/raul/or1k/minsoc/prj/../rtl/verilog/minsoc_startup/OR1K_startup_generic.v
/home/raul/or1k/minsoc/prj/../rtl/verilog/minsoc_tc_top.v
/home/raul/or1k/minsoc/prj/../rtl/verilog/minsoc_onchip_ram.v
/home/raul/or1k/minsoc/prj/../rtl/verilog/minsoc_clock_manager.v
/home/raul/or1k/minsoc/prj/../rtl/verilog/minsoc_onchip_ram_top.v
+incdir+/home/raul/or1k/minsoc/prj/../rtl/verilog/or1200/rtl/verilog
/home/raul/or1k/minsoc/prj/../rtl/verilog/or1200/rtl/verilog/or1200_spram_512x20.v
/home/raul/or1k/minsoc/prj/../rtl/verilog/or1200/rtl/verilog/or1200_spram_64x24.v
/minsoc/trunk/prj/xilinx/or1200_top.xst
1,7 → 1,7
set -tmpdir ./xst
run
-vlgincdir { "/home/raul/or1k/minsoc/prj/../rtl/verilog/or1200/rtl/verilog" }
-ifn /home/raul/or1k/minsoc/prj/../prj/or1200_top.prj
-ifn /home/raul/or1k/minsoc/prj/../prj/xilinx/or1200_top.prj
-ifmt Verilog
-ofn or1200_top
-ofmt NGC
/minsoc/trunk/prj/xilinx/jtag_top.xst
1,7 → 1,7
set -tmpdir ./xst
run
-vlgincdir { "/home/raul/or1k/minsoc/prj/../rtl/verilog/adv_debug_sys/Hardware/jtag/tap/rtl/verilog" }
-ifn /home/raul/or1k/minsoc/prj/../prj/jtag_top.prj
-ifn /home/raul/or1k/minsoc/prj/../prj/xilinx/jtag_top.prj
-ifmt Verilog
-ofn jtag_top
-ofmt NGC
/minsoc/trunk/prj/xilinx/minsoc_top.prj
1,20 → 1,21
`include "/home/raul/or1k/minsoc/prj/../backend/minsoc_defines.v"
`include "/home/raul/or1k/minsoc/prj/../backend/minsoc_bench_defines.v"
`include "/home/raul/or1k/minsoc/prj/../bench/verilog/minsoc_bench.v"
`include "/home/raul/or1k/minsoc/prj/../bench/verilog/minsoc_memory_model.v"
`include "/home/raul/or1k/minsoc/prj/../bench/verilog/vpi/dbg_comm_vpi.v"
`include "/home/raul/or1k/minsoc/prj/../bench/verilog/sim_lib/fpga_memory_primitives.v"
`include "/home/raul/or1k/minsoc/prj/../rtl/verilog/timescale.v"
`include "/home/raul/or1k/minsoc/prj/../rtl/verilog/or1200/rtl/verilog/timescale.v"
`include "/home/raul/or1k/minsoc/prj/../rtl/verilog/ethmac/rtl/verilog/timescale.v"
`include "/home/raul/or1k/minsoc/prj/../rtl/verilog/uart16550/rtl/verilog/timescale.v"
`include "/home/raul/or1k/minsoc/prj/../rtl/verilog/minsoc_top.v"
`include "/home/raul/or1k/minsoc/prj/../rtl/verilog/minsoc_tc_top.v"
`include "/home/raul/or1k/minsoc/prj/../rtl/verilog/minsoc_onchip_ram.v"
`include "/home/raul/or1k/minsoc/prj/../rtl/verilog/minsoc_onchip_ram_top.v"
`include "/home/raul/or1k/minsoc/prj/../rtl/verilog/minsoc_clock_manager.v"
`include "/home/raul/or1k/minsoc/prj/../rtl/verilog/altera_pll.v"
`include "/home/raul/or1k/minsoc/prj/../rtl/verilog/xilinx_dcm.v"
`include "/home/raul/or1k/minsoc/prj/../rtl/verilog/minsoc_xilinx_internal_jtag.v"
`include "/home/raul/or1k/minsoc/prj/../rtl/verilog/minsoc_startup/spi_top.v"
`include "/home/raul/or1k/minsoc/prj/../rtl/verilog/minsoc_startup/spi_defines.v"
`include "/home/raul/or1k/minsoc/prj/../rtl/verilog/minsoc_startup/spi_shift.v"
`include "/home/raul/or1k/minsoc/prj/../rtl/verilog/minsoc_startup/spi_clgen.v"
`include "/home/raul/or1k/minsoc/prj/../rtl/verilog/minsoc_startup/OR1K_startup_generic.v"
`include "/home/raul/or1k/minsoc/prj/../rtl/verilog/minsoc_tc_top.v"
`include "/home/raul/or1k/minsoc/prj/../rtl/verilog/minsoc_onchip_ram.v"
`include "/home/raul/or1k/minsoc/prj/../rtl/verilog/minsoc_clock_manager.v"
`include "/home/raul/or1k/minsoc/prj/../rtl/verilog/minsoc_onchip_ram_top.v"
`include "/home/raul/or1k/minsoc/prj/src/blackboxes/adbg_top.v"
`include "/home/raul/or1k/minsoc/prj/src/blackboxes/ethmac.v"
`include "/home/raul/or1k/minsoc/prj/src/blackboxes/or1200_top.v"
/minsoc/trunk/prj/xilinx/minsoc_top.xst
1,7 → 1,7
set -tmpdir ./xst
run
-vlgincdir { "/home/raul/or1k/minsoc/prj/../backend" "/home/raul/or1k/minsoc/prj/../bench/verilog" "/home/raul/or1k/minsoc/prj/../bench/verilog/vpi" "/home/raul/or1k/minsoc/prj/../bench/verilog/sim_lib" "/home/raul/or1k/minsoc/prj/../rtl/verilog" "/home/raul/or1k/minsoc/prj/../rtl/verilog/minsoc_startup" }
-ifn /home/raul/or1k/minsoc/prj/../prj/minsoc_top.prj
-vlgincdir { "/home/raul/or1k/minsoc/prj/../backend" "/home/raul/or1k/minsoc/prj/../bench/verilog" "/home/raul/or1k/minsoc/prj/../bench/verilog/vpi" "/home/raul/or1k/minsoc/prj/../bench/verilog/sim_lib" "/home/raul/or1k/minsoc/prj/../rtl/verilog" "/home/raul/or1k/minsoc/prj/../rtl/verilog/minsoc_startup" "/home/raul/or1k/minsoc/prj/../rtl/verilog/or1200/rtl/verilog" "/home/raul/or1k/minsoc/prj/../rtl/verilog/adv_debug_sys/Hardware/adv_dbg_if/rtl/verilog" "/home/raul/or1k/minsoc/prj/../rtl/verilog/ethmac/rtl/verilog" "/home/raul/or1k/minsoc/prj/../rtl/verilog/uart16550/rtl/verilog" }
-ifn /home/raul/or1k/minsoc/prj/../prj/xilinx/minsoc_top.prj
-ifmt Verilog
-ofn minsoc_top
-ofmt NGC
/minsoc/trunk/prj/xilinx/uart_top.xst
1,7 → 1,7
set -tmpdir ./xst
run
-vlgincdir { "/home/raul/or1k/minsoc/prj/../rtl/verilog/uart16550/rtl/verilog" }
-ifn /home/raul/or1k/minsoc/prj/../prj/uart_top.prj
-ifn /home/raul/or1k/minsoc/prj/../prj/xilinx/uart_top.prj
-ifmt Verilog
-ofn uart_top
-ofmt NGC
/minsoc/trunk/prj/xilinx/adbg_top.xst
1,7 → 1,7
set -tmpdir ./xst
run
-vlgincdir { "/home/raul/or1k/minsoc/prj/../rtl/verilog/adv_debug_sys/Hardware/adv_dbg_if/rtl/verilog" }
-ifn /home/raul/or1k/minsoc/prj/../prj/adbg_top.prj
-ifn /home/raul/or1k/minsoc/prj/../prj/xilinx/adbg_top.prj
-ifmt Verilog
-ofn adbg_top
-ofmt NGC
/minsoc/trunk/prj/xilinx/ethmac.xst
1,7 → 1,7
set -tmpdir ./xst
run
-vlgincdir { "/home/raul/or1k/minsoc/prj/../rtl/verilog/ethmac/rtl/verilog" }
-ifn /home/raul/or1k/minsoc/prj/../prj/ethmac.prj
-ifn /home/raul/or1k/minsoc/prj/../prj/xilinx/ethmac.prj
-ifmt Verilog
-ofn ethmac
-ofmt NGC
/minsoc/trunk/prj/Makefile
1,4 → 1,4
PROJECTS = minsoc_top.prj or1200_top.prj adbg_top.prj jtag_top.prj uart_top.prj ethmac.prj
PROJECTS = minsoc_bench.prj minsoc_top.prj or1200_top.prj adbg_top.prj jtag_top.prj uart_top.prj ethmac.prj
 
SRC_DIR = src
SCRIPTS_DIR = scripts

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