OpenCores
URL https://opencores.org/ocsvn/minsoc/minsoc/trunk

Subversion Repositories minsoc

Compare Revisions

  • This comparison shows the changes necessary to convert path 
    /minsoc/branches/rc-1.0/sw/drivers
    from Rev 80 to Rev 109
    ↔ Reverse comparison
  •

Rev 80 → Rev 109

/eth.c
0,0 → 1,99
#include <board.h>
#include <support.h>
#include "eth.h"
 
int eth_tx_done;
int eth_rx_done;
int eth_rx_len;
unsigned char eth_tx_packet[1536]; //max length
unsigned char eth_rx_packet[1536];
unsigned char * eth_tx_data;
unsigned char * eth_rx_data;
 
void eth_recv_ack(void)
{
eth_rx_done = 0;
eth_rx_len = 0;
//accept further data (reset RXBD to empty)
REG32(ETH_BASE + ETH_RXBD0L) = RX_READY; //len = 0 | IRQ & WR = 1 | EMPTY = 1
}
 
void eth_init()
{
//TXEN & RXEN = 1; PAD & CRC = 1; FULLD = 1
REG32(ETH_BASE + ETH_MODER) = ETH_TXEN | ETH_RXEN | ETH_PAD | ETH_CRCEN | ETH_FULLD;
//PHY Address = 0x001
REG32(ETH_BASE + ETH_MIIADDRESS) = 0x00000001;
 
//enable all interrupts
REG32(ETH_BASE + ETH_INT_MASK) = ETH_RXB | ETH_TXB;
 
//set MAC ADDRESS
REG32(ETH_BASE + ETH_MAC_ADDR1) = (OWN_MAC_ADDRESS_5 << 8) | OWN_MAC_ADDRESS_4; //low word = mac address high word
REG32(ETH_BASE + ETH_MAC_ADDR0) = (OWN_MAC_ADDRESS_3 << 24) | (OWN_MAC_ADDRESS_2 << 16)
| (OWN_MAC_ADDRESS_1 << 8) | OWN_MAC_ADDRESS_0; //mac address rest
 
//configure TXBD0
REG32(ETH_BASE + ETH_TXBD0H) = (unsigned long)eth_tx_packet; //address used for tx_data
REG32(ETH_BASE + ETH_TXBD0L) = TX_READY; //length = 0 | PAD & CRC = 1 | IRQ & WR = 1
 
//configure RXBD0
REG32(ETH_BASE + ETH_RXBD0H) = (unsigned long)eth_rx_packet; //address used for tx_data
REG32(ETH_BASE + ETH_RXBD0L) = RX_READY; //len = 0 | IRQ & WR = 1 | EMPTY = 1
 
//set txdata
eth_tx_packet[0] = BROADCAST_ADDRESS_5;
eth_tx_packet[1] = BROADCAST_ADDRESS_4;
eth_tx_packet[2] = BROADCAST_ADDRESS_3;
eth_tx_packet[3] = BROADCAST_ADDRESS_2;
eth_tx_packet[4] = BROADCAST_ADDRESS_1;
eth_tx_packet[5] = BROADCAST_ADDRESS_0;
 
eth_tx_packet[6] = OWN_MAC_ADDRESS_5;
eth_tx_packet[7] = OWN_MAC_ADDRESS_4;
eth_tx_packet[8] = OWN_MAC_ADDRESS_3;
eth_tx_packet[9] = OWN_MAC_ADDRESS_2;
eth_tx_packet[10] = OWN_MAC_ADDRESS_1;
eth_tx_packet[11] = OWN_MAC_ADDRESS_0;
 
//erase interrupts
REG32(ETH_BASE + ETH_INT_SOURCE) = ETH_RXC | ETH_TXC | ETH_BUSY | ETH_RXE | ETH_RXB | ETH_TXE | ETH_TXB;
 
eth_tx_done = 1;
eth_rx_done = 0;
eth_rx_len = 0;
eth_tx_data = &eth_tx_packet[HDR_LEN];
eth_rx_data = &eth_rx_packet[HDR_LEN];
}
 
int eth_send(int length)
{
if (!eth_tx_done) //if previous command not fully processed, bail out
return -1;
 
eth_tx_done = 0;
eth_tx_packet[12] = length >> 8;
eth_tx_packet[13] = length;
 
REG32(ETH_BASE + ETH_TXBD0L) = (( 0x0000FFFF & ( length + HDR_LEN ) ) << 16) | BD_SND;
 
return length;
}
 
void eth_interrupt()
{
unsigned long source = REG32(ETH_BASE + ETH_INT_SOURCE);
if ( source & ETH_TXB )
{
eth_tx_done = 1;
//erase interrupt
REG32(ETH_BASE + ETH_INT_SOURCE) |= ETH_TXB;
}
if ( source & ETH_RXB )
{
eth_rx_done = 1;
eth_rx_len = (REG32(ETH_BASE + ETH_RXBD0L) >> 16) - HDR_LEN - CRC_LEN;
//erase interrupt
REG32(ETH_BASE + ETH_INT_SOURCE) |= ETH_RXB;
}
}
/can.c
0,0 → 1,149
#include <board.h>
#include <support.h>
#include "can.h"
 
int can_rx_done, can_tx_done;
int can_rx_rd_ptr;
int can_rx_wr_ptr;
int can_rx_buf_overflow;
 
can_type can_rx_data[CAN_BUF_LEN], can_tx_data;
 
can_type * can_get(void)
{
if ( !can_rx_done )
return NULL;
 
can_rx_done--;
 
int tmp;
tmp = can_rx_rd_ptr;
 
if (can_rx_rd_ptr < CAN_BUF_LEN-1)
can_rx_rd_ptr++;
else
can_rx_rd_ptr = 0;
 
return &can_rx_data[tmp];
}
 
void can_init(void)
{
unsigned char sync_jmp, baudrate_presc, timing_seg1, timing_seg2, tripple_samp = 0;
unsigned char acpt_code, acpt_mask = 0;
unsigned char clk_div = 0 & CAN_BUS_CLKDIV_MASK;
 
sync_jmp = 1;
baudrate_presc = 1;
timing_seg1 = 11;
timing_seg2 = 2;
tripple_samp = 1;
 
acpt_code = 0x81;
acpt_mask = 0xFF;
 
char timing0, timing1 = 0;
 
timing0 = (sync_jmp << CAN_BUS_TIMING_0_SYNC_JMP_SHIFT) & CAN_BUS_TIMING_0_SYNC_JMP;
timing0 |= baudrate_presc & CAN_BUS_TIMING_0_BAUD_PRESC;
 
timing1 = (tripple_samp << CAN_BUS_TIMING_1_TRIPLE_SAMP_SHIFT) & CAN_BUS_TIMING_1_TRIPLE_SAMP;
timing1 |= (timing_seg2 << CAN_BUS_TIMING_1_TIME_SEG2_SHIFT) & CAN_BUS_TIMING_1_TIME_SEG2;
timing1 |= timing_seg1 & CAN_BUS_TIMING_1_TIME_SEG1;
 
REG8(CAN_BASE+CAN_MODE) = CAN_MODE_RESET;
 
REG8(CAN_BASE+CAN_BUS_TIMING_0) = timing0;
REG8(CAN_BASE+CAN_BUS_TIMING_1) = timing1;
 
REG8(CAN_BASE+CAN_ACPT_CODE0) = acpt_code;
REG8(CAN_BASE+CAN_ACPT_MASK0) = acpt_mask;
 
REG8(CAN_BASE+CAN_BUS_MODE) &= ~CAN_BUS_MODE_CLOCK_OFF & ~CAN_BUS_MODE_EXTENDED_MODE;
 
REG8(CAN_BASE+CAN_MODE) &= ~CAN_MODE_RESET;
REG8(CAN_BASE+CAN_BUS_CLKDIV) = clk_div;
 
REG8(CAN_BASE+CAN_MODE) |= CAN_MODE_TX_IRQ_EN | CAN_MODE_RECV_IRQ_EN;
 
can_tx_done = 1;
can_rx_done = 0;
can_rx_rd_ptr = 0;
can_rx_wr_ptr = 0;
can_rx_buf_overflow = 0;
}
 
void can_recv_basic()
{
unsigned char byte0, byte1;
 
byte0 = REG8(CAN_BASE+CAN_RX_BUF);
byte1 = REG8(CAN_BASE+CAN_RX_BUF+1);
 
can_rx_data[can_rx_wr_ptr].data[0] = REG8(CAN_BASE+CAN_RX_BUF+2);
can_rx_data[can_rx_wr_ptr].data[1] = REG8(CAN_BASE+CAN_RX_BUF+3);
can_rx_data[can_rx_wr_ptr].data[2] = REG8(CAN_BASE+CAN_RX_BUF+4);
can_rx_data[can_rx_wr_ptr].data[3] = REG8(CAN_BASE+CAN_RX_BUF+5);
can_rx_data[can_rx_wr_ptr].data[4] = REG8(CAN_BASE+CAN_RX_BUF+6);
can_rx_data[can_rx_wr_ptr].data[5] = REG8(CAN_BASE+CAN_RX_BUF+7);
can_rx_data[can_rx_wr_ptr].data[6] = REG8(CAN_BASE+CAN_RX_BUF+8);
can_rx_data[can_rx_wr_ptr].data[7] = REG8(CAN_BASE+CAN_RX_BUF+9);
 
REG8(CAN_BASE+CAN_CMD) = CAN_CMD_RELEASE_BUFFER;
 
can_rx_data[can_rx_wr_ptr].identifier = (byte0 << 3) | (byte1 >> 5);
can_rx_data[can_rx_wr_ptr].rtr = byte1 & 0x10;
can_rx_data[can_rx_wr_ptr].len = byte1 & 0x0F;
 
if (can_rx_wr_ptr < CAN_BUF_LEN-1)
can_rx_wr_ptr++;
else
can_rx_wr_ptr = 0;
 
if (can_rx_wr_ptr == can_rx_rd_ptr+1) //buffer overflow
{
can_rx_done = 1;
can_rx_buf_overflow++;
}
else
can_rx_done++;
}
 
int can_send_basic()
{
if (!can_tx_done) //if previous command not fully processed, bail out
return -1;
 
can_tx_done = 0;
REG8(CAN_BASE+CAN_TX_BUF) = can_tx_data.identifier >> 3;
REG8(CAN_BASE+CAN_TX_BUF+1) = (can_tx_data.identifier << 5) | ((can_tx_data.rtr << 4) & 0x10) | (can_tx_data.len & 0x0F);
 
REG8(CAN_BASE+CAN_TX_BUF+2) = can_tx_data.data[0];
REG8(CAN_BASE+CAN_TX_BUF+3) = can_tx_data.data[1];
REG8(CAN_BASE+CAN_TX_BUF+4) = can_tx_data.data[2];
REG8(CAN_BASE+CAN_TX_BUF+5) = can_tx_data.data[3];
REG8(CAN_BASE+CAN_TX_BUF+6) = can_tx_data.data[4];
REG8(CAN_BASE+CAN_TX_BUF+7) = can_tx_data.data[5];
REG8(CAN_BASE+CAN_TX_BUF+8) = can_tx_data.data[6];
REG8(CAN_BASE+CAN_TX_BUF+9) = can_tx_data.data[7];
 
REG8(CAN_BASE+CAN_CMD) = CAN_CMD_TX_REQ;
 
return can_tx_data.len;
}
 
void can_irq(void)
{
unsigned char irq_req, rx_done;
irq_req = REG8(CAN_BASE+IRQ_READ);
rx_done = irq_req & CAN_IRQ_READ_RX;
can_tx_done = irq_req & CAN_IRQ_READ_TX;
if (rx_done)
can_recv_basic();
}
 
void can_abort(void)
{
REG8(CAN_BASE+CAN_CMD) = CAN_CMD_ABORT_TX;
}
 
/uart.c
0,0 → 1,138
#include <board.h>
#include <support.h>
#include "uart.h"
 
#define BOTH_EMPTY (UART_LSR_TEMT | UART_LSR_THRE)
 
#define WAIT_FOR_XMITR \
do { \
lsr = REG8(UART_BASE + UART_LSR); \
} while ((lsr & BOTH_EMPTY) != BOTH_EMPTY)
 
#define WAIT_FOR_THRE \
do { \
lsr = REG8(UART_BASE + UART_LSR); \
} while ((lsr & UART_LSR_THRE) != UART_LSR_THRE)
 
#define CHECK_FOR_CHAR (REG8(UART_BASE + UART_LSR) & UART_LSR_DR)
 
#define WAIT_FOR_CHAR \
do { \
lsr = REG8(UART_BASE + UART_LSR); \
} while ((lsr & UART_LSR_DR) != UART_LSR_DR)
 
#define UART_TX_BUFF_LEN 32
#define UART_TX_BUFF_MASK (UART_TX_BUFF_LEN -1)
 
char tx_buff[UART_TX_BUFF_LEN];
volatile int tx_level, rx_level;
 
void uart_init(void)
{
int divisor;
 
/* Reset receiver and transmiter */
/* Set RX interrupt for each byte */
REG8(UART_BASE + UART_FCR) = UART_FCR_ENABLE_FIFO | UART_FCR_CLEAR_RCVR | UART_FCR_CLEAR_XMIT | UART_FCR_TRIGGER_1;
 
/* Enable RX interrupt */
REG8(UART_BASE + UART_IER) = UART_IER_RDI | UART_IER_THRI;
 
/* Set 8 bit char, 1 stop bit, no parity */
REG8(UART_BASE + UART_LCR) = UART_LCR_WLEN8 & ~(UART_LCR_STOP | UART_LCR_PARITY);
 
/* Set baud rate */
divisor = IN_CLK/(16 * UART_BAUD_RATE);
REG8(UART_BASE + UART_LCR) |= UART_LCR_DLAB;
REG8(UART_BASE + UART_DLM) = (divisor >> 8) & 0x000000ff;
REG8(UART_BASE + UART_DLL) = divisor & 0x000000ff;
REG8(UART_BASE + UART_LCR) &= ~(UART_LCR_DLAB);
 
return;
}
 
void uart_putc(char c)
{
unsigned char lsr;
 
WAIT_FOR_THRE;
REG8(UART_BASE + UART_TX) = c;
if(c == '\n') {
WAIT_FOR_THRE;
REG8(UART_BASE + UART_TX) = '\r';
}
WAIT_FOR_XMITR;
}
 
 
 
char uart_getc()
{
char c;
c = REG8(UART_BASE + UART_RX);
return c;
}
 
 
void uart_interrupt()
{
char lala;
unsigned char interrupt_id;
interrupt_id = REG8(UART_BASE + UART_IIR);
if ( interrupt_id & UART_IIR_RDI )
{
lala = uart_getc();
uart_putc(lala+1);
}
 
}
 
void uart_print_str(char *p)
{
while(*p != 0) {
uart_putc(*p);
p++;
}
}
 
void uart_print_long(unsigned long ul)
{
int i;
char c;
 
 
uart_print_str("0x");
for(i=0; i<8; i++) {
 
c = (char) (ul>>((7-i)*4)) & 0xf;
if(c >= 0x0 && c<=0x9)
c += '0';
else
c += 'a' - 10;
uart_putc(c);
}
 
}
 
void uart_print_short(unsigned long ul)
{
int i;
char c;
char flag=0;
 
 
uart_print_str("0x");
for(i=0; i<8; i++) {
 
c = (char) (ul>>((7-i)*4)) & 0xf;
if(c >= 0x0 && c<=0x9)
c += '0';
else
c += 'a' - 10;
if ((c != '0') || (i==7))
flag=1;
if(flag)
uart_putc(c);
}
 
}
/Makefile
0,0 → 1,125
include ../support/Makefile.inc
include $(BACKEND_DIR)/gcc-opt.mk
 
#USER INPUT
SRCS = can.c eth.c i2c.c interrupts.c uart.c
OR32_TARGET =
TARGET =
TARGETLIB = drivers
MODEL = static #dynamic|static
VERSION = 0.1
MODE = debug #release|debug
 
INCLUDEDIRS = $(BACKEND_DIR) $(SUPPORT_DIR)
#libsystemc or systemc (system ignores lib at the beginning)
LIBNAMES =
LIBDIRS =
DEPENDDIR = ./depend
 
 
#CONFIGURATION
DEBUGPARAM =
RELEASEPARAM =
 
DEBUGFLAGS = -g -O0
RELEASEFLAGS = -O2 -fomit-frame-pointer
 
CFLAGS = -Wall
CC = or32-elf-gcc
AR = or32-elf-ar
RANLIB = or32-elf-ranlib
 
CFLAGS += $(GCC_OPT)
 
 
#MECHANICS
INCLUDESPATH = $(addprefix -I, $(INCLUDEDIRS))
LIBSPATH = $(addprefix -L, $(LIBDIRS))
LIBSLINKAGE = $(addprefix -l, $(subst lib, , $(LIBNAMES)) )
COMMA = ,
RPATH = $(addprefix -Wl$(COMMA)-R, $(LIBDIRS))
 
OBJS = $(addsuffix .o, $(basename $(SRCS)))
DEPS = $(addprefix $(DEPENDDIR)/, $(addsuffix .d, $(basename $(SRCS) ) ) )
 
STATICLIB = $(addprefix lib, $(addsuffix .a, $(TARGETLIB) ) )
DYNAMICLIB = $(addprefix lib, $(addsuffix .so, $(TARGETLIB) ) )
SONAME = $(addsuffix .$(VERSION), $(DYNAMICLIB))
 
ifeq (debug,$(findstring debug, $(MODE)))
CFLAGS += $(DEBUGFLAGS) $(addprefix -D, $(DEBUGPARAM))
else
CFLAGS += $(RELEASEFLAGS) $(addprefix -D, $(RELEASEPARAM))
endif
 
ifdef TARGETLIB
ifeq (dynamic,$(findstring dynamic, $(MODEL)))
TARGET = $(DYNAMICLIB)
CFLAGS += -fPIC
else
TARGET = $(STATICLIB)
endif
endif
 
 
#MAKEFILE RULES
all: $(TARGET) $(OR32_TARGET)
 
depend: $(DEPS)
 
docs: Doxyfile
doxygen
 
distclean:
make clean
rm -rf $(DEPENDDIR) Doxygen
 
 
-include $(DEPS)
 
 
ifndef TARGETLIB
$(TARGET): $(OBJS)
$(CC) $(LIBSPATH) $(RPATH) -o $@ $^ $(LIBSLINKAGE)
endif
 
 
$(STATICLIB): $(OBJS)
$(AR) cru $@ $^
$(RANLIB) $@
 
$(DYNAMICLIB): $(OBJS)
$(CC) -shared -Wl,-soname,$(SONAME) -o $@ $^
ln -fs $@ $(SONAME)
 
 
%.o: %.c
$(CC) $(CFLAGS) $(INCLUDESPATH) -c $< -o $@
 
 
$(DEPENDDIR)/%.d: %.c
mkdir -p $(DEPENDDIR)
$(CC) $(INCLUDESPATH) -MM -MF $@ $<
 
 
# DO NOT DELETE
 
STEM = $(subst .hex, , $(OR32_TARGET))
BINARY = $(addsuffix .bin, $(STEM) )
EXECUTABLE = $(addsuffix .or32, $(STEM) )
 
$(OR32_TARGET): $(BINARY)
$(BIN2HEX) $? 1 -size_word > $@
 
$(BINARY): $(EXECUTABLE)
$(OR32_TOOL_PREFIX)-objcopy -O binary $? $@
 
#except.o and reset.o should be already inside of $(SUPPORT) (libsupport.a) but for some reason the compiler ignores that fact
#(e.g. or32-elf-objdump -t libsupport.a shows it)
$(EXECUTABLE): $(OBJS) ../support/except.o ../support/reset.o $(SUPPORT) $(DRIVERS)
$(CC) $(CFLAGS) $(GCC_LIB_OPTS) -T $(LINKER_SCRIPT) $^ -o $@
 
clean:
rm -f *.o *~ $(TARGET) $(STATICLIB) $(DYNAMICLIB) $(SONAME) $(OR32_TARGET) $(BINARY) $(EXECUTABLE)
 
#EOF
/i2c.c
0,0 → 1,165
#include <board.h>
#include <support.h>
#include "i2c.h"
 
int i2c_rd_done, i2c_wr_done;
 
int i2c_pending_write;
 
int i2c_rd_ptr, i2c_wr_ptr;
 
int i2c_buf_overflow;
i2c_type i2c_data[I2C_BUF_LEN];
 
unsigned char start, pointer_write, write_hbyte, write_lbyte, read_hbyte, read_lbyte;
unsigned char cmd_list[5];
unsigned char dat_list[5];
int i2c_index;
int i2c_end;
 
i2c_type * i2c_get(void)
{
if ( !i2c_rd_done )
return NULL;
 
i2c_rd_done--;
 
int tmp;
tmp = i2c_rd_ptr;
 
if (i2c_rd_ptr < I2C_BUF_LEN-1)
i2c_rd_ptr++;
else
i2c_rd_ptr = 0;
 
return &i2c_data[tmp];
}
 
void i2c_init(void)
{
REG8(I2C_BASE+I2C_PRESC_HI) = 0x00;
REG8(I2C_BASE+I2C_PRESC_LO) = 49; //100kHz
REG8(I2C_BASE+I2C_CTR) = I2C_CTR_EN | I2C_CTR_IRQ_EN;
i2c_rd_done = 0;
i2c_wr_done = 0;
i2c_index = 0;
i2c_wr_ptr = 0;
i2c_rd_ptr = 0;
i2c_buf_overflow = 0;
}
 
void i2c_set_ack_lvl(int ack_lvl, int final_ack_lvl)
{
int ack, final_ack;
 
ack = ( ack_lvl ) ? I2C_CR_NACK : I2C_CR_ACK;
final_ack = ( final_ack_lvl ) ? I2C_CR_NACK : I2C_CR_ACK;
 
start = I2C_CR_STA | I2C_CR_WR | ack;
pointer_write = I2C_CR_WR | ack;
write_hbyte = I2C_CR_WR | ack;
write_lbyte = I2C_CR_WR | I2C_CR_STO | final_ack;
read_hbyte = I2C_CR_RD | ack;
read_lbyte = I2C_CR_RD | I2C_CR_STO | final_ack;
}
 
void i2c_byte_transfer(void)
{
if ( i2c_index > 0 )
if ( cmd_list[i2c_index-1] == read_hbyte )
i2c_data[i2c_wr_ptr].data = (REG8(I2C_BASE+I2C_RXR) << 8) & 0xFF00;
 
REG8(I2C_BASE+I2C_TXR) = dat_list[i2c_index];
REG8(I2C_BASE+I2C_CR) = cmd_list[i2c_index];
 
i2c_index++;
}
 
void i2c_irq(void)
{
REG8(I2C_BASE+I2C_CR) = I2C_CR_CLR_IRQ;
if (i2c_index <= i2c_end )
i2c_byte_transfer();
else
{
if ( cmd_list[i2c_index-1] == read_lbyte )
i2c_data[i2c_wr_ptr].data |= REG8(I2C_BASE+I2C_RXR);
 
i2c_index = 0;
 
if ( i2c_pending_write )
i2c_wr_done = 1;
else
{
if (i2c_wr_ptr < I2C_BUF_LEN-1)
i2c_wr_ptr++;
else
i2c_wr_ptr = 0;
 
if (i2c_wr_ptr == i2c_rd_ptr+1)
{
i2c_rd_done = 1;
i2c_buf_overflow++;
}
else
i2c_rd_done++;
}
}
}
 
int i2c_trans(i2c_mode * mode, i2c_type * data)
{
if ( i2c_index != 0 ) //if previous command not fully processed, bail out
return -1;
 
i2c_wr_done = 0;
 
int i = 0;
 
if ( mode->ptr_set || mode->read_write ) //start conditions with pointer set: (write always set ptr)
{
dat_list[i] = (data->address << 1) & I2C_TXR_ADR;
dat_list[i] |= I2C_TXR_W;
cmd_list[i++] = start;
 
dat_list[i] = data->pointer;
cmd_list[i++] = pointer_write;
 
if ( !mode->read_write ) //REstart for read, NO-REstart for write
{
dat_list[i] = (data->address << 1) & I2C_TXR_ADR;
dat_list[i] |= I2C_TXR_R;
cmd_list[i++] = start;
}
}
else //start conditions with NO pointer set (read only): ONE start
{
dat_list[i] = (data->address << 1) & I2C_TXR_ADR;
dat_list[i] |= I2C_TXR_R;
cmd_list[i++] = start;
}
 
if ( mode->byte_word ) //read/write high byte
{
dat_list[i] = data->data >> 8;
cmd_list[i++] = (mode->read_write) ? write_hbyte : read_hbyte;
}
 
dat_list[i] = data->data; //read/write low byte
cmd_list[i] = (mode->read_write) ? write_lbyte : read_lbyte;
 
i2c_end = i;
 
if ( !mode->read_write ) //set data to 0 for read, avoid or implications ((short)data |= byte)
{
i2c_data[i2c_wr_ptr] = *data;
i2c_data[i2c_wr_ptr].data = 0x0000;
}
 
i2c_pending_write = mode->read_write;
 
i2c_index = 0;
i2c_byte_transfer();
 
return mode->read_write+1;
}
/interrupts.c
0,0 → 1,14
// Dummy or32 except vectors
void buserr_except(){}
void dpf_except(){}
void ipf_except(){}
void align_except(){}
void illegal_except(){}
void dtlbmiss_except(){}
void itlbmiss_except(){}
void range_except(){}
void syscall_except(){}
void res1_except(){}
void trap_except(){}
void res2_except(){}
 
/uart.h
0,0 → 1,126
#define UART_RX 0 /* In: Receive buffer (DLAB=0) */
#define UART_TX 0 /* Out: Transmit buffer (DLAB=0) */
#define UART_DLL 0 /* Out: Divisor Latch Low (DLAB=1) */
#define UART_DLM 1 /* Out: Divisor Latch High (DLAB=1) */
#define UART_IER 1 /* Out: Interrupt Enable Register */
#define UART_IIR 2 /* In: Interrupt ID Register */
#define UART_FCR 2 /* Out: FIFO Control Register */
#define UART_EFR 2 /* I/O: Extended Features Register */
/* (DLAB=1, 16C660 only) */
#define UART_LCR 3 /* Out: Line Control Register */
#define UART_MCR 4 /* Out: Modem Control Register */
#define UART_LSR 5 /* In: Line Status Register */
#define UART_MSR 6 /* In: Modem Status Register */
#define UART_SCR 7 /* I/O: Scratch Register */
 
/*
* These are the definitions for the FIFO Control Register
* (16650 only)
*/
#define UART_FCR_ENABLE_FIFO 0x01 /* Enable the FIFO */
#define UART_FCR_CLEAR_RCVR 0x02 /* Clear the RCVR FIFO */
#define UART_FCR_CLEAR_XMIT 0x04 /* Clear the XMIT FIFO */
#define UART_FCR_DMA_SELECT 0x08 /* For DMA applications */
#define UART_FCR_TRIGGER_MASK 0xC0 /* Mask for the FIFO trigger range */
#define UART_FCR_TRIGGER_1 0x00 /* Mask for trigger set at 1 */
#define UART_FCR_TRIGGER_4 0x40 /* Mask for trigger set at 4 */
#define UART_FCR_TRIGGER_8 0x80 /* Mask for trigger set at 8 */
#define UART_FCR_TRIGGER_14 0xC0 /* Mask for trigger set at 14 */
 
/* 16650 redefinitions */
#define UART_FCR6_R_TRIGGER_8 0x00 /* Mask for receive trigger set at 1 */
#define UART_FCR6_R_TRIGGER_16 0x40 /* Mask for receive trigger set at 4 */
#define UART_FCR6_R_TRIGGER_24 0x80 /* Mask for receive trigger set at 8 */
#define UART_FCR6_R_TRIGGER_28 0xC0 /* Mask for receive trigger set at 14 */
#define UART_FCR6_T_TRIGGER_16 0x00 /* Mask for transmit trigger set at 16 */
#define UART_FCR6_T_TRIGGER_8 0x10 /* Mask for transmit trigger set at 8 */
#define UART_FCR6_T_TRIGGER_24 0x20 /* Mask for transmit trigger set at 24 */
#define UART_FCR6_T_TRIGGER_30 0x30 /* Mask for transmit trigger set at 30 */
 
/*
* These are the definitions for the Line Control Register
*
* Note: if the word length is 5 bits (UART_LCR_WLEN5), then setting
* UART_LCR_STOP will select 1.5 stop bits, not 2 stop bits.
*/
#define UART_LCR_DLAB 0x80 /* Divisor latch access bit */
#define UART_LCR_SBC 0x40 /* Set break control */
#define UART_LCR_SPAR 0x20 /* Stick parity (?) */
#define UART_LCR_EPAR 0x10 /* Even parity select */
#define UART_LCR_PARITY 0x08 /* Parity Enable */
#define UART_LCR_STOP 0x04 /* Stop bits: 0=1 stop bit, 1= 2 stop bits */
#define UART_LCR_WLEN5 0x00 /* Wordlength: 5 bits */
#define UART_LCR_WLEN6 0x01 /* Wordlength: 6 bits */
#define UART_LCR_WLEN7 0x02 /* Wordlength: 7 bits */
#define UART_LCR_WLEN8 0x03 /* Wordlength: 8 bits */
 
/*
* These are the definitions for the Line Status Register
*/
#define UART_LSR_TEMT 0x40 /* Transmitter empty */
#define UART_LSR_THRE 0x20 /* Transmit-hold-register empty */
#define UART_LSR_BI 0x10 /* Break interrupt indicator */
#define UART_LSR_FE 0x08 /* Frame error indicator */
#define UART_LSR_PE 0x04 /* Parity error indicator */
#define UART_LSR_OE 0x02 /* Overrun error indicator */
#define UART_LSR_DR 0x01 /* Receiver data ready */
 
/*
* These are the definitions for the Interrupt Identification Register
*/
#define UART_IIR_NO_INT 0x01 /* No interrupts pending */
#define UART_IIR_ID 0x06 /* Mask for the interrupt ID */
 
#define UART_IIR_MSI 0x00 /* Modem status interrupt */
#define UART_IIR_THRI 0x02 /* Transmitter holding register empty */
#define UART_IIR_TOI 0x0c /* Receive time out interrupt */
#define UART_IIR_RDI 0x04 /* Receiver data interrupt */
#define UART_IIR_RLSI 0x06 /* Receiver line status interrupt */
 
/*
* These are the definitions for the Interrupt Enable Register
*/
#define UART_IER_MSI 0x08 /* Enable Modem status interrupt */
#define UART_IER_RLSI 0x04 /* Enable receiver line status interrupt */
#define UART_IER_THRI 0x02 /* Enable Transmitter holding register int. */
#define UART_IER_RDI 0x01 /* Enable receiver data interrupt */
 
/*
* These are the definitions for the Modem Control Register
*/
#define UART_MCR_LOOP 0x10 /* Enable loopback test mode */
#define UART_MCR_OUT2 0x08 /* Out2 complement */
#define UART_MCR_OUT1 0x04 /* Out1 complement */
#define UART_MCR_RTS 0x02 /* RTS complement */
#define UART_MCR_DTR 0x01 /* DTR complement */
 
/*
* These are the definitions for the Modem Status Register
*/
#define UART_MSR_DCD 0x80 /* Data Carrier Detect */
#define UART_MSR_RI 0x40 /* Ring Indicator */
#define UART_MSR_DSR 0x20 /* Data Set Ready */
#define UART_MSR_CTS 0x10 /* Clear to Send */
#define UART_MSR_DDCD 0x08 /* Delta DCD */
#define UART_MSR_TERI 0x04 /* Trailing edge ring indicator */
#define UART_MSR_DDSR 0x02 /* Delta DSR */
#define UART_MSR_DCTS 0x01 /* Delta CTS */
#define UART_MSR_ANY_DELTA 0x0F /* Any of the delta bits! */
 
/*
* These are the definitions for the Extended Features Register
* (StarTech 16C660 only, when DLAB=1)
*/
#define UART_EFR_CTS 0x80 /* CTS flow control */
#define UART_EFR_RTS 0x40 /* RTS flow control */
#define UART_EFR_SCD 0x20 /* Special character detect */
#define UART_EFR_ENI 0x10 /* Enhanced Interrupt */
 
 
void uart_init(void);
void uart_putc(char);
char uart_getc(void);
void uart_print_str(char *);
void uart_print_long(unsigned long);
void uart_interrupt();
void uart_print_short(unsigned long ul);
/i2c.h
0,0 → 1,60
struct i2c_type
{
unsigned char address;
unsigned char pointer;
unsigned short data;
};
 
struct i2c_mode
{
unsigned char read_write;
unsigned char byte_word;
unsigned char ptr_set;
};
 
typedef struct i2c_type i2c_type;
typedef struct i2c_mode i2c_mode;
 
 
 
void i2c_init(void);
void i2c_irq(void);
 
i2c_type * i2c_get(void); //return pointer to first non read received data
 
void i2c_set_ack_lvl(int ack_lvl, int final_ack_lvl);
int i2c_trans(i2c_mode * mode, i2c_type * data); //return (-1) or length (still processing previous) or asserted
 
#define I2C_BUF_LEN 10
#define I2C_PRESC_LO 0x00
#define I2C_PRESC_HI 0x01
 
#define I2C_CTR 0x02
 
#define I2C_TXR 0x03
#define I2C_RXR 0x03
 
#define I2C_CR 0x04
#define I2C_SR 0x04
 
//BITS
#define I2C_CTR_EN 0x80
#define I2C_CTR_IRQ_EN 0x40
 
#define I2C_TXR_ADR 0xFE
#define I2C_TXR_W 0x00
#define I2C_TXR_R 0x01
 
#define I2C_CR_STA 0x80
#define I2C_CR_STO 0x40
#define I2C_CR_RD 0x20
#define I2C_CR_WR 0x10
#define I2C_CR_ACK 0x00
#define I2C_CR_NACK 0x08
#define I2C_CR_CLR_IRQ 0x01
 
#define I2C_SR_R_ACK 0x80
#define I2C_SR_BUSY 0x40
#define I2C_SR_ARB_LOST 0x20
#define I2C_SR_TX_BUSY 0x02
#define I2C_SR_IRQ_FLAG 0x01
/eth.h
0,0 → 1,108
void eth_init();
void eth_interrupt();
void eth_recv_ack(void);
 
int eth_send(int length); //return (-1) or length (still processing previous) or asserted
 
#define ETH_MODER 0x00
#define ETH_INT_SOURCE 0x04
#define ETH_INT_MASK 0x08
#define ETH_IPGT 0x0C
#define ETH_IPGR1 0x10
#define ETH_IPGR2 0x14
#define ETH_PACKETLEN 0x18
#define ETH_COLLCONF 0x1C
#define ETH_TX_BD_NUM 0x20
#define ETH_CTRLMODER 0x24
#define ETH_MIIMODER 0x28
#define ETH_MIICOMMAND 0x2C
#define ETH_MIIADDRESS 0x30
#define ETH_MIITX_DATA 0x34
#define ETH_MIIRX_DATA 0x38
#define ETH_MIISTATUS 0x3C
#define ETH_MAC_ADDR0 0x40
#define ETH_MAC_ADDR1 0x44
#define ETH_HASH0_ADR 0x48
#define ETH_HASH1_ADR 0x4C
#define ETH_TXCTRL 0x50
 
#define ETH_TXBD0H 0x404
#define ETH_TXBD0L 0x400
 
#define ETH_RXBD0H 0x604 //this depends on TX_BD_NUM but this is the standard value
#define ETH_RXBD0L 0x600 //this depends on TX_BD_NUM but this is the standard value
 
//MODER BITS
#define ETH_RECSMAL 0x00010000
#define ETH_PAD 0x00008000
#define ETH_HUGEN 0x00004000
#define ETH_CRCEN 0x00002000
#define ETH_DLYCRCEN 0x00001000
#define ETH_FULLD 0x00000400
#define ETH_EXDFREN 0x00000200
#define ETH_NOBCKOF 0x00000100
#define ETH_LOOPBCK 0x00000080
#define ETH_IFG 0x00000040
#define ETH_PRO 0x00000020
#define ETH_IAM 0x00000010
#define ETH_BRO 0x00000008
#define ETH_NOPRE 0x00000004
#define ETH_TXEN 0x00000002
#define ETH_RXEN 0x00000001
 
//INTERRUPTS BITS
#define ETH_RXC 0x00000040
#define ETH_TXC 0x00000020
#define ETH_BUSY 0x00000010
#define ETH_RXE 0x00000008
#define ETH_RXB 0x00000004
#define ETH_TXE 0x00000002
#define ETH_TXB 0x00000001
 
//BUFFER DESCRIPTOR BITS
#define ETH_RXBD_EMPTY 0x00008000
#define ETH_RXBD_IRQ 0x00004000
#define ETH_RXBD_WRAP 0x00002000
#define ETH_RXBD_CF 0x00000100
#define ETH_RXBD_MISS 0x00000080
#define ETH_RXBD_OR 0x00000040
#define ETH_RXBD_IS 0x00000020
#define ETH_RXBD_DN 0x00000010
#define ETH_RXBD_TL 0x00000008
#define ETH_RXBD_SF 0x00000004
#define ETH_RXBD_CRC 0x00000002
#define ETH_RXBD_LC 0x00000001
 
#define ETH_TXBD_READY 0x00008000
#define ETH_TXBD_IRQ 0x00004000
#define ETH_TXBD_WRAP 0x00002000
#define ETH_TXBD_PAD 0x00001000
#define ETH_TXBD_CRC 0x00000800
#define ETH_TXBD_UR 0x00000100
#define ETH_TXBD_RL 0x00000008
#define ETH_TXBD_LC 0x00000004
#define ETH_TXBD_DF 0x00000002
#define ETH_TXBD_CS 0x00000001
 
//user defines
#define OWN_MAC_ADDRESS_5 0x55
#define OWN_MAC_ADDRESS_4 0x47
#define OWN_MAC_ADDRESS_3 0x34
#define OWN_MAC_ADDRESS_2 0x22
#define OWN_MAC_ADDRESS_1 0x88
#define OWN_MAC_ADDRESS_0 0x92
 
#define BROADCAST_ADDRESS_5 0xFF
#define BROADCAST_ADDRESS_4 0xFF
#define BROADCAST_ADDRESS_3 0xFF
#define BROADCAST_ADDRESS_2 0xFF
#define BROADCAST_ADDRESS_1 0xFF
#define BROADCAST_ADDRESS_0 0xFF
 
#define HDR_LEN 14
#define CRC_LEN 4
#define BD_SND ( ETH_TXBD_READY | ETH_TXBD_IRQ | ETH_TXBD_WRAP | ETH_TXBD_PAD | ETH_TXBD_CRC )
#define RX_READY ( ETH_RXBD_EMPTY | ETH_RXBD_IRQ | ETH_RXBD_WRAP )
#define TX_READY ( ETH_TXBD_IRQ | ETH_TXBD_WRAP | ETH_TXBD_PAD | ETH_TXBD_CRC )
 
//~user defines
/can.h
0,0 → 1,156
struct can_type
{
unsigned char rtr;
unsigned char len;
unsigned short identifier;
unsigned char data[8];
};
 
typedef struct can_type can_type;
 
#define CAN_BUF_LEN 10
 
void can_init(void);
void can_irq(void);
 
can_type * can_get(void); //return pointer to first non read received data
 
int can_send_basic(); //return (-1) or length (still processing previous) or asserted
void can_abort(void);
 
//BOTH MODES
#define CAN_MODE 0x00
#define CAN_CMD 0x01
#define CAN_STATUS 0x02
#define IRQ_READ 0x03
 
#define CAN_ACPT_CODE0 0x04 //only writable while in reset mode
#define CAN_ACPT_MASK0 0x05 //only writable while in reset mode
 
#define CAN_BUS_TIMING_0 0x06 //only writable while in reset mode
#define CAN_BUS_TIMING_1 0x07 //only writable while in reset mode
 
#define CAN_BUS_CLKDIV 0x1F //only writable while NOT in reset mode
 
#define CAN_TX_BUF 0x0A //only accessable while NOT in reset mode
#define CAN_TX_LEN 10
 
#define CAN_RX_BUF 0x14 //free read access for basic mode
#define CAN_RX_LEN 10
 
//only accessable while in reset mode
#define CAN_BUS_MODE 0x1F
 
 
//EXTENDED MODE ONLY
//only for extended mode & only accessable while in reset mode
#define CAN_IRQ_EN_EXT 0x04 //also writable if NOT in reset mode
 
//read only regs
#define CAN_ARBIT_LOSS_CNT 0x0B //cnt of arbitration loss
#define CAN_ERROR_CAPTURE_CODE 0x0C
#define CAN_RX_MSG_CNT 0x1D
//~read only regs
 
#define CAN_ERROR_WARN_LIMIT 0x0D
 
#define CAN_RX_ERR_CNT 0x0E
#define CAN_TX_ERR_CNT 0x0F
 
#define CAN_ACPT_CODE0_EXT 0x10 //also writable if NOT in reset mode
#define CAN_ACPT_CODE1 0x11
#define CAN_ACPT_CODE2 0x12
#define CAN_ACPT_CODE3 0x13
 
#define CAN_ACPT_MASK0_EXT 0x14 //also writable if NOT in reset mode
#define CAN_ACPT_MASK1 0x15
#define CAN_ACPT_MASK2 0x16
#define CAN_ACPT_MASK3 0x17
 
#define CAN_TX_BUF_EXT 0x10 //accessable if transmit_buffer_status=1
#define CAN_TX_LEN_EXT 13 //ignores reset mode
 
#define CAN_RX_BUF_EXT 0x10 //read access only in NOT reset mode
#define CAN_RX_LEN_EXT 13
 
 
//BITS DEFINITIONS
 
//BASIC MODE
#define CAN_MODE_RESET 0x01
#define CAN_MODE_LISTEN_ONLY_BASIC 0x20
#define CAN_MODE_RECV_IRQ_EN 0x02
#define CAN_MODE_TX_IRQ_EN 0x04
#define CAN_MODE_ERROR_IRQ_EN 0x08
#define CAN_MODE_OVERRUN_IRQ_EN 0x10
//EXTENDED MODE
#define CAN_MODE_LISTEN_ONLY_EXT 0x02
#define CAN_MODE_SELF_TEST_MODE 0x04
#define CAN_MODE_ACPT_FILTER_MODE 0x08
 
//CMD
#define CAN_CMD_CLR_DATA_OVERRUN 0x08
#define CAN_CMD_RELEASE_BUFFER 0x04
#define CAN_CMD_TX_REQ 0x11
#define CAN_CMD_ABORT_TX 0x02
 
//STATUS
#define CAN_STATUS_NODE_BUS_OFF 0x80
#define CAN_STATUS_ERROR 0x40
#define CAN_STATUS_TX 0x20
#define CAN_STATUS_RX 0x10
#define CAN_STATUS_TX_COMPLETE 0x08
#define CAN_STATUS_TX_BUF 0x04
#define CAN_STATUS_OVERRUN 0x02
#define CAN_STATUS_RX_BUF 0x01
 
//IRQ READ
#define CAN_IRQ_READ_BUS_ERROR 0x80
#define CAN_IRQ_READ_ARBIT_LOST 0x40
#define CAN_IRQ_READ_ERROR_PASSIV 0x20
#define CAN_IRQ_READ_OVERRUN 0x08
#define CAN_IRQ_READ_ERROR 0x04
#define CAN_IRQ_READ_TX 0x02
#define CAN_IRQ_READ_RX 0x01
 
//BUS_TIMING_0
#define CAN_BUS_TIMING_0_SYNC_JMP_SHIFT 6
#define CAN_BUS_TIMING_0_SYNC_JMP 0xC0
#define CAN_BUS_TIMING_0_BAUD_PRESC 0x3F
 
//BUS_TIMING_1
#define CAN_BUS_TIMING_1_TRIPLE_SAMP_SHIFT 7
#define CAN_BUS_TIMING_1_TRIPLE_SAMP 0x80
#define CAN_BUS_TIMING_1_TIME_SEG2_SHIFT 4
#define CAN_BUS_TIMING_1_TIME_SEG2 0x70
#define CAN_BUS_TIMING_1_TIME_SEG1 0x0F
 
//CLKDIV
//only writable while NOT in reset mode
#define CAN_BUS_CLKDIV_MASK 0x07
 
 
//EXTENDED MODE ONLY
//CLKMODE
//only writable while in reset mode
#define CAN_BUS_MODE_CLOCK_OFF 0x08
#define CAN_BUS_MODE_EXTENDED_MODE 0x80
 
//EXTENDED MODE IRQ
#define CAN_IRQ_EN_EXT_BUS_ERROR 0x80
#define CAN_IRQ_EN_EXT_ARBIT_LOST 0x40
#define CAN_IRQ_EN_EXT_ERROR_PASSIV 0x20
#define CAN_IRQ_EN_EXT_OVERRUN 0x08
#define CAN_IRQ_EN_EXT_ERROR 0x04
#define CAN_IRQ_EN_EXT_TX 0x02
#define CAN_IRQ_EN_EXT_RX 0x01
 
//EXTENDED ERROR CODES
#define CAN_ERROR_CAPTURE_CODE_TYPE_SHIFT 6
#define CAN_ERROR_CAPTURE_CODE_TYPE 0xC0
#define CAN_ERROR_CAPTURE_CODE_TYPE_BIT 0x0
#define CAN_ERROR_CAPTURE_CODE_TYPE_FORM 0x1
#define CAN_ERROR_CAPTURE_CODE_TYPE_STUFF 0x2
#define CAN_ERROR_CAPTURE_CODE_TYPE_OTHER 0x3
#define CAN_ERROR_CAPTURE_CODE_DIR 0x40 //1 = TX | 0 = RX
#define CAN_ERROR_CAPTURE_CODE_SEG 0x1F

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.