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Rev 109 → Rev 139

/minsoc_onchip_ram_top_altera.v
0,0 → 1,310
//////////////////////////////////////////////////////////////////////
//// ////
//// Generic Wishbone controller for ////
//// Single-Port Synchronous RAM ////
//// ////
//// This file is part of memory library available from ////
//// http://www.opencores.org/cvsweb.shtml/minsoc/ ////
//// ////
//// Description ////
//// This Wishbone controller connects to the wrapper of ////
//// the single-port synchronous memory interface. ////
//// Besides universal memory due to onchip_ram it provides a ////
//// generic way to set the depth of the memory. ////
//// ////
//// To Do: ////
//// ////
//// Author(s): ////
//// - Raul Fajardo, rfajardo@gmail.com ////
//// ////
//////////////////////////////////////////////////////////////////////
//// ////
//// Copyright (C) 2000 Authors and OPENCORES.ORG ////
//// ////
//// This source file may be used and distributed without ////
//// restriction provided that this copyright statement is not ////
//// removed from the file and that any derivative work contains ////
//// the original copyright notice and the associated disclaimer. ////
//// ////
//// This source file is free software; you can redistribute it ////
//// and/or modify it under the terms of the GNU Lesser General ////
//// Public License as published by the Free Software Foundation; ////
//// either version 2.1 of the License, or (at your option) any ////
//// later version. ////
//// ////
//// This source is distributed in the hope that it will be ////
//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
//// PURPOSE. See the GNU Lesser General Public License for more ////
//// details. ////
//// ////
//// You should have received a copy of the GNU Lesser General ////
//// Public License along with this source; if not, download it ////
//// from http://www.gnu.org/licenses/lgpl.html ////
//// ////
//////////////////////////////////////////////////////////////////////
//
// Revision History
//
// Revision 1.1 2009/10/02 16:49 fajardo
// Not using the oe signal (output enable) from
// memories, instead multiplexing the outputs
// between the different instantiated blocks
//
//
// Revision 1.0 2009/08/18 15:15:00 fajardo
// Created interface and tested
//
`include "minsoc_defines.v"
 
`define mem_init_file "uart-nocache.mif" //specific memory initalization file name, which can be intel hex(.hex) or Altera mif file
//if no initalization file used, give a name of "UNUSED"
 
module minsoc_onchip_ram_top (
wb_clk_i, wb_rst_i,
wb_dat_i, wb_dat_o, wb_adr_i, wb_sel_i, wb_we_i, wb_cyc_i,
wb_stb_i, wb_ack_o, wb_err_o
);
//
// Parameters
//
parameter adr_width = 13; //Memory address width, is composed by blocks of aw_int, is not allowed to be less than 12
localparam aw_int = 11; //11 = 2048
localparam blocks = (1<<(adr_width-aw_int)); //generated memory contains "blocks" memory blocks of 2048x32 2048 depth x32 bit data
 
//
// I/O Ports
//
input wb_clk_i;
input wb_rst_i;
//
// WB slave i/f
//
input [31:0] wb_dat_i;
output [31:0] wb_dat_o;
input [31:0] wb_adr_i;
input [3:0] wb_sel_i;
input wb_we_i;
input wb_cyc_i;
input wb_stb_i;
output wb_ack_o;
output wb_err_o;
//
// Internal regs and wires
//
wire we;
wire [3:0] be_i;
wire [31:0] wb_dat_o;
reg ack_we;
reg ack_re;
//
// Aliases and simple assignments
//
assign wb_ack_o = ack_re | ack_we;
assign wb_err_o = wb_cyc_i & wb_stb_i & (|wb_adr_i[23:adr_width+2]); // If Access to > (8-bit leading prefix ignored)
assign we = wb_cyc_i & wb_stb_i & wb_we_i & (|wb_sel_i[3:0]);
assign be_i = (wb_cyc_i & wb_stb_i) * wb_sel_i;
//
// Write acknowledge
//
always @ (negedge wb_clk_i or posedge wb_rst_i)
begin
if (wb_rst_i)
ack_we <= 1'b0;
else
if (wb_cyc_i & wb_stb_i & wb_we_i & ~ack_we)
ack_we <= #1 1'b1;
else
ack_we <= #1 1'b0;
end
//
// read acknowledge
//
always @ (posedge wb_clk_i or posedge wb_rst_i)
begin
if (wb_rst_i)
ack_re <= 1'b0;
else
if (wb_cyc_i & wb_stb_i & ~wb_err_o & ~wb_we_i & ~ack_re)
ack_re <= #1 1'b1;
else
ack_re <= #1 1'b0;
end
 
`ifdef ALTERA_FPGA //only for altera memory initialization
 
//2^adr_width x 32bit single-port ram.
altsyncram altsyncram_component (
.wren_a (we),
.clock0 (wb_clk_i),
.byteena_a (be_i),
.address_a (wb_adr_i[adr_width+1:2]),
.data_a (wb_dat_i),
.q_a (wb_dat_o),
.aclr0 (1'b0),
.aclr1 (1'b0),
.address_b (1'b1),
.addressstall_a (1'b0),
.addressstall_b (1'b0),
.byteena_b (1'b1),
.clock1 (1'b1),
.clocken0 (1'b1),
.clocken1 (1'b1),
.clocken2 (1'b1),
.clocken3 (1'b1),
.data_b (1'b1),
.eccstatus (),
.q_b (),
.rden_a (1'b1),
.rden_b (1'b1),
.wren_b (1'b0));
defparam
altsyncram_component.clock_enable_input_a = "BYPASS",
altsyncram_component.clock_enable_output_a = "BYPASS",
altsyncram_component.init_file = `mem_init_file,
altsyncram_component.intended_device_family = "Stratix III",
altsyncram_component.lpm_hint = "ENABLE_RUNTIME_MOD=NO",
altsyncram_component.lpm_type = "altsyncram",
altsyncram_component.operation_mode = "SINGLE_PORT",
altsyncram_component.outdata_aclr_a = "NONE",
altsyncram_component.outdata_reg_a = "UNREGISTERED",
altsyncram_component.power_up_uninitialized = "FALSE",
altsyncram_component.read_during_write_mode_port_a = "NEW_DATA_NO_NBE_READ",
altsyncram_component.numwords_a = (1<<adr_width),
altsyncram_component.widthad_a = adr_width,
altsyncram_component.width_a = 32,
altsyncram_component.byte_size = 8,
altsyncram_component.width_byteena_a = 4;
 
 
`else //other FPGA Type
//Generic (multiple inputs x 1 output) MUX
localparam mux_in_nr = blocks;
localparam slices = adr_width-aw_int;
localparam mux_out_nr = blocks-1;
 
wire [31:0] int_dat_o[0:mux_in_nr-1];
wire [31:0] mux_out[0:mux_out_nr-1];
 
generate
genvar j, k;
for (j=0; j<slices; j=j+1) begin : SLICES
for (k=0; k<(mux_in_nr>>(j+1)); k=k+1) begin : MUX
if (j==0) begin
mux2 #
(
.dw(32)
)
mux_int(
.sel( wb_adr_i[aw_int+2+j] ),
.in1( int_dat_o[k*2] ),
.in2( int_dat_o[k*2+1] ),
.out( mux_out[k] )
);
end
else begin
mux2 #
(
.dw(32)
)
mux_int(
.sel( wb_adr_i[aw_int+2+j] ),
.in1( mux_out[(mux_in_nr-(mux_in_nr>>(j-1)))+k*2] ),
.in2( mux_out[(mux_in_nr-(mux_in_nr>>(j-1)))+k*2+1] ),
.out( mux_out[(mux_in_nr-(mux_in_nr>>j))+k] )
);
end
end
end
endgenerate
 
//last output = total output
assign wb_dat_o = mux_out[mux_out_nr-1];
 
//(mux_in_nr-(mux_in_nr>>j)):
//-Given sum of 2^i | i = x -> y series can be resumed to 2^(y+1)-2^x
//so, with this expression I'm evaluating how many times the internal loop has been run
 
wire [blocks-1:0] bank;
generate
genvar i;
for (i=0; i < blocks; i=i+1) begin : MEM
 
assign bank[i] = wb_adr_i[adr_width+1:aw_int+2] == i;
 
//BANK0
minsoc_onchip_ram block_ram_0 (
.clk(wb_clk_i),
.rst(wb_rst_i),
.addr(wb_adr_i[aw_int+1:2]),
.di(wb_dat_i[7:0]),
.doq(int_dat_o[i][7:0]),
.we(we & bank[i]),
.oe(1'b1),
.ce(be_i[0])
);
 
 
minsoc_onchip_ram block_ram_1 (
.clk(wb_clk_i),
.rst(wb_rst_i),
.addr(wb_adr_i[aw_int+1:2]),
.di(wb_dat_i[15:8]),
.doq(int_dat_o[i][15:8]),
.we(we & bank[i]),
.oe(1'b1),
.ce(be_i[1])
);
 
minsoc_onchip_ram block_ram_2 (
.clk(wb_clk_i),
.rst(wb_rst_i),
.addr(wb_adr_i[aw_int+1:2]),
.di(wb_dat_i[23:16]),
.doq(int_dat_o[i][23:16]),
.we(we & bank[i]),
.oe(1'b1),
.ce(be_i[2])
);
 
minsoc_onchip_ram block_ram_3 (
.clk(wb_clk_i),
.rst(wb_rst_i),
.addr(wb_adr_i[aw_int+1:2]),
.di(wb_dat_i[31:24]),
.doq(int_dat_o[i][31:24]),
.we(we & bank[i]),
.oe(1'b1),
.ce(be_i[3])
);
 
end
endgenerate
`endif
 
endmodule
 
module mux2(sel,in1,in2,out);
 
parameter dw = 32;
 
input sel;
input [dw-1:0] in1, in2;
output reg [dw-1:0] out;
 
always @ (sel or in1 or in2)
begin
case (sel)
1'b0: out = in1;
1'b1: out = in2;
endcase
end
 
endmodule
/bin2init.py
0,0 → 1,212
"""
*****************************************************************************
*
H E A D E R I N F O R M A T I O N *
*
*****************************************************************************
Project Name : SysPy (System Python)
http://cgi.di.uoa.gr/~evlog/syspy.html
 
File Name : bin2init.py
 
Created by : Evangelos Logaras
 
 
*****************************************************************************
*
C O P Y R I G H T N O T I C E *
*
*****************************************************************************
 
This library is free software; you can redistribute it and/or
modify it under the terms of the GNU Lesser General Public
License as published by the Free Software Foundation;
version 2.1 of the License, a copy of which is available from
http://www.gnu.org/licenses/old-licenses/lgpl-2.1.txt.
 
This library is distributed in the hope that it will be useful,
but WITHOUT ANY WARRANTY; without even the implied warranty of
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
Lesser General Public License for more details.
 
You should have received a copy of the GNU Lesser General Public
License along with this library; if not, write to the Free Software
Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA
 
 
*****************************************************************************
*
D E S C R I P T I O N *
*
*****************************************************************************
 
Generates block_ram.init file from binary images. Binary images are first converted in hex files
using bin2hex.c file, provided with the ORPSoC v2 project. bin2hex executable must exist in the same folder with this script.
 
Currently init file is generated for Xilinx's RAMB16_S9 BRAMs
 
Usage: python bin2init.py <file.bin> (Python 2.6)
"""
 
import commands
import sys
 
# Python's variable declarations
#----------------------------------------------------------------------------------------------------------------------------------
y = ' '
mem_arr = []
block_ram_num = 4
block0 = []
block1 = []
block2 = []
block3 = []
block_ram = [block3, block2, block1, block0]
init_arr = []
mem_size2 = 8192
mem_count = 0
bram_count = -1
init_count = -1
hex_count = 0
zero_pad = ''
filename = ''
#----------------------------------------------------------------------------------------------------------------------------------
 
# Exceptions' class
#----------------------------------------------------------------------------------------------------------------------------------
class MyExceptions(Exception):
def __init__(self, value):
self.value = value
def __str__(self):
return repr(self.value)
#----------------------------------------------------------------------------------------------------------------------------------
 
# Raising exception if a *.bin file is not provided as an argument
#----------------------------------------------------------------------------------------------------------------------------------
filename = sys.argv[len(sys.argv) - 1]
 
if (filename.find(".bin") == -1):
raise MyExceptions("*.bin file required")
#----------------------------------------------------------------------------------------------------------------------------------
 
i = filename.find(".bin")
 
filename = filename[:i]
 
# Deleting old *.hex and *.bin files
#----------------------------------------------------------------------------------------------------------------------------------
commands.getoutput("rm " + filename + ".hex")
commands.getoutput("rm " + filename + ".init")
#----------------------------------------------------------------------------------------------------------------------------------
 
## Calling bin2hex executable to convert *.bin file to *.hex
commands.getoutput("./bin2hex " + filename + ".bin 4 > "+ filename + ".hex")
 
# Opening the *.hex and the *.init file
#----------------------------------------------------------------------------------------------------------------------------------
hexFile = open(filename + ".hex", 'r')
initFile = open(filename + ".init", 'w')
#----------------------------------------------------------------------------------------------------------------------------------
 
# Reading the *.hex file and appending its contents to mem_arr[]
#----------------------------------------------------------------------------------------------------------------------------------
y = ' '
hex_count = 0
while(y):
hex_count = hex_count + 1
if (hex_count == 127):
mem_arr.append("00000000")
y = hexFile.readline()
mem_arr.append(y)
#----------------------------------------------------------------------------------------------------------------------------------
 
# Reading mem_arr[] and creating the contents of BRAMs
#----------------------------------------------------------------------------------------------------------------------------------
for i in range(len(mem_arr)):
bram_count = bram_count + 1
if (bram_count < 32):
block_ram[0].append(mem_arr[i][6:8])
block_ram[1].append(mem_arr[i][4:6])
block_ram[2].append(mem_arr[i][2:4])
block_ram[3].append(mem_arr[i][0:2])
elif (bram_count >= 32):
bram_count = 0
init_count = init_count + 1
 
if (init_count >= 64):
init_count = 0
mem_count = mem_count + 1
hex_init_count = str(hex(init_count))
hex_init_count = hex_init_count[2:]
hex_init_count = hex_init_count.upper()
if (init_count < 16):
hex_init_count = '0' + hex_init_count
for j in range((block_ram_num - 1), -1, -1):
if (j == (block_ram_num - 1)):
init_arr.append(";\ndefparam MEM[" + str(mem_count) + "].block_ram_" + str(j) + ".INIT_" + hex_init_count + " = 256'h")
block_ram[j].reverse()
for k in range(len(block_ram[j])):
init_arr.append(block_ram[j][k].replace("\n", ''))
else:
init_arr.append(";\ndefparam MEM[" + str(mem_count) + "].block_ram_" + str(j) + ".INIT_" + hex_init_count + " = 256'h")
block_ram[j].reverse()
for k in range(len(block_ram[j])):
init_arr.append(block_ram[j][k].replace("\n", ''))
 
block_ram[0] = []
block_ram[1] = []
block_ram[2] = []
block_ram[3] = []
block_ram[0].append(mem_arr[i][6:8])
block_ram[1].append(mem_arr[i][4:6])
block_ram[2].append(mem_arr[i][2:4])
block_ram[3].append(mem_arr[i][0:2])
 
if (bram_count != -1):
init_count = init_count + 1
hex_init_count = str(hex(init_count))
hex_init_count = hex_init_count[2:]
hex_init_count = hex_init_count.upper()
if (init_count < 16):
hex_init_count = '0' + hex_init_count
if (init_count == 0):
for j in range(64 - 2 * bram_count):
zero_pad = zero_pad + '0'
else:
for j in range(64 - 2 * bram_count):
zero_pad = zero_pad + '0'
 
for j in range((block_ram_num - 1), -1, -1):
init_arr.append(";\ndefparam MEM[" + str(mem_count) + "].block_ram_" + str(j) + ".INIT_" + hex_init_count + " = 256'h")
block_ram[j].reverse()
init_arr.append(zero_pad)
for k in range(len(block_ram[j])):
init_arr.append(block_ram[j][k].replace("\n", ''))
init_arr.append(';')
#----------------------------------------------------------------------------------------------------------------------------------
 
# Writing BRAMs contetns to *.init file
#----------------------------------------------------------------------------------------------------------------------------------
i = init_arr[0].find(";/n")
 
init_arr[0] = init_arr[0][i + 2:]
 
for i in range(len(init_arr)):
initFile.write(init_arr[i])
#----------------------------------------------------------------------------------------------------------------------------------
# Closing the *.hex and the *.init file
#----------------------------------------------------------------------------------------------------------------------------------
hexFile.close()
initFile.close()
#----------------------------------------------------------------------------------------------------------------------------------
/minsoc_onchip_ram_top_xilinx.v
0,0 → 1,312
//////////////////////////////////////////////////////////////////////
//// ////
//// Generic Wishbone controller for ////
//// Single-Port Synchronous RAM ////
//// ////
//// This file is part of memory library available from ////
//// http://www.opencores.org/cvsweb.shtml/minsoc/ ////
//// ////
//// Description ////
//// This Wishbone controller connects to the wrapper of ////
//// the single-port synchronous memory interface. ////
//// Besides universal memory due to onchip_ram it provides a ////
//// generic way to set the depth of the memory. ////
//// ////
//// To Do: ////
//// ////
//// Author(s): ////
//// - Raul Fajardo, rfajardo@gmail.com ////
//// ////
//////////////////////////////////////////////////////////////////////
//// ////
//// Copyright (C) 2000 Authors and OPENCORES.ORG ////
//// ////
//// This source file may be used and distributed without ////
//// restriction provided that this copyright statement is not ////
//// removed from the file and that any derivative work contains ////
//// the original copyright notice and the associated disclaimer. ////
//// ////
//// This source file is free software; you can redistribute it ////
//// and/or modify it under the terms of the GNU Lesser General ////
//// Public License as published by the Free Software Foundation; ////
//// either version 2.1 of the License, or (at your option) any ////
//// later version. ////
//// ////
//// This source is distributed in the hope that it will be ////
//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
//// PURPOSE. See the GNU Lesser General Public License for more ////
//// details. ////
//// ////
//// You should have received a copy of the GNU Lesser General ////
//// Public License along with this source; if not, download it ////
//// from http://www.gnu.org/licenses/lgpl.html ////
//// ////
//////////////////////////////////////////////////////////////////////
//
// Revision History
//
// Revision 1.1 2009/10/02 16:49 fajardo
// Not using the oe signal (output enable) from
// memories, instead multiplexing the outputs
// between the different instantiated blocks
//
//
// Revision 1.0 2009/08/18 15:15:00 fajardo
// Created interface and tested
//
`include "minsoc_defines.v"
 
module minsoc_onchip_ram_top (
wb_clk_i, wb_rst_i,
wb_dat_i, wb_dat_o, wb_adr_i, wb_sel_i, wb_we_i, wb_cyc_i,
wb_stb_i, wb_ack_o, wb_err_o
);
//
// Parameters
//
parameter adr_width = 13; //Memory address width, is composed by blocks of aw_int, is not allowed to be less than 12
localparam aw_int = 11; //11 = 2048
localparam blocks = (1<<(adr_width-aw_int)); //generated memory contains "blocks" memory blocks of 2048x32 2048 depth x32 bit data
 
//
// I/O Ports
//
input wb_clk_i;
input wb_rst_i;
//
// WB slave i/f
//
input [31:0] wb_dat_i;
output [31:0] wb_dat_o;
input [31:0] wb_adr_i;
input [3:0] wb_sel_i;
input wb_we_i;
input wb_cyc_i;
input wb_stb_i;
output wb_ack_o;
output wb_err_o;
//
// Internal regs and wires
//
wire we;
wire [3:0] be_i;
wire [31:0] wb_dat_o;
reg ack_we;
reg ack_re;
//
// Aliases and simple assignments
//
assign wb_ack_o = ack_re | ack_we;
assign wb_err_o = wb_cyc_i & wb_stb_i & (|wb_adr_i[23:adr_width+2]); // If Access to > (8-bit leading prefix ignored)
assign we = wb_cyc_i & wb_stb_i & wb_we_i & (|wb_sel_i[3:0]);
assign be_i = (wb_cyc_i & wb_stb_i) * wb_sel_i;
//
// Write acknowledge
//
always @ (negedge wb_clk_i or posedge wb_rst_i)
begin
if (wb_rst_i)
ack_we <= 1'b0;
else
if (wb_cyc_i & wb_stb_i & wb_we_i & ~ack_we)
ack_we <= #1 1'b1;
else
ack_we <= #1 1'b0;
end
//
// read acknowledge
//
always @ (posedge wb_clk_i or posedge wb_rst_i)
begin
if (wb_rst_i)
ack_re <= 1'b0;
else
if (wb_cyc_i & wb_stb_i & ~wb_err_o & ~wb_we_i & ~ack_re)
ack_re <= #1 1'b1;
else
ack_re <= #1 1'b0;
end
 
//Generic (multiple inputs x 1 output) MUX
localparam mux_in_nr = blocks;
localparam slices = adr_width-aw_int;
localparam mux_out_nr = blocks-1;
 
wire [31:0] int_dat_o[0:mux_in_nr-1];
wire [31:0] mux_out[0:mux_out_nr-1];
 
generate
genvar j, k;
for (j=0; j<slices; j=j+1) begin : SLICES
for (k=0; k<(mux_in_nr>>(j+1)); k=k+1) begin : MUX
if (j==0) begin
mux21 #
(
.dw(32)
)
mux_int(
.sel( wb_adr_i[aw_int+2+j] ),
.in1( int_dat_o[k*2] ),
.in2( int_dat_o[k*2+1] ),
.out( mux_out[k] )
);
end
else begin
mux21 #
(
.dw(32)
)
mux_int(
.sel( wb_adr_i[aw_int+2+j] ),
.in1( mux_out[(mux_in_nr-(mux_in_nr>>(j-1)))+k*2] ),
.in2( mux_out[(mux_in_nr-(mux_in_nr>>(j-1)))+k*2+1] ),
.out( mux_out[(mux_in_nr-(mux_in_nr>>j))+k] )
);
end
end
end
endgenerate
 
//last output = total output
assign wb_dat_o = mux_out[mux_out_nr-1];
 
//(mux_in_nr-(mux_in_nr>>j)):
//-Given sum of 2^i | i = x -> y series can be resumed to 2^(y+1)-2^x
//so, with this expression I'm evaluating how many times the internal loop has been run
 
wire [blocks-1:0] bank;
generate
genvar i;
for (i=0; i < blocks; i=i+1) begin : MEM
 
assign bank[i] = wb_adr_i[adr_width+1:aw_int+2] == i;
 
//BANK0
/* minsoc_onchip_ram block_ram_0 (
.clk(wb_clk_i),
.rst(wb_rst_i),
.addr(wb_adr_i[aw_int+1:2]),
.di(wb_dat_i[7:0]),
.doq(int_dat_o[i][7:0]),
.we(we & bank[i]),
.oe(1'b1),
.ce(be_i[0])
);
*/
RAMB16_S9 block_ram_0(
.CLK(wb_clk_i),
.SSR(wb_rst_i),
.ADDR(wb_adr_i[aw_int+1:2]),
.DI(wb_dat_i[7:0]),
.DIP(1'b0),
.EN(be_i[0]),
.WE(we & bank[i]),
.DO(int_dat_o[i][7:0]),
.DOP()
);
 
/*
minsoc_onchip_ram block_ram_1 (
.clk(wb_clk_i),
.rst(wb_rst_i),
.addr(wb_adr_i[aw_int+1:2]),
.di(wb_dat_i[15:8]),
.doq(int_dat_o[i][15:8]),
.we(we & bank[i]),
.oe(1'b1),
.ce(be_i[1])
);
*/
RAMB16_S9 block_ram_1(
.CLK(wb_clk_i),
.SSR(wb_rst_i),
.ADDR(wb_adr_i[aw_int+1:2]),
.DI(wb_dat_i[15:8]),
.DIP(1'b0),
.EN(be_i[1]),
.WE(we & bank[i]),
.DO(int_dat_o[i][15:8]),
.DOP()
);
/*
minsoc_onchip_ram block_ram_2 (
.clk(wb_clk_i),
.rst(wb_rst_i),
.addr(wb_adr_i[aw_int+1:2]),
.di(wb_dat_i[23:16]),
.doq(int_dat_o[i][23:16]),
.we(we & bank[i]),
.oe(1'b1),
.ce(be_i[2])
);
*/
RAMB16_S9 block_ram_2(
.CLK(wb_clk_i),
.SSR(wb_rst_i),
.ADDR(wb_adr_i[aw_int+1:2]),
.DI(wb_dat_i[23:16]),
.DIP(1'b0),
.EN(be_i[2]),
.WE(we & bank[i]),
.DO(int_dat_o[i][23:16]),
.DOP()
);
 
/*
minsoc_onchip_ram block_ram_3 (
.clk(wb_clk_i),
.rst(wb_rst_i),
.addr(wb_adr_i[aw_int+1:2]),
.di(wb_dat_i[31:24]),
.doq(int_dat_o[i][31:24]),
.we(we & bank[i]),
.oe(1'b1),
.ce(be_i[3])
);
*/
RAMB16_S9 block_ram_3(
.CLK(wb_clk_i),
.SSR(wb_rst_i),
.ADDR(wb_adr_i[aw_int+1:2]),
.DI(wb_dat_i[31:24]),
.DIP(1'b0),
.EN(be_i[3]),
.WE(we & bank[i]),
.DO(int_dat_o[i][31:24]),
.DOP()
);
 
end
endgenerate
 
`ifdef BLOCK_RAM_INIT
`include "block_ram.init"
`endif
 
endmodule
 
module mux21(sel,in1,in2,out);
 
parameter dw = 32;
 
input sel;
input [dw-1:0] in1, in2;
output reg [dw-1:0] out;
 
always @ (sel or in1 or in2)
begin
case (sel)
1'b0: out = in1;
1'b1: out = in2;
endcase
end
 
endmodule

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