Subversion Repositories minsoc

/minsoc_top.v

minsoc_top.v Property changes : Added: svn:executable ## -0,0 +1 ## +* \ No newline at end of property Index: minsoc_defines.v =================================================================== --- minsoc_defines.v (nonexistent) +++ minsoc_defines.v (revision 42) @@ -0,0 +1,117 @@ +// +// Define FPGA manufacturer +// +//`define GENERIC_FPGA +//`define ALTERA_FPGA +`define XILINX_FPGA + +// +// Define FPGA Model (comment all out for ALTERA) +// +//`define SPARTAN2 +//`define SPARTAN3 +//`define SPARTAN3E +`define SPARTAN3A +//`define VIRTEX +//`define VIRTEX2 +//`define VIRTEX4 +//`define VIRTEX5 + + +// +// Memory +// +`define MEMORY_ADR_WIDTH 13 //MEMORY_ADR_WIDTH IS NOT ALLOWED TO BE LESS THAN 12, memory is composed by blocks of address width 11 + //Address width of memory -> select memory depth, 2 powers MEMORY_ADR_WIDTH defines the memory depth + //the memory data width is 32 bit, memory amount in Bytes = 4*memory depth + +// +// Memory type (uncomment something if ASIC or generic memory) +// +//`define GENERIC_MEMORY +//`define AVANT_ATP +//`define VIRAGE_SSP +//`define VIRTUALSILICON_SSP + + +// +// TAP selection +// +//`define GENERIC_TAP +`define FPGA_TAP + +// +// Clock Division selection +// +//`define NO_CLOCK_DIVISION +//`define GENERIC_CLOCK_DIVISION +`define FPGA_CLOCK_DIVISION //Altera ALTPLL is not implemented, didn't find the code for its verilog instantiation + //if you selected altera and this, the GENERIC_CLOCK_DIVISION will be automatically taken + +// +// Define division +// +`define CLOCK_DIVISOR 5 //in case of GENERIC_CLOCK_DIVISION the real value will be rounded down to an even value + //in FPGA case, check minsoc_clock_manager for allowed divisors + //DO NOT USE CLOCK_DIVISOR = 1 COMMENT THE CLOCK DIVISION SELECTION INSTEAD + +// +// Reset polarity +// +//`define NEGATIVE_RESET //rstn +`define POSITIVE_RESET //rst + +// +// Start-up circuit (only necessary later to load firmware automatically from SPI memory) +// +//`define START_UP + +// +// Connected modules +// +`define UART +//`define ETHERNET + +// +// Ethernet reset +// +//`define ETH_RESET 1'b0 +`define ETH_RESET 1'b1 + +// +// Interrupts +// +`define APP_INT_RES1 1:0 +`define APP_INT_UART 2 +`define APP_INT_RES2 3 +`define APP_INT_ETH 4 +`define APP_INT_PS2 5 +`define APP_INT_RES3 19:6 + +// +// Address map +// +`define APP_ADDR_DEC_W 8 +`define APP_ADDR_SRAM `APP_ADDR_DEC_W'h00 +`define APP_ADDR_FLASH `APP_ADDR_DEC_W'h04 +`define APP_ADDR_DECP_W 4 +`define APP_ADDR_PERIP `APP_ADDR_DECP_W'h9 +`define APP_ADDR_SPI `APP_ADDR_DEC_W'h97 +`define APP_ADDR_ETH `APP_ADDR_DEC_W'h92 +`define APP_ADDR_AUDIO `APP_ADDR_DEC_W'h9d +`define APP_ADDR_UART `APP_ADDR_DEC_W'h90 +`define APP_ADDR_PS2 `APP_ADDR_DEC_W'h94 +`define APP_ADDR_RES1 `APP_ADDR_DEC_W'h9e +`define APP_ADDR_RES2 `APP_ADDR_DEC_W'h9f + +// +// Set-up GENERIC_TAP, GENERIC_MEMORY if GENERIC_FPGA was chosen +// and GENERIC_CLOCK_DIVISION if NO_CLOCK_DIVISION was not set +// +`ifdef GENERIC_FPGA + `define GENERIC_TAP + `define GENERIC_MEMORY + `ifndef NO_CLOCK_DIVISION + `define GENERIC_CLOCK_DIVISION + `endif +`endif

minsoc_defines.v Property changes : Added: svn:executable ## -0,0 +1 ## +* \ No newline at end of property Index: minsoc_startup/spi_top.v =================================================================== --- minsoc_startup/spi_top.v (nonexistent) +++ minsoc_startup/spi_top.v (revision 42) @@ -0,0 +1,224 @@ +////////////////////////////////////////////////////////////////////// +//// //// +//// spi_top.v //// +//// //// +//// This file is part of the SPI IP core project //// +//// http://www.opencores.org/projects/spi/ //// +//// //// +//// Author(s): //// +//// - Simon Srot (simons@opencores.org) //// +//// //// +//// All additional information is avaliable in the Readme.txt //// +//// file. //// +//// //// +////////////////////////////////////////////////////////////////////// +//// //// +//// Copyright (C) 2002 Authors //// +//// //// +//// This source file may be used and distributed without //// +//// restriction provided that this copyright statement is not //// +//// removed from the file and that any derivative work contains //// +//// the original copyright notice and the associated disclaimer. //// +//// //// +//// This source file is free software; you can redistribute it //// +//// and/or modify it under the terms of the GNU Lesser General //// +//// Public License as published by the Free Software Foundation; //// +//// either version 2.1 of the License, or (at your option) any //// +//// later version. //// +//// //// +//// This source is distributed in the hope that it will be //// +//// useful, but WITHOUT ANY WARRANTY; without even the implied //// +//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR //// +//// PURPOSE. See the GNU Lesser General Public License for more //// +//// details. //// +//// //// +//// You should have received a copy of the GNU Lesser General //// +//// Public License along with this source; if not, download it //// +//// from http://www.opencores.org/lgpl.shtml //// +//// //// +////////////////////////////////////////////////////////////////////// + + +`include "spi_defines.v" +`include "timescale.v" + +module spi_flash_top + ( + // Wishbone signals + wb_clk_i, wb_rst_i, wb_adr_i, wb_dat_i, wb_dat_o, wb_sel_i, + wb_we_i, wb_stb_i, wb_cyc_i, wb_ack_o, + // SPI signals + ss_pad_o, sclk_pad_o, mosi_pad_o, miso_pad_i + ); + + parameter divider_len = 2; + parameter divider = 0; + + parameter Tp = 1; + + // Wishbone signals + input wb_clk_i; // master clock input + input wb_rst_i; // synchronous active high reset + input [4:2] wb_adr_i; // lower address bits + input [31:0] wb_dat_i; // databus input + output [31:0] wb_dat_o; // databus output + input [3:0] wb_sel_i; // byte select inputs + input wb_we_i; // write enable input + input wb_stb_i; // stobe/core select signal + input wb_cyc_i; // valid bus cycle input + output wb_ack_o; // bus cycle acknowledge output + + // SPI signals + output [`SPI_SS_NB-1:0] ss_pad_o; // slave select + output sclk_pad_o; // serial clock + output mosi_pad_o; // master out slave in + input miso_pad_i; // master in slave out + + reg [31:0] wb_dat_o; + reg wb_ack_o; + + // Internal signals + // reg [`SPI_DIVIDER_LEN-1:0] divider; // Divider register + wire [`SPI_CTRL_BIT_NB-1:0] ctrl; // Control and status register + reg [`SPI_SS_NB-1:0] ss; // Slave select register + wire [`SPI_MAX_CHAR-1:0] rx; // Rx register + + wire [5:0] char_len; + reg char_len_ctrl; // char len + reg go; // go + + wire spi_ctrl_sel; // ctrl register select + wire spi_tx_sel; // tx_l register select + wire spi_ss_sel; // ss register select + wire tip; // transfer in progress + wire pos_edge; // recognize posedge of sclk + wire neg_edge; // recognize negedge of sclk + wire last_bit; // marks last character bit + + wire rx_negedge; // miso is sampled on negative edge + wire tx_negedge; // mosi is driven on negative edge + wire lsb; // lsb first on line + wire ass; // automatic slave select + + // Address decoder + assign spi_ctrl_sel = wb_cyc_i & wb_stb_i & (wb_adr_i[`SPI_OFS_BITS] == `SPI_CTRL); + assign spi_tx_sel = wb_cyc_i & wb_stb_i & (wb_adr_i[`SPI_OFS_BITS] == `SPI_TX_0); + assign spi_ss_sel = wb_cyc_i & wb_stb_i & (wb_adr_i[`SPI_OFS_BITS] == `SPI_SS); + + // Read from registers + // Wb data out + always @(posedge wb_clk_i or posedge wb_rst_i) + begin + if (wb_rst_i) + wb_dat_o <= #Tp 32'b0; + else + case (wb_adr_i[`SPI_OFS_BITS]) + `SPI_RX_0: wb_dat_o <= rx; + `SPI_CTRL: wb_dat_o <= {18'd0, ctrl}; + `SPI_DEVIDE: wb_dat_o <= divider; + `SPI_SS: wb_dat_o <= {{32-`SPI_SS_NB{1'b0}}, ss}; + default: wb_dat_o <= rx; + endcase + end + + // Wb acknowledge + always @(posedge wb_clk_i or posedge wb_rst_i) + begin + if (wb_rst_i) + wb_ack_o <= #Tp 1'b0; + else + wb_ack_o <= #Tp wb_cyc_i & wb_stb_i & ~wb_ack_o; + end + + // Ctrl register + always @(posedge wb_clk_i or posedge wb_rst_i) + begin + if (wb_rst_i) + {go,char_len_ctrl} <= #Tp 2'b01; + else if(spi_ctrl_sel && wb_we_i && !tip) + begin + if (wb_sel_i[0]) + char_len_ctrl <= #Tp wb_dat_i[5]; + if (wb_sel_i[1]) + go <= #Tp wb_dat_i[8]; + end + else if(tip && last_bit && pos_edge) + go <= #Tp 1'b0; + end + + assign char_len = char_len_ctrl ? 6'd32 : 6'd8; +`ifdef SPI_CTRL_ASS + assign ass = 1'b1; +`else + assign ass = 1'b0; +`endif +`ifdef SPI_CTRL_LSB + assign lsb = 1'b1; +`else + assign lsb = 1'b0; +`endif +`ifdef SPI_CTRL_RX_NEGEDGE + assign rx_negedge = 1'b1; +`else + assign rx_negedge = 1'b0; +`endif +`ifdef SPI_CTRL_TX_NEGEDGE + assign tx_negedge = 1'b1; +`else + assign tx_negedge = 1'b0; +`endif + + assign ctrl = {ass,1'b0,lsb,tx_negedge,rx_negedge,go,1'b0,1'b0,char_len}; + + // Slave select register + always @(posedge wb_clk_i or posedge wb_rst_i) + if (wb_rst_i) + ss <= #Tp {`SPI_SS_NB{1'b0}}; + else if(spi_ss_sel && wb_we_i && !tip) + if (wb_sel_i[0]) + ss <= #Tp wb_dat_i[`SPI_SS_NB-1:0]; + + assign ss_pad_o = ~((ss & {`SPI_SS_NB{tip & ass}}) | (ss & {`SPI_SS_NB{!ass}})); + + spi_flash_clgen + # + ( + .divider_len(divider_len), + .divider(divider) + ) + clgen + ( + .clk_in(wb_clk_i), + .rst(wb_rst_i), + .go(go), + .enable(tip), + .last_clk(last_bit), + .clk_out(sclk_pad_o), + .pos_edge(pos_edge), + .neg_edge(neg_edge) + ); + + spi_flash_shift shift + ( + .clk(wb_clk_i), + .rst(wb_rst_i), + .len(char_len[`SPI_CHAR_LEN_BITS-1:0]), + .latch(spi_tx_sel & wb_we_i), + .byte_sel(wb_sel_i), + .go(go), + .pos_edge(pos_edge), + .neg_edge(neg_edge), + .lsb(lsb), + .rx_negedge(rx_negedge), + .tx_negedge(tx_negedge), + .tip(tip), + .last(last_bit), + .p_in(wb_dat_i), + .p_out(rx), + .s_clk(sclk_pad_o), + .s_in(miso_pad_i), + .s_out(mosi_pad_o) + ); + +endmodule +

minsoc_startup/spi_top.v Property changes : Added: svn:executable ## -0,0 +1 ## +* \ No newline at end of property Index: minsoc_startup/spi_clgen.v =================================================================== --- minsoc_startup/spi_clgen.v (nonexistent) +++ minsoc_startup/spi_clgen.v (revision 42) @@ -0,0 +1,110 @@ +////////////////////////////////////////////////////////////////////// +//// //// +//// spi_clgen.v //// +//// //// +//// This file is part of the SPI IP core project //// +//// http://www.opencores.org/projects/spi/ //// +//// //// +//// Author(s): //// +//// - Simon Srot (simons@opencores.org) //// +//// //// +//// All additional information is avaliable in the Readme.txt //// +//// file. //// +//// //// +////////////////////////////////////////////////////////////////////// +//// //// +//// Copyright (C) 2002 Authors //// +//// //// +//// This source file may be used and distributed without //// +//// restriction provided that this copyright statement is not //// +//// removed from the file and that any derivative work contains //// +//// the original copyright notice and the associated disclaimer. //// +//// //// +//// This source file is free software; you can redistribute it //// +//// and/or modify it under the terms of the GNU Lesser General //// +//// Public License as published by the Free Software Foundation; //// +//// either version 2.1 of the License, or (at your option) any //// +//// later version. //// +//// //// +//// This source is distributed in the hope that it will be //// +//// useful, but WITHOUT ANY WARRANTY; without even the implied //// +//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR //// +//// PURPOSE. See the GNU Lesser General Public License for more //// +//// details. //// +//// //// +//// You should have received a copy of the GNU Lesser General //// +//// Public License along with this source; if not, download it //// +//// from http://www.opencores.org/lgpl.shtml //// +//// //// +////////////////////////////////////////////////////////////////////// + +`include "spi_defines.v" +`include "timescale.v" + +module spi_flash_clgen (clk_in, rst, go, enable, last_clk, clk_out, pos_edge, neg_edge); + + parameter divider_len = 2; + parameter divider = 1; + + parameter Tp = 1; + + input clk_in; // input clock (system clock) + input rst; // reset + input enable; // clock enable + input go; // start transfer + input last_clk; // last clock + //input [spi_divider_len-1:0] divider; // clock divider (output clock is divided by this value) + output clk_out; // output clock + output pos_edge; // pulse marking positive edge of clk_out + output neg_edge; // pulse marking negative edge of clk_out + + reg clk_out; + reg pos_edge; + reg neg_edge; + + reg [divider_len-1:0] cnt; // clock counter + wire cnt_zero; // conter is equal to zero + wire cnt_one; // conter is equal to one + + + assign cnt_zero = cnt == {divider_len{1'b0}}; + assign cnt_one = cnt == {{divider_len-1{1'b0}}, 1'b1}; + + // Counter counts half period + always @(posedge clk_in or posedge rst) + begin + if(rst) + cnt <= #Tp {divider_len{1'b1}}; + else + begin + if(!enable || cnt_zero) + cnt <= #Tp divider; + else + cnt <= #Tp cnt - {{divider_len-1{1'b0}}, 1'b1}; + end + end + + // clk_out is asserted every other half period + always @(posedge clk_in or posedge rst) + begin + if(rst) + clk_out <= #Tp 1'b0; + else + clk_out <= #Tp (enable && cnt_zero && (!last_clk || clk_out)) ? ~clk_out : clk_out; + end + + // Pos and neg edge signals + always @(posedge clk_in or posedge rst) + begin + if(rst) + begin + pos_edge <= #Tp 1'b0; + neg_edge <= #Tp 1'b0; + end + else + begin + pos_edge <= #Tp (enable && !clk_out && cnt_one) || (!(|divider) && clk_out) || (!(|divider) && go && !enable); + neg_edge <= #Tp (enable && clk_out && cnt_one) || (!(|divider) && !clk_out && enable); + end + end +endmodule

minsoc_startup/spi_clgen.v Property changes : Added: svn:executable ## -0,0 +1 ## +* \ No newline at end of property Index: minsoc_startup/spi_shift.v =================================================================== --- minsoc_startup/spi_shift.v (nonexistent) +++ minsoc_startup/spi_shift.v (revision 42) @@ -0,0 +1,149 @@ +////////////////////////////////////////////////////////////////////// +//// //// +//// spi_shift.v //// +//// //// +//// This file is part of the SPI IP core project //// +//// http://www.opencores.org/projects/spi/ //// +//// //// +//// Author(s): //// +//// - Simon Srot (simons@opencores.org) //// +//// //// +//// All additional information is avaliable in the Readme.txt //// +//// file. //// +//// //// +////////////////////////////////////////////////////////////////////// +//// //// +//// Copyright (C) 2002 Authors //// +//// //// +//// This source file may be used and distributed without //// +//// restriction provided that this copyright statement is not //// +//// removed from the file and that any derivative work contains //// +//// the original copyright notice and the associated disclaimer. //// +//// //// +//// This source file is free software; you can redistribute it //// +//// and/or modify it under the terms of the GNU Lesser General //// +//// Public License as published by the Free Software Foundation; //// +//// either version 2.1 of the License, or (at your option) any //// +//// later version. //// +//// //// +//// This source is distributed in the hope that it will be //// +//// useful, but WITHOUT ANY WARRANTY; without even the implied //// +//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR //// +//// PURPOSE. See the GNU Lesser General Public License for more //// +//// details. //// +//// //// +//// You should have received a copy of the GNU Lesser General //// +//// Public License along with this source; if not, download it //// +//// from http://www.opencores.org/lgpl.shtml //// +//// //// +////////////////////////////////////////////////////////////////////// + +`include "spi_defines.v" +`include "timescale.v" + +module spi_flash_shift + ( + clk, rst, latch, byte_sel, len, go, + pos_edge, neg_edge, + lsb, rx_negedge, tx_negedge, + tip, last, + p_in, p_out, s_clk, s_in, s_out); + + parameter Tp = 1; + + input clk; // system clock + input rst; // reset + input latch; // latch signal for storing the data in shift register + input [3:0] byte_sel; // byte select signals for storing the data in shift register + input [`SPI_CHAR_LEN_BITS-1:0] len; // data len in bits (minus one) + input lsb; // lbs first on the line + input tx_negedge; + input rx_negedge; + input go; // start stansfer + input pos_edge; // recognize posedge of sclk + input neg_edge; // recognize negedge of sclk + output tip; // transfer in progress + output last; // last bit + input [31:0] p_in; // parallel in + output [`SPI_MAX_CHAR-1:0] p_out; // parallel out + input s_clk; // serial clock + input s_in; // serial in + output s_out; // serial out + + reg s_out; + reg tip; + + reg [`SPI_CHAR_LEN_BITS:0] cnt; // data bit count + reg [`SPI_MAX_CHAR-1:0] data; // shift register + wire [`SPI_CHAR_LEN_BITS:0] tx_bit_pos; // next bit position + wire [`SPI_CHAR_LEN_BITS:0] rx_bit_pos; // next bit position + wire rx_clk; // rx clock enable + wire tx_clk; // tx clock enable + + + assign p_out = data; + + assign tx_bit_pos = lsb ? {!(|len), len} - cnt : cnt - {{`SPI_CHAR_LEN_BITS{1'b0}},1'b1}; + assign rx_bit_pos = lsb ? {!(|len), len} - (rx_negedge ? cnt + {{`SPI_CHAR_LEN_BITS{1'b0}},1'b1} : cnt) : (rx_negedge ? cnt : cnt - {{`SPI_CHAR_LEN_BITS{1'b0}},1'b1}); + + assign last = !(|cnt); + + assign rx_clk = (rx_negedge ? neg_edge : pos_edge) && (!last || s_clk); + + assign tx_clk = (tx_negedge ? neg_edge : pos_edge) && !last; + + // Character bit counter + always @(posedge clk or posedge rst) + begin + if(rst) + cnt <= #Tp {`SPI_CHAR_LEN_BITS+1{1'b0}}; + else + begin + if(tip) + cnt <= #Tp pos_edge ? (cnt - {{`SPI_CHAR_LEN_BITS{1'b0}}, 1'b1}) : cnt; + else + cnt <= #Tp !(|len) ? {1'b1, {`SPI_CHAR_LEN_BITS{1'b0}}} : {1'b0, len}; + end + end + + // Transfer in progress + always @(posedge clk or posedge rst) + begin + if(rst) + tip <= #Tp 1'b0; + else if(go && ~tip) + tip <= #Tp 1'b1; + else if(tip && last && pos_edge) + tip <= #Tp 1'b0; + end + + // Sending bits to the line + always @(posedge clk or posedge rst) + begin + if (rst) + s_out <= #Tp 1'b0; + else + s_out <= #Tp (tx_clk || !tip) ? data[tx_bit_pos[`SPI_CHAR_LEN_BITS-1:0]] : s_out; + end + + // Receiving bits from the line + always @(posedge clk or posedge rst) + if (rst) + data <= #Tp `SPI_CHAR_RST; + else + if (latch & !tip) + begin + if (byte_sel[0]) + data[7:0] <= #Tp p_in[7:0]; + if (byte_sel[1]) + data[15:8] <= #Tp p_in[15:8]; + if (byte_sel[2]) + data[23:16] <= #Tp p_in[23:16]; + if (byte_sel[3]) + data[31:24] <= #Tp p_in[31:24]; + end + else + data[rx_bit_pos[`SPI_CHAR_LEN_BITS-1:0]] <= #Tp rx_clk ? s_in : data[rx_bit_pos[`SPI_CHAR_LEN_BITS-1:0]]; + +endmodule +

minsoc_startup/spi_shift.v Property changes : Added: svn:executable ## -0,0 +1 ## +* \ No newline at end of property Index: minsoc_startup/spi_defines.v =================================================================== --- minsoc_startup/spi_defines.v (nonexistent) +++ minsoc_startup/spi_defines.v (revision 42) @@ -0,0 +1,139 @@ +////////////////////////////////////////////////////////////////////// +//// //// +//// spi_define.v //// +//// //// +//// This file is part of the SPI IP core project //// +//// http://www.opencores.org/projects/spi/ //// +//// //// +//// Author(s): //// +//// - Simon Srot (simons@opencores.org) //// +//// //// +//// All additional information is avaliable in the Readme.txt //// +//// file. //// +//// //// +////////////////////////////////////////////////////////////////////// +//// //// +//// Copyright (C) 2002 Authors //// +//// //// +//// This source file may be used and distributed without //// +//// restriction provided that this copyright statement is not //// +//// removed from the file and that any derivative work contains //// +//// the original copyright notice and the associated disclaimer. //// +//// //// +//// This source file is free software; you can redistribute it //// +//// and/or modify it under the terms of the GNU Lesser General //// +//// Public License as published by the Free Software Foundation; //// +//// either version 2.1 of the License, or (at your option) any //// +//// later version. //// +//// //// +//// This source is distributed in the hope that it will be //// +//// useful, but WITHOUT ANY WARRANTY; without even the implied //// +//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR //// +//// PURPOSE. See the GNU Lesser General Public License for more //// +//// details. //// +//// //// +//// You should have received a copy of the GNU Lesser General //// +//// Public License along with this source; if not, download it //// +//// from http://www.opencores.org/lgpl.shtml //// +//// //// +////////////////////////////////////////////////////////////////////// + +// +// Number of bits used for devider register. If used in system with +// low frequency of system clock this can be reduced. +// Use SPI_DIVIDER_LEN for fine tuning theexact number. +// +`define SPI_DIVIDER_LEN_8 +//`define SPI_DIVIDER_LEN_16 +//`define SPI_DIVIDER_LEN_24 +//`define SPI_DIVIDER_LEN_32 + +`ifdef SPI_DIVIDER_LEN_8 + `define SPI_DIVIDER_LEN 4 // Can be set from 1 to 8 +`endif +`ifdef SPI_DIVIDER_LEN_16 + `define SPI_DIVIDER_LEN 16 // Can be set from 9 to 16 +`endif +`ifdef SPI_DIVIDER_LEN_24 + `define SPI_DIVIDER_LEN 24 // Can be set from 17 to 24 +`endif +`ifdef SPI_DIVIDER_LEN_32 + `define SPI_DIVIDER_LEN 32 // Can be set from 25 to 32 +`endif + +// +// Maximum nuber of bits that can be send/received at once. +// Use SPI_MAX_CHAR for fine tuning the exact number, when using +// SPI_MAX_CHAR_32, SPI_MAX_CHAR_24, SPI_MAX_CHAR_16, SPI_MAX_CHAR_8. +// +//`define SPI_MAX_CHAR_128 +//`define SPI_MAX_CHAR_64 +`define SPI_MAX_CHAR_32 +//`define SPI_MAX_CHAR_24 +//`define SPI_MAX_CHAR_16 +//`define SPI_MAX_CHAR_8 + +`ifdef SPI_MAX_CHAR_128 + `define SPI_MAX_CHAR 128 // Can only be set to 128 + `define SPI_CHAR_LEN_BITS 7 +`endif +`ifdef SPI_MAX_CHAR_64 + `define SPI_MAX_CHAR 64 // Can only be set to 64 + `define SPI_CHAR_LEN_BITS 6 +`endif +`ifdef SPI_MAX_CHAR_32 + `define SPI_MAX_CHAR 32 // Can be set from 25 to 32 + `define SPI_CHAR_LEN_BITS 6 + `define SPI_CHAR_RST 32'h03000000 +`endif +`ifdef SPI_MAX_CHAR_24 + `define SPI_MAX_CHAR 24 // Can be set from 17 to 24 + `define SPI_CHAR_LEN_BITS 5 +`endif +`ifdef SPI_MAX_CHAR_16 + `define SPI_MAX_CHAR 16 // Can be set from 9 to 16 + `define SPI_CHAR_LEN_BITS 4 +`endif +`ifdef SPI_MAX_CHAR_8 + `define SPI_MAX_CHAR 8 // Can be set from 1 to 8 + `define SPI_CHAR_LEN_BITS 3 +`endif + +// +// Number of device select signals. Use SPI_SS_NB for fine tuning the +// exact number. +// +`define SPI_SS_NB 2 // Can be set from 1 to 2 + +// +// Bits of WISHBONE address used for partial decoding of SPI registers. +// +`define SPI_OFS_BITS 4:2 + +// +// Register offset +// +`define SPI_RX_0 0 +`define SPI_RX_1 1 +`define SPI_RX_2 2 +`define SPI_RX_3 3 +`define SPI_TX_0 0 +`define SPI_TX_1 1 +`define SPI_TX_2 2 +`define SPI_TX_3 3 +`define SPI_CTRL 4 +`define SPI_DEVIDE 5 +`define SPI_SS 6 + +// +// Number of bits in ctrl register +// +`define SPI_CTRL_BIT_NB 14 +`define SPI_CTRL_BIT_RST 14'h420 +// +// Control register bits +// +//`define SPI_CTRL_LSB +`define SPI_CTRL_TX_NEGEDGE +//`define SPI_CTRL_RX_NEGEDGE +

minsoc_startup/spi_defines.v Property changes : Added: svn:executable ## -0,0 +1 ## +* \ No newline at end of property Index: minsoc_startup/OR1K_startup_generic.v =================================================================== --- minsoc_startup/OR1K_startup_generic.v (nonexistent) +++ minsoc_startup/OR1K_startup_generic.v (revision 42) @@ -0,0 +1,60 @@ + +`include "minsoc_defines.v" + +module OR1K_startup + ( + input [6:2] wb_adr_i, + input wb_stb_i, + input wb_cyc_i, + output reg [31:0] wb_dat_o, + output reg wb_ack_o, + input wb_clk, + input wb_rst + ); + + always @ (posedge wb_clk or posedge wb_rst) + if (wb_rst) + wb_dat_o <= 32'h15000000; + else + case (wb_adr_i) + 0 : wb_dat_o <= 32'h18000000; + 1 : wb_dat_o <= 32'hA8200000; + 2 : wb_dat_o <= { 16'h1880 , `APP_ADDR_SPI , 8'h00 }; + 3 : wb_dat_o <= 32'hA8A00520; + 4 : wb_dat_o <= 32'hA8600001; + 5 : wb_dat_o <= 32'h04000014; + 6 : wb_dat_o <= 32'hD4041818; + 7 : wb_dat_o <= 32'h04000012; + 8 : wb_dat_o <= 32'hD4040000; + 9 : wb_dat_o <= 32'hE0431804; + 10 : wb_dat_o <= 32'h0400000F; + 11 : wb_dat_o <= 32'h9C210008; + 12 : wb_dat_o <= 32'h0400000D; + 13 : wb_dat_o <= 32'hE1031804; + 14 : wb_dat_o <= 32'hE4080000; + 15 : wb_dat_o <= 32'h0FFFFFFB; + 16 : wb_dat_o <= 32'hD4081800; + 17 : wb_dat_o <= 32'h04000008; + 18 : wb_dat_o <= 32'h9C210004; + 19 : wb_dat_o <= 32'hD4011800; + 20 : wb_dat_o <= 32'hE4011000; + 21 : wb_dat_o <= 32'h0FFFFFFC; + 22 : wb_dat_o <= 32'hA8C00100; + 23 : wb_dat_o <= 32'h44003000; + 24 : wb_dat_o <= 32'hD4040018; + 25 : wb_dat_o <= 32'hD4042810; + 26 : wb_dat_o <= 32'h84640010; + 27 : wb_dat_o <= 32'hBC030520; + 28 : wb_dat_o <= 32'h13FFFFFE; + 29 : wb_dat_o <= 32'h15000000; + 30 : wb_dat_o <= 32'h44004800; + 31 : wb_dat_o <= 32'h84640000; + endcase + + always @ (posedge wb_clk or posedge wb_rst) + if (wb_rst) + wb_ack_o <= 1'b0; + else + wb_ack_o <= wb_stb_i & wb_cyc_i & !wb_ack_o; + +endmodule // OR1K_startup

minsoc_startup/OR1K_startup_generic.v Property changes : Added: svn:executable ## -0,0 +1 ## +* \ No newline at end of property Index: minsoc_tc_top.v =================================================================== --- minsoc_tc_top.v (nonexistent) +++ minsoc_tc_top.v (revision 42) @@ -0,0 +1,1684 @@ +////////////////////////////////////////////////////////////////////// +//// //// +//// Xess Traffic Cop //// +//// //// +//// This file is part of the OR1K test application //// +//// http://www.opencores.org/cores/or1k/ //// +//// //// +//// Description //// +//// This block connectes the RISC and peripheral controller //// +//// cores together. //// +//// //// +//// To Do: //// +//// - nothing really //// +//// //// +//// Author(s): //// +//// - Damjan Lampret, lampret@opencores.org //// +//// //// +////////////////////////////////////////////////////////////////////// +//// //// +//// Copyright (C) 2002 OpenCores //// +//// //// +//// This source file may be used and distributed without //// +//// restriction provided that this copyright statement is not //// +//// removed from the file and that any derivative work contains //// +//// the original copyright notice and the associated disclaimer. //// +//// //// +//// This source file is free software; you can redistribute it //// +//// and/or modify it under the terms of the GNU Lesser General //// +//// Public License as published by the Free Software Foundation; //// +//// either version 2.1 of the License, or (at your option) any //// +//// later version. //// +//// //// +//// This source is distributed in the hope that it will be //// +//// useful, but WITHOUT ANY WARRANTY; without even the implied //// +//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR //// +//// PURPOSE. See the GNU Lesser General Public License for more //// +//// details. //// +//// //// +//// You should have received a copy of the GNU Lesser General //// +//// Public License along with this source; if not, download it //// +//// from http://www.opencores.org/lgpl.shtml //// +//// //// +////////////////////////////////////////////////////////////////////// +// +// CVS Revision History +// +// $Log: tc_top.v,v $ +// Revision 1.4 2004/04/05 08:44:34 lampret +// Merged branch_qmem into main tree. +// +// Revision 1.2 2002/03/29 20:57:30 lampret +// Removed unused ports wb_clki and wb_rst_i +// +// Revision 1.1.1.1 2002/03/21 16:55:44 lampret +// First import of the "new" XESS XSV environment. +// +// +// + +// synopsys translate_off +`include "timescale.v" +// synopsys translate_on + +// +// Width of address bus +// +`define TC_AW 32 + +// +// Width of data bus +// +`define TC_DW 32 + +// +// Width of byte select bus +// +`define TC_BSW 4 + +// +// Width of WB target inputs (coming from WB slave) +// +// data bus width + ack + err +// +`define TC_TIN_W `TC_DW+1+1 + +// +// Width of WB initiator inputs (coming from WB masters) +// +// cyc + stb + address bus width + +// byte select bus width + we + data bus width +// +`define TC_IIN_W 1+1+1+`TC_AW+`TC_BSW+1+`TC_DW + +// +// Traffic Cop Top +// +module minsoc_tc_top ( + wb_clk_i, + wb_rst_i, + + i0_wb_cyc_i, + i0_wb_stb_i, + i0_wb_adr_i, + i0_wb_sel_i, + i0_wb_we_i, + i0_wb_dat_i, + i0_wb_dat_o, + i0_wb_ack_o, + i0_wb_err_o, + + i1_wb_cyc_i, + i1_wb_stb_i, + i1_wb_adr_i, + i1_wb_sel_i, + i1_wb_we_i, + i1_wb_dat_i, + i1_wb_dat_o, + i1_wb_ack_o, + i1_wb_err_o, + + i2_wb_cyc_i, + i2_wb_stb_i, + i2_wb_adr_i, + i2_wb_sel_i, + i2_wb_we_i, + i2_wb_dat_i, + i2_wb_dat_o, + i2_wb_ack_o, + i2_wb_err_o, + + i3_wb_cyc_i, + i3_wb_stb_i, + i3_wb_adr_i, + i3_wb_sel_i, + i3_wb_we_i, + i3_wb_dat_i, + i3_wb_dat_o, + i3_wb_ack_o, + i3_wb_err_o, + + i4_wb_cyc_i, + i4_wb_stb_i, + i4_wb_adr_i, + i4_wb_sel_i, + i4_wb_we_i, + i4_wb_dat_i, + i4_wb_dat_o, + i4_wb_ack_o, + i4_wb_err_o, + + i5_wb_cyc_i, + i5_wb_stb_i, + i5_wb_adr_i, + i5_wb_sel_i, + i5_wb_we_i, + i5_wb_dat_i, + i5_wb_dat_o, + i5_wb_ack_o, + i5_wb_err_o, + + i6_wb_cyc_i, + i6_wb_stb_i, + i6_wb_adr_i, + i6_wb_sel_i, + i6_wb_we_i, + i6_wb_dat_i, + i6_wb_dat_o, + i6_wb_ack_o, + i6_wb_err_o, + + i7_wb_cyc_i, + i7_wb_stb_i, + i7_wb_adr_i, + i7_wb_sel_i, + i7_wb_we_i, + i7_wb_dat_i, + i7_wb_dat_o, + i7_wb_ack_o, + i7_wb_err_o, + + t0_wb_cyc_o, + t0_wb_stb_o, + t0_wb_adr_o, + t0_wb_sel_o, + t0_wb_we_o, + t0_wb_dat_o, + t0_wb_dat_i, + t0_wb_ack_i, + t0_wb_err_i, + + t1_wb_cyc_o, + t1_wb_stb_o, + t1_wb_adr_o, + t1_wb_sel_o, + t1_wb_we_o, + t1_wb_dat_o, + t1_wb_dat_i, + t1_wb_ack_i, + t1_wb_err_i, + + t2_wb_cyc_o, + t2_wb_stb_o, + t2_wb_adr_o, + t2_wb_sel_o, + t2_wb_we_o, + t2_wb_dat_o, + t2_wb_dat_i, + t2_wb_ack_i, + t2_wb_err_i, + + t3_wb_cyc_o, + t3_wb_stb_o, + t3_wb_adr_o, + t3_wb_sel_o, + t3_wb_we_o, + t3_wb_dat_o, + t3_wb_dat_i, + t3_wb_ack_i, + t3_wb_err_i, + + t4_wb_cyc_o, + t4_wb_stb_o, + t4_wb_adr_o, + t4_wb_sel_o, + t4_wb_we_o, + t4_wb_dat_o, + t4_wb_dat_i, + t4_wb_ack_i, + t4_wb_err_i, + + t5_wb_cyc_o, + t5_wb_stb_o, + t5_wb_adr_o, + t5_wb_sel_o, + t5_wb_we_o, + t5_wb_dat_o, + t5_wb_dat_i, + t5_wb_ack_i, + t5_wb_err_i, + + t6_wb_cyc_o, + t6_wb_stb_o, + t6_wb_adr_o, + t6_wb_sel_o, + t6_wb_we_o, + t6_wb_dat_o, + t6_wb_dat_i, + t6_wb_ack_i, + t6_wb_err_i, + + t7_wb_cyc_o, + t7_wb_stb_o, + t7_wb_adr_o, + t7_wb_sel_o, + t7_wb_we_o, + t7_wb_dat_o, + t7_wb_dat_i, + t7_wb_ack_i, + t7_wb_err_i, + + t8_wb_cyc_o, + t8_wb_stb_o, + t8_wb_adr_o, + t8_wb_sel_o, + t8_wb_we_o, + t8_wb_dat_o, + t8_wb_dat_i, + t8_wb_ack_i, + t8_wb_err_i + +); + +// +// Parameters +// +parameter t0_addr_w = 4; +parameter t0_addr = 4'd8; +parameter t1_addr_w = 4; +parameter t1_addr = 4'd0; +parameter t28c_addr_w = 4; +parameter t28_addr = 4'd0; +parameter t28i_addr_w = 4; +parameter t2_addr = 4'd1; +parameter t3_addr = 4'd2; +parameter t4_addr = 4'd3; +parameter t5_addr = 4'd4; +parameter t6_addr = 4'd5; +parameter t7_addr = 4'd6; +parameter t8_addr = 4'd7; + +// +// I/O Ports +// +input wb_clk_i; +input wb_rst_i; + +// +// WB slave i/f connecting initiator 0 +// +input i0_wb_cyc_i; +input i0_wb_stb_i; +input [`TC_AW-1:0] i0_wb_adr_i; +input [`TC_BSW-1:0] i0_wb_sel_i; +input i0_wb_we_i; +input [`TC_DW-1:0] i0_wb_dat_i; +output [`TC_DW-1:0] i0_wb_dat_o; +output i0_wb_ack_o; +output i0_wb_err_o; + +// +// WB slave i/f connecting initiator 1 +// +input i1_wb_cyc_i; +input i1_wb_stb_i; +input [`TC_AW-1:0] i1_wb_adr_i; +input [`TC_BSW-1:0] i1_wb_sel_i; +input i1_wb_we_i; +input [`TC_DW-1:0] i1_wb_dat_i; +output [`TC_DW-1:0] i1_wb_dat_o; +output i1_wb_ack_o; +output i1_wb_err_o; + +// +// WB slave i/f connecting initiator 2 +// +input i2_wb_cyc_i; +input i2_wb_stb_i; +input [`TC_AW-1:0] i2_wb_adr_i; +input [`TC_BSW-1:0] i2_wb_sel_i; +input i2_wb_we_i; +input [`TC_DW-1:0] i2_wb_dat_i; +output [`TC_DW-1:0] i2_wb_dat_o; +output i2_wb_ack_o; +output i2_wb_err_o; + +// +// WB slave i/f connecting initiator 3 +// +input i3_wb_cyc_i; +input i3_wb_stb_i; +input [`TC_AW-1:0] i3_wb_adr_i; +input [`TC_BSW-1:0] i3_wb_sel_i; +input i3_wb_we_i; +input [`TC_DW-1:0] i3_wb_dat_i; +output [`TC_DW-1:0] i3_wb_dat_o; +output i3_wb_ack_o; +output i3_wb_err_o; + +// +// WB slave i/f connecting initiator 4 +// +input i4_wb_cyc_i; +input i4_wb_stb_i; +input [`TC_AW-1:0] i4_wb_adr_i; +input [`TC_BSW-1:0] i4_wb_sel_i; +input i4_wb_we_i; +input [`TC_DW-1:0] i4_wb_dat_i; +output [`TC_DW-1:0] i4_wb_dat_o; +output i4_wb_ack_o; +output i4_wb_err_o; + +// +// WB slave i/f connecting initiator 5 +// +input i5_wb_cyc_i; +input i5_wb_stb_i; +input [`TC_AW-1:0] i5_wb_adr_i; +input [`TC_BSW-1:0] i5_wb_sel_i; +input i5_wb_we_i; +input [`TC_DW-1:0] i5_wb_dat_i; +output [`TC_DW-1:0] i5_wb_dat_o; +output i5_wb_ack_o; +output i5_wb_err_o; + +// +// WB slave i/f connecting initiator 6 +// +input i6_wb_cyc_i; +input i6_wb_stb_i; +input [`TC_AW-1:0] i6_wb_adr_i; +input [`TC_BSW-1:0] i6_wb_sel_i; +input i6_wb_we_i; +input [`TC_DW-1:0] i6_wb_dat_i; +output [`TC_DW-1:0] i6_wb_dat_o; +output i6_wb_ack_o; +output i6_wb_err_o; + +// +// WB slave i/f connecting initiator 7 +// +input i7_wb_cyc_i; +input i7_wb_stb_i; +input [`TC_AW-1:0] i7_wb_adr_i; +input [`TC_BSW-1:0] i7_wb_sel_i; +input i7_wb_we_i; +input [`TC_DW-1:0] i7_wb_dat_i; +output [`TC_DW-1:0] i7_wb_dat_o; +output i7_wb_ack_o; +output i7_wb_err_o; + +// +// WB master i/f connecting target 0 +// +output t0_wb_cyc_o; +output t0_wb_stb_o; +output [`TC_AW-1:0] t0_wb_adr_o; +output [`TC_BSW-1:0] t0_wb_sel_o; +output t0_wb_we_o; +output [`TC_DW-1:0] t0_wb_dat_o; +input [`TC_DW-1:0] t0_wb_dat_i; +input t0_wb_ack_i; +input t0_wb_err_i; + +// +// WB master i/f connecting target 1 +// +output t1_wb_cyc_o; +output t1_wb_stb_o; +output [`TC_AW-1:0] t1_wb_adr_o; +output [`TC_BSW-1:0] t1_wb_sel_o; +output t1_wb_we_o; +output [`TC_DW-1:0] t1_wb_dat_o; +input [`TC_DW-1:0] t1_wb_dat_i; +input t1_wb_ack_i; +input t1_wb_err_i; + +// +// WB master i/f connecting target 2 +// +output t2_wb_cyc_o; +output t2_wb_stb_o; +output [`TC_AW-1:0] t2_wb_adr_o; +output [`TC_BSW-1:0] t2_wb_sel_o; +output t2_wb_we_o; +output [`TC_DW-1:0] t2_wb_dat_o; +input [`TC_DW-1:0] t2_wb_dat_i; +input t2_wb_ack_i; +input t2_wb_err_i; + +// +// WB master i/f connecting target 3 +// +output t3_wb_cyc_o; +output t3_wb_stb_o; +output [`TC_AW-1:0] t3_wb_adr_o; +output [`TC_BSW-1:0] t3_wb_sel_o; +output t3_wb_we_o; +output [`TC_DW-1:0] t3_wb_dat_o; +input [`TC_DW-1:0] t3_wb_dat_i; +input t3_wb_ack_i; +input t3_wb_err_i; + +// +// WB master i/f connecting target 4 +// +output t4_wb_cyc_o; +output t4_wb_stb_o; +output [`TC_AW-1:0] t4_wb_adr_o; +output [`TC_BSW-1:0] t4_wb_sel_o; +output t4_wb_we_o; +output [`TC_DW-1:0] t4_wb_dat_o; +input [`TC_DW-1:0] t4_wb_dat_i; +input t4_wb_ack_i; +input t4_wb_err_i; + +// +// WB master i/f connecting target 5 +// +output t5_wb_cyc_o; +output t5_wb_stb_o; +output [`TC_AW-1:0] t5_wb_adr_o; +output [`TC_BSW-1:0] t5_wb_sel_o; +output t5_wb_we_o; +output [`TC_DW-1:0] t5_wb_dat_o; +input [`TC_DW-1:0] t5_wb_dat_i; +input t5_wb_ack_i; +input t5_wb_err_i; + +// +// WB master i/f connecting target 6 +// +output t6_wb_cyc_o; +output t6_wb_stb_o; +output [`TC_AW-1:0] t6_wb_adr_o; +output [`TC_BSW-1:0] t6_wb_sel_o; +output t6_wb_we_o; +output [`TC_DW-1:0] t6_wb_dat_o; +input [`TC_DW-1:0] t6_wb_dat_i; +input t6_wb_ack_i; +input t6_wb_err_i; + +// +// WB master i/f connecting target 7 +// +output t7_wb_cyc_o; +output t7_wb_stb_o; +output [`TC_AW-1:0] t7_wb_adr_o; +output [`TC_BSW-1:0] t7_wb_sel_o; +output t7_wb_we_o; +output [`TC_DW-1:0] t7_wb_dat_o; +input [`TC_DW-1:0] t7_wb_dat_i; +input t7_wb_ack_i; +input t7_wb_err_i; + +// +// WB master i/f connecting target 8 +// +output t8_wb_cyc_o; +output t8_wb_stb_o; +output [`TC_AW-1:0] t8_wb_adr_o; +output [`TC_BSW-1:0] t8_wb_sel_o; +output t8_wb_we_o; +output [`TC_DW-1:0] t8_wb_dat_o; +input [`TC_DW-1:0] t8_wb_dat_i; +input t8_wb_ack_i; +input t8_wb_err_i; + +// +// Internal wires & registers +// + +// +// Outputs for initiators from both mi_to_st blocks +// +wire [`TC_DW-1:0] xi0_wb_dat_o; +wire xi0_wb_ack_o; +wire xi0_wb_err_o; +wire [`TC_DW-1:0] xi1_wb_dat_o; +wire xi1_wb_ack_o; +wire xi1_wb_err_o; +wire [`TC_DW-1:0] xi2_wb_dat_o; +wire xi2_wb_ack_o; +wire xi2_wb_err_o; +wire [`TC_DW-1:0] xi3_wb_dat_o; +wire xi3_wb_ack_o; +wire xi3_wb_err_o; +wire [`TC_DW-1:0] xi4_wb_dat_o; +wire xi4_wb_ack_o; +wire xi4_wb_err_o; +wire [`TC_DW-1:0] xi5_wb_dat_o; +wire xi5_wb_ack_o; +wire xi5_wb_err_o; +wire [`TC_DW-1:0] xi6_wb_dat_o; +wire xi6_wb_ack_o; +wire xi6_wb_err_o; +wire [`TC_DW-1:0] xi7_wb_dat_o; +wire xi7_wb_ack_o; +wire xi7_wb_err_o; +wire [`TC_DW-1:0] yi0_wb_dat_o; +wire yi0_wb_ack_o; +wire yi0_wb_err_o; +wire [`TC_DW-1:0] yi1_wb_dat_o; +wire yi1_wb_ack_o; +wire yi1_wb_err_o; +wire [`TC_DW-1:0] yi2_wb_dat_o; +wire yi2_wb_ack_o; +wire yi2_wb_err_o; +wire [`TC_DW-1:0] yi3_wb_dat_o; +wire yi3_wb_ack_o; +wire yi3_wb_err_o; +wire [`TC_DW-1:0] yi4_wb_dat_o; +wire yi4_wb_ack_o; +wire yi4_wb_err_o; +wire [`TC_DW-1:0] yi5_wb_dat_o; +wire yi5_wb_ack_o; +wire yi5_wb_err_o; +wire [`TC_DW-1:0] yi6_wb_dat_o; +wire yi6_wb_ack_o; +wire yi6_wb_err_o; +wire [`TC_DW-1:0] yi7_wb_dat_o; +wire yi7_wb_ack_o; +wire yi7_wb_err_o; + +// +// Intermediate signals connecting peripheral channel's +// mi_to_st and si_to_mt blocks. +// +wire z_wb_cyc_i; +wire z_wb_stb_i; +wire [`TC_AW-1:0] z_wb_adr_i; +wire [`TC_BSW-1:0] z_wb_sel_i; +wire z_wb_we_i; +wire [`TC_DW-1:0] z_wb_dat_i; +wire [`TC_DW-1:0] z_wb_dat_t; +wire z_wb_ack_t; +wire z_wb_err_t; + +// +// Outputs for initiators are ORed from both mi_to_st blocks +// +assign i0_wb_dat_o = xi0_wb_dat_o | yi0_wb_dat_o; +assign i0_wb_ack_o = xi0_wb_ack_o | yi0_wb_ack_o; +assign i0_wb_err_o = xi0_wb_err_o | yi0_wb_err_o; +assign i1_wb_dat_o = xi1_wb_dat_o | yi1_wb_dat_o; +assign i1_wb_ack_o = xi1_wb_ack_o | yi1_wb_ack_o; +assign i1_wb_err_o = xi1_wb_err_o | yi1_wb_err_o; +assign i2_wb_dat_o = xi2_wb_dat_o | yi2_wb_dat_o; +assign i2_wb_ack_o = xi2_wb_ack_o | yi2_wb_ack_o; +assign i2_wb_err_o = xi2_wb_err_o | yi2_wb_err_o; +assign i3_wb_dat_o = xi3_wb_dat_o | yi3_wb_dat_o; +assign i3_wb_ack_o = xi3_wb_ack_o | yi3_wb_ack_o; +assign i3_wb_err_o = xi3_wb_err_o | yi3_wb_err_o; +assign i4_wb_dat_o = xi4_wb_dat_o | yi4_wb_dat_o; +assign i4_wb_ack_o = xi4_wb_ack_o | yi4_wb_ack_o; +assign i4_wb_err_o = xi4_wb_err_o | yi4_wb_err_o; +assign i5_wb_dat_o = xi5_wb_dat_o | yi5_wb_dat_o; +assign i5_wb_ack_o = xi5_wb_ack_o | yi5_wb_ack_o; +assign i5_wb_err_o = xi5_wb_err_o | yi5_wb_err_o; +assign i6_wb_dat_o = xi6_wb_dat_o | yi6_wb_dat_o; +assign i6_wb_ack_o = xi6_wb_ack_o | yi6_wb_ack_o; +assign i6_wb_err_o = xi6_wb_err_o | yi6_wb_err_o; +assign i7_wb_dat_o = xi7_wb_dat_o | yi7_wb_dat_o; +assign i7_wb_ack_o = xi7_wb_ack_o | yi7_wb_ack_o; +assign i7_wb_err_o = xi7_wb_err_o | yi7_wb_err_o; + +// +// From initiators to target 0 +// +tc_mi_to_st #(t0_addr_w, t0_addr, + 0, t0_addr_w, t0_addr) t0_ch( + .wb_clk_i(wb_clk_i), + .wb_rst_i(wb_rst_i), + + .i0_wb_cyc_i(i0_wb_cyc_i), + .i0_wb_stb_i(i0_wb_stb_i), + .i0_wb_adr_i(i0_wb_adr_i), + .i0_wb_sel_i(i0_wb_sel_i), + .i0_wb_we_i(i0_wb_we_i), + .i0_wb_dat_i(i0_wb_dat_i), + .i0_wb_dat_o(xi0_wb_dat_o), + .i0_wb_ack_o(xi0_wb_ack_o), + .i0_wb_err_o(xi0_wb_err_o), + + .i1_wb_cyc_i(i1_wb_cyc_i), + .i1_wb_stb_i(i1_wb_stb_i), + .i1_wb_adr_i(i1_wb_adr_i), + .i1_wb_sel_i(i1_wb_sel_i), + .i1_wb_we_i(i1_wb_we_i), + .i1_wb_dat_i(i1_wb_dat_i), + .i1_wb_dat_o(xi1_wb_dat_o), + .i1_wb_ack_o(xi1_wb_ack_o), + .i1_wb_err_o(xi1_wb_err_o), + + .i2_wb_cyc_i(i2_wb_cyc_i), + .i2_wb_stb_i(i2_wb_stb_i), + .i2_wb_adr_i(i2_wb_adr_i), + .i2_wb_sel_i(i2_wb_sel_i), + .i2_wb_we_i(i2_wb_we_i), + .i2_wb_dat_i(i2_wb_dat_i), + .i2_wb_dat_o(xi2_wb_dat_o), + .i2_wb_ack_o(xi2_wb_ack_o), + .i2_wb_err_o(xi2_wb_err_o), + + .i3_wb_cyc_i(i3_wb_cyc_i), + .i3_wb_stb_i(i3_wb_stb_i), + .i3_wb_adr_i(i3_wb_adr_i), + .i3_wb_sel_i(i3_wb_sel_i), + .i3_wb_we_i(i3_wb_we_i), + .i3_wb_dat_i(i3_wb_dat_i), + .i3_wb_dat_o(xi3_wb_dat_o), + .i3_wb_ack_o(xi3_wb_ack_o), + .i3_wb_err_o(xi3_wb_err_o), + + .i4_wb_cyc_i(i4_wb_cyc_i), + .i4_wb_stb_i(i4_wb_stb_i), + .i4_wb_adr_i(i4_wb_adr_i), + .i4_wb_sel_i(i4_wb_sel_i), + .i4_wb_we_i(i4_wb_we_i), + .i4_wb_dat_i(i4_wb_dat_i), + .i4_wb_dat_o(xi4_wb_dat_o), + .i4_wb_ack_o(xi4_wb_ack_o), + .i4_wb_err_o(xi4_wb_err_o), + + .i5_wb_cyc_i(i5_wb_cyc_i), + .i5_wb_stb_i(i5_wb_stb_i), + .i5_wb_adr_i(i5_wb_adr_i), + .i5_wb_sel_i(i5_wb_sel_i), + .i5_wb_we_i(i5_wb_we_i), + .i5_wb_dat_i(i5_wb_dat_i), + .i5_wb_dat_o(xi5_wb_dat_o), + .i5_wb_ack_o(xi5_wb_ack_o), + .i5_wb_err_o(xi5_wb_err_o), + + .i6_wb_cyc_i(i6_wb_cyc_i), + .i6_wb_stb_i(i6_wb_stb_i), + .i6_wb_adr_i(i6_wb_adr_i), + .i6_wb_sel_i(i6_wb_sel_i), + .i6_wb_we_i(i6_wb_we_i), + .i6_wb_dat_i(i6_wb_dat_i), + .i6_wb_dat_o(xi6_wb_dat_o), + .i6_wb_ack_o(xi6_wb_ack_o), + .i6_wb_err_o(xi6_wb_err_o), + + .i7_wb_cyc_i(i7_wb_cyc_i), + .i7_wb_stb_i(i7_wb_stb_i), + .i7_wb_adr_i(i7_wb_adr_i), + .i7_wb_sel_i(i7_wb_sel_i), + .i7_wb_we_i(i7_wb_we_i), + .i7_wb_dat_i(i7_wb_dat_i), + .i7_wb_dat_o(xi7_wb_dat_o), + .i7_wb_ack_o(xi7_wb_ack_o), + .i7_wb_err_o(xi7_wb_err_o), + + .t0_wb_cyc_o(t0_wb_cyc_o), + .t0_wb_stb_o(t0_wb_stb_o), + .t0_wb_adr_o(t0_wb_adr_o), + .t0_wb_sel_o(t0_wb_sel_o), + .t0_wb_we_o(t0_wb_we_o), + .t0_wb_dat_o(t0_wb_dat_o), + .t0_wb_dat_i(t0_wb_dat_i), + .t0_wb_ack_i(t0_wb_ack_i), + .t0_wb_err_i(t0_wb_err_i) + +); + +// +// From initiators to targets 1-8 (upper part) +// +tc_mi_to_st #(t1_addr_w, t1_addr, + 1, t28c_addr_w, t28_addr) t18_ch_upper( + .wb_clk_i(wb_clk_i), + .wb_rst_i(wb_rst_i), + + .i0_wb_cyc_i(i0_wb_cyc_i), + .i0_wb_stb_i(i0_wb_stb_i), + .i0_wb_adr_i(i0_wb_adr_i), + .i0_wb_sel_i(i0_wb_sel_i), + .i0_wb_we_i(i0_wb_we_i), + .i0_wb_dat_i(i0_wb_dat_i), + .i0_wb_dat_o(yi0_wb_dat_o), + .i0_wb_ack_o(yi0_wb_ack_o), + .i0_wb_err_o(yi0_wb_err_o), + + .i1_wb_cyc_i(i1_wb_cyc_i), + .i1_wb_stb_i(i1_wb_stb_i), + .i1_wb_adr_i(i1_wb_adr_i), + .i1_wb_sel_i(i1_wb_sel_i), + .i1_wb_we_i(i1_wb_we_i), + .i1_wb_dat_i(i1_wb_dat_i), + .i1_wb_dat_o(yi1_wb_dat_o), + .i1_wb_ack_o(yi1_wb_ack_o), + .i1_wb_err_o(yi1_wb_err_o), + + .i2_wb_cyc_i(i2_wb_cyc_i), + .i2_wb_stb_i(i2_wb_stb_i), + .i2_wb_adr_i(i2_wb_adr_i), + .i2_wb_sel_i(i2_wb_sel_i), + .i2_wb_we_i(i2_wb_we_i), + .i2_wb_dat_i(i2_wb_dat_i), + .i2_wb_dat_o(yi2_wb_dat_o), + .i2_wb_ack_o(yi2_wb_ack_o), + .i2_wb_err_o(yi2_wb_err_o), + + .i3_wb_cyc_i(i3_wb_cyc_i), + .i3_wb_stb_i(i3_wb_stb_i), + .i3_wb_adr_i(i3_wb_adr_i), + .i3_wb_sel_i(i3_wb_sel_i), + .i3_wb_we_i(i3_wb_we_i), + .i3_wb_dat_i(i3_wb_dat_i), + .i3_wb_dat_o(yi3_wb_dat_o), + .i3_wb_ack_o(yi3_wb_ack_o), + .i3_wb_err_o(yi3_wb_err_o), + + .i4_wb_cyc_i(i4_wb_cyc_i), + .i4_wb_stb_i(i4_wb_stb_i), + .i4_wb_adr_i(i4_wb_adr_i), + .i4_wb_sel_i(i4_wb_sel_i), + .i4_wb_we_i(i4_wb_we_i), + .i4_wb_dat_i(i4_wb_dat_i), + .i4_wb_dat_o(yi4_wb_dat_o), + .i4_wb_ack_o(yi4_wb_ack_o), + .i4_wb_err_o(yi4_wb_err_o), + + .i5_wb_cyc_i(i5_wb_cyc_i), + .i5_wb_stb_i(i5_wb_stb_i), + .i5_wb_adr_i(i5_wb_adr_i), + .i5_wb_sel_i(i5_wb_sel_i), + .i5_wb_we_i(i5_wb_we_i), + .i5_wb_dat_i(i5_wb_dat_i), + .i5_wb_dat_o(yi5_wb_dat_o), + .i5_wb_ack_o(yi5_wb_ack_o), + .i5_wb_err_o(yi5_wb_err_o), + + .i6_wb_cyc_i(i6_wb_cyc_i), + .i6_wb_stb_i(i6_wb_stb_i), + .i6_wb_adr_i(i6_wb_adr_i), + .i6_wb_sel_i(i6_wb_sel_i), + .i6_wb_we_i(i6_wb_we_i), + .i6_wb_dat_i(i6_wb_dat_i), + .i6_wb_dat_o(yi6_wb_dat_o), + .i6_wb_ack_o(yi6_wb_ack_o), + .i6_wb_err_o(yi6_wb_err_o), + + .i7_wb_cyc_i(i7_wb_cyc_i), + .i7_wb_stb_i(i7_wb_stb_i), + .i7_wb_adr_i(i7_wb_adr_i), + .i7_wb_sel_i(i7_wb_sel_i), + .i7_wb_we_i(i7_wb_we_i), + .i7_wb_dat_i(i7_wb_dat_i), + .i7_wb_dat_o(yi7_wb_dat_o), + .i7_wb_ack_o(yi7_wb_ack_o), + .i7_wb_err_o(yi7_wb_err_o), + + .t0_wb_cyc_o(z_wb_cyc_i), + .t0_wb_stb_o(z_wb_stb_i), + .t0_wb_adr_o(z_wb_adr_i), + .t0_wb_sel_o(z_wb_sel_i), + .t0_wb_we_o(z_wb_we_i), + .t0_wb_dat_o(z_wb_dat_i), + .t0_wb_dat_i(z_wb_dat_t), + .t0_wb_ack_i(z_wb_ack_t), + .t0_wb_err_i(z_wb_err_t) + +); + +// +// From initiators to targets 1-8 (lower part) +// +tc_si_to_mt #(t1_addr_w, t1_addr, t28i_addr_w, t2_addr, t3_addr, + t4_addr, t5_addr, t6_addr, t7_addr, t8_addr) t18_ch_lower( + + .i0_wb_cyc_i(z_wb_cyc_i), + .i0_wb_stb_i(z_wb_stb_i), + .i0_wb_adr_i(z_wb_adr_i), + .i0_wb_sel_i(z_wb_sel_i), + .i0_wb_we_i(z_wb_we_i), + .i0_wb_dat_i(z_wb_dat_i), + .i0_wb_dat_o(z_wb_dat_t), + .i0_wb_ack_o(z_wb_ack_t), + .i0_wb_err_o(z_wb_err_t), + + .t0_wb_cyc_o(t1_wb_cyc_o), + .t0_wb_stb_o(t1_wb_stb_o), + .t0_wb_adr_o(t1_wb_adr_o), + .t0_wb_sel_o(t1_wb_sel_o), + .t0_wb_we_o(t1_wb_we_o), + .t0_wb_dat_o(t1_wb_dat_o), + .t0_wb_dat_i(t1_wb_dat_i), + .t0_wb_ack_i(t1_wb_ack_i), + .t0_wb_err_i(t1_wb_err_i), + + .t1_wb_cyc_o(t2_wb_cyc_o), + .t1_wb_stb_o(t2_wb_stb_o), + .t1_wb_adr_o(t2_wb_adr_o), + .t1_wb_sel_o(t2_wb_sel_o), + .t1_wb_we_o(t2_wb_we_o), + .t1_wb_dat_o(t2_wb_dat_o), + .t1_wb_dat_i(t2_wb_dat_i), + .t1_wb_ack_i(t2_wb_ack_i), + .t1_wb_err_i(t2_wb_err_i), + + .t2_wb_cyc_o(t3_wb_cyc_o), + .t2_wb_stb_o(t3_wb_stb_o), + .t2_wb_adr_o(t3_wb_adr_o), + .t2_wb_sel_o(t3_wb_sel_o), + .t2_wb_we_o(t3_wb_we_o), + .t2_wb_dat_o(t3_wb_dat_o), + .t2_wb_dat_i(t3_wb_dat_i), + .t2_wb_ack_i(t3_wb_ack_i), + .t2_wb_err_i(t3_wb_err_i), + + .t3_wb_cyc_o(t4_wb_cyc_o), + .t3_wb_stb_o(t4_wb_stb_o), + .t3_wb_adr_o(t4_wb_adr_o), + .t3_wb_sel_o(t4_wb_sel_o), + .t3_wb_we_o(t4_wb_we_o), + .t3_wb_dat_o(t4_wb_dat_o), + .t3_wb_dat_i(t4_wb_dat_i), + .t3_wb_ack_i(t4_wb_ack_i), + .t3_wb_err_i(t4_wb_err_i), + + .t4_wb_cyc_o(t5_wb_cyc_o), + .t4_wb_stb_o(t5_wb_stb_o), + .t4_wb_adr_o(t5_wb_adr_o), + .t4_wb_sel_o(t5_wb_sel_o), + .t4_wb_we_o(t5_wb_we_o), + .t4_wb_dat_o(t5_wb_dat_o), + .t4_wb_dat_i(t5_wb_dat_i), + .t4_wb_ack_i(t5_wb_ack_i), + .t4_wb_err_i(t5_wb_err_i), + + .t5_wb_cyc_o(t6_wb_cyc_o), + .t5_wb_stb_o(t6_wb_stb_o), + .t5_wb_adr_o(t6_wb_adr_o), + .t5_wb_sel_o(t6_wb_sel_o), + .t5_wb_we_o(t6_wb_we_o), + .t5_wb_dat_o(t6_wb_dat_o), + .t5_wb_dat_i(t6_wb_dat_i), + .t5_wb_ack_i(t6_wb_ack_i), + .t5_wb_err_i(t6_wb_err_i), + + .t6_wb_cyc_o(t7_wb_cyc_o), + .t6_wb_stb_o(t7_wb_stb_o), + .t6_wb_adr_o(t7_wb_adr_o), + .t6_wb_sel_o(t7_wb_sel_o), + .t6_wb_we_o(t7_wb_we_o), + .t6_wb_dat_o(t7_wb_dat_o), + .t6_wb_dat_i(t7_wb_dat_i), + .t6_wb_ack_i(t7_wb_ack_i), + .t6_wb_err_i(t7_wb_err_i), + + .t7_wb_cyc_o(t8_wb_cyc_o), + .t7_wb_stb_o(t8_wb_stb_o), + .t7_wb_adr_o(t8_wb_adr_o), + .t7_wb_sel_o(t8_wb_sel_o), + .t7_wb_we_o(t8_wb_we_o), + .t7_wb_dat_o(t8_wb_dat_o), + .t7_wb_dat_i(t8_wb_dat_i), + .t7_wb_ack_i(t8_wb_ack_i), + .t7_wb_err_i(t8_wb_err_i) + +); + +endmodule + +// +// Multiple initiator to single target +// +module tc_mi_to_st ( + wb_clk_i, + wb_rst_i, + + i0_wb_cyc_i, + i0_wb_stb_i, + i0_wb_adr_i, + i0_wb_sel_i, + i0_wb_we_i, + i0_wb_dat_i, + i0_wb_dat_o, + i0_wb_ack_o, + i0_wb_err_o, + + i1_wb_cyc_i, + i1_wb_stb_i, + i1_wb_adr_i, + i1_wb_sel_i, + i1_wb_we_i, + i1_wb_dat_i, + i1_wb_dat_o, + i1_wb_ack_o, + i1_wb_err_o, + + i2_wb_cyc_i, + i2_wb_stb_i, + i2_wb_adr_i, + i2_wb_sel_i, + i2_wb_we_i, + i2_wb_dat_i, + i2_wb_dat_o, + i2_wb_ack_o, + i2_wb_err_o, + + i3_wb_cyc_i, + i3_wb_stb_i, + i3_wb_adr_i, + i3_wb_sel_i, + i3_wb_we_i, + i3_wb_dat_i, + i3_wb_dat_o, + i3_wb_ack_o, + i3_wb_err_o, + + i4_wb_cyc_i, + i4_wb_stb_i, + i4_wb_adr_i, + i4_wb_sel_i, + i4_wb_we_i, + i4_wb_dat_i, + i4_wb_dat_o, + i4_wb_ack_o, + i4_wb_err_o, + + i5_wb_cyc_i, + i5_wb_stb_i, + i5_wb_adr_i, + i5_wb_sel_i, + i5_wb_we_i, + i5_wb_dat_i, + i5_wb_dat_o, + i5_wb_ack_o, + i5_wb_err_o, + + i6_wb_cyc_i, + i6_wb_stb_i, + i6_wb_adr_i, + i6_wb_sel_i, + i6_wb_we_i, + i6_wb_dat_i, + i6_wb_dat_o, + i6_wb_ack_o, + i6_wb_err_o, + + i7_wb_cyc_i, + i7_wb_stb_i, + i7_wb_adr_i, + i7_wb_sel_i, + i7_wb_we_i, + i7_wb_dat_i, + i7_wb_dat_o, + i7_wb_ack_o, + i7_wb_err_o, + + t0_wb_cyc_o, + t0_wb_stb_o, + t0_wb_adr_o, + t0_wb_sel_o, + t0_wb_we_o, + t0_wb_dat_o, + t0_wb_dat_i, + t0_wb_ack_i, + t0_wb_err_i + +); + +// +// Parameters +// +parameter t0_addr_w = 2; +parameter t0_addr = 2'b00; +parameter multitarg = 1'b0; +parameter t17_addr_w = 2; +parameter t17_addr = 2'b00; + +// +// I/O Ports +// +input wb_clk_i; +input wb_rst_i; + +// +// WB slave i/f connecting initiator 0 +// +input i0_wb_cyc_i; +input i0_wb_stb_i; +input [`TC_AW-1:0] i0_wb_adr_i; +input [`TC_BSW-1:0] i0_wb_sel_i; +input i0_wb_we_i; +input [`TC_DW-1:0] i0_wb_dat_i; +output [`TC_DW-1:0] i0_wb_dat_o; +output i0_wb_ack_o; +output i0_wb_err_o; + +// +// WB slave i/f connecting initiator 1 +// +input i1_wb_cyc_i; +input i1_wb_stb_i; +input [`TC_AW-1:0] i1_wb_adr_i; +input [`TC_BSW-1:0] i1_wb_sel_i; +input i1_wb_we_i; +input [`TC_DW-1:0] i1_wb_dat_i; +output [`TC_DW-1:0] i1_wb_dat_o; +output i1_wb_ack_o; +output i1_wb_err_o; + +// +// WB slave i/f connecting initiator 2 +// +input i2_wb_cyc_i; +input i2_wb_stb_i; +input [`TC_AW-1:0] i2_wb_adr_i; +input [`TC_BSW-1:0] i2_wb_sel_i; +input i2_wb_we_i; +input [`TC_DW-1:0] i2_wb_dat_i; +output [`TC_DW-1:0] i2_wb_dat_o; +output i2_wb_ack_o; +output i2_wb_err_o; + +// +// WB slave i/f connecting initiator 3 +// +input i3_wb_cyc_i; +input i3_wb_stb_i; +input [`TC_AW-1:0] i3_wb_adr_i; +input [`TC_BSW-1:0] i3_wb_sel_i; +input i3_wb_we_i; +input [`TC_DW-1:0] i3_wb_dat_i; +output [`TC_DW-1:0] i3_wb_dat_o; +output i3_wb_ack_o; +output i3_wb_err_o; + +// +// WB slave i/f connecting initiator 4 +// +input i4_wb_cyc_i; +input i4_wb_stb_i; +input [`TC_AW-1:0] i4_wb_adr_i; +input [`TC_BSW-1:0] i4_wb_sel_i; +input i4_wb_we_i; +input [`TC_DW-1:0] i4_wb_dat_i; +output [`TC_DW-1:0] i4_wb_dat_o; +output i4_wb_ack_o; +output i4_wb_err_o; + +// +// WB slave i/f connecting initiator 5 +// +input i5_wb_cyc_i; +input i5_wb_stb_i; +input [`TC_AW-1:0] i5_wb_adr_i; +input [`TC_BSW-1:0] i5_wb_sel_i; +input i5_wb_we_i; +input [`TC_DW-1:0] i5_wb_dat_i; +output [`TC_DW-1:0] i5_wb_dat_o; +output i5_wb_ack_o; +output i5_wb_err_o; + +// +// WB slave i/f connecting initiator 6 +// +input i6_wb_cyc_i; +input i6_wb_stb_i; +input [`TC_AW-1:0] i6_wb_adr_i; +input [`TC_BSW-1:0] i6_wb_sel_i; +input i6_wb_we_i; +input [`TC_DW-1:0] i6_wb_dat_i; +output [`TC_DW-1:0] i6_wb_dat_o; +output i6_wb_ack_o; +output i6_wb_err_o; + +// +// WB slave i/f connecting initiator 7 +// +input i7_wb_cyc_i; +input i7_wb_stb_i; +input [`TC_AW-1:0] i7_wb_adr_i; +input [`TC_BSW-1:0] i7_wb_sel_i; +input i7_wb_we_i; +input [`TC_DW-1:0] i7_wb_dat_i; +output [`TC_DW-1:0] i7_wb_dat_o; +output i7_wb_ack_o; +output i7_wb_err_o; + +// +// WB master i/f connecting target +// +output t0_wb_cyc_o; +output t0_wb_stb_o; +output [`TC_AW-1:0] t0_wb_adr_o; +output [`TC_BSW-1:0] t0_wb_sel_o; +output t0_wb_we_o; +output [`TC_DW-1:0] t0_wb_dat_o; +input [`TC_DW-1:0] t0_wb_dat_i; +input t0_wb_ack_i; +input t0_wb_err_i; + +// +// Internal wires & registers +// +wire [`TC_IIN_W-1:0] i0_in, i1_in, + i2_in, i3_in, + i4_in, i5_in, + i6_in, i7_in; +wire [`TC_TIN_W-1:0] i0_out, i1_out, + i2_out, i3_out, + i4_out, i5_out, + i6_out, i7_out; +wire [`TC_IIN_W-1:0] t0_out; +wire [`TC_TIN_W-1:0] t0_in; +wire [7:0] req_i; +wire [2:0] req_won; +reg req_cont; +reg [2:0] req_r; + +// +// Group WB initiator 0 i/f inputs and outputs +// +assign i0_in = {i0_wb_cyc_i, i0_wb_stb_i, i0_wb_adr_i, + i0_wb_sel_i, i0_wb_we_i, i0_wb_dat_i}; +assign {i0_wb_dat_o, i0_wb_ack_o, i0_wb_err_o} = i0_out; + +// +// Group WB initiator 1 i/f inputs and outputs +// +assign i1_in = {i1_wb_cyc_i, i1_wb_stb_i, i1_wb_adr_i, + i1_wb_sel_i, i1_wb_we_i, i1_wb_dat_i}; +assign {i1_wb_dat_o, i1_wb_ack_o, i1_wb_err_o} = i1_out; + +// +// Group WB initiator 2 i/f inputs and outputs +// +assign i2_in = {i2_wb_cyc_i, i2_wb_stb_i, i2_wb_adr_i, + i2_wb_sel_i, i2_wb_we_i, i2_wb_dat_i}; +assign {i2_wb_dat_o, i2_wb_ack_o, i2_wb_err_o} = i2_out; + +// +// Group WB initiator 3 i/f inputs and outputs +// +assign i3_in = {i3_wb_cyc_i, i3_wb_stb_i, i3_wb_adr_i, + i3_wb_sel_i, i3_wb_we_i, i3_wb_dat_i}; +assign {i3_wb_dat_o, i3_wb_ack_o, i3_wb_err_o} = i3_out; + +// +// Group WB initiator 4 i/f inputs and outputs +// +assign i4_in = {i4_wb_cyc_i, i4_wb_stb_i, i4_wb_adr_i, + i4_wb_sel_i, i4_wb_we_i, i4_wb_dat_i}; +assign {i4_wb_dat_o, i4_wb_ack_o, i4_wb_err_o} = i4_out; + +// +// Group WB initiator 5 i/f inputs and outputs +// +assign i5_in = {i5_wb_cyc_i, i5_wb_stb_i, i5_wb_adr_i, + i5_wb_sel_i, i5_wb_we_i, i5_wb_dat_i}; +assign {i5_wb_dat_o, i5_wb_ack_o, i5_wb_err_o} = i5_out; + +// +// Group WB initiator 6 i/f inputs and outputs +// +assign i6_in = {i6_wb_cyc_i, i6_wb_stb_i, i6_wb_adr_i, + i6_wb_sel_i, i6_wb_we_i, i6_wb_dat_i}; +assign {i6_wb_dat_o, i6_wb_ack_o, i6_wb_err_o} = i6_out; + +// +// Group WB initiator 7 i/f inputs and outputs +// +assign i7_in = {i7_wb_cyc_i, i7_wb_stb_i, i7_wb_adr_i, + i7_wb_sel_i, i7_wb_we_i, i7_wb_dat_i}; +assign {i7_wb_dat_o, i7_wb_ack_o, i7_wb_err_o} = i7_out; + +// +// Group WB target 0 i/f inputs and outputs +// +assign {t0_wb_cyc_o, t0_wb_stb_o, t0_wb_adr_o, + t0_wb_sel_o, t0_wb_we_o, t0_wb_dat_o} = t0_out; +assign t0_in = {t0_wb_dat_i, t0_wb_ack_i, t0_wb_err_i}; + +// +// Assign to WB initiator i/f outputs +// +// Either inputs from the target are assigned or zeros. +// +assign i0_out = (req_won == 3'd0) ? t0_in : {`TC_TIN_W{1'b0}}; +assign i1_out = (req_won == 3'd1) ? t0_in : {`TC_TIN_W{1'b0}}; +assign i2_out = (req_won == 3'd2) ? t0_in : {`TC_TIN_W{1'b0}}; +assign i3_out = (req_won == 3'd3) ? t0_in : {`TC_TIN_W{1'b0}}; +assign i4_out = (req_won == 3'd4) ? t0_in : {`TC_TIN_W{1'b0}}; +assign i5_out = (req_won == 3'd5) ? t0_in : {`TC_TIN_W{1'b0}}; +assign i6_out = (req_won == 3'd6) ? t0_in : {`TC_TIN_W{1'b0}}; +assign i7_out = (req_won == 3'd7) ? t0_in : {`TC_TIN_W{1'b0}}; + +// +// Assign to WB target i/f outputs +// +// Assign inputs from initiator to target outputs according to +// which initiator has won. If there is no request for the target, +// assign zeros. +// +assign t0_out = (req_won == 3'd0) ? i0_in : + (req_won == 3'd1) ? i1_in : + (req_won == 3'd2) ? i2_in : + (req_won == 3'd3) ? i3_in : + (req_won == 3'd4) ? i4_in : + (req_won == 3'd5) ? i5_in : + (req_won == 3'd6) ? i6_in : + (req_won == 3'd7) ? i7_in : {`TC_IIN_W{1'b0}}; + +// +// Determine if an initiator has address of the target. +// +assign req_i[0] = i0_wb_cyc_i & + ((i0_wb_adr_i[`TC_AW-1:`TC_AW-t0_addr_w] == t0_addr) | + multitarg & (i0_wb_adr_i[`TC_AW-1:`TC_AW-t17_addr_w] == t17_addr)); +assign req_i[1] = i1_wb_cyc_i & + ((i1_wb_adr_i[`TC_AW-1:`TC_AW-t0_addr_w] == t0_addr) | + multitarg & (i1_wb_adr_i[`TC_AW-1:`TC_AW-t17_addr_w] == t17_addr)); +assign req_i[2] = i2_wb_cyc_i & + ((i2_wb_adr_i[`TC_AW-1:`TC_AW-t0_addr_w] == t0_addr) | + multitarg & (i2_wb_adr_i[`TC_AW-1:`TC_AW-t17_addr_w] == t17_addr)); +assign req_i[3] = i3_wb_cyc_i & + ((i3_wb_adr_i[`TC_AW-1:`TC_AW-t0_addr_w] == t0_addr) | + multitarg & (i3_wb_adr_i[`TC_AW-1:`TC_AW-t17_addr_w] == t17_addr)); +assign req_i[4] = i4_wb_cyc_i & + ((i4_wb_adr_i[`TC_AW-1:`TC_AW-t0_addr_w] == t0_addr) | + multitarg & (i4_wb_adr_i[`TC_AW-1:`TC_AW-t17_addr_w] == t17_addr)); +assign req_i[5] = i5_wb_cyc_i & + ((i5_wb_adr_i[`TC_AW-1:`TC_AW-t0_addr_w] == t0_addr) | + multitarg & (i5_wb_adr_i[`TC_AW-1:`TC_AW-t17_addr_w] == t17_addr)); +assign req_i[6] = i6_wb_cyc_i & + ((i6_wb_adr_i[`TC_AW-1:`TC_AW-t0_addr_w] == t0_addr) | + multitarg & (i6_wb_adr_i[`TC_AW-1:`TC_AW-t17_addr_w] == t17_addr)); +assign req_i[7] = i7_wb_cyc_i & + ((i7_wb_adr_i[`TC_AW-1:`TC_AW-t0_addr_w] == t0_addr) | + multitarg & (i7_wb_adr_i[`TC_AW-1:`TC_AW-t17_addr_w] == t17_addr)); + +// +// Determine who gets current access to the target. +// +// If current initiator still asserts request, do nothing +// (keep current initiator). +// Otherwise check each initiator's request, starting from initiator 0 +// (highest priority). +// If there is no requests from initiators, park initiator 0. +// +assign req_won = req_cont ? req_r : + req_i[0] ? 3'd0 : + req_i[1] ? 3'd1 : + req_i[2] ? 3'd2 : + req_i[3] ? 3'd3 : + req_i[4] ? 3'd4 : + req_i[5] ? 3'd5 : + req_i[6] ? 3'd6 : + req_i[7] ? 3'd7 : 3'd0; + +// +// Check if current initiator still wants access to the target and if +// it does, assert req_cont. +// +always @(req_r or req_i) + case (req_r) // synopsys parallel_case + 3'd0: req_cont = req_i[0]; + 3'd1: req_cont = req_i[1]; + 3'd2: req_cont = req_i[2]; + 3'd3: req_cont = req_i[3]; + 3'd4: req_cont = req_i[4]; + 3'd5: req_cont = req_i[5]; + 3'd6: req_cont = req_i[6]; + 3'd7: req_cont = req_i[7]; + endcase + +// +// Register who has current access to the target. +// +always @(posedge wb_clk_i or posedge wb_rst_i) + if (wb_rst_i) + req_r <= #1 3'd0; + else + req_r <= #1 req_won; + +endmodule + +// +// Single initiator to multiple targets +// +module tc_si_to_mt ( + + i0_wb_cyc_i, + i0_wb_stb_i, + i0_wb_adr_i, + i0_wb_sel_i, + i0_wb_we_i, + i0_wb_dat_i, + i0_wb_dat_o, + i0_wb_ack_o, + i0_wb_err_o, + + t0_wb_cyc_o, + t0_wb_stb_o, + t0_wb_adr_o, + t0_wb_sel_o, + t0_wb_we_o, + t0_wb_dat_o, + t0_wb_dat_i, + t0_wb_ack_i, + t0_wb_err_i, + + t1_wb_cyc_o, + t1_wb_stb_o, + t1_wb_adr_o, + t1_wb_sel_o, + t1_wb_we_o, + t1_wb_dat_o, + t1_wb_dat_i, + t1_wb_ack_i, + t1_wb_err_i, + + t2_wb_cyc_o, + t2_wb_stb_o, + t2_wb_adr_o, + t2_wb_sel_o, + t2_wb_we_o, + t2_wb_dat_o, + t2_wb_dat_i, + t2_wb_ack_i, + t2_wb_err_i, + + t3_wb_cyc_o, + t3_wb_stb_o, + t3_wb_adr_o, + t3_wb_sel_o, + t3_wb_we_o, + t3_wb_dat_o, + t3_wb_dat_i, + t3_wb_ack_i, + t3_wb_err_i, + + t4_wb_cyc_o, + t4_wb_stb_o, + t4_wb_adr_o, + t4_wb_sel_o, + t4_wb_we_o, + t4_wb_dat_o, + t4_wb_dat_i, + t4_wb_ack_i, + t4_wb_err_i, + + t5_wb_cyc_o, + t5_wb_stb_o, + t5_wb_adr_o, + t5_wb_sel_o, + t5_wb_we_o, + t5_wb_dat_o, + t5_wb_dat_i, + t5_wb_ack_i, + t5_wb_err_i, + + t6_wb_cyc_o, + t6_wb_stb_o, + t6_wb_adr_o, + t6_wb_sel_o, + t6_wb_we_o, + t6_wb_dat_o, + t6_wb_dat_i, + t6_wb_ack_i, + t6_wb_err_i, + + t7_wb_cyc_o, + t7_wb_stb_o, + t7_wb_adr_o, + t7_wb_sel_o, + t7_wb_we_o, + t7_wb_dat_o, + t7_wb_dat_i, + t7_wb_ack_i, + t7_wb_err_i + +); + +// +// Parameters +// +parameter t0_addr_w = 3; +parameter t0_addr = 3'd0; +parameter t17_addr_w = 3; +parameter t1_addr = 3'd1; +parameter t2_addr = 3'd2; +parameter t3_addr = 3'd3; +parameter t4_addr = 3'd4; +parameter t5_addr = 3'd5; +parameter t6_addr = 3'd6; +parameter t7_addr = 3'd7; + +// +// I/O Ports +// + +// +// WB slave i/f connecting initiator 0 +// +input i0_wb_cyc_i; +input i0_wb_stb_i; +input [`TC_AW-1:0] i0_wb_adr_i; +input [`TC_BSW-1:0] i0_wb_sel_i; +input i0_wb_we_i; +input [`TC_DW-1:0] i0_wb_dat_i; +output [`TC_DW-1:0] i0_wb_dat_o; +output i0_wb_ack_o; +output i0_wb_err_o; + +// +// WB master i/f connecting target 0 +// +output t0_wb_cyc_o; +output t0_wb_stb_o; +output [`TC_AW-1:0] t0_wb_adr_o; +output [`TC_BSW-1:0] t0_wb_sel_o; +output t0_wb_we_o; +output [`TC_DW-1:0] t0_wb_dat_o; +input [`TC_DW-1:0] t0_wb_dat_i; +input t0_wb_ack_i; +input t0_wb_err_i; + +// +// WB master i/f connecting target 1 +// +output t1_wb_cyc_o; +output t1_wb_stb_o; +output [`TC_AW-1:0] t1_wb_adr_o; +output [`TC_BSW-1:0] t1_wb_sel_o; +output t1_wb_we_o; +output [`TC_DW-1:0] t1_wb_dat_o; +input [`TC_DW-1:0] t1_wb_dat_i; +input t1_wb_ack_i; +input t1_wb_err_i; + +// +// WB master i/f connecting target 2 +// +output t2_wb_cyc_o; +output t2_wb_stb_o; +output [`TC_AW-1:0] t2_wb_adr_o; +output [`TC_BSW-1:0] t2_wb_sel_o; +output t2_wb_we_o; +output [`TC_DW-1:0] t2_wb_dat_o; +input [`TC_DW-1:0] t2_wb_dat_i; +input t2_wb_ack_i; +input t2_wb_err_i; + +// +// WB master i/f connecting target 3 +// +output t3_wb_cyc_o; +output t3_wb_stb_o; +output [`TC_AW-1:0] t3_wb_adr_o; +output [`TC_BSW-1:0] t3_wb_sel_o; +output t3_wb_we_o; +output [`TC_DW-1:0] t3_wb_dat_o; +input [`TC_DW-1:0] t3_wb_dat_i; +input t3_wb_ack_i; +input t3_wb_err_i; + +// +// WB master i/f connecting target 4 +// +output t4_wb_cyc_o; +output t4_wb_stb_o; +output [`TC_AW-1:0] t4_wb_adr_o; +output [`TC_BSW-1:0] t4_wb_sel_o; +output t4_wb_we_o; +output [`TC_DW-1:0] t4_wb_dat_o; +input [`TC_DW-1:0] t4_wb_dat_i; +input t4_wb_ack_i; +input t4_wb_err_i; + +// +// WB master i/f connecting target 5 +// +output t5_wb_cyc_o; +output t5_wb_stb_o; +output [`TC_AW-1:0] t5_wb_adr_o; +output [`TC_BSW-1:0] t5_wb_sel_o; +output t5_wb_we_o; +output [`TC_DW-1:0] t5_wb_dat_o; +input [`TC_DW-1:0] t5_wb_dat_i; +input t5_wb_ack_i; +input t5_wb_err_i; + +// +// WB master i/f connecting target 6 +// +output t6_wb_cyc_o; +output t6_wb_stb_o; +output [`TC_AW-1:0] t6_wb_adr_o; +output [`TC_BSW-1:0] t6_wb_sel_o; +output t6_wb_we_o; +output [`TC_DW-1:0] t6_wb_dat_o; +input [`TC_DW-1:0] t6_wb_dat_i; +input t6_wb_ack_i; +input t6_wb_err_i; + +// +// WB master i/f connecting target 7 +// +output t7_wb_cyc_o; +output t7_wb_stb_o; +output [`TC_AW-1:0] t7_wb_adr_o; +output [`TC_BSW-1:0] t7_wb_sel_o; +output t7_wb_we_o; +output [`TC_DW-1:0] t7_wb_dat_o; +input [`TC_DW-1:0] t7_wb_dat_i; +input t7_wb_ack_i; +input t7_wb_err_i; + +// +// Internal wires & registers +// +wire [`TC_IIN_W-1:0] i0_in; +wire [`TC_TIN_W-1:0] i0_out; +wire [`TC_IIN_W-1:0] t0_out, t1_out, + t2_out, t3_out, + t4_out, t5_out, + t6_out, t7_out; +wire [`TC_TIN_W-1:0] t0_in, t1_in, + t2_in, t3_in, + t4_in, t5_in, + t6_in, t7_in; +wire [7:0] req_t; + +// +// Group WB initiator 0 i/f inputs and outputs +// +assign i0_in = {i0_wb_cyc_i, i0_wb_stb_i, i0_wb_adr_i, + i0_wb_sel_i, i0_wb_we_i, i0_wb_dat_i}; +assign {i0_wb_dat_o, i0_wb_ack_o, i0_wb_err_o} = i0_out; + +// +// Group WB target 0 i/f inputs and outputs +// +assign {t0_wb_cyc_o, t0_wb_stb_o, t0_wb_adr_o, + t0_wb_sel_o, t0_wb_we_o, t0_wb_dat_o} = t0_out; +assign t0_in = {t0_wb_dat_i, t0_wb_ack_i, t0_wb_err_i}; + +// +// Group WB target 1 i/f inputs and outputs +// +assign {t1_wb_cyc_o, t1_wb_stb_o, t1_wb_adr_o, + t1_wb_sel_o, t1_wb_we_o, t1_wb_dat_o} = t1_out; +assign t1_in = {t1_wb_dat_i, t1_wb_ack_i, t1_wb_err_i}; + +// +// Group WB target 2 i/f inputs and outputs +// +assign {t2_wb_cyc_o, t2_wb_stb_o, t2_wb_adr_o, + t2_wb_sel_o, t2_wb_we_o, t2_wb_dat_o} = t2_out; +assign t2_in = {t2_wb_dat_i, t2_wb_ack_i, t2_wb_err_i}; + +// +// Group WB target 3 i/f inputs and outputs +// +assign {t3_wb_cyc_o, t3_wb_stb_o, t3_wb_adr_o, + t3_wb_sel_o, t3_wb_we_o, t3_wb_dat_o} = t3_out; +assign t3_in = {t3_wb_dat_i, t3_wb_ack_i, t3_wb_err_i}; + +// +// Group WB target 4 i/f inputs and outputs +// +assign {t4_wb_cyc_o, t4_wb_stb_o, t4_wb_adr_o, + t4_wb_sel_o, t4_wb_we_o, t4_wb_dat_o} = t4_out; +assign t4_in = {t4_wb_dat_i, t4_wb_ack_i, t4_wb_err_i}; + +// +// Group WB target 5 i/f inputs and outputs +// +assign {t5_wb_cyc_o, t5_wb_stb_o, t5_wb_adr_o, + t5_wb_sel_o, t5_wb_we_o, t5_wb_dat_o} = t5_out; +assign t5_in = {t5_wb_dat_i, t5_wb_ack_i, t5_wb_err_i}; + +// +// Group WB target 6 i/f inputs and outputs +// +assign {t6_wb_cyc_o, t6_wb_stb_o, t6_wb_adr_o, + t6_wb_sel_o, t6_wb_we_o, t6_wb_dat_o} = t6_out; +assign t6_in = {t6_wb_dat_i, t6_wb_ack_i, t6_wb_err_i}; + +// +// Group WB target 7 i/f inputs and outputs +// +assign {t7_wb_cyc_o, t7_wb_stb_o, t7_wb_adr_o, + t7_wb_sel_o, t7_wb_we_o, t7_wb_dat_o} = t7_out; +assign t7_in = {t7_wb_dat_i, t7_wb_ack_i, t7_wb_err_i}; + +// +// Assign to WB target i/f outputs +// +// Either inputs from the initiator are assigned or zeros. +// +assign t0_out = req_t[0] ? i0_in : {`TC_IIN_W{1'b0}}; +assign t1_out = req_t[1] ? i0_in : {`TC_IIN_W{1'b0}}; +assign t2_out = req_t[2] ? i0_in : {`TC_IIN_W{1'b0}}; +assign t3_out = req_t[3] ? i0_in : {`TC_IIN_W{1'b0}}; +assign t4_out = req_t[4] ? i0_in : {`TC_IIN_W{1'b0}}; +assign t5_out = req_t[5] ? i0_in : {`TC_IIN_W{1'b0}}; +assign t6_out = req_t[6] ? i0_in : {`TC_IIN_W{1'b0}}; +assign t7_out = req_t[7] ? i0_in : {`TC_IIN_W{1'b0}}; + +// +// Assign to WB initiator i/f outputs +// +// Assign inputs from target to initiator outputs according to +// which target is accessed. If there is no request for a target, +// assign zeros. +// +assign i0_out = req_t[0] ? t0_in : + req_t[1] ? t1_in : + req_t[2] ? t2_in : + req_t[3] ? t3_in : + req_t[4] ? t4_in : + req_t[5] ? t5_in : + req_t[6] ? t6_in : + req_t[7] ? t7_in : {`TC_TIN_W{1'b0}}; + +// +// Determine which target is being accessed. +// +assign req_t[0] = i0_wb_cyc_i & (i0_wb_adr_i[`TC_AW-1:`TC_AW-t0_addr_w] == t0_addr); +assign req_t[1] = i0_wb_cyc_i & (i0_wb_adr_i[`TC_AW-1:`TC_AW-t17_addr_w] == t1_addr); +assign req_t[2] = i0_wb_cyc_i & (i0_wb_adr_i[`TC_AW-1:`TC_AW-t17_addr_w] == t2_addr); +assign req_t[3] = i0_wb_cyc_i & (i0_wb_adr_i[`TC_AW-1:`TC_AW-t17_addr_w] == t3_addr); +assign req_t[4] = i0_wb_cyc_i & (i0_wb_adr_i[`TC_AW-1:`TC_AW-t17_addr_w] == t4_addr); +assign req_t[5] = i0_wb_cyc_i & (i0_wb_adr_i[`TC_AW-1:`TC_AW-t17_addr_w] == t5_addr); +assign req_t[6] = i0_wb_cyc_i & (i0_wb_adr_i[`TC_AW-1:`TC_AW-t17_addr_w] == t6_addr); +assign req_t[7] = i0_wb_cyc_i & (i0_wb_adr_i[`TC_AW-1:`TC_AW-t17_addr_w] == t7_addr); + +endmodule

minsoc_tc_top.v Property changes : Added: svn:executable ## -0,0 +1 ## +* \ No newline at end of property Index: minsoc_onchip_ram.v =================================================================== --- minsoc_onchip_ram.v (nonexistent) +++ minsoc_onchip_ram.v (revision 42) @@ -0,0 +1,458 @@ +////////////////////////////////////////////////////////////////////// +//// //// +//// Generic Single-Port Synchronous RAM //// +//// //// +//// This file is part of memory library available from //// +//// http://www.opencores.org/cvsweb.shtml/minsoc/ //// +//// //// +//// Description //// +//// This block is a wrapper with common single-port //// +//// synchronous memory interface for different //// +//// types of ASIC and FPGA RAMs. Beside universal memory //// +//// interface it also provides behavioral model of generic //// +//// single-port synchronous RAM. //// +//// It should be used in all OPENCORES designs that want to be //// +//// portable accross different target technologies and //// +//// independent of target memory. //// +//// //// +//// Supported ASIC RAMs are: //// +//// - Artisan Single-Port Sync RAM //// +//// - Avant! Two-Port Sync RAM (*) //// +//// - Virage Single-Port Sync RAM //// +//// - Virtual Silicon Single-Port Sync RAM //// +//// //// +//// Supported FPGA RAMs are: //// +//// - Xilinx Virtex RAMB16 //// +//// - Xilinx Virtex RAMB4 //// +//// - Altera LPM //// +//// //// +//// To Do: //// +//// - fix avant! two-port ram //// +//// - add additional RAMs //// +//// //// +//// Author(s): //// +//// - Raul Fajardo, rfajardo@gmail.com //// +//// - Damjan Lampret, lampret@opencores.org //// +//// //// +////////////////////////////////////////////////////////////////////// +//// //// +//// Copyright (C) 2000 Authors and OPENCORES.ORG //// +//// //// +//// This source file may be used and distributed without //// +//// restriction provided that this copyright statement is not //// +//// removed from the file and that any derivative work contains //// +//// the original copyright notice and the associated disclaimer. //// +//// //// +//// This source file is free software; you can redistribute it //// +//// and/or modify it under the terms of the GNU Lesser General //// +//// Public License as published by the Free Software Foundation; //// +//// either version 2.1 of the License, or (at your option) any //// +//// later version. //// +//// //// +//// This source is distributed in the hope that it will be //// +//// useful, but WITHOUT ANY WARRANTY; without even the implied //// +//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR //// +//// PURPOSE. See the GNU Lesser General Public License for more //// +//// details. //// +//// //// +//// You should have received a copy of the GNU Lesser General //// +//// Public License along with this source; if not, download it //// +//// from http://www.gnu.org/licenses/lgpl.html //// +//// //// +////////////////////////////////////////////////////////////////////// +// +// Revision History +// +// +// Revision 2.1 2009/08/23 16:41:00 fajardo +// Sensitivity of addr_reg and memory write changed back to posedge clk for GENERIC_MEMORY +// This actually models appropriately the behavior of the FPGA internal RAMs +// +// Revision 2.0 2009/09/10 11:30:00 fajardo +// Added tri-state buffering for altera output +// Sensitivity of addr_reg and memory write changed to negedge clk for GENERIC_MEMORY +// +// Revision 1.9 2009/08/18 15:15:00 fajardo +// Added tri-state buffering for xilinx and generic memory output +// +// $Log: not supported by cvs2svn $ +// Revision 1.8 2004/06/08 18:15:32 lampret +// Changed behavior of the simulation generic models +// +// Revision 1.7 2004/04/05 08:29:57 lampret +// Merged branch_qmem into main tree. +// +// Revision 1.3.4.1 2003/12/09 11:46:48 simons +// Mbist nameing changed, Artisan ram instance signal names fixed, some synthesis waning fixed. +// +// Revision 1.3 2003/04/07 01:19:07 lampret +// Added Altera LPM RAMs. Changed generic RAM output when OE inactive. +// +// Revision 1.2 2002/10/17 20:04:40 lampret +// Added BIST scan. Special VS RAMs need to be used to implement BIST. +// +// Revision 1.1 2002/01/03 08:16:15 lampret +// New prefixes for RTL files, prefixed module names. Updated cache controllers and MMUs. +// +// Revision 1.8 2001/11/02 18:57:14 lampret +// Modified virtual silicon instantiations. +// +// Revision 1.7 2001/10/21 17:57:16 lampret +// Removed params from generic_XX.v. Added translate_off/on in sprs.v and id.v. Removed spr_addr from dc.v and ic.v. Fixed CR+LF. +// +// Revision 1.6 2001/10/14 13:12:09 lampret +// MP3 version. +// +// Revision 1.1.1.1 2001/10/06 10:18:36 igorm +// no message +// +// Revision 1.1 2001/08/09 13:39:33 lampret +// Major clean-up. +// +// Revision 1.2 2001/07/30 05:38:02 lampret +// Adding empty directories required by HDL coding guidelines +// +// + +// synopsys translate_off +`include "timescale.v" +// synopsys translate_on +`include "minsoc_defines.v" + +module minsoc_onchip_ram( +`ifdef BIST + // RAM BIST + mbist_si_i, mbist_so_o, mbist_ctrl_i, +`endif + // Generic synchronous single-port RAM interface + clk, rst, ce, we, oe, addr, di, doq +); + +// +// Default address and data buses width +// +parameter aw = 11; +parameter dw = 8; + +`ifdef BIST +// +// RAM BIST +// +input mbist_si_i; +input [`MBIST_CTRL_WIDTH - 1:0] mbist_ctrl_i; +output mbist_so_o; +`endif + +// +// Generic synchronous single-port RAM interface +// +input clk; // Clock +input rst; // Reset +input ce; // Chip enable input +input we; // Write enable input +input oe; // Output enable input +input [aw-1:0] addr; // address bus inputs +input [dw-1:0] di; // input data bus +output [dw-1:0] doq; // output data bus + +// +// Decide memory implementation for Xilinx FPGAs +// +`ifdef SPARTAN2 + `define MINSOC_XILINX_RAMB4 +`elsif VIRTEX + `define MINSOC_XILINX_RAMB4 +`endif // !SPARTAN2/VIRTEX + +`ifdef SPARTAN3 + `define MINSOC_XILINX_RAMB16 +`elsif SPARTAN3E + `define MINSOC_XILINX_RAMB16 +`elsif SPARTAN3A + `define MINSOC_XILINX_RAMB16 +`elsif VIRTEX2 + `define MINSOC_XILINX_RAMB16 +`elsif VIRTEX4 + `define MINSOC_XILINX_RAMB16 +`elsif VIRTEX5 + `define MINSOC_XILINX_RAMB16 +`endif // !SPARTAN3/SPARTAN3E/SPARTAN3A/VIRTEX2/VIRTEX4/VIRTEX5 + + +// +// Internal wires and registers +// + +`ifdef ARTISAN_SSP +`else +`ifdef VIRTUALSILICON_SSP +`else +`ifdef BIST +assign mbist_so_o = mbist_si_i; +`endif +`endif +`endif + + +`ifdef GENERIC_MEMORY +// +// Generic single-port synchronous RAM model +// + +// +// Generic RAM's registers and wires +// +reg [dw-1:0] mem [(1<

minsoc_onchip_ram.v Property changes : Added: svn:executable ## -0,0 +1 ## +* \ No newline at end of property Index: minsoc_onchip_ram_top.v =================================================================== --- minsoc_onchip_ram_top.v (nonexistent) +++ minsoc_onchip_ram_top.v (revision 42) @@ -0,0 +1,259 @@ +////////////////////////////////////////////////////////////////////// +//// //// +//// Generic Wishbone controller for //// +//// Single-Port Synchronous RAM //// +//// //// +//// This file is part of memory library available from //// +//// http://www.opencores.org/cvsweb.shtml/minsoc/ //// +//// //// +//// Description //// +//// This Wishbone controller connects to the wrapper of //// +//// the single-port synchronous memory interface. //// +//// Besides universal memory due to onchip_ram it provides a //// +//// generic way to set the depth of the memory. //// +//// //// +//// To Do: //// +//// //// +//// Author(s): //// +//// - Raul Fajardo, rfajardo@gmail.com //// +//// //// +////////////////////////////////////////////////////////////////////// +//// //// +//// Copyright (C) 2000 Authors and OPENCORES.ORG //// +//// //// +//// This source file may be used and distributed without //// +//// restriction provided that this copyright statement is not //// +//// removed from the file and that any derivative work contains //// +//// the original copyright notice and the associated disclaimer. //// +//// //// +//// This source file is free software; you can redistribute it //// +//// and/or modify it under the terms of the GNU Lesser General //// +//// Public License as published by the Free Software Foundation; //// +//// either version 2.1 of the License, or (at your option) any //// +//// later version. //// +//// //// +//// This source is distributed in the hope that it will be //// +//// useful, but WITHOUT ANY WARRANTY; without even the implied //// +//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR //// +//// PURPOSE. See the GNU Lesser General Public License for more //// +//// details. //// +//// //// +//// You should have received a copy of the GNU Lesser General //// +//// Public License along with this source; if not, download it //// +//// from http://www.gnu.org/licenses/lgpl.html //// +//// //// +////////////////////////////////////////////////////////////////////// +// +// Revision History +// +// Revision 1.1 2009/10/02 16:49 fajardo +// Not using the oe signal (output enable) from +// memories, instead multiplexing the outputs +// between the different instantiated blocks +// +// +// Revision 1.0 2009/08/18 15:15:00 fajardo +// Created interface and tested +// + + +module minsoc_onchip_ram_top ( + wb_clk_i, wb_rst_i, + + wb_dat_i, wb_dat_o, wb_adr_i, wb_sel_i, wb_we_i, wb_cyc_i, + wb_stb_i, wb_ack_o, wb_err_o +); + +// +// Parameters +// +parameter adr_width = 13; //Memory address width, is composed by blocks of aw_int, is not allowed to be less than 12 +localparam aw_int = 11; //11 = 2048 +localparam blocks = (1<<(adr_width-aw_int)); //generated memory contains "blocks" memory blocks of 2048x32 2048 depth x32 bit data + +// +// I/O Ports +// +input wb_clk_i; +input wb_rst_i; + +// +// WB slave i/f +// +input [31:0] wb_dat_i; +output [31:0] wb_dat_o; +input [31:0] wb_adr_i; +input [3:0] wb_sel_i; +input wb_we_i; +input wb_cyc_i; +input wb_stb_i; +output wb_ack_o; +output wb_err_o; + +// +// Internal regs and wires +// +wire we; +wire [3:0] be_i; +wire [31:0] wb_dat_o; +reg ack_we; +reg ack_re; +// +// Aliases and simple assignments +// +assign wb_ack_o = ack_re | ack_we; +assign wb_err_o = wb_cyc_i & wb_stb_i & (|wb_adr_i[23:adr_width+2]); // If Access to > (8-bit leading prefix ignored) +assign we = wb_cyc_i & wb_stb_i & wb_we_i & (|wb_sel_i[3:0]); +assign be_i = (wb_cyc_i & wb_stb_i) * wb_sel_i; + +// +// Write acknowledge +// +always @ (negedge wb_clk_i or posedge wb_rst_i) +begin +if (wb_rst_i) + ack_we <= 1'b0; + else + if (wb_cyc_i & wb_stb_i & wb_we_i & ~ack_we) + ack_we <= #1 1'b1; + else + ack_we <= #1 1'b0; +end + +// +// read acknowledge +// +always @ (posedge wb_clk_i or posedge wb_rst_i) +begin + if (wb_rst_i) + ack_re <= 1'b0; + else + if (wb_cyc_i & wb_stb_i & ~wb_err_o & ~wb_we_i & ~ack_re) + ack_re <= #1 1'b1; + else + ack_re <= #1 1'b0; +end + +//Generic (multiple inputs x 1 output) MUX +localparam mux_in_nr = blocks; +localparam slices = adr_width-aw_int; +localparam mux_out_nr = blocks-1; + +wire [31:0] int_dat_o[0:mux_in_nr-1]; +wire [31:0] mux_out[0:mux_out_nr-1]; + +generate +genvar j, k; + for (j=0; j>(j+1)); k=k+1) begin : MUX + if (j==0) begin + mux2 # + ( + .dw(32) + ) + mux_int( + .sel( wb_adr_i[aw_int+2+j] ), + .in1( int_dat_o[k*2] ), + .in2( int_dat_o[k*2+1] ), + .out( mux_out[k] ) + ); + end + else begin + mux2 # + ( + .dw(32) + ) + mux_int( + .sel( wb_adr_i[aw_int+2+j] ), + .in1( mux_out[(mux_in_nr-(mux_in_nr>>(j-1)))+k*2] ), + .in2( mux_out[(mux_in_nr-(mux_in_nr>>(j-1)))+k*2+1] ), + .out( mux_out[(mux_in_nr-(mux_in_nr>>j))+k] ) + ); + end + end + end +endgenerate + +//last output = total output +assign wb_dat_o = mux_out[mux_out_nr-1]; + +//(mux_in_nr-(mux_in_nr>>j)): +//-Given sum of 2^i | i = x -> y series can be resumed to 2^(y+1)-2^x +//so, with this expression I'm evaluating how many times the internal loop has been run + +wire [blocks-1:0] bank; + +generate +genvar i; + for (i=0; i < blocks; i=i+1) begin : MEM + + assign bank[i] = wb_adr_i[adr_width+1:aw_int+2] == i; + + //BANK0 + minsoc_onchip_ram block_ram_0 ( + .clk(wb_clk_i), + .rst(wb_rst_i), + .addr(wb_adr_i[aw_int+1:2]), + .di(wb_dat_i[7:0]), + .doq(int_dat_o[i][7:0]), + .we(we & bank[i]), + .oe(1'b1), + .ce(be_i[0]) + ); + + + minsoc_onchip_ram block_ram_1 ( + .clk(wb_clk_i), + .rst(wb_rst_i), + .addr(wb_adr_i[aw_int+1:2]), + .di(wb_dat_i[15:8]), + .doq(int_dat_o[i][15:8]), + .we(we & bank[i]), + .oe(1'b1), + .ce(be_i[1]) + ); + + minsoc_onchip_ram block_ram_2 ( + .clk(wb_clk_i), + .rst(wb_rst_i), + .addr(wb_adr_i[aw_int+1:2]), + .di(wb_dat_i[23:16]), + .doq(int_dat_o[i][23:16]), + .we(we & bank[i]), + .oe(1'b1), + .ce(be_i[2]) + ); + + minsoc_onchip_ram block_ram_3 ( + .clk(wb_clk_i), + .rst(wb_rst_i), + .addr(wb_adr_i[aw_int+1:2]), + .di(wb_dat_i[31:24]), + .doq(int_dat_o[i][31:24]), + .we(we & bank[i]), + .oe(1'b1), + .ce(be_i[3]) + ); + + end +endgenerate + +endmodule + +module mux2(sel,in1,in2,out); + +parameter dw = 32; + +input sel; +input [dw-1:0] in1, in2; +output reg [dw-1:0] out; + +always @ (sel or in1 or in2) +begin + case (sel) + 1'b0: out = in1; + 1'b1: out = in2; + endcase +end + +endmodule

minsoc_onchip_ram_top.v Property changes : Added: svn:executable ## -0,0 +1 ## +* \ No newline at end of property Index: minsoc_clock_manager.v =================================================================== --- minsoc_clock_manager.v (nonexistent) +++ minsoc_clock_manager.v (revision 42) @@ -0,0 +1,255 @@ + +`include "minsoc_defines.v" + +module minsoc_clock_manager( + clk_i, + clk_o +); + +// +// Parameters +// +parameter divisor = 5; + +input clk_i; +output clk_o; + +`ifdef NO_CLOCK_DIVISION +assign clk_o = clk_i; + +`elsif GENERIC_CLOCK_DIVISION +reg [31:0] clock_divisor; +reg clk_int; +always @ (posedge clk_i) +begin + clock_divisor <= clock_divisor + 1'b1; + if ( clock_divisor >= divisor/2 - 1 ) begin + clk_int <= ~clk_int; + clock_divisor <= 32'h0000_0000; + end +end +assign clk_o = clk_int; +`elsif FPGA_CLOCK_DIVISION + +`ifdef ALTERA_FPGA +reg [31:0] clock_divisor; +reg clk_int; +always @ (posedge clk_i) +begin + clock_divisor <= clock_divisor + 1'b1; + if ( clock_divisor >= divisor/2 - 1 ) begin + clk_int <= ~clk_int; + clock_divisor <= 32'h0000_0000; + end +end +assign clk_o = clk_int; + +`elsif XILINX_FPGA + +`ifdef SPARTAN2 + `define MINSOC_DLL +`elsif VIRTEX + `define MINSOC_DLL +`endif // !SPARTAN2/VIRTEX + +`ifdef SPARTAN3 + `define MINSOC_DCM +`elsif VIRTEX2 + `define MINSOC_DCM +`endif // !SPARTAN3/VIRTEX2 + +`ifdef SPARTAN3E + `define MINSOC_DCM_SP +`elsif SPARTAN3A + `define MINSOC_DCM_SP +`endif // !SPARTAN3E/SPARTAN3A + +`ifdef VIRTEX4 + `define MINSOC_DCM_ADV + `define MINSOC_DCM_COMPONENT "VIRTEX4" +`elsif VIRTEX5 + `define MINSOC_DCM_ADV + `define MINSOC_DCM_COMPONENT "VIRTEX5" +`endif // !VIRTEX4/VIRTEX5 + +wire CLKIN_IN; +wire CLKDV_OUT; + +assign CLKIN_IN = clk_i; +assign clk_o = CLKDV_OUT; + +wire CLKIN_IBUFG; +wire CLK0_BUF; +wire CLKFB_IN; +wire CLKDV_BUF; + +IBUFG CLKIN_IBUFG_INST ( + .I(CLKIN_IN), + .O(CLKIN_IBUFG) +); + +BUFG CLK0_BUFG_INST ( + .I(CLK0_BUF), + .O(CLKFB_IN) +); + +BUFG CLKDV_BUFG_INST ( + .I(CLKDV_BUF), + .O(CLKDV_OUT) +); + +`ifdef MINSOC_DLL + +CLKDLL #( + .CLKDV_DIVIDE(divisor), // Divide by: 1.5,2.0,2.5,3.0,4.0,5.0,8.0 or 16.0 + .DUTY_CYCLE_CORRECTION("TRUE"), // Duty cycle correction, TRUE or FALSE + .FACTORY_JF(16'hC080), // FACTORY JF Values + .STARTUP_WAIT("FALSE") // Delay config DONE until DLL LOCK, TRUE/FALSE +) CLKDLL_inst ( + .CLK0(CLK0_BUF), // 0 degree DLL CLK output + .CLK180(), // 180 degree DLL CLK output + .CLK270(), // 270 degree DLL CLK output + .CLK2X(), // 2X DLL CLK output + .CLK90(), // 90 degree DLL CLK output + .CLKDV(CLKDV_BUF), // Divided DLL CLK out (CLKDV_DIVIDE) + .LOCKED(), // DLL LOCK status output + .CLKFB(CLKFB_IN), // DLL clock feedback + .CLKIN(CLKIN_IBUFG), // Clock input (from IBUFG, BUFG or DLL) + .RST(1'b0) // DLL asynchronous reset input +); + +`elsif MINSOC_DCM + +DCM #( + .SIM_MODE("SAFE"), // Simulation: "SAFE" vs. "FAST", see "Synthesis and Simulation Design Guide" for details + .CLKDV_DIVIDE(divisor), // Divide by: 1.5,2.0,2.5,3.0,3.5,4.0,4.5,5.0,5.5,6.0,6.5 + // 7.0,7.5,8.0,9.0,10.0,11.0,12.0,13.0,14.0,15.0 or 16.0 + .CLKFX_DIVIDE(1), // Can be any integer from 1 to 32 + .CLKFX_MULTIPLY(4), // Can be any integer from 2 to 32 + .CLKIN_DIVIDE_BY_2("FALSE"), // TRUE/FALSE to enable CLKIN divide by two feature + .CLKIN_PERIOD(0.0), // Specify period of input clock + .CLKOUT_PHASE_SHIFT("NONE"), // Specify phase shift of NONE, FIXED or VARIABLE + .CLK_FEEDBACK("1X"), // Specify clock feedback of NONE, 1X or 2X + .DESKEW_ADJUST("SYSTEM_SYNCHRONOUS"), // SOURCE_SYNCHRONOUS, SYSTEM_SYNCHRONOUS or + // an integer from 0 to 15 + .DFS_FREQUENCY_MODE("LOW"), // HIGH or LOW frequency mode for frequency synthesis + .DLL_FREQUENCY_MODE("LOW"), // HIGH or LOW frequency mode for DLL + .DUTY_CYCLE_CORRECTION("TRUE"), // Duty cycle correction, TRUE or FALSE + .FACTORY_JF(16'hC080), // FACTORY JF values + .PHASE_SHIFT(0), // Amount of fixed phase shift from -255 to 255 + .STARTUP_WAIT("FALSE") // Delay configuration DONE until DCM LOCK, TRUE/FALSE +) DCM_inst ( + .CLK0(CLK0_BUF), // 0 degree DCM CLK output + .CLK180(), // 180 degree DCM CLK output + .CLK270(), // 270 degree DCM CLK output + .CLK2X(), // 2X DCM CLK output + .CLK2X180(), // 2X, 180 degree DCM CLK out + .CLK90(), // 90 degree DCM CLK output + .CLKDV(CLKDV_BUF), // Divided DCM CLK out (CLKDV_DIVIDE) + .CLKFX(), // DCM CLK synthesis out (M/D) + .CLKFX180(), // 180 degree CLK synthesis out + .LOCKED(), // DCM LOCK status output + .PSDONE(), // Dynamic phase adjust done output + .STATUS(), // 8-bit DCM status bits output + .CLKFB(CLKFB_IN), // DCM clock feedback + .CLKIN(CLKIN_IBUFG), // Clock input (from IBUFG, BUFG or DCM) + .PSCLK(1'b0), // Dynamic phase adjust clock input + .PSEN(1'b0), // Dynamic phase adjust enable input + .PSINCDEC(1'b0), // Dynamic phase adjust increment/decrement + .RST(1'b0) // DCM asynchronous reset input +); + +`elsif MINSOC_DCM_SP + +DCM_SP #( + .CLKDV_DIVIDE(divisor), // Divide by: 1.5,2.0,2.5,3.0,3.5,4.0,4.5,5.0,5.5,6.0,6.5 + // 7.0,7.5,8.0,9.0,10.0,11.0,12.0,13.0,14.0,15.0 or 16.0 + .CLKFX_DIVIDE(1), // Can be any integer from 1 to 32 + .CLKFX_MULTIPLY(4), // Can be any integer from 2 to 32 + .CLKIN_DIVIDE_BY_2("FALSE"), // TRUE/FALSE to enable CLKIN divide by two feature + .CLKIN_PERIOD(0.0), // Specify period of input clock + .CLKOUT_PHASE_SHIFT("NONE"), // Specify phase shift of NONE, FIXED or VARIABLE + .CLK_FEEDBACK("1X"), // Specify clock feedback of NONE, 1X or 2X + .DESKEW_ADJUST("SYSTEM_SYNCHRONOUS"), // SOURCE_SYNCHRONOUS, SYSTEM_SYNCHRONOUS or + // an integer from 0 to 15 + .DLL_FREQUENCY_MODE("LOW"), // HIGH or LOW frequency mode for DLL + .DUTY_CYCLE_CORRECTION("TRUE"), // Duty cycle correction, TRUE or FALSE + .PHASE_SHIFT(0), // Amount of fixed phase shift from -255 to 255 + .STARTUP_WAIT("FALSE") // Delay configuration DONE until DCM LOCK, TRUE/FALSE +) DCM_SP_inst ( + .CLK0(CLK0_BUF), // 0 degree DCM CLK output + .CLK180(), // 180 degree DCM CLK output + .CLK270(), // 270 degree DCM CLK output + .CLK2X(), // 2X DCM CLK output + .CLK2X180(), // 2X, 180 degree DCM CLK out + .CLK90(), // 90 degree DCM CLK output + .CLKDV(CLKDV_BUF), // Divided DCM CLK out (CLKDV_DIVIDE) + .CLKFX(), // DCM CLK synthesis out (M/D) + .CLKFX180(), // 180 degree CLK synthesis out + .LOCKED(), // DCM LOCK status output + .PSDONE(), // Dynamic phase adjust done output + .STATUS(), // 8-bit DCM status bits output + .CLKFB(CLKFB_IN), // DCM clock feedback + .CLKIN(CLKIN_IBUFG), // Clock input (from IBUFG, BUFG or DCM) + .PSCLK(1'b0), // Dynamic phase adjust clock input + .PSEN(1'b0), // Dynamic phase adjust enable input + .PSINCDEC(1'b0), // Dynamic phase adjust increment/decrement + .RST(1'b0) // DCM asynchronous reset input +); + +`elsif MINSOC_DCM_ADV + +DCM_ADV #( + .CLKDV_DIVIDE(divisor), // Divide by: 1.5,2.0,2.5,3.0,3.5,4.0,4.5,5.0,5.5,6.0,6.5 + // 7.0,7.5,8.0,9.0,10.0,11.0,12.0,13.0,14.0,15.0 or 16.0 + .CLKFX_DIVIDE(1), // Can be any integer from 1 to 32 + .CLKFX_MULTIPLY(4), // Can be any integer from 2 to 32 + .CLKIN_DIVIDE_BY_2("FALSE"), // TRUE/FALSE to enable CLKIN divide by two feature + .CLKIN_PERIOD(10.0), // Specify period of input clock in ns from 1.25 to 1000.00 + .CLKOUT_PHASE_SHIFT("NONE"), // Specify phase shift mode of NONE, FIXED, + // VARIABLE_POSITIVE, VARIABLE_CENTER or DIRECT + .CLK_FEEDBACK("1X"), // Specify clock feedback of NONE, 1X or 2X + .DCM_AUTOCALIBRATION("TRUE"), // DCM calibration circuitry "TRUE"/"FALSE" + .DCM_PERFORMANCE_MODE("MAX_SPEED"), // Can be MAX_SPEED or MAX_RANGE + .DESKEW_ADJUST("SYSTEM_SYNCHRONOUS"), // SOURCE_SYNCHRONOUS, SYSTEM_SYNCHRONOUS or + // an integer from 0 to 15 + .DFS_FREQUENCY_MODE("LOW"), // HIGH or LOW frequency mode for frequency synthesis + .DLL_FREQUENCY_MODE("LOW"), // LOW, HIGH, or HIGH_SER frequency mode for DLL + .DUTY_CYCLE_CORRECTION("TRUE"), // Duty cycle correction, "TRUE"/"FALSE" + .FACTORY_JF(16'hf0f0), // FACTORY JF value suggested to be set to 16’hf0f0 + .PHASE_SHIFT(0), // Amount of fixed phase shift from -255 to 1023 + .SIM_DEVICE(`MINSOC_DCM_COMPONENT), // Set target device, "VIRTEX4" or "VIRTEX5" + .STARTUP_WAIT("FALSE") // Delay configuration DONE until DCM LOCK, "TRUE"/"FALSE" +) DCM_ADV_inst ( + .CLK0(CLK0_BUF), // 0 degree DCM CLK output + .CLK180(), // 180 degree DCM CLK output + .CLK270(), // 270 degree DCM CLK output + .CLK2X(), // 2X DCM CLK output + .CLK2X180(), // 2X, 180 degree DCM CLK out + .CLK90(), // 90 degree DCM CLK output + .CLKDV(CLKDV_BUF), // Divided DCM CLK out (CLKDV_DIVIDE) + .CLKFX(), // DCM CLK synthesis out (M/D) + .CLKFX180(), // 180 degree CLK synthesis out + .DO(), // 16-bit data output for Dynamic Reconfiguration Port (DRP) + .DRDY(), // Ready output signal from the DRP + .LOCKED(), // DCM LOCK status output + .PSDONE(), // Dynamic phase adjust done output + .CLKFB(CLKFB_IN), // DCM clock feedback + .CLKIN(CLKIN_IBUFG), // Clock input (from IBUFG, BUFG or DCM) + .DADDR(7'h00), // 7-bit address for the DRP + .DCLK(1'b0), // Clock for the DRP + .DEN(1'b0), // Enable input for the DRP + .DI(16'h0000), // 16-bit data input for the DRP + .DWE(1'b0), // Active high allows for writing configuration memory + .PSCLK(1'b0), // Dynamic phase adjust clock input + .PSEN(1'b0), // Dynamic phase adjust enable input + .PSINCDEC(1'b0), // Dynamic phase adjust increment/decrement + .RST(1'b0) // DCM asynchronous reset input +); + +`endif // !MINSOC_DLL/MINSOC_DCM/MINSOC_DCM_SP/MINSOC_DCM_ADV +`endif // !ALTERA_FPGA/XILINX_FPGA +`endif // !NO_CLOCK_DIVISION/GENERIC_CLOCK_DIVISION/FPGA_CLOCK_DIVISION + + +endmodule

minsoc_clock_manager.v Property changes : Added: svn:executable ## -0,0 +1 ## +* \ No newline at end of property Index: minsoc_xilinx_internal_jtag.v =================================================================== --- minsoc_xilinx_internal_jtag.v (nonexistent) +++ minsoc_xilinx_internal_jtag.v (revision 42) @@ -0,0 +1,441 @@ +/////////////////////////////////////////////////////////////////////// +//// //// +//// xilinx_internal_jtag.v //// +//// //// +//// //// +//// //// +//// Author(s): //// +//// Nathan Yawn (nathan.yawn@opencores.org) //// +//// //// +//// //// +//// //// +////////////////////////////////////////////////////////////////////// +//// //// +//// Copyright (C) 2008 Authors //// +//// //// +//// This source file may be used and distributed without //// +//// restriction provided that this copyright statement is not //// +//// removed from the file and that any derivative work contains //// +//// the original copyright notice and the associated disclaimer. //// +//// //// +//// This source file is free software; you can redistribute it //// +//// and/or modify it under the terms of the GNU Lesser General //// +//// Public License as published by the Free Software Foundation; //// +//// either version 2.1 of the License, or (at your option) any //// +//// later version. //// +//// //// +//// This source is distributed in the hope that it will be //// +//// useful, but WITHOUT ANY WARRANTY; without even the implied //// +//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR //// +//// PURPOSE. See the GNU Lesser General Public License for more //// +//// details. //// +//// //// +//// You should have received a copy of the GNU Lesser General //// +//// Public License along with this source; if not, download it //// +//// from http://www.opencores.org/lgpl.shtml //// +//// //// +////////////////////////////////////////////////////////////////////// +// // +// This file is a wrapper for the various Xilinx internal BSCAN // +// TAP devices. It is designed to take the place of a separate TAP // +// controller in Xilinx systems, to allow a user to access a CPU // +// debug module (such as that of the OR1200) through the FPGA's // +// dedicated JTAG / configuration port. // +// // +////////////////////////////////////////////////////////////////////// +// +// CVS Revision History +// +// $Log: xilinx_internal_jtag.v,v $ +// Revision 1.3 2009/06/16 02:54:23 Nathan +// Changed some signal names for better consistency between different hardware modules. +// +// Revision 1.2 2009/05/17 20:54:16 Nathan +// Changed email address to opencores.org +// +// Revision 1.1 2008/07/18 20:07:32 Nathan +// Changed the directory structure to match existing projects. +// +// Revision 1.4 2008/07/11 08:26:10 Nathan +// Ran through dos2unix +// +// Revision 1.3 2008/07/11 08:25:52 Nathan +// Added logic to provide CAPTURE_DR signal when necessary, and to provide a TCK while UPDATE_DR is asserted. Note that there is no TCK event between SHIFT_DR and UPDATE_DR, and no TCK event between UPDATE_DR and the next CAPTURE_DR; the Xilinx BSCAN devices do not provide it. Tested successfully with the adv_dbg_if on Virtex-4. +// +// Revision 1.2 2008/06/09 19:34:14 Nathan +// Syntax and functional fixes made after compiling each type of BSCAN module using Xilinx tools. +// +// Revision 1.1 2008/05/22 19:54:07 Nathan +// Initial version +// + + +`include "minsoc_defines.v" + +// Note that the SPARTAN BSCAN controllers have more than one channel. +// This implementation always uses channel 1, this is not configurable. +// If you want to use another channel, then it is probably because you +// want to attach multiple devices to the BSCAN device, which means +// you'll be making changes to this file anyway. +// Virtex BSCAN devices are instantiated separately for each channel. +// To select something other than the default (1), change the parameter +// "virtex_jtag_chain". + + +module minsoc_xilinx_internal_jtag ( + tck_o, + debug_tdo_i, + tdi_o, + test_logic_reset_o, + run_test_idle_o, + shift_dr_o, + capture_dr_o, + pause_dr_o, + update_dr_o, + debug_select_o +); + +// May be 1, 2, 3, or 4 +// Only used for Virtex 4/5 devices +parameter virtex_jtag_chain = 1; + +input debug_tdo_i; +output tck_o; +output tdi_o; +output test_logic_reset_o; +output run_test_idle_o; +output shift_dr_o; +output capture_dr_o; +output pause_dr_o; +output update_dr_o; +output debug_select_o; + +wire debug_tdo_i; +wire tck_o; +wire drck; +wire tdi_o; +wire test_logic_reset_o; +wire run_test_idle_o; +wire shift_dr_o; +wire pause_dr_o; +wire update_dr_o; +wire debug_select_o; + +`ifdef SPARTAN3E + `define SPARTAN3 +`endif + +`ifdef SPARTAN2 + +// Note that this version is missing three outputs. +// It also does not have a real TCK...DRCK1 is only active when USER1 is selected +// AND the TAP is in SHIFT_DR or CAPTURE_DR states...except there's no +// capture_dr output. + +reg capture_dr_o; +wire update_bscan; +reg update_out; + +BSCAN_SPARTAN2 BSCAN_SPARTAN2_inst ( +.DRCK1(drck), // Data register output for USER1 functions +.DRCK2(), // Data register output for USER2 functions +.RESET(test_logic_reset_o), // Reset output from TAP controller +.SEL1(debug_select_o), // USER1 active output +.SEL2(), // USER2 active output +.SHIFT(shift_dr_o), // SHIFT output from TAP controller +.TDI(tdi_o), // TDI output from TAP controller +.UPDATE(update_bscan), // UPDATE output from TAP controller +.TDO1(debug_tdo_i), // Data input for USER1 function +.TDO2( 1'b0 ) // Data input for USER2 function +); + +assign pause_dr_o = 1'b0; +assign run_test_idle_o = 1'b0; + +// We get one TCK during capture_dr state (low,high,SHIFT goes high on next DRCK high) +// On that negative edge, set capture_dr, and it will get registered on the rising +// edge. +always @ (negedge tck_o) +begin + if(debug_select_o && !shift_dr_o) + capture_dr_o <= 1'b1; + else + capture_dr_o <= 1'b0; +end + +// The & !update_bscan tern will provide a clock edge so update_dr_o can be registered +// The &debug_select term will drop TCK when the module is un-selected (does not happen in the BSCAN block). +// This allows a user to kludge clock ticks in the IDLE state, which is needed by the advanced debug module. +assign tck_o = (drck & debug_select_o & !update_bscan); + +// This will hold the update_dr output so it can be registered on the rising edge +// of the clock created above. +always @(posedge update_bscan or posedge capture_dr_o or negedge debug_select_o) +begin + if(update_bscan) update_out <= 1'b1; + else if(capture_dr_o) update_out <= 1'b0; + else if(!debug_select_o) update_out <= 1'b0; +end + +assign update_dr_o = update_out; + +`else +`ifdef SPARTAN3 +// Note that this version is missing two outputs. +// It also does not have a real TCK...DRCK1 is only active when USER1 is selected. + +wire capture_dr_o; +wire update_bscan; +reg update_out; + +BSCAN_SPARTAN3 BSCAN_SPARTAN3_inst ( +.CAPTURE(capture_dr_o), // CAPTURE output from TAP controller +.DRCK1(drck), // Data register output for USER1 functions +.DRCK2(), // Data register output for USER2 functions +.RESET(test_logic_reset_o), // Reset output from TAP controller +.SEL1(debug_select_o), // USER1 active output +.SEL2(), // USER2 active output +.SHIFT(shift_dr_o), // SHIFT output from TAP controller +.TDI(tdi_o), // TDI output from TAP controller +.UPDATE(update_bscan), // UPDATE output from TAP controller +.TDO1(debug_tdo_i), // Data input for USER1 function +.TDO2(1'b0) // Data input for USER2 function +); + +assign pause_dr_o = 1'b0; +assign run_test_idle_o = 1'b0; + +// The & !update_bscan tern will provide a clock edge so update_dr_o can be registered +// The &debug_select term will drop TCK when the module is un-selected (does not happen in the BSCAN block). +// This allows a user to kludge clock ticks in the IDLE state, which is needed by the advanced debug module. +assign tck_o = (drck & debug_select_o & !update_bscan); + +// This will hold the update_dr output so it can be registered on the rising edge +// of the clock created above. +always @(posedge update_bscan or posedge capture_dr_o or negedge debug_select_o) +begin + if(update_bscan) update_out <= 1'b1; + else if(capture_dr_o) update_out <= 1'b0; + else if(!debug_select_o) update_out <= 1'b0; +end + +assign update_dr_o = update_out; + +`ifdef SPARTAN3E + `undef SPARTAN3 +`endif + +`else +`ifdef SPARTAN3A +// Note that this version is missing two outputs. +// At least it has a real TCK. + +wire capture_dr_o; + +BSCAN_SPARTAN3A BSCAN_SPARTAN3A_inst ( +.CAPTURE(capture_dr_o), // CAPTURE output from TAP controller +.DRCK1(), // Data register output for USER1 functions +.DRCK2(), // Data register output for USER2 functions +.RESET(test_logic_reset_o), // Reset output from TAP controller +.SEL1(debug_select_o), // USER1 active output +.SEL2(), // USER2 active output +.SHIFT(shift_dr_o), // SHIFT output from TAP controller +.TCK(tck_o), // TCK output from TAP controller +.TDI(tdi_o), // TDI output from TAP controller +.TMS(), // TMS output from TAP controller +.UPDATE(update_dr_o), // UPDATE output from TAP controller +.TDO1(debug_tdo_i), // Data input for USER1 function +.TDO2( 1'b0) // Data input for USER2 function +); + +assign pause_dr_o = 1'b0; +assign run_test_idle_o = 1'b0; + +`else +`ifdef VIRTEX + +// Note that this version is missing three outputs. +// It also does not have a real TCK...DRCK1 is only active when USER1 is selected. + +reg capture_dr_o; +wire update_bscan; +reg update_out; + +BSCAN_VIRTEX BSCAN_VIRTEX_inst ( +.DRCK1(drck), // Data register output for USER1 functions +.DRCK2(), // Data register output for USER2 functions +.RESET(test_logic_reset_o), // Reset output from TAP controller +.SEL1(debug_select_o), // USER1 active output +.SEL2(), // USER2 active output +.SHIFT(shift_dr_o), // SHIFT output from TAP controller +.TDI(tdi_o), // TDI output from TAP controller +.UPDATE(update_bscan), // UPDATE output from TAP controller +.TDO1(debug_tdo_i), // Data input for USER1 function +.TDO2( 1'b0) // Data input for USER2 function +); + +assign pause_dr_o = 1'b0; +assign run_test_idle_o = 1'b0; + +// We get one TCK during capture_dr state (low,high,SHIFT goes high on next DRCK low) +// On that negative edge, set capture_dr, and it will get registered on the rising +// edge, then de-asserted on the same edge that SHIFT goes high. +always @ (negedge tck_o) +begin + if(debug_select_o && !shift_dr_o) + capture_dr_o <= 1'b1; + else + capture_dr_o <= 1'b0; +end + +// The & !update_bscan tern will provide a clock edge so update_dr_o can be registered +// The &debug_select term will drop TCK when the module is un-selected (does not happen in the BSCAN block). +// This allows a user to kludge clock ticks in the IDLE state, which is needed by the advanced debug module. +assign tck_o = (drck & debug_select_o & !update_bscan); + +// This will hold the update_dr output so it can be registered on the rising edge +// of the clock created above. +always @(posedge update_bscan or posedge capture_dr_o or negedge debug_select_o) +begin + if(update_bscan) update_out <= 1'b1; + else if(capture_dr_o) update_out <= 1'b0; + else if(!debug_select_o) update_out <= 1'b0; +end + +assign update_dr_o = update_out; + +`else +`ifdef VIRTEX2 + +// Note that this version is missing two outputs. +// It also does not have a real TCK...DRCK1 is only active when USER1 is selected. + +wire capture_dr_o; +wire update_bscan; +reg update_out; + +BSCAN_VIRTEX2 BSCAN_VIRTEX2_inst ( +.CAPTURE(capture_dr_o), // CAPTURE output from TAP controller +.DRCK1(drck), // Data register output for USER1 functions +.DRCK2(), // Data register output for USER2 functions +.RESET(test_logic_reset_o), // Reset output from TAP controller +.SEL1(debug_select_o), // USER1 active output +.SEL2(), // USER2 active output +.SHIFT(shift_dr_o), // SHIFT output from TAP controller +.TDI(tdi_o), // TDI output from TAP controller +.UPDATE(update_bscan), // UPDATE output from TAP controller +.TDO1(debug_tdo_i), // Data input for USER1 function +.TDO2( 1'b0 ) // Data input for USER2 function +); + +assign pause_dr_o = 1'b0; +assign run_test_idle_o = 1'b0; + +// The & !update_bscan tern will provide a clock edge so update_dr_o can be registered +// The &debug_select term will drop TCK when the module is un-selected (does not happen in the BSCAN block). +// This allows a user to kludge clock ticks in the IDLE state, which is needed by the advanced debug module. +assign tck_o = (drck & debug_select_o & !update_bscan); + +// This will hold the update_dr output so it can be registered on the rising edge +// of the clock created above. +always @(posedge update_bscan or posedge capture_dr_o or negedge debug_select_o) +begin + if(update_bscan) update_out <= 1'b1; + else if(capture_dr_o) update_out <= 1'b0; + else if(!debug_select_o) update_out <= 1'b0; +end + +assign update_dr_o = update_out; + +`else +`ifdef VIRTEX4 +// Note that this version is missing two outputs. +// It also does not have a real TCK...DRCK is only active when USERn is selected. + +wire capture_dr_o; +wire update_bscan; +reg update_out; + +BSCAN_VIRTEX4 #( +.JTAG_CHAIN(virtex_jtag_chain) +) BSCAN_VIRTEX4_inst ( +.CAPTURE(capture_dr_o), // CAPTURE output from TAP controller +.DRCK(drck), // Data register output for USER function +.RESET(test_logic_reset_o), // Reset output from TAP controller +.SEL(debug_select_o), // USER active output +.SHIFT(shift_dr_o), // SHIFT output from TAP controller +.TDI(tdi_o), // TDI output from TAP controller +.UPDATE(update_bscan), // UPDATE output from TAP controller +.TDO( debug_tdo_i ) // Data input for USER function +); + +assign pause_dr_o = 1'b0; +assign run_test_idle_o = 1'b0; + +// The & !update_bscan tern will provide a clock edge so update_dr_o can be registered +// The &debug_select term will drop TCK when the module is un-selected (does not happen in the BSCAN block). +// This allows a user to kludge clock ticks in the IDLE state, which is needed by the advanced debug module. +assign tck_o = (drck & debug_select_o & !update_bscan); + +// This will hold the update_dr output so it can be registered on the rising edge +// of the clock created above. +always @(posedge update_bscan or posedge capture_dr_o or negedge debug_select_o) +begin + if(update_bscan) update_out <= 1'b1; + else if(capture_dr_o) update_out <= 1'b0; + else if(!debug_select_o) update_out <= 1'b0; +end + +assign update_dr_o = update_out; + +`else +`ifdef VIRTEX5 +// Note that this version is missing two outputs. +// It also does not have a real TCK...DRCK is only active when USERn is selected. + +wire capture_dr_o; +wire update_bscan; +reg update_out; + +BSCAN_VIRTEX5 #( +.JTAG_CHAIN(virtex_jtag_chain) +) BSCAN_VIRTEX5_inst ( +.CAPTURE(capture_dr_o), // CAPTURE output from TAP controller +.DRCK(drck), // Data register output for USER function +.RESET(test_logic_reset), // Reset output from TAP controller +.SEL(debug_select_o), // USER active output +.SHIFT(shift_dr_o), // SHIFT output from TAP controller +.TDI(tdi_o), // TDI output from TAP controller +.UPDATE(update_bscan), // UPDATE output from TAP controller +.TDO(debug_tdo_i) // Data input for USER function +); + +assign pause_dr_o = 1'b0; +assign run_test_idle_o = 1'b0; + +// The & !update_bscan tern will provide a clock edge so update_dr_o can be registered +// The &debug_select term will drop TCK when the module is un-selected (does not happen in the BSCAN block). +// This allows a user to kludge clock ticks in the IDLE state, which is needed by the advanced debug module. +assign tck_o = (drck & debug_select_o & !update_bscan); + +// This will hold the update_dr output so it can be registered on the rising edge +// of the clock created above. +always @(posedge update_bscan or posedge capture_dr_o or negedge debug_select_o) +begin + if(update_bscan) update_out <= 1'b1; + else if(capture_dr_o) update_out <= 1'b0; + else if(!debug_select_o) update_out <= 1'b0; +end + +assign update_dr_o = update_out; + + +`endif +`endif +`endif +`endif +`endif +`endif +`endif + +endmodule

minsoc_xilinx_internal_jtag.v Property changes : Added: svn:executable ## -0,0 +1 ## +* \ No newline at end of property