OpenCores
URL https://opencores.org/ocsvn/minsoc/minsoc/trunk

Subversion Repositories minsoc

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  • This comparison shows the changes necessary to convert path
    /minsoc/tags
    from Rev 42 to Rev 151
    Reverse comparison

Rev 42 → Rev 151

/release-1.0/utils/setup/minsoc-install.sh
0,0 → 1,247
#!/bin/bash
# Author: Constantinos Xanthopoulos & Raul Fajardo
# This script install MinSOC tree
# under a specific directory.
 
# ===== CONFIGURATIONS =====
# ==========================
MINSOC_SVN_URL=http://opencores.org/ocsvn/minsoc/minsoc/tags/release-1.0
export SCRIPT_DIR="$( cd -P "$( dirname "$0" )" && pwd )"
export DIR_TO_INSTALL=`pwd`
 
# Debug ?
export DEBUG=0;
. ${SCRIPT_DIR}/beautify.sh
 
function testtool
{
# is_missing=`which $1 2>&1 | grep no`
is_missing=`whereis -b $1 2>&1 | grep :$`
if [ -z "$is_missing" ]
then
cecho "$1 is installed, pass"
else
errormsg "$1 is not installed, install it and re-run this installation script."
fi
}
 
 
#Setting environment
ENV=`uname -o`
if [ "$ENV" != "GNU/Linux" ] && [ "$ENV" != "Cygwin" ]
then
errormsg "Environment $ENV not supported by this script."
fi
cecho "Building tools for ${ENV} system"
 
is_arch64=`uname -m | grep 64`
if [ -z $is_arch64 ]
then
KERNEL_ARCH="32"
else
KERNEL_ARCH="64"
fi
 
 
# User check!
if [ `whoami` = "root" ];
then
errormsg "You shouldn't be root for this script to run.";
fi;
 
 
# Testing necessary tools
cecho "Testing if necessary tools are installed, program "whereis" is required."
testtool wget
testtool svn
testtool bzip2
testtool tar
testtool sed
testtool patch
testtool gcc
testtool make
testtool makeinfo
testtool libncurses
testtool flex
testtool bison
testtool libz
if [ "$ENV" == "Cygwin" ]
then
testtool ioperm
testtool libusb
fi
 
 
# Wizard
if [ -z "${ALTDIR}" ]
then
cnecho "Give full path (ex. /home/foo/) for installation directory or leave empty for "${DIR_TO_INSTALL}": ";
read ALTDIR;
if [ ! -z "${ALTDIR}" ]
then
DIR_TO_INSTALL=${ALTDIR}
fi
cecho "${DIR_TO_INSTALL} selected";
fi
 
if [ ! -d ${DIR_TO_INSTALL} ]
then
cecho "Directory ${DIR_TO_INSTALL} doesn't exist."
execcmd "Creating directory ${DIR_TO_INSTALL}" "mkdir -p ${DIR_TO_INSTALL}"
if [ $? -ne 0 ]
then
errormsg "Connot create ${DIR_TO_INSTALL}";
fi
fi;
 
 
#Creating directory structure
cecho "\nCreating directory structure"
cd ${DIR_TO_INSTALL}
execcmd "Creating directory ./download for downloaded packages" "mkdir -p download"
execcmd "Creating directory ./tools for package binaries" "mkdir -p tools"
 
 
#Downloading everything we need
cecho "\nDownloading packages"
cd ${DIR_TO_INSTALL}
cecho "Download MinSoC"
svn co -q ${MINSOC_SVN_URL} minsoc #user need to input password, execcmd omits command output and should be this way
execcmd "cd ${DIR_TO_INSTALL}/download"
if [ "$ENV" == "Cygwin" ]
then
execcmd "Downloading GNU Toolchain" "wget ftp://ocuser:ocuser@openrisc.opencores.org/toolchain/or32-elf-cygwin-1.7.tar.bz2";
else
if [ $KERNEL_ARCH == "32" ];
then
execcmd "Downloading GNU Toolchain" "wget ftp://ocuser:ocuser@openrisc.opencores.org/toolchain/or32-elf-linux-x86.tar.bz2";
elif [ $KERNEL_ARCH == "64" ];
then
execcmd "Downloading GNU Toolchain" "wget ftp://ocuser:ocuser@openrisc.opencores.org/toolchain/or32-elf-linux-x86_64.tar.bz2";
fi
fi
execcmd "Downloading GDB" "wget ftp://anonymous:anonymous@ftp.gnu.org/gnu/gdb/gdb-6.8a.tar.bz2"
execcmd "wget ftp://ocuser:ocuser@openrisc.opencores.org/toolchain/or32-gdb-6.8-patch-2.4.bz2"
execcmd "svn export -q http://opencores.org/ocsvn/adv_debug_sys/adv_debug_sys/trunk/Patches/GDB6.8/gdb-6.8-bz436037-reg-no-longer-active.patch"
if [ "$ENV" != "Cygwin" ]
then
execcmd "Downloading libusb-0.1 for Advanced Debug System" "wget http://sourceforge.net/projects/libusb/files/libusb-0.1%20%28LEGACY%29/0.1.12/libusb-0.1.12.tar.gz"
fi
execcmd "Downloading libftdi for Advanced Debug System" "wget http://www.intra2net.com/en/developer/libftdi/download/libftdi-0.19.tar.gz"
execcmd "Downloading Icarus Verilog" "wget ftp://icarus.com/pub/eda/verilog/v0.9/verilog-0.9.4.tar.gz"
 
 
#Uncompressing everything
cecho "\nUncompressing packages"
if [ "$ENV" == "Cygwin" ]
then
execcmd "tar xf or32-elf-cygwin-1.7.tar.bz2";
else
if [ $KERNEL_ARCH == "32" ];
then
execcmd "tar xf or32-elf-linux-x86.tar.bz2";
elif [ $KERNEL_ARCH == "64" ];
then
execcmd "tar xf or32-elf-linux-x86_64.tar.bz2";
fi
fi
execcmd "tar -jxf gdb-6.8a.tar.bz2"
execcmd "bzip2 -d or32-gdb-6.8-patch-2.4.bz2"
if [ "$ENV" != "Cygwin" ]
then
execcmd "tar zxf libusb-0.1.12.tar.gz"
fi
execcmd "tar zxf libftdi-0.19.tar.gz"
execcmd "tar zxf verilog-0.9.4.tar.gz"
 
 
#Compiling and Installing all packages
cecho "\nCompiling and installing packages"
# Installing the GNU Toolchain
if [ "$ENV" == "Cygwin" ]
then
execcmd "Installing GNU Toolchain" "tar xf or32-elf-cygwin-1.7.tar.bz2 -C $DIR_TO_INSTALL/tools";
else
if [ $KERNEL_ARCH == "32" ];
then
execcmd "Installing GNU Toolchain" "tar xf or32-elf-linux-x86.tar.bz2 -C $DIR_TO_INSTALL/tools";
elif [ $KERNEL_ARCH == "64" ];
then
execcmd "Installing GNU Toolchain" "tar xf or32-elf-linux-x86_64.tar.bz2 -C $DIR_TO_INSTALL/tools";
fi
fi
PATH=$PATH:$DIR_TO_INSTALL/tools/or32-elf/bin
 
 
#Installing GDB
execcmd "cd gdb-6.8"
execcmd "patch -p1 < ../or32-gdb-6.8-patch-2.4"
execcmd "patch -p1 < ../gdb-6.8-bz436037-reg-no-longer-active.patch"
 
execcmd "mkdir -p build"
execcmd "cd build"
execcmd "../configure --target=or32-elf --disable-werror --prefix=$DIR_TO_INSTALL/tools"
execcmd "Compiling GDB" "make"
make install 1>>${SCRIPT_DIR}/progress.log 2>>${SCRIPT_DIR}/error.log #avoid Fedora failing due to missing Makeinfo
PATH=$PATH:${DIR_TO_INSTALL}/tools/bin
 
 
#Installing Advanced JTAG Bridge support libraries
if [ "$ENV" != "Cygwin" ]
then
execcmd "cd ${DIR_TO_INSTALL}/download/libusb-0.1.12"
execcmd "./configure --prefix=${DIR_TO_INSTALL}/tools"
execcmd "Installing libusb-0.1" "make"
execcmd "make install"
fi
 
execcmd "cd ${DIR_TO_INSTALL}/download/libftdi-0.19"
execcmd "./configure --prefix=${DIR_TO_INSTALL}/tools"
execcmd "Compiling libftdi" "make"
execcmd "make install"
 
 
#Installing Advanced JTAG Bridge
execcmd "cd ${DIR_TO_INSTALL}/minsoc/rtl/verilog/adv_debug_sys/Software/adv_jtag_bridge"
if [ `grep "INCLUDE_JSP_SERVER=true" Makefile` != "" ]
then
#Switching off the adv_jtag_bridge JSP_SERVER option
sed 's/INCLUDE_JSP_SERVER=true/INCLUDE_JSP_SERVER=false/' Makefile > TMPFILE && mv TMPFILE Makefile
fi
 
if [ "${ENV}" == "GNU/Linux" ]
then
#Setting the right build environment
sed 's/BUILD_ENVIRONMENT=cygwin/BUILD_ENVIRONMENT=linux/' Makefile > TMPFILE && mv TMPFILE Makefile
fi
 
#preparing the Makefile to find and link libraries
sed "s%prefix = /usr/local%prefix = ${DIR_TO_INSTALL}/tools%" Makefile > TMPFILE && mv TMPFILE Makefile
sed "s%\$(CC) \$(CFLAGS)%\$(CC) \$(CFLAGS) \$(INCLUDEDIRS)%" Makefile > TMPFILE && mv TMPFILE Makefile
sed "s%INCLUDEDIRS =%INCLUDEDIRS = -I${DIR_TO_INSTALL}/tools/include%" Makefile > TMPFILE && mv TMPFILE Makefile
sed "s%LIBS =%LIBS = -L${DIR_TO_INSTALL}/tools/lib -Wl,-R${DIR_TO_INSTALL}/tools/lib%" Makefile > TMPFILE && mv TMPFILE Makefile
 
#properly installing Advanced JTAG Bridge
execcmd "Compiling Advanced JTAG Bridge" "make"
execcmd "make install"
 
 
#Installing Icarus Verilog
execcmd "cd ${DIR_TO_INSTALL}/download/verilog-0.9.4"
execcmd "./configure --prefix=${DIR_TO_INSTALL}/tools"
execcmd "Compiling Icarus Verilog" "make"
execcmd "make install"
 
 
#Configuring MinSoC, Advanced Debug System and patching OpenRISC
bash ${SCRIPT_DIR}/configure.sh
 
 
#Setting-up new variables
cecho "\nSystem configurations"
execcmd "Adding MinSoC tools to PATH" "echo \"PATH=\\\$PATH:$DIR_TO_INSTALL/tools/bin\" >> /home/$(whoami)/.bashrc;";
execcmd "Adding OpenRISC toolchain to PATH" "echo \"PATH=\\\$PATH:$DIR_TO_INSTALL/tools/or32-elf/bin/\" >> /home/$(whoami)/.bashrc;";
 
cecho "\nInstallation Complete!"
cecho "Before using the system, load the new environment variables doing this: source /home/$(whoami)/.bashrc"
cecho "You may remove the ${DIR_TO_INSTALL}/download directory if you wish."
release-1.0/utils/setup/minsoc-install.sh Property changes : Added: svn:executable ## -0,0 +1 ## +* \ No newline at end of property Index: release-1.0/utils/setup/configure.sh =================================================================== --- release-1.0/utils/setup/configure.sh (nonexistent) +++ release-1.0/utils/setup/configure.sh (revision 151) @@ -0,0 +1,24 @@ +. ${SCRIPT_DIR}/beautify.sh + +#Configuring MinSoC +cecho "\nConfiguring MinSoC" +execcmd "cd ${DIR_TO_INSTALL}/minsoc/backend/std" +execcmd "Configuring MinSoC as standard board (simulatable but not synthesizable)" "./configure" +execcmd "cd ${DIR_TO_INSTALL}" + + +#Configuring Advanced Debug System to work with MinSoC +cecho "\nConfiguring Advanced Debug System to work with MinSoC" +execcmd "cd ${DIR_TO_INSTALL}/minsoc/rtl/verilog/adv_debug_sys/Hardware/adv_dbg_if/rtl/verilog" +execcmd "Turning off Advanced Debug System's JSP" "sed 's%\`define DBG_JSP_SUPPORTED%//\`define DBG_JSP_SUPPORTED%' adbg_defines.v > TMPFILE && mv TMPFILE adbg_defines.v" + +#Compiling and moving adv_jtag_bridge debug modules for simulation +execcmd "cd ${DIR_TO_INSTALL}/minsoc/rtl/verilog/adv_debug_sys/Software/adv_jtag_bridge/sim_lib/icarus" +execcmd "Compiling VPI interface to connect GDB with simulation" "make" +execcmd "cp jp-io-vpi.vpi ${DIR_TO_INSTALL}/minsoc/bench/verilog/vpi" + +#Patching OpenRISC Release 1 with Advanced Debug System patch for Watchpoints +execcmd "cd ${DIR_TO_INSTALL}/minsoc/rtl/verilog/or1200/rtl/verilog" +cecho "Patching OpenRISC for watchpoint support" +#patch -p0 < ${DIR_TO_INSTALL}/minsoc/rtl/verilog/adv_debug_sys/Patches/OR1200v1/or1200v1_hwbkpt.patch +patch -p0 < ${SCRIPT_DIR}/or1200v1_hwbkpt.patch Index: release-1.0/utils/setup/minsoc-setup.sh =================================================================== --- release-1.0/utils/setup/minsoc-setup.sh (nonexistent) +++ release-1.0/utils/setup/minsoc-setup.sh (revision 151) @@ -0,0 +1,74 @@ +#!/bin/bash +# Author: Constantinos Xanthopoulos & Raul Fajardo +# This script install MinSOC tree +# under a specific directory. + +# ===== CONFIGURATIONS ===== +# ========================== + +export SCRIPT_DIR="$( cd -P "$( dirname "$0" )" && pwd )" +export DIR_TO_INSTALL=`pwd` +# Debug ? +export DEBUG=0; +. ${SCRIPT_DIR}/beautify.sh + +function testtool +{ + # is_missing=`which $1 2>&1 | grep no` + is_missing=`whereis -b $1 2>&1 | grep :$` + if [ -z "$is_missing" ] + then + cecho "$1 is installed, pass" + else + errormsg "$1 is not installed, install it and re-run this installation script." + fi +} + + +#Setting environment +ENV=`uname -o` +if [ "$ENV" != "GNU/Linux" ] && [ "$ENV" != "Cygwin" ] +then + errormsg "Environment $ENV not supported by this script." +fi +cecho "Building tools for ${ENV} system" + +is_arch64=`uname -m | grep 64` +if [ -z $is_arch64 ] +then + KERNEL_ARCH="32" +else + KERNEL_ARCH="64" +fi + + +# User check! +if [ `whoami` = "root" ]; +then + errormsg "You shouldn't be root for this script to run."; +fi; + + +# Testing necessary tools +cecho "Testing if necessary tools are installed, program "whereis" is required." +testtool sed +testtool patch + +# Wizard +if [ -z "${ALTDIR}" ] +then + cnecho "Give full path (ex. /home/foo/) of the directory where minsoc is under or leave empty for "${DIR_TO_INSTALL}": "; + read ALTDIR; + if [ ! -z "${ALTDIR}" ] + then + DIR_TO_INSTALL=${ALTDIR} + fi + cecho "${DIR_TO_INSTALL} selected"; +fi + +if [ ! -d ${DIR_TO_INSTALL} ] +then + errormsg "Directory doesn't exist. Please create it"; +fi; + +bash ${SCRIPT_DIR}/configure.sh
release-1.0/utils/setup/minsoc-setup.sh Property changes : Added: svn:executable ## -0,0 +1 ## +* \ No newline at end of property Index: release-1.0/utils/setup/or1200v1_hwbkpt.patch =================================================================== --- release-1.0/utils/setup/or1200v1_hwbkpt.patch (nonexistent) +++ release-1.0/utils/setup/or1200v1_hwbkpt.patch (revision 151) @@ -0,0 +1,1272 @@ +--- ../../../Bennu/Hardware/or1200v1/rtl/verilog/or1200_defines.v 2010-08-25 23:25:38.000000000 -0500 ++++ ./or1200_defines.v 2010-08-26 21:31:42.000000000 -0500 +@@ -971,7 +971,7 @@ + // however already enough for use + // with or32 gdb) + // +-//`define OR1200_DU_HWBKPTS ++`define OR1200_DU_HWBKPTS + + // Number of DVR/DCR pairs if HW breakpoints enabled + `define OR1200_DU_DVRDCR_PAIRS 8 +@@ -1038,17 +1038,15 @@ + `define OR1200_DU_DMR1_CW7 15:14 + `define OR1200_DU_DMR1_CW8 17:16 + `define OR1200_DU_DMR1_CW9 19:18 +-`define OR1200_DU_DMR1_CW10 21:20 ++`define OR1200_DU_DMR1_RES 21:20 + `define OR1200_DU_DMR1_ST 22 + `define OR1200_DU_DMR1_BT 23 +-`define OR1200_DU_DMR1_DXFW 24 +-`define OR1200_DU_DMR1_ETE 25 + + // DMR2 bits + `define OR1200_DU_DMR2_WCE0 0 + `define OR1200_DU_DMR2_WCE1 1 +-`define OR1200_DU_DMR2_AWTC 12:2 +-`define OR1200_DU_DMR2_WGB 23:13 ++`define OR1200_DU_DMR2_AWTC 11:2 ++`define OR1200_DU_DMR2_WGB 21:12 + + // DWCR bits + `define OR1200_DU_DWCR_COUNT 15:0 +--- /cygdrive/c/Projects/Bennu/Hardware/or1200v1/rtl/verilog/or1200_top.v 2010-08-25 23:25:40.000000000 -0500 ++++ ./or1200_top.v 2010-06-12 16:59:02.000000000 -0500 +@@ -43,6 +43,13 @@ + // + // CVS Revision History + // ++// $Log: or1200v1_hwbkpt.patch,v $ ++// Revision 1.1 2010-08-27 02:43:07 Nathan ++// Moved patches for third-party software to a separate, dedicated directory structure. ++// ++// Revision 1.13 2004/06/08 18:17:36 lampret ++// Non-functional changes. Coding style fixes. ++// + // $Log: not supported by cvs2svn $ + // Revision 1.12 2004/04/05 08:29:57 lampret + // Merged branch_qmem into main tree. +@@ -933,6 +936,7 @@ or1200_du or1200_du( + .dcpu_cycstb_i(dcpu_cycstb_cpu), + .dcpu_we_i(dcpu_we_cpu), + .dcpu_adr_i(dcpu_adr_cpu), ++ .dcpu_be_i(dcpu_sel_cpu), + .dcpu_dat_lsu(dcpu_dat_cpu), + .dcpu_dat_dc(dcpu_dat_qmem), + .icpu_cycstb_i(icpu_cycstb_cpu), +--- /cygdrive/c/Projects/Bennu/Hardware/or1200v1/rtl/verilog/or1200_du.v 2010-08-25 23:25:38.000000000 -0500 ++++ ./or1200_du.v 2010-08-26 21:28:32.000000000 -0500 +@@ -124,8 +124,8 @@ + module or1200_du( + // RISC Internal Interface + clk, rst, +- dcpu_cycstb_i, dcpu_we_i, dcpu_adr_i, dcpu_dat_lsu, +- dcpu_dat_dc, icpu_cycstb_i, ++ dcpu_cycstb_i, dcpu_we_i, dcpu_adr_i, dcpu_be_i, ++ dcpu_dat_lsu, dcpu_dat_dc, icpu_cycstb_i, + ex_freeze, branch_op, ex_insn, id_pc, + spr_dat_npc, rf_dataw, + du_dsr, du_stall, du_addr, du_dat_i, du_dat_o, +@@ -152,6 +152,7 @@ input rst; // Reset + input dcpu_cycstb_i; // LSU status + input dcpu_we_i; // LSU status + input [31:0] dcpu_adr_i; // LSU addr ++input [3:0] dcpu_be_i; + input [31:0] dcpu_dat_lsu; // LSU store data + input [31:0] dcpu_dat_dc; // LSU load data + input [`OR1200_FETCHOP_WIDTH-1:0] icpu_cycstb_i; // IFETCH unit status +@@ -192,6 +193,7 @@ input [dw-1:0] dbg_dat_i; // External Da + output [dw-1:0] dbg_dat_o; // External Data Output + output dbg_ack_o; // External Data Acknowledge (not WB compatible) + ++reg [9:0] wp; + + // + // Some connections go directly from the CPU through DU to Debug I/F +@@ -216,7 +218,7 @@ assign dbg_is_o = 2'b00; + assign dbg_lss_o = dcpu_cycstb_i ? {dcpu_we_i, 3'b000} : 4'b0000; + assign dbg_is_o = {1'b0, icpu_cycstb_i}; + `endif +-assign dbg_wp_o = 11'b000_0000_0000; ++assign dbg_wp_o = {1'b0, wp}; //11'b000_0000_0000; + assign dbg_dat_o = du_dat_i; + + // +@@ -253,9 +255,9 @@ wire [24:0] dmr1; // DMR1 not impleme + // Debug Mode Register 2 + // + `ifdef OR1200_DU_DMR2 +-reg [23:0] dmr2; // DMR2 implemented ++reg [21:0] dmr2; // DMR2 implemented + `else +-wire [23:0] dmr2; // DMR2 not implemented ++wire [21:0] dmr2; // DMR2 not implemented + `endif + + // +@@ -473,6 +475,14 @@ reg [31:0] match_cond4_ct; + reg [31:0] match_cond5_ct; + reg [31:0] match_cond6_ct; + reg [31:0] match_cond7_ct; ++reg [31:0] match_cond0_tmp; ++reg [31:0] match_cond1_tmp; ++reg [31:0] match_cond2_tmp; ++reg [31:0] match_cond3_tmp; ++reg [31:0] match_cond4_tmp; ++reg [31:0] match_cond5_tmp; ++reg [31:0] match_cond6_tmp; ++reg [31:0] match_cond7_tmp; + reg match_cond0_stb; + reg match_cond1_stb; + reg match_cond2_stb; +@@ -491,9 +501,16 @@ reg match6; + reg match7; + reg wpcntr0_match; + reg wpcntr1_match; +-reg incr_wpcntr0; +-reg incr_wpcntr1; +-reg [10:0] wp; ++reg wpcntr0_armed; ++reg wpcntr0_oneshot; ++reg wpcntr1_armed; ++reg wpcntr1_oneshot; ++wire incr_wpcntr0; ++reg incr_wpcntr0_latched; ++wire incr_wpcntr1; ++reg incr_wpcntr1_latched; ++reg du_hwbkpt_latched; ++reg [9:0] wp_latched; + `endif + wire du_hwbkpt; + `ifdef OR1200_DU_READREGS +@@ -670,11 +687,11 @@ assign dmr1 = 25'h000_0000; + `ifdef OR1200_DU_DMR2 + always @(posedge clk or posedge rst) + if (rst) +- dmr2 <= 24'h00_0000; ++ dmr2 <= 22'h00_0000; + else if (dmr2_sel && spr_write) +- dmr2 <= #1 spr_dat_i[23:0]; ++ dmr2 <= #1 spr_dat_i[21:0]; + `else +-assign dmr2 = 24'h00_0000; ++assign dmr2 = 22'h00_0000; + `endif + + // +@@ -815,9 +832,9 @@ assign dvr7 = 32'h0000_0000; + `ifdef OR1200_DU_DCR0 + always @(posedge clk or posedge rst) + if (rst) +- dcr0 <= 8'h00; ++ dcr0 <= 8'h01; + else if (dcr0_sel && spr_write) +- dcr0 <= #1 spr_dat_i[7:0]; ++ dcr0 <= #1 {spr_dat_i[7:1], 1'b1}; + `else + assign dcr0 = 8'h00; + `endif +@@ -828,9 +845,9 @@ assign dcr0 = 8'h00; + `ifdef OR1200_DU_DCR1 + always @(posedge clk or posedge rst) + if (rst) +- dcr1 <= 8'h00; ++ dcr1 <= 8'h01; + else if (dcr1_sel && spr_write) +- dcr1 <= #1 spr_dat_i[7:0]; ++ dcr1 <= #1 {spr_dat_i[7:1], 1'b1}; + `else + assign dcr1 = 8'h00; + `endif +@@ -841,9 +858,9 @@ assign dcr1 = 8'h00; + `ifdef OR1200_DU_DCR2 + always @(posedge clk or posedge rst) + if (rst) +- dcr2 <= 8'h00; ++ dcr2 <= 8'h01; + else if (dcr2_sel && spr_write) +- dcr2 <= #1 spr_dat_i[7:0]; ++ dcr2 <= #1 {spr_dat_i[7:1], 1'b1}; + `else + assign dcr2 = 8'h00; + `endif +@@ -854,9 +871,9 @@ assign dcr2 = 8'h00; + `ifdef OR1200_DU_DCR3 + always @(posedge clk or posedge rst) + if (rst) +- dcr3 <= 8'h00; ++ dcr3 <= 8'h01; + else if (dcr3_sel && spr_write) +- dcr3 <= #1 spr_dat_i[7:0]; ++ dcr3 <= #1 {spr_dat_i[7:1], 1'b1}; + `else + assign dcr3 = 8'h00; + `endif +@@ -867,9 +884,9 @@ assign dcr3 = 8'h00; + `ifdef OR1200_DU_DCR4 + always @(posedge clk or posedge rst) + if (rst) +- dcr4 <= 8'h00; ++ dcr4 <= 8'h01; + else if (dcr4_sel && spr_write) +- dcr4 <= #1 spr_dat_i[7:0]; ++ dcr4 <= #1 {spr_dat_i[7:1], 1'b1}; + `else + assign dcr4 = 8'h00; + `endif +@@ -880,9 +897,9 @@ assign dcr4 = 8'h00; + `ifdef OR1200_DU_DCR5 + always @(posedge clk or posedge rst) + if (rst) +- dcr5 <= 8'h00; ++ dcr5 <= 8'h01; + else if (dcr5_sel && spr_write) +- dcr5 <= #1 spr_dat_i[7:0]; ++ dcr5 <= #1 {spr_dat_i[7:1], 1'b1}; + `else + assign dcr5 = 8'h00; + `endif +@@ -893,9 +910,9 @@ assign dcr5 = 8'h00; + `ifdef OR1200_DU_DCR6 + always @(posedge clk or posedge rst) + if (rst) +- dcr6 <= 8'h00; ++ dcr6 <= 8'h01; + else if (dcr6_sel && spr_write) +- dcr6 <= #1 spr_dat_i[7:0]; ++ dcr6 <= #1 {spr_dat_i[7:1], 1'b1}; + `else + assign dcr6 = 8'h00; + `endif +@@ -906,9 +923,9 @@ assign dcr6 = 8'h00; + `ifdef OR1200_DU_DCR7 + always @(posedge clk or posedge rst) + if (rst) +- dcr7 <= 8'h00; ++ dcr7 <= 8'h01; + else if (dcr7_sel && spr_write) +- dcr7 <= #1 spr_dat_i[7:0]; ++ dcr7 <= #1 {spr_dat_i[7:1], 1'b1}; + `else + assign dcr7 = 8'h00; + `endif +@@ -952,7 +969,7 @@ always @(spr_addr or dsr or drr or dmr1 + or dvr5 or dvr6 or dvr7 + or dcr0 or dcr1 or dcr2 or dcr3 or dcr4 + or dcr5 or dcr6 or dcr7 +- or dwcr0 or dwcr1 ++ or dwcr0 or dwcr1 or wp_latched + `ifdef OR1200_DU_TB_IMPLEMENTED + or tb_wadr or tbia_dat_o or tbim_dat_o + or tbar_dat_o or tbts_dat_o +@@ -1029,7 +1046,7 @@ always @(spr_addr or dsr or drr or dmr1 + `endif + `ifdef OR1200_DU_DMR2 + `OR1200_DU_DMR2: +- spr_dat_o = {8'h00, dmr2}; ++ spr_dat_o = {wp_latched, dmr2}; + `endif + `ifdef OR1200_DU_DWCR0 + `OR1200_DU_DWCR0: +@@ -1077,23 +1094,50 @@ assign du_dsr = dsr; + always @(dcr0 or id_pc or dcpu_adr_i or dcpu_dat_dc + or dcpu_dat_lsu or dcpu_we_i) + case (dcr0[`OR1200_DU_DCR_CT]) // synopsys parallel_case +- 3'b001: match_cond0_ct = id_pc; // insn fetch EA +- 3'b010: match_cond0_ct = dcpu_adr_i; // load EA +- 3'b011: match_cond0_ct = dcpu_adr_i; // store EA +- 3'b100: match_cond0_ct = dcpu_dat_dc; // load data +- 3'b101: match_cond0_ct = dcpu_dat_lsu; // store data +- 3'b110: match_cond0_ct = dcpu_adr_i; // load/store EA +- default:match_cond0_ct = dcpu_we_i ? dcpu_dat_lsu : dcpu_dat_dc; +- endcase ++ 3'b001: match_cond0_tmp = id_pc; // insn fetch EA ++ 3'b010: match_cond0_tmp = dcpu_adr_i; // load EA ++ 3'b011: match_cond0_tmp = dcpu_adr_i; // store EA ++ 3'b100: match_cond0_tmp = dcpu_dat_dc; // load data ++ 3'b101: match_cond0_tmp = dcpu_dat_lsu; // store data ++ 3'b110: match_cond0_tmp = dcpu_adr_i; // load/store EA ++ default:match_cond0_tmp = dcpu_we_i ? dcpu_dat_lsu : dcpu_dat_dc; ++ endcase ++ ++// Transparently handle 8/16/32 bit bus accesses (Match Condition 0) ++// For addresses, leave unchanged ++// for 32-bit data, leave unchanged ++// for 8- or 16-bit data, move the active byte lane(s) to the LSB position ++// This will allow the value to be compared to the LSB(s) of the DVR ++always @(match_cond0_tmp or dcr0 or dcpu_be_i) ++ case (dcr0[`OR1200_DU_DCR_CT]) // synopsys parallel_case ++ 3'b100, ++ 3'b101, ++ 3'b111: begin // We're comparing to data ++ case (dcpu_be_i) ++ 4'b1000: match_cond0_ct = { {24{dcr0[`OR1200_DU_DCR_SC] & match_cond0_tmp[31]}}, match_cond0_tmp[31:24]}; ++ 4'b0100: match_cond0_ct = { {24{dcr0[`OR1200_DU_DCR_SC] & match_cond0_tmp[23]}}, match_cond0_tmp[23:16]}; ++ 4'b0010: match_cond0_ct = { {24{dcr0[`OR1200_DU_DCR_SC] & match_cond0_tmp[15]}}, match_cond0_tmp[15:8]}; ++ 4'b0001: match_cond0_ct = { {24{dcr0[`OR1200_DU_DCR_SC] & match_cond0_tmp[7] }}, match_cond0_tmp[7:0]}; ++ 4'b1100: match_cond0_ct = { {16{dcr0[`OR1200_DU_DCR_SC] & match_cond0_tmp[31]}}, match_cond0_tmp[31:16]}; ++ 4'b0011: match_cond0_ct = { {16{dcr0[`OR1200_DU_DCR_SC] & match_cond0_tmp[15]}}, match_cond0_tmp[15:0]}; ++ default: match_cond0_ct = match_cond0_tmp; ++ endcase ++ end ++ default: match_cond0_ct = match_cond0_tmp; // We're comparing an address ++ endcase + + // + // When To Compare (Match Condition 0) + // +-always @(dcr0 or dcpu_cycstb_i) +- case (dcr0[`OR1200_DU_DCR_CT]) // synopsys parallel_case ++always @(dcr0 or dcpu_cycstb_i or dcpu_we_i) ++ case (dcr0[`OR1200_DU_DCR_CT]) // synopsys parallel_case + 3'b000: match_cond0_stb = 1'b0; //comparison disabled + 3'b001: match_cond0_stb = 1'b1; // insn fetch EA +- default:match_cond0_stb = dcpu_cycstb_i; // any load/store ++ 3'b010: match_cond0_stb = (dcpu_cycstb_i & (~dcpu_we_i)); // data load addr ++ 3'b011: match_cond0_stb = (dcpu_cycstb_i & dcpu_we_i); // data store addr ++ 3'b100: match_cond0_stb = (dcpu_cycstb_i & (~dcpu_we_i)); // data load val ++ 3'b101: match_cond0_stb = (dcpu_cycstb_i & dcpu_we_i); // data store val ++ default: match_cond0_stb = dcpu_cycstb_i; // any load/store + endcase + + // +@@ -1105,33 +1149,32 @@ always @(match_cond0_stb or dcr0 or dvr0 + 4'b1_000, + 4'b1_111: match0 = 1'b0; + 4'b1_001: match0 = +- ((match_cond0_ct[31] ^ dcr0[`OR1200_DU_DCR_SC]) == +- (dvr0[31] ^ dcr0[`OR1200_DU_DCR_SC])); ++ (match_cond0_ct == dvr0); + 4'b1_010: match0 = +- ((match_cond0_ct[31] ^ dcr0[`OR1200_DU_DCR_SC]) < +- (dvr0[31] ^ dcr0[`OR1200_DU_DCR_SC])); ++ ({(match_cond0_ct[31] ^ dcr0[`OR1200_DU_DCR_SC]), match_cond0_ct[30:0]} < ++ {(dvr0[31] ^ dcr0[`OR1200_DU_DCR_SC]), dvr0[30:0]} ); + 4'b1_011: match0 = +- ((match_cond0_ct[31] ^ dcr0[`OR1200_DU_DCR_SC]) <= +- (dvr0[31] ^ dcr0[`OR1200_DU_DCR_SC])); ++ ({(match_cond0_ct[31] ^ dcr0[`OR1200_DU_DCR_SC]), match_cond0_ct[30:0]} <= ++ {(dvr0[31] ^ dcr0[`OR1200_DU_DCR_SC]), dvr0[30:0]} ); + 4'b1_100: match0 = +- ((match_cond0_ct[31] ^ dcr0[`OR1200_DU_DCR_SC]) > +- (dvr0[31] ^ dcr0[`OR1200_DU_DCR_SC])); ++ ({(match_cond0_ct[31] ^ dcr0[`OR1200_DU_DCR_SC]), match_cond0_ct[30:0]} > ++ {(dvr0[31] ^ dcr0[`OR1200_DU_DCR_SC]), dvr0[30:0]} ); + 4'b1_101: match0 = +- ((match_cond0_ct[31] ^ dcr0[`OR1200_DU_DCR_SC]) >= +- (dvr0[31] ^ dcr0[`OR1200_DU_DCR_SC])); ++ ({(match_cond0_ct[31] ^ dcr0[`OR1200_DU_DCR_SC]), match_cond0_ct[30:0]} >= ++ {(dvr0[31] ^ dcr0[`OR1200_DU_DCR_SC]), dvr0[30:0]} ); + 4'b1_110: match0 = +- ((match_cond0_ct[31] ^ dcr0[`OR1200_DU_DCR_SC]) != +- (dvr0[31] ^ dcr0[`OR1200_DU_DCR_SC])); ++ (match_cond0_ct != dvr0); + endcase + ++ + // + // Watchpoint 0 + // +-always @(dmr1 or match0) ++always @(dmr1 or match0 or dbg_ewt_i) + case (dmr1[`OR1200_DU_DMR1_CW0]) + 2'b00: wp[0] = match0; +- 2'b01: wp[0] = match0; +- 2'b10: wp[0] = match0; ++ 2'b01: wp[0] = match0 & dbg_ewt_i; ++ 2'b10: wp[0] = match0 | dbg_ewt_i; + 2'b11: wp[0] = 1'b0; + endcase + +@@ -1141,23 +1184,50 @@ always @(dmr1 or match0) + always @(dcr1 or id_pc or dcpu_adr_i or dcpu_dat_dc + or dcpu_dat_lsu or dcpu_we_i) + case (dcr1[`OR1200_DU_DCR_CT]) // synopsys parallel_case +- 3'b001: match_cond1_ct = id_pc; // insn fetch EA +- 3'b010: match_cond1_ct = dcpu_adr_i; // load EA +- 3'b011: match_cond1_ct = dcpu_adr_i; // store EA +- 3'b100: match_cond1_ct = dcpu_dat_dc; // load data +- 3'b101: match_cond1_ct = dcpu_dat_lsu; // store data +- 3'b110: match_cond1_ct = dcpu_adr_i; // load/store EA +- default:match_cond1_ct = dcpu_we_i ? dcpu_dat_lsu : dcpu_dat_dc; +- endcase ++ 3'b001: match_cond1_tmp = id_pc; // insn fetch EA ++ 3'b010: match_cond1_tmp = dcpu_adr_i; // load EA ++ 3'b011: match_cond1_tmp = dcpu_adr_i; // store EA ++ 3'b100: match_cond1_tmp = dcpu_dat_dc; // load data ++ 3'b101: match_cond1_tmp = dcpu_dat_lsu; // store data ++ 3'b110: match_cond1_tmp = dcpu_adr_i; // load/store EA ++ default:match_cond1_tmp = dcpu_we_i ? dcpu_dat_lsu : dcpu_dat_dc; ++ endcase ++ ++// Transparently handle 8/16/32 bit bus accesses (Match Condition 1) ++// For addresses, leave unchanged ++// for 32-bit data, leave unchanged ++// for 8- or 16-bit data, move the active byte lane(s) to the LSB position ++// This will allow the value to be compared to the LSB(s) of the DVR ++always @(match_cond1_tmp or dcr1 or dcpu_be_i) ++ case (dcr1[`OR1200_DU_DCR_CT]) // synopsys parallel_case ++ 3'b100, ++ 3'b101, ++ 3'b111: begin // We're comparing to data ++ case (dcpu_be_i) ++ 4'b1000: match_cond1_ct = { {24{dcr1[`OR1200_DU_DCR_SC] & match_cond1_tmp[31]}}, match_cond1_tmp[31:24]}; ++ 4'b0100: match_cond1_ct = { {24{dcr1[`OR1200_DU_DCR_SC] & match_cond1_tmp[23]}}, match_cond1_tmp[23:16]}; ++ 4'b0010: match_cond1_ct = { {24{dcr1[`OR1200_DU_DCR_SC] & match_cond1_tmp[15]}}, match_cond1_tmp[15:8]}; ++ 4'b0001: match_cond1_ct = { {24{dcr1[`OR1200_DU_DCR_SC] & match_cond1_tmp[7] }}, match_cond1_tmp[7:0]}; ++ 4'b1100: match_cond1_ct = { {16{dcr1[`OR1200_DU_DCR_SC] & match_cond1_tmp[31]}}, match_cond1_tmp[31:16]}; ++ 4'b0011: match_cond1_ct = { {16{dcr1[`OR1200_DU_DCR_SC] & match_cond1_tmp[15]}}, match_cond1_tmp[15:0]}; ++ default: match_cond1_ct = match_cond1_tmp; ++ endcase ++ end ++ default: match_cond1_ct = match_cond1_tmp; // We're comparing an address ++ endcase + + // + // When To Compare (Match Condition 1) + // +-always @(dcr1 or dcpu_cycstb_i) +- case (dcr1[`OR1200_DU_DCR_CT]) // synopsys parallel_case ++always @(dcr1 or dcpu_cycstb_i or dcpu_we_i) ++ case (dcr1[`OR1200_DU_DCR_CT]) // synopsys parallel_case + 3'b000: match_cond1_stb = 1'b0; //comparison disabled + 3'b001: match_cond1_stb = 1'b1; // insn fetch EA +- default:match_cond1_stb = dcpu_cycstb_i; // any load/store ++ 3'b010: match_cond1_stb = (dcpu_cycstb_i & (~dcpu_we_i)); // data load addr ++ 3'b011: match_cond1_stb = (dcpu_cycstb_i & dcpu_we_i); // data store addr ++ 3'b100: match_cond1_stb = (dcpu_cycstb_i & (~dcpu_we_i)); // data load val ++ 3'b101: match_cond1_stb = (dcpu_cycstb_i & dcpu_we_i); // data store val ++ default: match_cond1_stb = dcpu_cycstb_i; // any load/store + endcase + + // +@@ -1169,23 +1239,21 @@ always @(match_cond1_stb or dcr1 or dvr1 + 4'b1_000, + 4'b1_111: match1 = 1'b0; + 4'b1_001: match1 = +- ((match_cond1_ct[31] ^ dcr1[`OR1200_DU_DCR_SC]) == +- (dvr1[31] ^ dcr1[`OR1200_DU_DCR_SC])); ++ (match_cond1_ct == dvr1); + 4'b1_010: match1 = +- ((match_cond1_ct[31] ^ dcr1[`OR1200_DU_DCR_SC]) < +- (dvr1[31] ^ dcr1[`OR1200_DU_DCR_SC])); ++ ({(match_cond1_ct[31] ^ dcr1[`OR1200_DU_DCR_SC]), match_cond1_ct[30:0]} < ++ {(dvr1[31] ^ dcr1[`OR1200_DU_DCR_SC]), dvr1[30:0]} ); + 4'b1_011: match1 = +- ((match_cond1_ct[31] ^ dcr1[`OR1200_DU_DCR_SC]) <= +- (dvr1[31] ^ dcr1[`OR1200_DU_DCR_SC])); ++ ({(match_cond1_ct[31] ^ dcr1[`OR1200_DU_DCR_SC]), match_cond1_ct[30:0]} <= ++ {(dvr1[31] ^ dcr1[`OR1200_DU_DCR_SC]), dvr1[30:0]} ); + 4'b1_100: match1 = +- ((match_cond1_ct[31] ^ dcr1[`OR1200_DU_DCR_SC]) > +- (dvr1[31] ^ dcr1[`OR1200_DU_DCR_SC])); ++ ({(match_cond1_ct[31] ^ dcr1[`OR1200_DU_DCR_SC]), match_cond1_ct[30:0]} > ++ {(dvr1[31] ^ dcr1[`OR1200_DU_DCR_SC]), dvr1[30:0]} ); + 4'b1_101: match1 = +- ((match_cond1_ct[31] ^ dcr1[`OR1200_DU_DCR_SC]) >= +- (dvr1[31] ^ dcr1[`OR1200_DU_DCR_SC])); ++ ({(match_cond1_ct[31] ^ dcr1[`OR1200_DU_DCR_SC]), match_cond1_ct[30:0]} >= ++ {(dvr1[31] ^ dcr1[`OR1200_DU_DCR_SC]), dvr1[30:0]} ); + 4'b1_110: match1 = +- ((match_cond1_ct[31] ^ dcr1[`OR1200_DU_DCR_SC]) != +- (dvr1[31] ^ dcr1[`OR1200_DU_DCR_SC])); ++ (match_cond1_ct != dvr1); + endcase + + // +@@ -1199,29 +1267,57 @@ always @(dmr1 or match1 or wp) + 2'b11: wp[1] = 1'b0; + endcase + ++ + // + // Compare To What (Match Condition 2) + // + always @(dcr2 or id_pc or dcpu_adr_i or dcpu_dat_dc + or dcpu_dat_lsu or dcpu_we_i) + case (dcr2[`OR1200_DU_DCR_CT]) // synopsys parallel_case +- 3'b001: match_cond2_ct = id_pc; // insn fetch EA +- 3'b010: match_cond2_ct = dcpu_adr_i; // load EA +- 3'b011: match_cond2_ct = dcpu_adr_i; // store EA +- 3'b100: match_cond2_ct = dcpu_dat_dc; // load data +- 3'b101: match_cond2_ct = dcpu_dat_lsu; // store data +- 3'b110: match_cond2_ct = dcpu_adr_i; // load/store EA +- default:match_cond2_ct = dcpu_we_i ? dcpu_dat_lsu : dcpu_dat_dc; +- endcase ++ 3'b001: match_cond2_tmp = id_pc; // insn fetch EA ++ 3'b010: match_cond2_tmp = dcpu_adr_i; // load EA ++ 3'b011: match_cond2_tmp = dcpu_adr_i; // store EA ++ 3'b100: match_cond2_tmp = dcpu_dat_dc; // load data ++ 3'b101: match_cond2_tmp = dcpu_dat_lsu; // store data ++ 3'b110: match_cond2_tmp = dcpu_adr_i; // load/store EA ++ default:match_cond2_tmp = dcpu_we_i ? dcpu_dat_lsu : dcpu_dat_dc; ++ endcase ++ ++// Transparently handle 8/16/32 bit bus accesses (Match Condition 2) ++// For addresses, leave unchanged ++// for 32-bit data, leave unchanged ++// for 8- or 16-bit data, move the active byte lane(s) to the LSB position ++// This will allow the value to be compared to the LSB(s) of the DVR ++always @(match_cond2_tmp or dcr2 or dcpu_be_i) ++ case (dcr2[`OR1200_DU_DCR_CT]) // synopsys parallel_case ++ 3'b100, ++ 3'b101, ++ 3'b111: begin // We're comparing to data ++ case (dcpu_be_i) ++ 4'b1000: match_cond2_ct = { {24{dcr2[`OR1200_DU_DCR_SC] & match_cond2_tmp[31]}}, match_cond2_tmp[31:24]}; ++ 4'b0100: match_cond2_ct = { {24{dcr2[`OR1200_DU_DCR_SC] & match_cond2_tmp[23]}}, match_cond2_tmp[23:16]}; ++ 4'b0010: match_cond2_ct = { {24{dcr2[`OR1200_DU_DCR_SC] & match_cond2_tmp[15]}}, match_cond2_tmp[15:8]}; ++ 4'b0001: match_cond2_ct = { {24{dcr2[`OR1200_DU_DCR_SC] & match_cond2_tmp[7] }}, match_cond2_tmp[7:0]}; ++ 4'b1100: match_cond2_ct = { {16{dcr2[`OR1200_DU_DCR_SC] & match_cond2_tmp[31]}}, match_cond2_tmp[31:16]}; ++ 4'b0011: match_cond2_ct = { {16{dcr2[`OR1200_DU_DCR_SC] & match_cond2_tmp[15]}}, match_cond2_tmp[15:0]}; ++ default: match_cond2_ct = match_cond2_tmp; ++ endcase ++ end ++ default: match_cond2_ct = match_cond2_tmp; // We're comparing an address ++ endcase + + // + // When To Compare (Match Condition 2) + // +-always @(dcr2 or dcpu_cycstb_i) +- case (dcr2[`OR1200_DU_DCR_CT]) // synopsys parallel_case ++always @(dcr2 or dcpu_cycstb_i or dcpu_we_i) ++ case (dcr2[`OR1200_DU_DCR_CT]) // synopsys parallel_case + 3'b000: match_cond2_stb = 1'b0; //comparison disabled + 3'b001: match_cond2_stb = 1'b1; // insn fetch EA +- default:match_cond2_stb = dcpu_cycstb_i; // any load/store ++ 3'b010: match_cond2_stb = (dcpu_cycstb_i & (~dcpu_we_i)); // data load addr ++ 3'b011: match_cond2_stb = (dcpu_cycstb_i & dcpu_we_i); // data store addr ++ 3'b100: match_cond2_stb = (dcpu_cycstb_i & (~dcpu_we_i)); // data load val ++ 3'b101: match_cond2_stb = (dcpu_cycstb_i & dcpu_we_i); // data store val ++ default: match_cond2_stb = dcpu_cycstb_i; // any load/store + endcase + + // +@@ -1233,23 +1329,21 @@ always @(match_cond2_stb or dcr2 or dvr2 + 4'b1_000, + 4'b1_111: match2 = 1'b0; + 4'b1_001: match2 = +- ((match_cond2_ct[31] ^ dcr2[`OR1200_DU_DCR_SC]) == +- (dvr2[31] ^ dcr2[`OR1200_DU_DCR_SC])); ++ (match_cond2_ct == dvr2); + 4'b1_010: match2 = +- ((match_cond2_ct[31] ^ dcr2[`OR1200_DU_DCR_SC]) < +- (dvr2[31] ^ dcr2[`OR1200_DU_DCR_SC])); ++ ({(match_cond2_ct[31] ^ dcr2[`OR1200_DU_DCR_SC]), match_cond2_ct[30:0]} < ++ {(dvr2[31] ^ dcr2[`OR1200_DU_DCR_SC]), dvr2[30:0]} ); + 4'b1_011: match2 = +- ((match_cond2_ct[31] ^ dcr2[`OR1200_DU_DCR_SC]) <= +- (dvr2[31] ^ dcr2[`OR1200_DU_DCR_SC])); ++ ({(match_cond2_ct[31] ^ dcr2[`OR1200_DU_DCR_SC]), match_cond2_ct[30:0]} <= ++ {(dvr2[31] ^ dcr2[`OR1200_DU_DCR_SC]), dvr2[30:0]} ); + 4'b1_100: match2 = +- ((match_cond2_ct[31] ^ dcr2[`OR1200_DU_DCR_SC]) > +- (dvr2[31] ^ dcr2[`OR1200_DU_DCR_SC])); ++ ({(match_cond2_ct[31] ^ dcr2[`OR1200_DU_DCR_SC]), match_cond2_ct[30:0]} > ++ {(dvr2[31] ^ dcr2[`OR1200_DU_DCR_SC]), dvr2[30:0]} ); + 4'b1_101: match2 = +- ((match_cond2_ct[31] ^ dcr2[`OR1200_DU_DCR_SC]) >= +- (dvr2[31] ^ dcr2[`OR1200_DU_DCR_SC])); ++ ({(match_cond2_ct[31] ^ dcr2[`OR1200_DU_DCR_SC]), match_cond2_ct[30:0]} >= ++ {(dvr2[31] ^ dcr2[`OR1200_DU_DCR_SC]), dvr2[30:0]} ); + 4'b1_110: match2 = +- ((match_cond2_ct[31] ^ dcr2[`OR1200_DU_DCR_SC]) != +- (dvr2[31] ^ dcr2[`OR1200_DU_DCR_SC])); ++ (match_cond2_ct != dvr2); + endcase + + // +@@ -1263,29 +1357,57 @@ always @(dmr1 or match2 or wp) + 2'b11: wp[2] = 1'b0; + endcase + ++ + // + // Compare To What (Match Condition 3) + // + always @(dcr3 or id_pc or dcpu_adr_i or dcpu_dat_dc + or dcpu_dat_lsu or dcpu_we_i) + case (dcr3[`OR1200_DU_DCR_CT]) // synopsys parallel_case +- 3'b001: match_cond3_ct = id_pc; // insn fetch EA +- 3'b010: match_cond3_ct = dcpu_adr_i; // load EA +- 3'b011: match_cond3_ct = dcpu_adr_i; // store EA +- 3'b100: match_cond3_ct = dcpu_dat_dc; // load data +- 3'b101: match_cond3_ct = dcpu_dat_lsu; // store data +- 3'b110: match_cond3_ct = dcpu_adr_i; // load/store EA +- default:match_cond3_ct = dcpu_we_i ? dcpu_dat_lsu : dcpu_dat_dc; +- endcase ++ 3'b001: match_cond3_tmp = id_pc; // insn fetch EA ++ 3'b010: match_cond3_tmp = dcpu_adr_i; // load EA ++ 3'b011: match_cond3_tmp = dcpu_adr_i; // store EA ++ 3'b100: match_cond3_tmp = dcpu_dat_dc; // load data ++ 3'b101: match_cond3_tmp = dcpu_dat_lsu; // store data ++ 3'b110: match_cond3_tmp = dcpu_adr_i; // load/store EA ++ default:match_cond3_tmp = dcpu_we_i ? dcpu_dat_lsu : dcpu_dat_dc; ++ endcase ++ ++// Transparently handle 8/16/32 bit bus accesses (Match Condition 3) ++// For addresses, leave unchanged ++// for 32-bit data, leave unchanged ++// for 8- or 16-bit data, move the active byte lane(s) to the LSB position ++// This will allow the value to be compared to the LSB(s) of the DVR ++always @(match_cond3_tmp or dcr3 or dcpu_be_i) ++ case (dcr3[`OR1200_DU_DCR_CT]) // synopsys parallel_case ++ 3'b100, ++ 3'b101, ++ 3'b111: begin // We're comparing to data ++ case (dcpu_be_i) ++ 4'b1000: match_cond3_ct = { {24{dcr3[`OR1200_DU_DCR_SC] & match_cond3_tmp[31]}}, match_cond3_tmp[31:24]}; ++ 4'b0100: match_cond3_ct = { {24{dcr3[`OR1200_DU_DCR_SC] & match_cond3_tmp[23]}}, match_cond3_tmp[23:16]}; ++ 4'b0010: match_cond3_ct = { {24{dcr3[`OR1200_DU_DCR_SC] & match_cond3_tmp[15]}}, match_cond3_tmp[15:8]}; ++ 4'b0001: match_cond3_ct = { {24{dcr3[`OR1200_DU_DCR_SC] & match_cond3_tmp[7] }}, match_cond3_tmp[7:0]}; ++ 4'b1100: match_cond3_ct = { {16{dcr3[`OR1200_DU_DCR_SC] & match_cond3_tmp[31]}}, match_cond3_tmp[31:16]}; ++ 4'b0011: match_cond3_ct = { {16{dcr3[`OR1200_DU_DCR_SC] & match_cond3_tmp[15]}}, match_cond3_tmp[15:0]}; ++ default: match_cond3_ct = match_cond3_tmp; ++ endcase ++ end ++ default: match_cond3_ct = match_cond3_tmp; // We're comparing an address ++ endcase + + // + // When To Compare (Match Condition 3) + // +-always @(dcr3 or dcpu_cycstb_i) +- case (dcr3[`OR1200_DU_DCR_CT]) // synopsys parallel_case ++always @(dcr3 or dcpu_cycstb_i or dcpu_we_i) ++ case (dcr3[`OR1200_DU_DCR_CT]) // synopsys parallel_case + 3'b000: match_cond3_stb = 1'b0; //comparison disabled + 3'b001: match_cond3_stb = 1'b1; // insn fetch EA +- default:match_cond3_stb = dcpu_cycstb_i; // any load/store ++ 3'b010: match_cond3_stb = (dcpu_cycstb_i & (~dcpu_we_i)); // data load addr ++ 3'b011: match_cond3_stb = (dcpu_cycstb_i & dcpu_we_i); // data store addr ++ 3'b100: match_cond3_stb = (dcpu_cycstb_i & (~dcpu_we_i)); // data load val ++ 3'b101: match_cond3_stb = (dcpu_cycstb_i & dcpu_we_i); // data store val ++ default: match_cond3_stb = dcpu_cycstb_i; // any load/store + endcase + + // +@@ -1297,23 +1419,21 @@ always @(match_cond3_stb or dcr3 or dvr3 + 4'b1_000, + 4'b1_111: match3 = 1'b0; + 4'b1_001: match3 = +- ((match_cond3_ct[31] ^ dcr3[`OR1200_DU_DCR_SC]) == +- (dvr3[31] ^ dcr3[`OR1200_DU_DCR_SC])); ++ (match_cond3_ct == dvr3); + 4'b1_010: match3 = +- ((match_cond3_ct[31] ^ dcr3[`OR1200_DU_DCR_SC]) < +- (dvr3[31] ^ dcr3[`OR1200_DU_DCR_SC])); ++ ({(match_cond3_ct[31] ^ dcr3[`OR1200_DU_DCR_SC]), match_cond3_ct[30:0]} < ++ {(dvr3[31] ^ dcr3[`OR1200_DU_DCR_SC]), dvr3[30:0]} ); + 4'b1_011: match3 = +- ((match_cond3_ct[31] ^ dcr3[`OR1200_DU_DCR_SC]) <= +- (dvr3[31] ^ dcr3[`OR1200_DU_DCR_SC])); ++ ({(match_cond3_ct[31] ^ dcr3[`OR1200_DU_DCR_SC]), match_cond3_ct[30:0]} <= ++ {(dvr3[31] ^ dcr3[`OR1200_DU_DCR_SC]), dvr3[30:0]} ); + 4'b1_100: match3 = +- ((match_cond3_ct[31] ^ dcr3[`OR1200_DU_DCR_SC]) > +- (dvr3[31] ^ dcr3[`OR1200_DU_DCR_SC])); ++ ({(match_cond3_ct[31] ^ dcr3[`OR1200_DU_DCR_SC]), match_cond3_ct[30:0]} > ++ {(dvr3[31] ^ dcr3[`OR1200_DU_DCR_SC]), dvr3[30:0]} ); + 4'b1_101: match3 = +- ((match_cond3_ct[31] ^ dcr3[`OR1200_DU_DCR_SC]) >= +- (dvr3[31] ^ dcr3[`OR1200_DU_DCR_SC])); ++ ({(match_cond3_ct[31] ^ dcr3[`OR1200_DU_DCR_SC]), match_cond3_ct[30:0]} >= ++ {(dvr3[31] ^ dcr3[`OR1200_DU_DCR_SC]), dvr3[30:0]} ); + 4'b1_110: match3 = +- ((match_cond3_ct[31] ^ dcr3[`OR1200_DU_DCR_SC]) != +- (dvr3[31] ^ dcr3[`OR1200_DU_DCR_SC])); ++ (match_cond3_ct != dvr3); + endcase + + // +@@ -1327,29 +1447,57 @@ always @(dmr1 or match3 or wp) + 2'b11: wp[3] = 1'b0; + endcase + ++ + // + // Compare To What (Match Condition 4) + // + always @(dcr4 or id_pc or dcpu_adr_i or dcpu_dat_dc + or dcpu_dat_lsu or dcpu_we_i) + case (dcr4[`OR1200_DU_DCR_CT]) // synopsys parallel_case +- 3'b001: match_cond4_ct = id_pc; // insn fetch EA +- 3'b010: match_cond4_ct = dcpu_adr_i; // load EA +- 3'b011: match_cond4_ct = dcpu_adr_i; // store EA +- 3'b100: match_cond4_ct = dcpu_dat_dc; // load data +- 3'b101: match_cond4_ct = dcpu_dat_lsu; // store data +- 3'b110: match_cond4_ct = dcpu_adr_i; // load/store EA +- default:match_cond4_ct = dcpu_we_i ? dcpu_dat_lsu : dcpu_dat_dc; +- endcase ++ 3'b001: match_cond4_tmp = id_pc; // insn fetch EA ++ 3'b010: match_cond4_tmp = dcpu_adr_i; // load EA ++ 3'b011: match_cond4_tmp = dcpu_adr_i; // store EA ++ 3'b100: match_cond4_tmp = dcpu_dat_dc; // load data ++ 3'b101: match_cond4_tmp = dcpu_dat_lsu; // store data ++ 3'b110: match_cond4_tmp = dcpu_adr_i; // load/store EA ++ default:match_cond4_tmp = dcpu_we_i ? dcpu_dat_lsu : dcpu_dat_dc; ++ endcase ++ ++// Transparently handle 8/16/32 bit bus accesses (Match Condition 4) ++// For addresses, leave unchanged ++// for 32-bit data, leave unchanged ++// for 8- or 16-bit data, move the active byte lane(s) to the LSB position ++// This will allow the value to be compared to the LSB(s) of the DVR ++always @(match_cond4_tmp or dcr4 or dcpu_be_i) ++ case (dcr4[`OR1200_DU_DCR_CT]) // synopsys parallel_case ++ 3'b100, ++ 3'b101, ++ 3'b111: begin // We're comparing to data ++ case (dcpu_be_i) ++ 4'b1000: match_cond4_ct = { {24{dcr4[`OR1200_DU_DCR_SC] & match_cond4_tmp[31]}}, match_cond4_tmp[31:24]}; ++ 4'b0100: match_cond4_ct = { {24{dcr4[`OR1200_DU_DCR_SC] & match_cond4_tmp[23]}}, match_cond4_tmp[23:16]}; ++ 4'b0010: match_cond4_ct = { {24{dcr4[`OR1200_DU_DCR_SC] & match_cond4_tmp[15]}}, match_cond4_tmp[15:8]}; ++ 4'b0001: match_cond4_ct = { {24{dcr4[`OR1200_DU_DCR_SC] & match_cond4_tmp[7] }}, match_cond4_tmp[7:0]}; ++ 4'b1100: match_cond4_ct = { {16{dcr4[`OR1200_DU_DCR_SC] & match_cond4_tmp[31]}}, match_cond4_tmp[31:16]}; ++ 4'b0011: match_cond4_ct = { {16{dcr4[`OR1200_DU_DCR_SC] & match_cond4_tmp[15]}}, match_cond4_tmp[15:0]}; ++ default: match_cond4_ct = match_cond4_tmp; ++ endcase ++ end ++ default: match_cond4_ct = match_cond4_tmp; // We're comparing an address ++ endcase + + // + // When To Compare (Match Condition 4) + // +-always @(dcr4 or dcpu_cycstb_i) +- case (dcr4[`OR1200_DU_DCR_CT]) // synopsys parallel_case ++always @(dcr4 or dcpu_cycstb_i or dcpu_we_i) ++ case (dcr4[`OR1200_DU_DCR_CT]) // synopsys parallel_case + 3'b000: match_cond4_stb = 1'b0; //comparison disabled + 3'b001: match_cond4_stb = 1'b1; // insn fetch EA +- default:match_cond4_stb = dcpu_cycstb_i; // any load/store ++ 3'b010: match_cond4_stb = (dcpu_cycstb_i & (~dcpu_we_i)); // data load addr ++ 3'b011: match_cond4_stb = (dcpu_cycstb_i & dcpu_we_i); // data store addr ++ 3'b100: match_cond4_stb = (dcpu_cycstb_i & (~dcpu_we_i)); // data load val ++ 3'b101: match_cond4_stb = (dcpu_cycstb_i & dcpu_we_i); // data store val ++ default: match_cond4_stb = dcpu_cycstb_i; // any load/store + endcase + + // +@@ -1361,23 +1509,21 @@ always @(match_cond4_stb or dcr4 or dvr4 + 4'b1_000, + 4'b1_111: match4 = 1'b0; + 4'b1_001: match4 = +- ((match_cond4_ct[31] ^ dcr4[`OR1200_DU_DCR_SC]) == +- (dvr4[31] ^ dcr4[`OR1200_DU_DCR_SC])); ++ (match_cond4_ct == dvr4); + 4'b1_010: match4 = +- ((match_cond4_ct[31] ^ dcr4[`OR1200_DU_DCR_SC]) < +- (dvr4[31] ^ dcr4[`OR1200_DU_DCR_SC])); ++ ({(match_cond4_ct[31] ^ dcr4[`OR1200_DU_DCR_SC]), match_cond4_ct[30:0]} < ++ {(dvr4[31] ^ dcr4[`OR1200_DU_DCR_SC]), dvr4[30:0]} ); + 4'b1_011: match4 = +- ((match_cond4_ct[31] ^ dcr4[`OR1200_DU_DCR_SC]) <= +- (dvr4[31] ^ dcr4[`OR1200_DU_DCR_SC])); ++ ({(match_cond4_ct[31] ^ dcr4[`OR1200_DU_DCR_SC]), match_cond4_ct[30:0]} <= ++ {(dvr4[31] ^ dcr4[`OR1200_DU_DCR_SC]), dvr4[30:0]} ); + 4'b1_100: match4 = +- ((match_cond4_ct[31] ^ dcr4[`OR1200_DU_DCR_SC]) > +- (dvr4[31] ^ dcr4[`OR1200_DU_DCR_SC])); ++ ({(match_cond4_ct[31] ^ dcr4[`OR1200_DU_DCR_SC]), match_cond4_ct[30:0]} > ++ {(dvr4[31] ^ dcr4[`OR1200_DU_DCR_SC]), dvr4[30:0]} ); + 4'b1_101: match4 = +- ((match_cond4_ct[31] ^ dcr4[`OR1200_DU_DCR_SC]) >= +- (dvr4[31] ^ dcr4[`OR1200_DU_DCR_SC])); ++ ({(match_cond4_ct[31] ^ dcr4[`OR1200_DU_DCR_SC]), match_cond4_ct[30:0]} >= ++ {(dvr4[31] ^ dcr4[`OR1200_DU_DCR_SC]), dvr4[30:0]} ); + 4'b1_110: match4 = +- ((match_cond4_ct[31] ^ dcr4[`OR1200_DU_DCR_SC]) != +- (dvr4[31] ^ dcr4[`OR1200_DU_DCR_SC])); ++ (match_cond4_ct != dvr4); + endcase + + // +@@ -1391,29 +1537,57 @@ always @(dmr1 or match4 or wp) + 2'b11: wp[4] = 1'b0; + endcase + ++ + // + // Compare To What (Match Condition 5) + // + always @(dcr5 or id_pc or dcpu_adr_i or dcpu_dat_dc + or dcpu_dat_lsu or dcpu_we_i) + case (dcr5[`OR1200_DU_DCR_CT]) // synopsys parallel_case +- 3'b001: match_cond5_ct = id_pc; // insn fetch EA +- 3'b010: match_cond5_ct = dcpu_adr_i; // load EA +- 3'b011: match_cond5_ct = dcpu_adr_i; // store EA +- 3'b100: match_cond5_ct = dcpu_dat_dc; // load data +- 3'b101: match_cond5_ct = dcpu_dat_lsu; // store data +- 3'b110: match_cond5_ct = dcpu_adr_i; // load/store EA +- default:match_cond5_ct = dcpu_we_i ? dcpu_dat_lsu : dcpu_dat_dc; +- endcase ++ 3'b001: match_cond5_tmp = id_pc; // insn fetch EA ++ 3'b010: match_cond5_tmp = dcpu_adr_i; // load EA ++ 3'b011: match_cond5_tmp = dcpu_adr_i; // store EA ++ 3'b100: match_cond5_tmp = dcpu_dat_dc; // load data ++ 3'b101: match_cond5_tmp = dcpu_dat_lsu; // store data ++ 3'b110: match_cond5_tmp = dcpu_adr_i; // load/store EA ++ default:match_cond5_tmp = dcpu_we_i ? dcpu_dat_lsu : dcpu_dat_dc; ++ endcase ++ ++// Transparently handle 8/16/32 bit bus accesses (Match Condition 5) ++// For addresses, leave unchanged ++// for 32-bit data, leave unchanged ++// for 8- or 16-bit data, move the active byte lane(s) to the LSB position ++// This will allow the value to be compared to the LSB(s) of the DVR ++always @(match_cond5_tmp or dcr5 or dcpu_be_i) ++ case (dcr5[`OR1200_DU_DCR_CT]) // synopsys parallel_case ++ 3'b100, ++ 3'b101, ++ 3'b111: begin // We're comparing to data ++ case (dcpu_be_i) ++ 4'b1000: match_cond5_ct = { {24{dcr5[`OR1200_DU_DCR_SC] & match_cond5_tmp[31]}}, match_cond5_tmp[31:24]}; ++ 4'b0100: match_cond5_ct = { {24{dcr5[`OR1200_DU_DCR_SC] & match_cond5_tmp[23]}}, match_cond5_tmp[23:16]}; ++ 4'b0010: match_cond5_ct = { {24{dcr5[`OR1200_DU_DCR_SC] & match_cond5_tmp[15]}}, match_cond5_tmp[15:8]}; ++ 4'b0001: match_cond5_ct = { {24{dcr5[`OR1200_DU_DCR_SC] & match_cond5_tmp[7] }}, match_cond5_tmp[7:0]}; ++ 4'b1100: match_cond5_ct = { {16{dcr5[`OR1200_DU_DCR_SC] & match_cond5_tmp[31]}}, match_cond5_tmp[31:16]}; ++ 4'b0011: match_cond5_ct = { {16{dcr5[`OR1200_DU_DCR_SC] & match_cond5_tmp[15]}}, match_cond5_tmp[15:0]}; ++ default: match_cond5_ct = match_cond5_tmp; ++ endcase ++ end ++ default: match_cond5_ct = match_cond5_tmp; // We're comparing an address ++ endcase + + // + // When To Compare (Match Condition 5) + // +-always @(dcr5 or dcpu_cycstb_i) +- case (dcr5[`OR1200_DU_DCR_CT]) // synopsys parallel_case ++always @(dcr5 or dcpu_cycstb_i or dcpu_we_i) ++ case (dcr5[`OR1200_DU_DCR_CT]) // synopsys parallel_case + 3'b000: match_cond5_stb = 1'b0; //comparison disabled + 3'b001: match_cond5_stb = 1'b1; // insn fetch EA +- default:match_cond5_stb = dcpu_cycstb_i; // any load/store ++ 3'b010: match_cond5_stb = (dcpu_cycstb_i & (~dcpu_we_i)); // data load addr ++ 3'b011: match_cond5_stb = (dcpu_cycstb_i & dcpu_we_i); // data store addr ++ 3'b100: match_cond5_stb = (dcpu_cycstb_i & (~dcpu_we_i)); // data load val ++ 3'b101: match_cond5_stb = (dcpu_cycstb_i & dcpu_we_i); // data store val ++ default: match_cond5_stb = dcpu_cycstb_i; // any load/store + endcase + + // +@@ -1425,23 +1599,21 @@ always @(match_cond5_stb or dcr5 or dvr5 + 4'b1_000, + 4'b1_111: match5 = 1'b0; + 4'b1_001: match5 = +- ((match_cond5_ct[31] ^ dcr5[`OR1200_DU_DCR_SC]) == +- (dvr5[31] ^ dcr5[`OR1200_DU_DCR_SC])); ++ (match_cond5_ct == dvr5); + 4'b1_010: match5 = +- ((match_cond5_ct[31] ^ dcr5[`OR1200_DU_DCR_SC]) < +- (dvr5[31] ^ dcr5[`OR1200_DU_DCR_SC])); ++ ({(match_cond5_ct[31] ^ dcr5[`OR1200_DU_DCR_SC]), match_cond5_ct[30:0]} < ++ {(dvr5[31] ^ dcr5[`OR1200_DU_DCR_SC]), dvr5[30:0]} ); + 4'b1_011: match5 = +- ((match_cond5_ct[31] ^ dcr5[`OR1200_DU_DCR_SC]) <= +- (dvr5[31] ^ dcr5[`OR1200_DU_DCR_SC])); ++ ({(match_cond5_ct[31] ^ dcr5[`OR1200_DU_DCR_SC]), match_cond5_ct[30:0]} <= ++ {(dvr5[31] ^ dcr5[`OR1200_DU_DCR_SC]), dvr5[30:0]} ); + 4'b1_100: match5 = +- ((match_cond5_ct[31] ^ dcr5[`OR1200_DU_DCR_SC]) > +- (dvr5[31] ^ dcr5[`OR1200_DU_DCR_SC])); ++ ({(match_cond5_ct[31] ^ dcr5[`OR1200_DU_DCR_SC]), match_cond5_ct[30:0]} > ++ {(dvr5[31] ^ dcr5[`OR1200_DU_DCR_SC]), dvr5[30:0]} ); + 4'b1_101: match5 = +- ((match_cond5_ct[31] ^ dcr5[`OR1200_DU_DCR_SC]) >= +- (dvr5[31] ^ dcr5[`OR1200_DU_DCR_SC])); ++ ({(match_cond5_ct[31] ^ dcr5[`OR1200_DU_DCR_SC]), match_cond5_ct[30:0]} >= ++ {(dvr5[31] ^ dcr5[`OR1200_DU_DCR_SC]), dvr5[30:0]} ); + 4'b1_110: match5 = +- ((match_cond5_ct[31] ^ dcr5[`OR1200_DU_DCR_SC]) != +- (dvr5[31] ^ dcr5[`OR1200_DU_DCR_SC])); ++ (match_cond5_ct != dvr5); + endcase + + // +@@ -1455,29 +1627,57 @@ always @(dmr1 or match5 or wp) + 2'b11: wp[5] = 1'b0; + endcase + ++ + // + // Compare To What (Match Condition 6) + // + always @(dcr6 or id_pc or dcpu_adr_i or dcpu_dat_dc + or dcpu_dat_lsu or dcpu_we_i) + case (dcr6[`OR1200_DU_DCR_CT]) // synopsys parallel_case +- 3'b001: match_cond6_ct = id_pc; // insn fetch EA +- 3'b010: match_cond6_ct = dcpu_adr_i; // load EA +- 3'b011: match_cond6_ct = dcpu_adr_i; // store EA +- 3'b100: match_cond6_ct = dcpu_dat_dc; // load data +- 3'b101: match_cond6_ct = dcpu_dat_lsu; // store data +- 3'b110: match_cond6_ct = dcpu_adr_i; // load/store EA +- default:match_cond6_ct = dcpu_we_i ? dcpu_dat_lsu : dcpu_dat_dc; +- endcase ++ 3'b001: match_cond6_tmp = id_pc; // insn fetch EA ++ 3'b010: match_cond6_tmp = dcpu_adr_i; // load EA ++ 3'b011: match_cond6_tmp = dcpu_adr_i; // store EA ++ 3'b100: match_cond6_tmp = dcpu_dat_dc; // load data ++ 3'b101: match_cond6_tmp = dcpu_dat_lsu; // store data ++ 3'b110: match_cond6_tmp = dcpu_adr_i; // load/store EA ++ default:match_cond6_tmp = dcpu_we_i ? dcpu_dat_lsu : dcpu_dat_dc; ++ endcase ++ ++// Transparently handle 8/16/32 bit bus accesses: ++// For addresses, leave unchanged ++// for 32-bit data, leave unchanged ++// for 8- or 16-bit data, move the active byte lane(s) to the LSB position ++// This will allow the value to be compared to the LSB(s) of the DVR ++always @(match_cond6_tmp or dcr6 or dcpu_be_i) ++ case (dcr6[`OR1200_DU_DCR_CT]) // synopsys parallel_case ++ 3'b100, ++ 3'b101, ++ 3'b111: begin // We're comparing to data ++ case (dcpu_be_i) ++ 4'b1000: match_cond6_ct = { {24{dcr6[`OR1200_DU_DCR_SC] & match_cond6_tmp[31]}}, match_cond6_tmp[31:24]}; ++ 4'b0100: match_cond6_ct = { {24{dcr6[`OR1200_DU_DCR_SC] & match_cond6_tmp[23]}}, match_cond6_tmp[23:16]}; ++ 4'b0010: match_cond6_ct = { {24{dcr6[`OR1200_DU_DCR_SC] & match_cond6_tmp[15]}}, match_cond6_tmp[15:8]}; ++ 4'b0001: match_cond6_ct = { {24{dcr6[`OR1200_DU_DCR_SC] & match_cond6_tmp[7] }}, match_cond6_tmp[7:0]}; ++ 4'b1100: match_cond6_ct = { {16{dcr6[`OR1200_DU_DCR_SC] & match_cond6_tmp[31]}}, match_cond6_tmp[31:16]}; ++ 4'b0011: match_cond6_ct = { {16{dcr6[`OR1200_DU_DCR_SC] & match_cond6_tmp[15]}}, match_cond6_tmp[15:0]}; ++ default: match_cond6_ct = match_cond6_tmp; ++ endcase ++ end ++ default: match_cond6_ct = match_cond6_tmp; // We're comparing an address ++ endcase + + // + // When To Compare (Match Condition 6) + // +-always @(dcr6 or dcpu_cycstb_i) +- case (dcr6[`OR1200_DU_DCR_CT]) // synopsys parallel_case ++always @(dcr6 or dcpu_cycstb_i or dcpu_we_i) ++ case (dcr6[`OR1200_DU_DCR_CT]) // synopsys parallel_case + 3'b000: match_cond6_stb = 1'b0; //comparison disabled + 3'b001: match_cond6_stb = 1'b1; // insn fetch EA +- default:match_cond6_stb = dcpu_cycstb_i; // any load/store ++ 3'b010: match_cond6_stb = (dcpu_cycstb_i & (~dcpu_we_i)); // data load addr ++ 3'b011: match_cond6_stb = (dcpu_cycstb_i & dcpu_we_i); // data store addr ++ 3'b100: match_cond6_stb = (dcpu_cycstb_i & (~dcpu_we_i)); // data load val ++ 3'b101: match_cond6_stb = (dcpu_cycstb_i & dcpu_we_i); // data store val ++ default: match_cond6_stb = dcpu_cycstb_i; // any load/store + endcase + + // +@@ -1489,23 +1689,21 @@ always @(match_cond6_stb or dcr6 or dvr6 + 4'b1_000, + 4'b1_111: match6 = 1'b0; + 4'b1_001: match6 = +- ((match_cond6_ct[31] ^ dcr6[`OR1200_DU_DCR_SC]) == +- (dvr6[31] ^ dcr6[`OR1200_DU_DCR_SC])); ++ (match_cond6_ct == dvr6); + 4'b1_010: match6 = +- ((match_cond6_ct[31] ^ dcr6[`OR1200_DU_DCR_SC]) < +- (dvr6[31] ^ dcr6[`OR1200_DU_DCR_SC])); ++ ({(match_cond6_ct[31] ^ dcr6[`OR1200_DU_DCR_SC]), match_cond6_ct[30:0]} < ++ {(dvr6[31] ^ dcr6[`OR1200_DU_DCR_SC]), dvr6[30:0]} ); + 4'b1_011: match6 = +- ((match_cond6_ct[31] ^ dcr6[`OR1200_DU_DCR_SC]) <= +- (dvr6[31] ^ dcr6[`OR1200_DU_DCR_SC])); ++ ({(match_cond6_ct[31] ^ dcr6[`OR1200_DU_DCR_SC]), match_cond6_ct[30:0]} <= ++ {(dvr6[31] ^ dcr6[`OR1200_DU_DCR_SC]), dvr6[30:0]} ); + 4'b1_100: match6 = +- ((match_cond6_ct[31] ^ dcr6[`OR1200_DU_DCR_SC]) > +- (dvr6[31] ^ dcr6[`OR1200_DU_DCR_SC])); ++ ({(match_cond6_ct[31] ^ dcr6[`OR1200_DU_DCR_SC]), match_cond6_ct[30:0]} > ++ {(dvr6[31] ^ dcr6[`OR1200_DU_DCR_SC]), dvr6[30:0]} ); + 4'b1_101: match6 = +- ((match_cond6_ct[31] ^ dcr6[`OR1200_DU_DCR_SC]) >= +- (dvr6[31] ^ dcr6[`OR1200_DU_DCR_SC])); ++ ({(match_cond6_ct[31] ^ dcr6[`OR1200_DU_DCR_SC]), match_cond6_ct[30:0]} >= ++ {(dvr6[31] ^ dcr6[`OR1200_DU_DCR_SC]), dvr6[30:0]} ); + 4'b1_110: match6 = +- ((match_cond6_ct[31] ^ dcr6[`OR1200_DU_DCR_SC]) != +- (dvr6[31] ^ dcr6[`OR1200_DU_DCR_SC])); ++ (match_cond6_ct != dvr6); + endcase + + // +@@ -1525,27 +1723,58 @@ always @(dmr1 or match6 or wp) + always @(dcr7 or id_pc or dcpu_adr_i or dcpu_dat_dc + or dcpu_dat_lsu or dcpu_we_i) + case (dcr7[`OR1200_DU_DCR_CT]) // synopsys parallel_case +- 3'b001: match_cond7_ct = id_pc; // insn fetch EA +- 3'b010: match_cond7_ct = dcpu_adr_i; // load EA +- 3'b011: match_cond7_ct = dcpu_adr_i; // store EA +- 3'b100: match_cond7_ct = dcpu_dat_dc; // load data +- 3'b101: match_cond7_ct = dcpu_dat_lsu; // store data +- 3'b110: match_cond7_ct = dcpu_adr_i; // load/store EA +- default:match_cond7_ct = dcpu_we_i ? dcpu_dat_lsu : dcpu_dat_dc; +- endcase ++ 3'b001: match_cond7_tmp = id_pc; // insn fetch EA -- *** use spr_dat_npc?? *** ++ 3'b010: match_cond7_tmp = dcpu_adr_i; // load EA ++ 3'b011: match_cond7_tmp = dcpu_adr_i; // store EA ++ 3'b100: match_cond7_tmp = dcpu_dat_dc; // load data ++ 3'b101: match_cond7_tmp = dcpu_dat_lsu; // store data ++ 3'b110: match_cond7_tmp = dcpu_adr_i; // load/store EA ++ default:match_cond7_tmp = dcpu_we_i ? dcpu_dat_lsu : dcpu_dat_dc; ++ endcase ++ ++// Transparently handle 8/16/32 bit bus accesses: ++// For addresses, leave unchanged ++// for 32-bit data, leave unchanged ++// for 8- or 16-bit data, move the active byte lane(s) to the LSB position ++// This will allow the value to be compared to the LSB(s) of the DVR. ++// If we're doing a signed compare (DCR_SC is set), we sign-extend. If not, zero-pad. ++// This means that for a signed comparison, the DVR must ALWAYS be a 32-bit signed ++// number, even if only doing on 8-bit compare! ++always @(match_cond7_tmp or dcr7 or dcpu_be_i) ++ case (dcr7[`OR1200_DU_DCR_CT]) // synopsys parallel_case ++ 3'b100, ++ 3'b101, ++ 3'b111: begin // We're comparing to data ++ case (dcpu_be_i) ++ 4'b1000: match_cond7_ct = { {24{dcr7[`OR1200_DU_DCR_SC] & match_cond7_tmp[31]}}, match_cond7_tmp[31:24]}; ++ 4'b0100: match_cond7_ct = { {24{dcr7[`OR1200_DU_DCR_SC] & match_cond7_tmp[23]}}, match_cond7_tmp[23:16]}; ++ 4'b0010: match_cond7_ct = { {24{dcr7[`OR1200_DU_DCR_SC] & match_cond7_tmp[15]}}, match_cond7_tmp[15:8]}; ++ 4'b0001: match_cond7_ct = { {24{dcr7[`OR1200_DU_DCR_SC] & match_cond7_tmp[7] }}, match_cond7_tmp[7:0]}; ++ 4'b1100: match_cond7_ct = { {16{dcr7[`OR1200_DU_DCR_SC] & match_cond7_tmp[31]}}, match_cond7_tmp[31:16]}; ++ 4'b0011: match_cond7_ct = { {16{dcr7[`OR1200_DU_DCR_SC] & match_cond7_tmp[15]}}, match_cond7_tmp[15:0]}; ++ default: match_cond7_ct = match_cond7_tmp; ++ endcase ++ end ++ default: match_cond7_ct = match_cond7_tmp; // We're comparing an address ++ endcase + + // + // When To Compare (Match Condition 7) + // +-always @(dcr7 or dcpu_cycstb_i) ++always @(dcr7 or dcpu_cycstb_i or dcpu_we_i) + case (dcr7[`OR1200_DU_DCR_CT]) // synopsys parallel_case + 3'b000: match_cond7_stb = 1'b0; //comparison disabled + 3'b001: match_cond7_stb = 1'b1; // insn fetch EA +- default:match_cond7_stb = dcpu_cycstb_i; // any load/store ++ 3'b010: match_cond7_stb = (dcpu_cycstb_i & (~dcpu_we_i)); // data load addr ++ 3'b011: match_cond7_stb = (dcpu_cycstb_i & dcpu_we_i); // data store addr ++ 3'b100: match_cond7_stb = (dcpu_cycstb_i & (~dcpu_we_i)); // data load val ++ 3'b101: match_cond7_stb = (dcpu_cycstb_i & dcpu_we_i); // data store val ++ default: match_cond7_stb = dcpu_cycstb_i; // any load/store + endcase + + // + // Match Condition 7 ++// To do a signed comparison, we invert the MSB then do an unsigned comparison. + // + always @(match_cond7_stb or dcr7 or dvr7 or match_cond7_ct) + casex ({match_cond7_stb, dcr7[`OR1200_DU_DCR_CC]}) +@@ -1553,23 +1782,21 @@ always @(match_cond7_stb or dcr7 or dvr7 + 4'b1_000, + 4'b1_111: match7 = 1'b0; + 4'b1_001: match7 = +- ((match_cond7_ct[31] ^ dcr7[`OR1200_DU_DCR_SC]) == +- (dvr7[31] ^ dcr7[`OR1200_DU_DCR_SC])); ++ (match_cond7_ct == dvr7); + 4'b1_010: match7 = +- ((match_cond7_ct[31] ^ dcr7[`OR1200_DU_DCR_SC]) < +- (dvr7[31] ^ dcr7[`OR1200_DU_DCR_SC])); ++ ({(match_cond7_ct[31] ^ dcr7[`OR1200_DU_DCR_SC]), match_cond7_ct[30:0]} < ++ {(dvr7[31] ^ dcr7[`OR1200_DU_DCR_SC]), dvr7[30:0]} ); + 4'b1_011: match7 = +- ((match_cond7_ct[31] ^ dcr7[`OR1200_DU_DCR_SC]) <= +- (dvr7[31] ^ dcr7[`OR1200_DU_DCR_SC])); ++ ({(match_cond7_ct[31] ^ dcr7[`OR1200_DU_DCR_SC]), match_cond7_ct[30:0]} <= ++ {(dvr7[31] ^ dcr7[`OR1200_DU_DCR_SC]), dvr7[30:0]} ); + 4'b1_100: match7 = +- ((match_cond7_ct[31] ^ dcr7[`OR1200_DU_DCR_SC]) > +- (dvr7[31] ^ dcr7[`OR1200_DU_DCR_SC])); ++ ({(match_cond7_ct[31] ^ dcr7[`OR1200_DU_DCR_SC]), match_cond7_ct[30:0]} > ++ {(dvr7[31] ^ dcr7[`OR1200_DU_DCR_SC]), dvr7[30:0]} ); + 4'b1_101: match7 = +- ((match_cond7_ct[31] ^ dcr7[`OR1200_DU_DCR_SC]) >= +- (dvr7[31] ^ dcr7[`OR1200_DU_DCR_SC])); ++ ({(match_cond7_ct[31] ^ dcr7[`OR1200_DU_DCR_SC]), match_cond7_ct[30:0]} >= ++ {(dvr7[31] ^ dcr7[`OR1200_DU_DCR_SC]), dvr7[30:0]} ); + 4'b1_110: match7 = +- ((match_cond7_ct[31] ^ dcr7[`OR1200_DU_DCR_SC]) != +- (dvr7[31] ^ dcr7[`OR1200_DU_DCR_SC])); ++ (match_cond7_ct != dvr7); + endcase + + // +@@ -1586,11 +1813,19 @@ always @(dmr1 or match7 or wp) + // + // Increment Watchpoint Counter 0 + // +-always @(wp or dmr2) +- if (dmr2[`OR1200_DU_DMR2_WCE0]) +- incr_wpcntr0 = |(wp & ~dmr2[`OR1200_DU_DMR2_AWTC]); +- else +- incr_wpcntr0 = 1'b0; ++ ++// A watchpoint may hold it's wp bit high for >1 clock while ex_freeze ++// is high, but drop it when ex_freeze is low. So, increment on wp will over-increment, ++// but AND'ing with ex_freeze will never increment. Solution: hold the wp when set, ++// inc the counter only when ex_freeze is false. ++always @ (posedge clk) ++begin ++ if(rst) incr_wpcntr0_latched <= 1'b0; ++ else if(ex_freeze & (|(wp & ~dmr2[`OR1200_DU_DMR2_AWTC]))) incr_wpcntr0_latched <= 1'b1; ++ else if(~ex_freeze) incr_wpcntr0_latched <= 1'b0; ++end ++ ++assign incr_wpcntr0 = dmr2[`OR1200_DU_DMR2_WCE0] & (~ex_freeze & (incr_wpcntr0_latched | (|(wp & ~dmr2[`OR1200_DU_DMR2_AWTC])))); + + // + // Match Condition Watchpoint Counter 0 +@@ -1601,15 +1836,35 @@ always @(dwcr0) + else + wpcntr0_match = 1'b0; + ++// ++// Breakpoint Triggering - Counter 1 ++// While the standard watchpoint hardware won't give a match for more than one ++// clock cycle, the counters will give a constant match. This will be registered, ++// causing a second trap condition after a continue. To fix this, just pulse the ++// break output high for 1 clock cycle, and don't do it again until the match ++// condition has been negated for at least 1 clock cycle. The new break output ++// is called wpcntrX_oneshot. ++// ++always @ (posedge clk) ++begin ++ if(wpcntr0_match & wpcntr0_armed) wpcntr0_oneshot = 1'b1; ++ else wpcntr0_oneshot = 1'b0; ++end ++ ++always @(posedge clk) ++begin ++ if(wpcntr0_match) wpcntr0_armed = 1'b0; ++ else wpcntr0_armed = 1'b1; ++end + + // +-// Watchpoint 8 ++// Watchpoint 8 (Counter 0) + // +-always @(dmr1 or wpcntr0_match or wp) ++always @(dmr1 or wpcntr0_oneshot or wp) + case (dmr1[`OR1200_DU_DMR1_CW8]) +- 2'b00: wp[8] = wpcntr0_match; +- 2'b01: wp[8] = wpcntr0_match & wp[7]; +- 2'b10: wp[8] = wpcntr0_match | wp[7]; ++ 2'b00: wp[8] = wpcntr0_oneshot; ++ 2'b01: wp[8] = wpcntr0_oneshot & wp[3]; ++ 2'b10: wp[8] = wpcntr0_oneshot | wp[3]; + 2'b11: wp[8] = 1'b0; + endcase + +@@ -1617,11 +1872,18 @@ always @(dmr1 or wpcntr0_match or wp) + // + // Increment Watchpoint Counter 1 + // +-always @(wp or dmr2) +- if (dmr2[`OR1200_DU_DMR2_WCE1]) +- incr_wpcntr1 = |(wp & dmr2[`OR1200_DU_DMR2_AWTC]); +- else +- incr_wpcntr1 = 1'b0; ++// A watchpoint may hold it's wp bit high for >1 clock while ex_freeze ++// is high, but drop it when ex_freeze is low. So, increment on wp will over-increment, ++// but AND'ing with ex_freeze will never increment. Solution: hold the wp when set, ++// inc the counter only when ex_freeze is false. ++always @ (posedge clk) ++begin ++ if(rst) incr_wpcntr1_latched <= 1'b0; ++ else if(ex_freeze & (|(wp & dmr2[`OR1200_DU_DMR2_AWTC]))) incr_wpcntr1_latched <= 1'b1; ++ else if(~ex_freeze) incr_wpcntr1_latched <= 1'b0; ++end ++ ++assign incr_wpcntr1 = dmr2[`OR1200_DU_DMR2_WCE1] & (~ex_freeze & (incr_wpcntr1_latched | (|(wp & dmr2[`OR1200_DU_DMR2_AWTC])))); + + // + // Match Condition Watchpoint Counter 1 +@@ -1633,36 +1895,70 @@ always @(dwcr1) + wpcntr1_match = 1'b0; + + // +-// Watchpoint 9 +-// +-always @(dmr1 or wpcntr1_match or wp) +- case (dmr1[`OR1200_DU_DMR1_CW9]) +- 2'b00: wp[9] = wpcntr1_match; +- 2'b01: wp[9] = wpcntr1_match & wp[8]; +- 2'b10: wp[9] = wpcntr1_match | wp[8]; +- 2'b11: wp[9] = 1'b0; +- endcase ++// Breakpoint Triggering - Counter 1 ++// While the standard watchpoint hardware won't give a match for more than one ++// clock cycle, the counters will give a constant match. This will be registered, ++// causing a second trap condition after a continue. To fix this, just pulse the ++// break output high for 1 clock cycle, and don't do it again until the match ++// condition has been negated for at least 1 clock cycle. The new break output ++// is called wpcntrX_oneshot. ++// ++always @ (posedge clk) ++begin ++ if(wpcntr1_match & wpcntr1_armed) wpcntr1_oneshot = 1'b1; ++ else wpcntr1_oneshot = 1'b0; ++end ++ ++always @(posedge clk) ++begin ++ if(wpcntr1_match) wpcntr1_armed = 1'b0; ++ else wpcntr1_armed = 1'b1; ++end + + // +-// Watchpoint 10 ++// Watchpoint 9 (Counter 1) + // +-always @(dmr1 or dbg_ewt_i or wp) +- case (dmr1[`OR1200_DU_DMR1_CW10]) +- 2'b00: wp[10] = dbg_ewt_i; +- 2'b01: wp[10] = dbg_ewt_i & wp[9]; +- 2'b10: wp[10] = dbg_ewt_i | wp[9]; +- 2'b11: wp[10] = 1'b0; ++always @(dmr1 or wpcntr1_oneshot or wp) ++ case (dmr1[`OR1200_DU_DMR1_CW9]) ++ 2'b00: wp[9] = wpcntr1_oneshot; ++ 2'b01: wp[9] = wpcntr1_oneshot & wp[7]; ++ 2'b10: wp[9] = wpcntr1_oneshot | wp[7]; ++ 2'b11: wp[9] = 1'b0; + endcase + + `endif + ++ + // + // Watchpoints can cause trap exception + // + `ifdef OR1200_DU_HWBKPTS +-assign du_hwbkpt = |(wp & dmr2[`OR1200_DU_DMR2_WGB]); ++ ++// We must hold the du_hwbkpt signal high until it's noticed by the execution unit, ++// which means until the 'freeze' signal goes inactive. ++ ++always @ (posedge clk) ++begin ++ if(rst) du_hwbkpt_latched <= 1'b0; ++ else if(ex_freeze & (|(wp & dmr2[`OR1200_DU_DMR2_WGB]))) du_hwbkpt_latched <= 1'b1; ++ else if(~ex_freeze) du_hwbkpt_latched <= 1'b0; ++end ++ ++assign du_hwbkpt = du_hwbkpt_latched | (|(wp & dmr2[`OR1200_DU_DMR2_WGB])); ++ ++ `ifdef OR1200_DU_DMR2 ++// Spec doesn't state what resets the WGB bits in DMR2. ++// This implementation resets on any write to the DMR2. ++always @ (posedge clk) ++begin ++ if(rst | (dmr2_sel & spr_write)) wp_latched <= 10'h000; ++ else if((|(wp & dmr2[`OR1200_DU_DMR2_WGB]))/*du_hwbkpt*/ & !(|wp_latched)) wp_latched <= (wp & dmr2[`OR1200_DU_DMR2_WGB]); ++end ++ `endif ++ + `else + assign du_hwbkpt = 1'b0; ++assign wp_latched = 10'h000; + `endif + + `ifdef OR1200_DU_TB_IMPLEMENTED Index: release-1.0/utils/setup/required-cygwin-tools.txt =================================================================== --- release-1.0/utils/setup/required-cygwin-tools.txt (nonexistent) +++ release-1.0/utils/setup/required-cygwin-tools.txt (revision 151) @@ -0,0 +1,12 @@ +packages: +util-linux (for whereis) +wget +subversion +patch +gcc +make +libncurses-devel +ioperm +libusb-win32 +flex +bison \ No newline at end of file Index: release-1.0/utils/setup/beautify.sh =================================================================== --- release-1.0/utils/setup/beautify.sh (nonexistent) +++ release-1.0/utils/setup/beautify.sh (revision 151) @@ -0,0 +1,64 @@ +#!/bin/bash +# Xanthopoulos Constantinos +# Some useful function for my scripts + +function cecho +{ + echo -e "\033[1m\033[33m$1\033[0m" + echo -e "\033[1m\033[33m$1\033[0m" >> ${SCRIPT_DIR}/progress.log +} + +function cnecho +{ + echo -e -n "\033[0m\033[33m$1\033[0m" + echo -e -n "\033[0m\033[33m$1\033[0m" >> ${SCRIPT_DIR}/progress.log +} + +function errormsg +{ + echo -e "\033[1m\033[31mError: $1\033[0m\n"; + echo -e "\033[1m\033[31mError: $1\033[0m\n" >> ${SCRIPT_DIR}/error.log + exit 1; +} + +function _execcmd +{ + # Print Message + echo -e "\033[35m$1...\033[0m\n" >> ${SCRIPT_DIR}/progress.log + if [ -n "$1" ] + then + echo -e -n "\033[35m$1...\033[0m" + fi + # Execute command + if [ $DEBUG -ne 1 ]; + then + eval $2 1>>${SCRIPT_DIR}/progress.log 2>>${SCRIPT_DIR}/error.log; + fi; + # Check Execution + if [ $? -eq 0 ] + then + if [ -n "$1" ] + then + echo -e "\033[32mcomplete\033[0m"; + echo -e "\033[32mcomplete\033[0m" >> ${SCRIPT_DIR}/progress.log + fi + else + errormsg "Command: $2 Description: $1"; + exit 1; + fi +} + +function execcmd +{ + if [ -z "$2" ] + then + _execcmd "" "$1" + else + _execcmd "$1" "$2" + fi +} + +if [ $DEBUG -eq 1 ] +then + cecho "Debug mode on! Nothing will actually run"; +fi Index: release-1.0/utils/setup/install_time.txt =================================================================== --- release-1.0/utils/setup/install_time.txt (nonexistent) +++ release-1.0/utils/setup/install_time.txt (revision 151) @@ -0,0 +1,5 @@ +Debian Linux | Intel Q6600 2.4 GHz | single core compilation + 7 minutes + +Cygwin on Windows XP | VMware virtual machine | Intel Q6600 2.4 GHz | single core compilation + 50 minutes \ No newline at end of file Index: release-1.0/utils/contributions/gpio/todo.txt =================================================================== --- release-1.0/utils/contributions/gpio/todo.txt (nonexistent) +++ release-1.0/utils/contributions/gpio/todo.txt (revision 151) @@ -0,0 +1,38 @@ +I still have some important hints to you regarding this. + +minsoc_top.v: on line 817 you should also include: +assign wb_gpio_err_o = 1'b0; (otherwise simulation might drive crazy and prob real life if it doesn't "automatically" be set to 0. + +You probably missed it since these are gathered together around line 358 for uart, spi and start_up. And I forgot myself to add it for Ethernet. + +On gpio_defines.v, the GPIO_IOS definition I'd set directly to 32. Instantiation would be instead of GPIO_IOS + 1, GPIO_IOS only. Is there any problem regarding this? The definitions generally are more human friendly than coding, so the register definitions of reg [GPIOS_IOS-1:0] which considers 0 to be something is let for the implementation. That's more or less standard I'd say. It is the same as when you define the address width on minsoc_defines.v you define it and I implement it considering the necessary -1s. + +GPIO_LINES32 instead of GPIO_LINES31. + +I'd substitute the whole minsoc_spartan_3a_starter_kit_ios.v. Instead of it, place a bidirectional port on minsoc_top if GPIO is enabled. +`ifdef GPIO +, gpio_io +`endif + +// +// GPIO +// +inout [GPIO_IOS-1:0] gpio_io; + +// +// GPIO tri-state +// +// I hope this works without generate, otherwise it is also easy but I'd first try this way +integer iterate; +for (iterate = 0; iterate < GPIO_IOS; iterate = iterate + 1) + assign gpio_io[iterate] = ext_pad_oe_o[iterate] ? ext_pad_o[iterate] : 1'bZ; + +assign ext_pad_i = gpio_io; + +And then only define the pins for the inout port on the ucf file. Like this: +NET "gpio_io(31)" LOC = "a1(pin number)" | DRIVE = 12 | SLEW = SLOW; +NET "gpio_io(30)" LOC = "a1(pin number)" | DRIVE = 12 | SLEW = SLOW; +... +NET "gpio_io(0)" LOC = "a1(pin number)" | DRIVE = 12 | SLEW = SLOW; + +After that you only need the definition GPIO on minsoc_defines.v. Of course, interrupt and address you also still need. \ No newline at end of file Index: release-1.0/utils/contributions/gpio/rtl/gpio_defines.v =================================================================== --- release-1.0/utils/contributions/gpio/rtl/gpio_defines.v (nonexistent) +++ release-1.0/utils/contributions/gpio/rtl/gpio_defines.v (revision 151) @@ -0,0 +1,326 @@ +////////////////////////////////////////////////////////////////////// +//// //// +//// WISHBONE GPIO Definitions //// +//// //// +//// This file is part of the GPIO project //// +//// http://www.opencores.org/cores/gpio/ //// +//// //// +//// Description //// +//// GPIO IP Definitions. //// +//// //// +//// To Do: //// +//// Nothing //// +//// //// +//// Author(s): //// +//// - Damjan Lampret, lampret@opencores.org //// +//// //// +////////////////////////////////////////////////////////////////////// +//// //// +//// Copyright (C) 2000 Authors and OPENCORES.ORG //// +//// //// +//// This source file may be used and distributed without //// +//// restriction provided that this copyright statement is not //// +//// removed from the file and that any derivative work contains //// +//// the original copyright notice and the associated disclaimer. //// +//// //// +//// This source file is free software; you can redistribute it //// +//// and/or modify it under the terms of the GNU Lesser General //// +//// Public License as published by the Free Software Foundation; //// +//// either version 2.1 of the License, or (at your option) any //// +//// later version. //// +//// //// +//// This source is distributed in the hope that it will be //// +//// useful, but WITHOUT ANY WARRANTY; without even the implied //// +//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR //// +//// PURPOSE. See the GNU Lesser General Public License for more //// +//// details. //// +//// //// +//// You should have received a copy of the GNU Lesser General //// +//// Public License along with this source; if not, download it //// +//// from http://www.opencores.org/lgpl.shtml //// +//// //// +////////////////////////////////////////////////////////////////////// +// +// CVS Revision History +// +// $Log: not supported by cvs2svn $ +// Revision 1.8 2003/12/17 13:00:52 gorand +// added ECLK and NEC registers, all tests passed. +// +// Revision 1.7 2003/12/01 17:10:44 simons +// ifndef directive is not supported by all tools. +// +// Revision 1.6 2003/11/06 13:59:07 gorand +// added support for 8-bit access to registers. +// +// Revision 1.2 2003/10/02 18:54:35 simons +// GPIO signals muxed with other peripherals, higland_board fixed. +// +// Revision 1.1.1.1 2003/06/24 09:09:23 simons +// This files were moved here from toplevel folder. +// +// Revision 1.1.1.1 2003/06/11 18:51:13 simons +// Initial import. +// +// Revision 1.5 2002/11/11 21:36:28 lampret +// Added ifdef to remove mux from clk_pad_i if mux is not allowed. This also removes RGPIO_CTRL[NEC]. +// +// Revision 1.4 2002/05/06 18:25:31 lampret +// negedge flops are enabled by default. +// +// Revision 1.3 2001/12/25 17:12:35 lampret +// Added RGPIO_INTS. +// +// Revision 1.2 2001/11/15 02:24:37 lampret +// Added GPIO_REGISTERED_WB_OUTPUTS, GPIO_REGISTERED_IO_OUTPUTS and GPIO_NO_NEGEDGE_FLOPS. +// +// Revision 1.1 2001/09/18 18:49:07 lampret +// Changed top level ptc into gpio_top. Changed defines.v into gpio_defines.v. +// +// Revision 1.1 2001/08/21 21:39:28 lampret +// Changed directory structure, port names and drfines. +// +// Revision 1.3 2001/07/15 00:21:10 lampret +// Registers can be omitted and will have certain default values +// +// Revision 1.2 2001/07/14 20:39:26 lampret +// Better configurability. +// +// Revision 1.1 2001/06/05 07:45:26 lampret +// Added initial RTL and test benches. There are still some issues with these files. +// +// + +// +// Number of GPIO I/O signals +// +// This is the most important parameter of the GPIO IP core. It defines how many +// I/O signals core has. Range is from 1 to 32. If more than 32 I/O signals are +// required, use several instances of GPIO IP core. +// +// Default is 16. +// +`define GPIO_IOS 31 + +//depending on number of GPIO_IOS, define this... +// for example: if there is 26 GPIO_IOS, define GPIO_LINES26 +// + +`define GPIO_LINES31 + +// +// Undefine this one if you don't want to remove GPIO block from your design +// but you also don't need it. When it is undefined, all GPIO ports still +// remain valid and the core can be synthesized however internally there is +// no GPIO funationality. +// +// Defined by default (duhh !). +// +`define GPIO_IMPLEMENTED + +// +// Define to register all WISHBONE outputs. +// +// Register outputs if you are using GPIO core as a block and synthesizing +// and place&routing it separately from the rest of the system. +// +// If you do not need registered outputs, you can save some area by not defining +// this macro. By default it is defined. +// +`define GPIO_REGISTERED_WB_OUTPUTS + +// +// Define to register all GPIO pad outputs. +// +// Register outputs if you are using GPIO core as a block and synthesizing +// and place&routing it separately from the rest of the system. +// +// If you do not need registered outputs, you can save some area by not defining +// this macro. By default it is defined. +// +`define GPIO_REGISTERED_IO_OUTPUTS + +// +// Implement aux feature. If this define is not defined also aux_i port and +// RGPIO_AUX register will be removed +// +// Defined by default. +// +//`define GPIO_AUX_IMPLEMENT + +// +// If this is not defined clk_pad_i will be removed. Input lines will be lached on +// positive edge of system clock +// if disabled defines GPIO_NO_NEGEDGE_FLOPS, GPIO_NO_CLKPAD_LOGIC will have no effect. +// +// Defined by default. +// +//`define GPIO_CLKPAD + +// +// Define to avoid using negative edge clock flip-flops for external clock +// (caused by NEC register. Instead an inverted external clock with +// positive edge clock flip-flops will be used. +// This define don't have any effect if GPIO_CLKPAD is not defined and if GPIO_SYNC_IN_CLK is defined +// +// By default it is not defined. +// +//`define GPIO_NO_NEGEDGE_FLOPS + +// +// If GPIO_NO_NEGEDGE_FLOPS is defined, a mux needs to be placed on external clock +// clk_pad_i to implement RGPIO_CTRL[NEC] functionality. If no mux is allowed on +// clock signal, enable the following define. +// This define don't have any effect if GPIO_CLKPAD is not defined and if GPIO_SYNC_IN_CLK is defined +// +// By default it is not defined. +// +//`define GPIO_NO_CLKPAD_LOGIC + + +// +// synchronization defines +// +// Two synchronization flops to input lineis added. +// system clock synchronization. +// +`define GPIO_SYNC_IN_WB + +// +// Add synchronization flops to external clock input line. Gpio will have just one clock domain, +// everithing will be synchronized to wishbone clock. External clock muas be at least 2-3x slower +// as systam clock. +// +`define GPIO_SYNC_CLK_WB + +// +// Add synchronization to input pads. synchronization to external clock. +// Don't hawe any effect if GPIO_SYNC_CLK_WB is defined. +// +//`define GPIO_SYNC_IN_CLK + +// +// Add synchronization flops between system clock and external clock. +// Only possible if external clock is enabled and clock synchroization is disabled. +// +//`define GPIO_SYNC_IN_CLK_WB + + + +// +// Undefine if you don't need to read GPIO registers except for RGPIO_IN register. +// When it is undefined all reads of GPIO registers return RGPIO_IN register. This +// is usually useful if you want really small area (for example when implemented in +// FPGA). +// +// To follow GPIO IP core specification document this one must be defined. Also to +// successfully run the test bench it must be defined. By default it is defined. +// +`define GPIO_READREGS + +// +// Full WISHBONE address decoding +// +// It is is undefined, partial WISHBONE address decoding is performed. +// Undefine it if you need to save some area. +// +// By default it is defined. +// +`define GPIO_FULL_DECODE + +// +// Strict 32-bit WISHBONE access +// +// If this one is defined, all WISHBONE accesses must be 32-bit. If it is +// not defined, err_o is asserted whenever 8- or 16-bit access is made. +// Undefine it if you need to save some area. +// +// By default it is defined. +// +//`define GPIO_STRICT_32BIT_ACCESS +// +`ifdef GPIO_STRICT_32BIT_ACCESS +`else +// added by gorand : +// if GPIO_STRICT_32BIT_ACCESS is not defined, +// depending on number of gpio I/O lines, the following are defined : +// if the number of I/O lines is in range 1-8, GPIO_WB_BYTES1 is defined, +// if the number of I/O lines is in range 9-16, GPIO_WB_BYTES2 is defined, +// if the number of I/O lines is in range 17-24, GPIO_WB_BYTES3 is defined, +// if the number of I/O lines is in range 25-32, GPIO_WB_BYTES4 is defined, + +`define GPIO_WB_BYTES4 +//`define GPIO_WB_BYTES3 +//`define GPIO_WB_BYTES2 +//`define GPIO_WB_BYTES1 + +`endif + +// +// WISHBONE address bits used for full decoding of GPIO registers. +// +`define GPIO_ADDRHH 7 +`define GPIO_ADDRHL 6 +`define GPIO_ADDRLH 1 +`define GPIO_ADDRLL 0 + +// +// Bits of WISHBONE address used for partial decoding of GPIO registers. +// +// Default 5:2. +// +`define GPIO_OFS_BITS `GPIO_ADDRHL-1:`GPIO_ADDRLH+1 + +// +// Addresses of GPIO registers +// +// To comply with GPIO IP core specification document they must go from +// address 0 to address 0x18 in the following order: RGPIO_IN, RGPIO_OUT, +// RGPIO_OE, RGPIO_INTE, RGPIO_PTRIG, RGPIO_AUX and RGPIO_CTRL +// +// If particular register is not needed, it's address definition can be omitted +// and the register will not be implemented. Instead a fixed default value will +// be used. +// +`define GPIO_RGPIO_IN 4'h0 // Address 0x00 +`define GPIO_RGPIO_OUT 4'h1 // Address 0x04 +`define GPIO_RGPIO_OE 4'h2 // Address 0x08 +`define GPIO_RGPIO_INTE 4'h3 // Address 0x0c +`define GPIO_RGPIO_PTRIG 4'h4 // Address 0x10 + +`ifdef GPIO_AUX_IMPLEMENT +`define GPIO_RGPIO_AUX 4'h5 // Address 0x14 +`endif // GPIO_AUX_IMPLEMENT + +`define GPIO_RGPIO_CTRL 4'h6 // Address 0x18 +`define GPIO_RGPIO_INTS 4'h7 // Address 0x1c + +`ifdef GPIO_CLKPAD +`define GPIO_RGPIO_ECLK 4'h8 // Address 0x20 +`define GPIO_RGPIO_NEC 4'h9 // Address 0x24 +`endif // GPIO_CLKPAD + +// +// Default values for unimplemented GPIO registers +// +`define GPIO_DEF_RGPIO_IN `GPIO_IOS'h0 +`define GPIO_DEF_RGPIO_OUT `GPIO_IOS'h0 +`define GPIO_DEF_RGPIO_OE `GPIO_IOS'h0 +`define GPIO_DEF_RGPIO_INTE `GPIO_IOS'h0 +`define GPIO_DEF_RGPIO_PTRIG `GPIO_IOS'h0 +`define GPIO_DEF_RGPIO_AUX `GPIO_IOS'h0 +`define GPIO_DEF_RGPIO_CTRL `GPIO_IOS'h0 +`define GPIO_DEF_RGPIO_ECLK `GPIO_IOS'h0 +`define GPIO_DEF_RGPIO_NEC `GPIO_IOS'h0 + + +// +// RGPIO_CTRL bits +// +// To comply with the GPIO IP core specification document they must go from +// bit 0 to bit 1 in the following order: INTE, INT +// +`define GPIO_RGPIO_CTRL_INTE 0 +`define GPIO_RGPIO_CTRL_INTS 1 + + Index: release-1.0/utils/contributions/gpio/rtl/gpio_top.v =================================================================== --- release-1.0/utils/contributions/gpio/rtl/gpio_top.v (nonexistent) +++ release-1.0/utils/contributions/gpio/rtl/gpio_top.v (revision 151) @@ -0,0 +1,1135 @@ +////////////////////////////////////////////////////////////////////// +//// //// +//// WISHBONE General-Purpose I/O //// +//// //// +//// This file is part of the GPIO project //// +//// http://www.opencores.org/cores/gpio/ //// +//// //// +//// Description //// +//// Implementation of GPIO IP core according to //// +//// GPIO IP core specification document. //// +//// //// +//// To Do: //// +//// Nothing //// +//// //// +//// Author(s): //// +//// - Damjan Lampret, lampret@opencores.org //// +//// //// +////////////////////////////////////////////////////////////////////// +//// //// +//// Copyright (C) 2000 Authors and OPENCORES.ORG //// +//// //// +//// This source file may be used and distributed without //// +//// restriction provided that this copyright statement is not //// +//// removed from the file and that any derivative work contains //// +//// the original copyright notice and the associated disclaimer. //// +//// //// +//// This source file is free software; you can redistribute it //// +//// and/or modify it under the terms of the GNU Lesser General //// +//// Public License as published by the Free Software Foundation; //// +//// either version 2.1 of the License, or (at your option) any //// +//// later version. //// +//// //// +//// This source is distributed in the hope that it will be //// +//// useful, but WITHOUT ANY WARRANTY; without even the implied //// +//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR //// +//// PURPOSE. See the GNU Lesser General Public License for more //// +//// details. //// +//// //// +//// You should have received a copy of the GNU Lesser General //// +//// Public License along with this source; if not, download it //// +//// from http://www.opencores.org/lgpl.shtml //// +//// //// +////////////////////////////////////////////////////////////////////// +// +// CVS Revision History +// +// $Log: not supported by cvs2svn $ +// Revision 1.17 2004/05/05 08:21:00 andreje +// Bugfixes when GPIO_RGPIO_ECLK/GPIO_RGPIO_NEC disabled, gpio oe name change and set to active-high according to spec +// +// Revision 1.16 2003/12/17 13:00:52 gorand +// added ECLK and NEC registers, all tests passed. +// +// Revision 1.15 2003/11/10 23:21:22 gorand +// bug fixed. all tests passed. +// +// Revision 1.14 2003/11/06 13:59:07 gorand +// added support for 8-bit access to registers. +// +// Revision 1.13 2002/11/18 22:35:18 lampret +// Bug fix. Interrupts were also asserted when condition was not met. +// +// Revision 1.12 2002/11/11 21:36:28 lampret +// Added ifdef to remove mux from clk_pad_i if mux is not allowed. This also removes RGPIO_CTRL[NEC]. +// +// Revision 1.11 2002/03/13 20:56:28 lampret +// Removed zero padding as per Avi Shamli suggestion. +// +// Revision 1.10 2002/03/13 20:47:57 lampret +// Ports changed per Ran Aviram suggestions. +// +// Revision 1.9 2002/03/09 03:43:27 lampret +// Interrupt is asserted only when an input changes (code patch by Jacob Gorban) +// +// Revision 1.8 2002/01/14 19:06:28 lampret +// Changed registered WISHBONE outputs wb_ack_o/wb_err_o to follow WB specification. +// +// Revision 1.7 2001/12/25 17:21:21 lampret +// Fixed two typos. +// +// Revision 1.6 2001/12/25 17:12:35 lampret +// Added RGPIO_INTS. +// +// Revision 1.5 2001/12/12 20:35:53 lampret +// Fixing style. +// +// Revision 1.4 2001/12/12 07:12:58 lampret +// Fixed bug when wb_inta_o is registered (GPIO_WB_REGISTERED_OUTPUTS) +// +// Revision 1.3 2001/11/15 02:24:37 lampret +// Added GPIO_REGISTERED_WB_OUTPUTS, GPIO_REGISTERED_IO_OUTPUTS and GPIO_NO_NEGEDGE_FLOPS. +// +// Revision 1.2 2001/10/31 02:26:51 lampret +// Fixed wb_err_o. +// +// Revision 1.1 2001/09/18 18:49:07 lampret +// Changed top level ptc into gpio_top. Changed defines.v into gpio_defines.v. +// +// Revision 1.1 2001/08/21 21:39:28 lampret +// Changed directory structure, port names and drfines. +// +// Revision 1.2 2001/07/14 20:39:26 lampret +// Better configurability. +// +// Revision 1.1 2001/06/05 07:45:26 lampret +// Added initial RTL and test benches. There are still some issues with these files. +// +// + +// synopsys translate_off +`include "timescale.v" +// synopsys translate_on +`include "gpio_defines.v" + +module gpio_top( + // WISHBONE Interface + wb_clk_i, wb_rst_i, wb_cyc_i, wb_adr_i, wb_dat_i, wb_sel_i, wb_we_i, wb_stb_i, + wb_dat_o, wb_ack_o, wb_err_o, wb_inta_o, + +`ifdef GPIO_AUX_IMPLEMENT + // Auxiliary inputs interface + aux_i, +`endif // GPIO_AUX_IMPLEMENT + + // External GPIO Interface + ext_pad_i, ext_pad_o, ext_padoe_o +`ifdef GPIO_CLKPAD + , clk_pad_i +`endif +); + +parameter dw = 32; +parameter aw = `GPIO_ADDRHH+1; +parameter gw = `GPIO_IOS; +// +// WISHBONE Interface +// +input wb_clk_i; // Clock +input wb_rst_i; // Reset +input wb_cyc_i; // cycle valid input +input [aw-1:0] wb_adr_i; // address bus inputs +input [dw-1:0] wb_dat_i; // input data bus +input [3:0] wb_sel_i; // byte select inputs +input wb_we_i; // indicates write transfer +input wb_stb_i; // strobe input +output [dw-1:0] wb_dat_o; // output data bus +output wb_ack_o; // normal termination +output wb_err_o; // termination w/ error +output wb_inta_o; // Interrupt request output + +`ifdef GPIO_AUX_IMPLEMENT +// Auxiliary Inputs Interface +input [gw-1:0] aux_i; // Auxiliary inputs +`endif // GPIO_AUX_IMPLEMENT + +// +// External GPIO Interface +// +input [gw-1:0] ext_pad_i; // GPIO Inputs +`ifdef GPIO_CLKPAD +input clk_pad_i; // GPIO Eclk +`endif // GPIO_CLKPAD +output [gw-1:0] ext_pad_o; // GPIO Outputs +output [gw-1:0] ext_padoe_o; // GPIO output drivers enables + +`ifdef GPIO_IMPLEMENTED + +// +// GPIO Input Register (or no register) +// +`ifdef GPIO_RGPIO_IN +reg [gw-1:0] rgpio_in; // RGPIO_IN register +`else +wire [gw-1:0] rgpio_in; // No register +`endif + +// +// GPIO Output Register (or no register) +// +`ifdef GPIO_RGPIO_OUT +reg [gw-1:0] rgpio_out; // RGPIO_OUT register +`else +wire [gw-1:0] rgpio_out; // No register +`endif + +// +// GPIO Output Driver Enable Register (or no register) +// +`ifdef GPIO_RGPIO_OE +reg [gw-1:0] rgpio_oe; // RGPIO_OE register +`else +wire [gw-1:0] rgpio_oe; // No register +`endif + +// +// GPIO Interrupt Enable Register (or no register) +// +`ifdef GPIO_RGPIO_INTE +reg [gw-1:0] rgpio_inte; // RGPIO_INTE register +`else +wire [gw-1:0] rgpio_inte; // No register +`endif + +// +// GPIO Positive edge Triggered Register (or no register) +// +`ifdef GPIO_RGPIO_PTRIG +reg [gw-1:0] rgpio_ptrig; // RGPIO_PTRIG register +`else +wire [gw-1:0] rgpio_ptrig; // No register +`endif + +// +// GPIO Auxiliary select Register (or no register) +// +`ifdef GPIO_RGPIO_AUX +reg [gw-1:0] rgpio_aux; // RGPIO_AUX register +`else +wire [gw-1:0] rgpio_aux; // No register +`endif + +// +// GPIO Control Register (or no register) +// +`ifdef GPIO_RGPIO_CTRL +reg [1:0] rgpio_ctrl; // RGPIO_CTRL register +`else +wire [1:0] rgpio_ctrl; // No register +`endif + +// +// GPIO Interrupt Status Register (or no register) +// +`ifdef GPIO_RGPIO_INTS +reg [gw-1:0] rgpio_ints; // RGPIO_INTS register +`else +wire [gw-1:0] rgpio_ints; // No register +`endif + +// +// GPIO Enable Clock Register (or no register) +// +`ifdef GPIO_RGPIO_ECLK +reg [gw-1:0] rgpio_eclk; // RGPIO_ECLK register +`else +wire [gw-1:0] rgpio_eclk; // No register +`endif + +// +// GPIO Active Negative Edge Register (or no register) +// +`ifdef GPIO_RGPIO_NEC +reg [gw-1:0] rgpio_nec; // RGPIO_NEC register +`else +wire [gw-1:0] rgpio_nec; // No register +`endif + + +// +// Synchronization flops for input signals +// +`ifdef GPIO_SYNC_IN_WB +reg [gw-1:0] sync , + ext_pad_s ; +`else +wire [gw-1:0] ext_pad_s ; +`endif + + + +// +// Internal wires & regs +// +wire rgpio_out_sel; // RGPIO_OUT select +wire rgpio_oe_sel; // RGPIO_OE select +wire rgpio_inte_sel; // RGPIO_INTE select +wire rgpio_ptrig_sel;// RGPIO_PTRIG select +wire rgpio_aux_sel; // RGPIO_AUX select +wire rgpio_ctrl_sel; // RGPIO_CTRL select +wire rgpio_ints_sel; // RGPIO_INTS select +wire rgpio_eclk_sel ; +wire rgpio_nec_sel ; +wire full_decoding; // Full address decoding qualification +wire [gw-1:0] in_muxed; // Muxed inputs +wire wb_ack; // WB Acknowledge +wire wb_err; // WB Error +wire wb_inta; // WB Interrupt +reg [dw-1:0] wb_dat; // WB Data out +`ifdef GPIO_REGISTERED_WB_OUTPUTS +reg wb_ack_o; // WB Acknowledge +reg wb_err_o; // WB Error +reg wb_inta_o; // WB Interrupt +reg [dw-1:0] wb_dat_o; // WB Data out +`endif +wire [gw-1:0] out_pad; // GPIO Outputs +`ifdef GPIO_REGISTERED_IO_OUTPUTS +reg [gw-1:0] ext_pad_o; // GPIO Outputs +`endif +`ifdef GPIO_CLKPAD +wire [gw-1:0] extc_in; // Muxed inputs sampled by external clock +wire [gw-1:0] pext_clk; // External clock for posedge flops +reg [gw-1:0] pextc_sampled; // Posedge external clock sampled inputs +`ifdef GPIO_NO_NEGEDGE_FLOPS +`ifdef GPIO_NO_CLKPAD_LOGIC +`else +reg [gw-1:0] nextc_sampled; // Negedge external clock sampled inputs +`endif // GPIO_NO_CLKPAD_LOGIC +`else +reg [gw-1:0] nextc_sampled; // Negedge external clock sampled inputs +`endif +`endif // GPIO_CLKPAD + + +// +// All WISHBONE transfer terminations are successful except when: +// a) full address decoding is enabled and address doesn't match +// any of the GPIO registers +// b) wb_sel_i evaluation is enabled and one of the wb_sel_i inputs is zero +// + +// +// WB Acknowledge +// +assign wb_ack = wb_cyc_i & wb_stb_i & !wb_err_o; + +// +// Optional registration of WB Ack +// +`ifdef GPIO_REGISTERED_WB_OUTPUTS +always @(posedge wb_clk_i or posedge wb_rst_i) + if (wb_rst_i) + wb_ack_o <= #1 1'b0; + else + wb_ack_o <= #1 wb_ack & ~wb_ack_o & (!wb_err) ; +`else +assign wb_ack_o = wb_ack; +`endif + +// +// WB Error +// +`ifdef GPIO_FULL_DECODE +`ifdef GPIO_STRICT_32BIT_ACCESS +assign wb_err = wb_cyc_i & wb_stb_i & (!full_decoding | (wb_sel_i != 4'b1111)); +`else +assign wb_err = wb_cyc_i & wb_stb_i & !full_decoding; +`endif +`else +`ifdef GPIO_STRICT_32BIT_ACCESS +assign wb_err = wb_cyc_i & wb_stb_i & (wb_sel_i != 4'b1111); +`else +assign wb_err = 1'b0; +`endif +`endif + +// +// Optional registration of WB error +// +`ifdef GPIO_REGISTERED_WB_OUTPUTS +always @(posedge wb_clk_i or posedge wb_rst_i) + if (wb_rst_i) + wb_err_o <= #1 1'b0; + else + wb_err_o <= #1 wb_err & ~wb_err_o; +`else +assign wb_err_o = wb_err; +`endif + +// +// Full address decoder +// +`ifdef GPIO_FULL_DECODE +assign full_decoding = (wb_adr_i[`GPIO_ADDRHH:`GPIO_ADDRHL] == {`GPIO_ADDRHH-`GPIO_ADDRHL+1{1'b0}}) & + (wb_adr_i[`GPIO_ADDRLH:`GPIO_ADDRLL] == {`GPIO_ADDRLH-`GPIO_ADDRLL+1{1'b0}}); +`else +assign full_decoding = 1'b1; +`endif + +// +// GPIO registers address decoder +// +`ifdef GPIO_RGPIO_OUT +assign rgpio_out_sel = wb_cyc_i & wb_stb_i & (wb_adr_i[`GPIO_OFS_BITS] == `GPIO_RGPIO_OUT) & full_decoding; +`endif +`ifdef GPIO_RGPIO_OE +assign rgpio_oe_sel = wb_cyc_i & wb_stb_i & (wb_adr_i[`GPIO_OFS_BITS] == `GPIO_RGPIO_OE) & full_decoding; +`endif +`ifdef GPIO_RGPIO_INTE +assign rgpio_inte_sel = wb_cyc_i & wb_stb_i & (wb_adr_i[`GPIO_OFS_BITS] == `GPIO_RGPIO_INTE) & full_decoding; +`endif +`ifdef GPIO_RGPIO_PTRIG +assign rgpio_ptrig_sel = wb_cyc_i & wb_stb_i & (wb_adr_i[`GPIO_OFS_BITS] == `GPIO_RGPIO_PTRIG) & full_decoding; +`endif +`ifdef GPIO_RGPIO_AUX +assign rgpio_aux_sel = wb_cyc_i & wb_stb_i & (wb_adr_i[`GPIO_OFS_BITS] == `GPIO_RGPIO_AUX) & full_decoding; +`endif +`ifdef GPIO_RGPIO_CTRL +assign rgpio_ctrl_sel = wb_cyc_i & wb_stb_i & (wb_adr_i[`GPIO_OFS_BITS] == `GPIO_RGPIO_CTRL) & full_decoding; +`endif +`ifdef GPIO_RGPIO_INTS +assign rgpio_ints_sel = wb_cyc_i & wb_stb_i & (wb_adr_i[`GPIO_OFS_BITS] == `GPIO_RGPIO_INTS) & full_decoding; +`endif +`ifdef GPIO_RGPIO_ECLK +assign rgpio_eclk_sel = wb_cyc_i & wb_stb_i & (wb_adr_i[`GPIO_OFS_BITS] == `GPIO_RGPIO_ECLK) & full_decoding; +`endif +`ifdef GPIO_RGPIO_NEC +assign rgpio_nec_sel = wb_cyc_i & wb_stb_i & (wb_adr_i[`GPIO_OFS_BITS] == `GPIO_RGPIO_NEC) & full_decoding; +`endif + + +// +// Write to RGPIO_CTRL or update of RGPIO_CTRL[INT] bit +// +`ifdef GPIO_RGPIO_CTRL +always @(posedge wb_clk_i or posedge wb_rst_i) + if (wb_rst_i) + rgpio_ctrl <= #1 2'b0; + else if (rgpio_ctrl_sel && wb_we_i) + rgpio_ctrl <= #1 wb_dat_i[1:0]; + else if (rgpio_ctrl[`GPIO_RGPIO_CTRL_INTE]) + rgpio_ctrl[`GPIO_RGPIO_CTRL_INTS] <= #1 rgpio_ctrl[`GPIO_RGPIO_CTRL_INTS] | wb_inta_o; +`else +assign rgpio_ctrl = 2'h01; // RGPIO_CTRL[EN] = 1 +`endif + +// +// Write to RGPIO_OUT +// +`ifdef GPIO_RGPIO_OUT +always @(posedge wb_clk_i or posedge wb_rst_i) + if (wb_rst_i) + rgpio_out <= #1 {gw{1'b0}}; + else if (rgpio_out_sel && wb_we_i) + begin +`ifdef GPIO_STRICT_32BIT_ACCESS + rgpio_out <= #1 wb_dat_i[gw-1:0]; +`endif + +`ifdef GPIO_WB_BYTES4 + if ( wb_sel_i [3] == 1'b1 ) + rgpio_out [gw-1:24] <= #1 wb_dat_i [gw-1:24] ; + if ( wb_sel_i [2] == 1'b1 ) + rgpio_out [23:16] <= #1 wb_dat_i [23:16] ; + if ( wb_sel_i [1] == 1'b1 ) + rgpio_out [15:8] <= #1 wb_dat_i [15:8] ; + if ( wb_sel_i [0] == 1'b1 ) + rgpio_out [7:0] <= #1 wb_dat_i [7:0] ; +`endif +`ifdef GPIO_WB_BYTES3 + if ( wb_sel_i [2] == 1'b1 ) + rgpio_out [gw-1:16] <= #1 wb_dat_i [gw-1:16] ; + if ( wb_sel_i [1] == 1'b1 ) + rgpio_out [15:8] <= #1 wb_dat_i [15:8] ; + if ( wb_sel_i [0] == 1'b1 ) + rgpio_out [7:0] <= #1 wb_dat_i [7:0] ; +`endif +`ifdef GPIO_WB_BYTES2 + if ( wb_sel_i [1] == 1'b1 ) + rgpio_out [gw-1:8] <= #1 wb_dat_i [gw-1:8] ; + if ( wb_sel_i [0] == 1'b1 ) + rgpio_out [7:0] <= #1 wb_dat_i [7:0] ; +`endif +`ifdef GPIO_WB_BYTES1 + if ( wb_sel_i [0] == 1'b1 ) + rgpio_out [gw-1:0] <= #1 wb_dat_i [gw-1:0] ; +`endif + end + +`else +assign rgpio_out = `GPIO_DEF_RGPIO_OUT; // RGPIO_OUT = 0x0 +`endif + +// +// Write to RGPIO_OE. +// +`ifdef GPIO_RGPIO_OE +always @(posedge wb_clk_i or posedge wb_rst_i) + if (wb_rst_i) + rgpio_oe <= #1 {gw{1'b0}}; + else if (rgpio_oe_sel && wb_we_i) + begin +`ifdef GPIO_STRICT_32BIT_ACCESS + rgpio_oe <= #1 wb_dat_i[gw-1:0]; +`endif + +`ifdef GPIO_WB_BYTES4 + if ( wb_sel_i [3] == 1'b1 ) + rgpio_oe [gw-1:24] <= #1 wb_dat_i [gw-1:24] ; + if ( wb_sel_i [2] == 1'b1 ) + rgpio_oe [23:16] <= #1 wb_dat_i [23:16] ; + if ( wb_sel_i [1] == 1'b1 ) + rgpio_oe [15:8] <= #1 wb_dat_i [15:8] ; + if ( wb_sel_i [0] == 1'b1 ) + rgpio_oe [7:0] <= #1 wb_dat_i [7:0] ; +`endif +`ifdef GPIO_WB_BYTES3 + if ( wb_sel_i [2] == 1'b1 ) + rgpio_oe [gw-1:16] <= #1 wb_dat_i [gw-1:16] ; + if ( wb_sel_i [1] == 1'b1 ) + rgpio_oe [15:8] <= #1 wb_dat_i [15:8] ; + if ( wb_sel_i [0] == 1'b1 ) + rgpio_oe [7:0] <= #1 wb_dat_i [7:0] ; +`endif +`ifdef GPIO_WB_BYTES2 + if ( wb_sel_i [1] == 1'b1 ) + rgpio_oe [gw-1:8] <= #1 wb_dat_i [gw-1:8] ; + if ( wb_sel_i [0] == 1'b1 ) + rgpio_oe [7:0] <= #1 wb_dat_i [7:0] ; +`endif +`ifdef GPIO_WB_BYTES1 + if ( wb_sel_i [0] == 1'b1 ) + rgpio_oe [gw-1:0] <= #1 wb_dat_i [gw-1:0] ; +`endif + end + +`else +assign rgpio_oe = `GPIO_DEF_RGPIO_OE; // RGPIO_OE = 0x0 +`endif + +// +// Write to RGPIO_INTE +// +`ifdef GPIO_RGPIO_INTE +always @(posedge wb_clk_i or posedge wb_rst_i) + if (wb_rst_i) + rgpio_inte <= #1 {gw{1'b0}}; + else if (rgpio_inte_sel && wb_we_i) + begin +`ifdef GPIO_STRICT_32BIT_ACCESS + rgpio_inte <= #1 wb_dat_i[gw-1:0]; +`endif + +`ifdef GPIO_WB_BYTES4 + if ( wb_sel_i [3] == 1'b1 ) + rgpio_inte [gw-1:24] <= #1 wb_dat_i [gw-1:24] ; + if ( wb_sel_i [2] == 1'b1 ) + rgpio_inte [23:16] <= #1 wb_dat_i [23:16] ; + if ( wb_sel_i [1] == 1'b1 ) + rgpio_inte [15:8] <= #1 wb_dat_i [15:8] ; + if ( wb_sel_i [0] == 1'b1 ) + rgpio_inte [7:0] <= #1 wb_dat_i [7:0] ; +`endif +`ifdef GPIO_WB_BYTES3 + if ( wb_sel_i [2] == 1'b1 ) + rgpio_inte [gw-1:16] <= #1 wb_dat_i [gw-1:16] ; + if ( wb_sel_i [1] == 1'b1 ) + rgpio_inte [15:8] <= #1 wb_dat_i [15:8] ; + if ( wb_sel_i [0] == 1'b1 ) + rgpio_inte [7:0] <= #1 wb_dat_i [7:0] ; +`endif +`ifdef GPIO_WB_BYTES2 + if ( wb_sel_i [1] == 1'b1 ) + rgpio_inte [gw-1:8] <= #1 wb_dat_i [gw-1:8] ; + if ( wb_sel_i [0] == 1'b1 ) + rgpio_inte [7:0] <= #1 wb_dat_i [7:0] ; +`endif +`ifdef GPIO_WB_BYTES1 + if ( wb_sel_i [0] == 1'b1 ) + rgpio_inte [gw-1:0] <= #1 wb_dat_i [gw-1:0] ; +`endif + end + + +`else +assign rgpio_inte = `GPIO_DEF_RGPIO_INTE; // RGPIO_INTE = 0x0 +`endif + +// +// Write to RGPIO_PTRIG +// +`ifdef GPIO_RGPIO_PTRIG +always @(posedge wb_clk_i or posedge wb_rst_i) + if (wb_rst_i) + rgpio_ptrig <= #1 {gw{1'b0}}; + else if (rgpio_ptrig_sel && wb_we_i) + begin +`ifdef GPIO_STRICT_32BIT_ACCESS + rgpio_ptrig <= #1 wb_dat_i[gw-1:0]; +`endif + +`ifdef GPIO_WB_BYTES4 + if ( wb_sel_i [3] == 1'b1 ) + rgpio_ptrig [gw-1:24] <= #1 wb_dat_i [gw-1:24] ; + if ( wb_sel_i [2] == 1'b1 ) + rgpio_ptrig [23:16] <= #1 wb_dat_i [23:16] ; + if ( wb_sel_i [1] == 1'b1 ) + rgpio_ptrig [15:8] <= #1 wb_dat_i [15:8] ; + if ( wb_sel_i [0] == 1'b1 ) + rgpio_ptrig [7:0] <= #1 wb_dat_i [7:0] ; +`endif +`ifdef GPIO_WB_BYTES3 + if ( wb_sel_i [2] == 1'b1 ) + rgpio_ptrig [gw-1:16] <= #1 wb_dat_i [gw-1:16] ; + if ( wb_sel_i [1] == 1'b1 ) + rgpio_ptrig [15:8] <= #1 wb_dat_i [15:8] ; + if ( wb_sel_i [0] == 1'b1 ) + rgpio_ptrig [7:0] <= #1 wb_dat_i [7:0] ; +`endif +`ifdef GPIO_WB_BYTES2 + if ( wb_sel_i [1] == 1'b1 ) + rgpio_ptrig [gw-1:8] <= #1 wb_dat_i [gw-1:8] ; + if ( wb_sel_i [0] == 1'b1 ) + rgpio_ptrig [7:0] <= #1 wb_dat_i [7:0] ; +`endif +`ifdef GPIO_WB_BYTES1 + if ( wb_sel_i [0] == 1'b1 ) + rgpio_ptrig [gw-1:0] <= #1 wb_dat_i [gw-1:0] ; +`endif + end + +`else +assign rgpio_ptrig = `GPIO_DEF_RGPIO_PTRIG; // RGPIO_PTRIG = 0x0 +`endif + +// +// Write to RGPIO_AUX +// +`ifdef GPIO_RGPIO_AUX +always @(posedge wb_clk_i or posedge wb_rst_i) + if (wb_rst_i) + rgpio_aux <= #1 {gw{1'b0}}; + else if (rgpio_aux_sel && wb_we_i) + begin +`ifdef GPIO_STRICT_32BIT_ACCESS + rgpio_aux <= #1 wb_dat_i[gw-1:0]; +`endif + +`ifdef GPIO_WB_BYTES4 + if ( wb_sel_i [3] == 1'b1 ) + rgpio_aux [gw-1:24] <= #1 wb_dat_i [gw-1:24] ; + if ( wb_sel_i [2] == 1'b1 ) + rgpio_aux [23:16] <= #1 wb_dat_i [23:16] ; + if ( wb_sel_i [1] == 1'b1 ) + rgpio_aux [15:8] <= #1 wb_dat_i [15:8] ; + if ( wb_sel_i [0] == 1'b1 ) + rgpio_aux [7:0] <= #1 wb_dat_i [7:0] ; +`endif +`ifdef GPIO_WB_BYTES3 + if ( wb_sel_i [2] == 1'b1 ) + rgpio_aux [gw-1:16] <= #1 wb_dat_i [gw-1:16] ; + if ( wb_sel_i [1] == 1'b1 ) + rgpio_aux [15:8] <= #1 wb_dat_i [15:8] ; + if ( wb_sel_i [0] == 1'b1 ) + rgpio_aux [7:0] <= #1 wb_dat_i [7:0] ; +`endif +`ifdef GPIO_WB_BYTES2 + if ( wb_sel_i [1] == 1'b1 ) + rgpio_aux [gw-1:8] <= #1 wb_dat_i [gw-1:8] ; + if ( wb_sel_i [0] == 1'b1 ) + rgpio_aux [7:0] <= #1 wb_dat_i [7:0] ; +`endif +`ifdef GPIO_WB_BYTES1 + if ( wb_sel_i [0] == 1'b1 ) + rgpio_aux [gw-1:0] <= #1 wb_dat_i [gw-1:0] ; +`endif + end + +`else +assign rgpio_aux = `GPIO_DEF_RGPIO_AUX; // RGPIO_AUX = 0x0 +`endif + + +// +// Write to RGPIO_ECLK +// +`ifdef GPIO_RGPIO_ECLK +always @(posedge wb_clk_i or posedge wb_rst_i) + if (wb_rst_i) + rgpio_eclk <= #1 {gw{1'b0}}; + else if (rgpio_eclk_sel && wb_we_i) + begin +`ifdef GPIO_STRICT_32BIT_ACCESS + rgpio_eclk <= #1 wb_dat_i[gw-1:0]; +`endif + +`ifdef GPIO_WB_BYTES4 + if ( wb_sel_i [3] == 1'b1 ) + rgpio_eclk [gw-1:24] <= #1 wb_dat_i [gw-1:24] ; + if ( wb_sel_i [2] == 1'b1 ) + rgpio_eclk [23:16] <= #1 wb_dat_i [23:16] ; + if ( wb_sel_i [1] == 1'b1 ) + rgpio_eclk [15:8] <= #1 wb_dat_i [15:8] ; + if ( wb_sel_i [0] == 1'b1 ) + rgpio_eclk [7:0] <= #1 wb_dat_i [7:0] ; +`endif +`ifdef GPIO_WB_BYTES3 + if ( wb_sel_i [2] == 1'b1 ) + rgpio_eclk [gw-1:16] <= #1 wb_dat_i [gw-1:16] ; + if ( wb_sel_i [1] == 1'b1 ) + rgpio_eclk [15:8] <= #1 wb_dat_i [15:8] ; + if ( wb_sel_i [0] == 1'b1 ) + rgpio_eclk [7:0] <= #1 wb_dat_i [7:0] ; +`endif +`ifdef GPIO_WB_BYTES2 + if ( wb_sel_i [1] == 1'b1 ) + rgpio_eclk [gw-1:8] <= #1 wb_dat_i [gw-1:8] ; + if ( wb_sel_i [0] == 1'b1 ) + rgpio_eclk [7:0] <= #1 wb_dat_i [7:0] ; +`endif +`ifdef GPIO_WB_BYTES1 + if ( wb_sel_i [0] == 1'b1 ) + rgpio_eclk [gw-1:0] <= #1 wb_dat_i [gw-1:0] ; +`endif + end + + +`else +assign rgpio_eclk = `GPIO_DEF_RGPIO_ECLK; // RGPIO_ECLK = 0x0 +`endif + + + +// +// Write to RGPIO_NEC +// +`ifdef GPIO_RGPIO_NEC +always @(posedge wb_clk_i or posedge wb_rst_i) + if (wb_rst_i) + rgpio_nec <= #1 {gw{1'b0}}; + else if (rgpio_nec_sel && wb_we_i) + begin +`ifdef GPIO_STRICT_32BIT_ACCESS + rgpio_nec <= #1 wb_dat_i[gw-1:0]; +`endif + +`ifdef GPIO_WB_BYTES4 + if ( wb_sel_i [3] == 1'b1 ) + rgpio_nec [gw-1:24] <= #1 wb_dat_i [gw-1:24] ; + if ( wb_sel_i [2] == 1'b1 ) + rgpio_nec [23:16] <= #1 wb_dat_i [23:16] ; + if ( wb_sel_i [1] == 1'b1 ) + rgpio_nec [15:8] <= #1 wb_dat_i [15:8] ; + if ( wb_sel_i [0] == 1'b1 ) + rgpio_nec [7:0] <= #1 wb_dat_i [7:0] ; +`endif +`ifdef GPIO_WB_BYTES3 + if ( wb_sel_i [2] == 1'b1 ) + rgpio_nec [gw-1:16] <= #1 wb_dat_i [gw-1:16] ; + if ( wb_sel_i [1] == 1'b1 ) + rgpio_nec [15:8] <= #1 wb_dat_i [15:8] ; + if ( wb_sel_i [0] == 1'b1 ) + rgpio_nec [7:0] <= #1 wb_dat_i [7:0] ; +`endif +`ifdef GPIO_WB_BYTES2 + if ( wb_sel_i [1] == 1'b1 ) + rgpio_nec [gw-1:8] <= #1 wb_dat_i [gw-1:8] ; + if ( wb_sel_i [0] == 1'b1 ) + rgpio_nec [7:0] <= #1 wb_dat_i [7:0] ; +`endif +`ifdef GPIO_WB_BYTES1 + if ( wb_sel_i [0] == 1'b1 ) + rgpio_nec [gw-1:0] <= #1 wb_dat_i [gw-1:0] ; +`endif + end + + +`else +assign rgpio_nec = `GPIO_DEF_RGPIO_NEC; // RGPIO_NEC = 0x0 +`endif + +// +// synchronize inputs to systam clock +// +`ifdef GPIO_SYNC_IN_WB +always @(posedge wb_clk_i or posedge wb_rst_i) + if (wb_rst_i) begin + sync <= #1 {gw{1'b0}} ; + ext_pad_s <= #1 {gw{1'b0}} ; + end else begin + sync <= #1 ext_pad_i ; + ext_pad_s <= #1 sync ; + end +`else +assign ext_pad_s = ext_pad_i; +`endif // GPIO_SYNC_IN_WB + +// +// Latch into RGPIO_IN +// +`ifdef GPIO_RGPIO_IN +always @(posedge wb_clk_i or posedge wb_rst_i) + if (wb_rst_i) + rgpio_in <= #1 {gw{1'b0}}; + else + rgpio_in <= #1 in_muxed; +`else +assign rgpio_in = in_muxed; +`endif + +`ifdef GPIO_CLKPAD + +`ifdef GPIO_SYNC_CLK_WB +// +// external clock enabled +// synchronized to system clock +// (one clock domain) +// + +reg sync_clk, + clk_s , + clk_r ; +wire pedge , + nedge ; +wire [gw-1:0] pedge_vec , + nedge_vec ; +wire [gw-1:0] in_lach ; + +assign pedge = clk_s & !clk_r ; +assign nedge = !clk_s & clk_r ; +assign pedge_vec = {gw{pedge}} ; +assign nedge_vec = {gw{nedge}} ; + +assign in_lach = (~rgpio_nec & pedge_vec) | (rgpio_nec & nedge_vec) ; +assign extc_in = (in_lach & ext_pad_s) | (~in_lach & pextc_sampled) ; + +always @(posedge wb_clk_i or posedge wb_rst_i) + if (wb_rst_i) begin + sync_clk <= #1 1'b0 ; + clk_s <= #1 1'b0 ; + clk_r <= #1 1'b0 ; + end else begin + sync_clk <= #1 clk_pad_i ; + clk_s <= #1 sync_clk ; + clk_r <= #1 clk_s ; + end + +always @(posedge wb_clk_i or posedge wb_rst_i) + if (wb_rst_i) begin + pextc_sampled <= #1 {gw{1'b0}}; + end else begin + pextc_sampled <= #1 extc_in ; + end + +assign in_muxed = (rgpio_eclk & pextc_sampled) | (~rgpio_eclk & ext_pad_s) ; + +`else +// +// external clock enabled +// not synchronized to system clock +// (two clock domains) +// + +`ifdef GPIO_SYNC_IN_CLK_WB + +reg [gw-1:0] syn_extc , + extc_s ; + +always @(posedge wb_clk_i or posedge wb_rst_i) + if (wb_rst_i) begin + syn_extc <= #1 {gw{1'b0}}; + extc_s <= #1 {gw{1'b0}}; + end else begin + syn_extc <= #1 extc_in ; + extc_s <= #1 syn_extc; + end + +`else + +wire [gw-1:0] extc_s ; +assign extc_s = syn_extc ; + +`endif // GPIO_SYNC_IN_CLK_WB + +`ifdef GPIO_SYNC_IN_CLK +reg [gw-1:0] syn_pclk , + ext_pad_spc ; + +always @(posedge clk_pad_i or posedge wb_rst_i) + if (wb_rst_i) begin + syn_pclk <= #1 {gw{1'b0}} ; + ext_pad_spc <= #1 {gw{1'b0}} ; + end else begin + syn_pclk <= #1 ext_pad_i ; + ext_pad_spc <= #1 syn_pclk ; + end + +`else + +wire [gw-1:0] ext_pad_spc ; +assign ext_pad_spc = ext_pad_i ; + +`endif // GPIO_SYNC_IN_CLK + +always @(posedge clk_pad_i or posedge wb_rst_i) + if (wb_rst_i) begin + pextc_sampled <= #1 {gw{1'b0}}; + end else begin + pextc_sampled <= #1 ext_pad_spc ; + end + + +`ifdef GPIO_NO_NEGEDGE_FLOPS + +`ifdef GPIO_NO_CLKPAD_LOGIC + +assign extc_in = pextc_sampled; + +`else + +wire clk_n; +assign clk_n = !clk_pad_i; + +`ifdef GPIO_SYNC_IN_CLK +reg [gw-1:0] syn_nclk , + ext_pad_snc ; + +always @(posedge clk_n or posedge wb_rst_i) + if (wb_rst_i) begin + syn_nclk <= #1 {gw{1'b0}} ; + ext_pad_snc <= #1 {gw{1'b0}} ; + end else begin + syn_nclk <= #1 ext_pad_i ; + ext_pad_snc <= #1 syn_nclk ; + end + +`else + +wire [gw-1:0] ext_pad_snc ; +assign ext_pad_snc = ext_pad_i ; + +`endif // GPIO_SYNC_IN_CLK + +always @(posedge clk_n or posedge wb_rst_i) + if (wb_rst_i) begin + nextc_sampled <= #1 {gw{1'b0}}; + end else begin + nextc_sampled <= #1 ext_pad_snc ; + end + +assign extc_in = (~rgpio_nec & pextc_sampled) | (rgpio_nec & nextc_sampled) ; + +`endif // GPIO_NO_CLKPAD_LOGIC + + +`else + +`ifdef GPIO_SYNC_IN_CLK +reg [gw-1:0] syn_nclk , + ext_pad_snc ; + +always @(negedge clk_n or posedge wb_rst_i) + if (wb_rst_i) begin + syn_nclk <= #1 {gw{1'b0}} ; + ext_pad_snc <= #1 {gw{1'b0}} ; + end else begin + syn_nclk <= #1 ext_pad_i ; + ext_pad_snc <= #1 syn_nclk ; + end + +`else + +wire [gw-1:0] ext_pad_snc ; +assign ext_pad_snc = ext_pad_i ; + +`endif // GPIO_SYNC_IN_CLK + +always @(negedge clk_pad_i or posedge wb_rst_i) + if (wb_rst_i) begin + nextc_sampled <= #1 {gw{1'b0}}; + end else begin + nextc_sampled <= #1 ext_pad_snc ; + end + +assign extc_in = (~rgpio_nec & pextc_sampled) | (rgpio_nec & nextc_sampled) ; + +`endif // GPIO_NO_NEGEDGE_FLOPS + +assign in_muxed = (rgpio_eclk & extc_s) | (~rgpio_eclk & ext_pad_s) ; + + +`endif // GPIO_SYNC_CLK_WB + + +`else + +assign in_muxed = ext_pad_s ; + +`endif // GPIO_CLKPAD + + + +// +// Mux all registers when doing a read of GPIO registers +// +always @(wb_adr_i or rgpio_in or rgpio_out or rgpio_oe or rgpio_inte or + rgpio_ptrig or rgpio_aux or rgpio_ctrl or rgpio_ints or rgpio_eclk or rgpio_nec) + case (wb_adr_i[`GPIO_OFS_BITS]) // synopsys full_case parallel_case +`ifdef GPIO_READREGS + `ifdef GPIO_RGPIO_OUT + `GPIO_RGPIO_OUT: begin + wb_dat[dw-1:0] = rgpio_out; + end + `endif + `ifdef GPIO_RGPIO_OE + `GPIO_RGPIO_OE: begin + wb_dat[dw-1:0] = rgpio_oe; + end + `endif + `ifdef GPIO_RGPIO_INTE + `GPIO_RGPIO_INTE: begin + wb_dat[dw-1:0] = rgpio_inte; + end + `endif + `ifdef GPIO_RGPIO_PTRIG + `GPIO_RGPIO_PTRIG: begin + wb_dat[dw-1:0] = rgpio_ptrig; + end + `endif + `ifdef GPIO_RGPIO_NEC + `GPIO_RGPIO_NEC: begin + wb_dat[dw-1:0] = rgpio_nec; + end + `endif + `ifdef GPIO_RGPIO_ECLK + `GPIO_RGPIO_ECLK: begin + wb_dat[dw-1:0] = rgpio_eclk; + end + `endif + `ifdef GPIO_RGPIO_AUX + `GPIO_RGPIO_AUX: begin + wb_dat[dw-1:0] = rgpio_aux; + end + `endif + `ifdef GPIO_RGPIO_CTRL + `GPIO_RGPIO_CTRL: begin + wb_dat[1:0] = rgpio_ctrl; + wb_dat[dw-1:2] = {dw-2{1'b0}}; + end + `endif +`endif + `ifdef GPIO_RGPIO_INTS + `GPIO_RGPIO_INTS: begin + wb_dat[dw-1:0] = rgpio_ints; + end + `endif + default: begin + wb_dat[dw-1:0] = rgpio_in; + end + endcase + +// +// WB data output +// +`ifdef GPIO_REGISTERED_WB_OUTPUTS +always @(posedge wb_clk_i or posedge wb_rst_i) + if (wb_rst_i) + wb_dat_o <= #1 {dw{1'b0}}; + else + wb_dat_o <= #1 wb_dat; +`else +assign wb_dat_o = wb_dat; +`endif + +// +// RGPIO_INTS +// +`ifdef GPIO_RGPIO_INTS +always @(posedge wb_clk_i or posedge wb_rst_i) + if (wb_rst_i) + rgpio_ints <= #1 {gw{1'b0}}; + else if (rgpio_ints_sel && wb_we_i) + rgpio_ints <= #1 wb_dat_i[gw-1:0]; + else if (rgpio_ctrl[`GPIO_RGPIO_CTRL_INTE]) + rgpio_ints <= #1 (rgpio_ints | ((in_muxed ^ rgpio_in) & ~(in_muxed ^ rgpio_ptrig)) & rgpio_inte); +`else +assign rgpio_ints = (rgpio_ints | ((in_muxed ^ rgpio_in) & ~(in_muxed ^ rgpio_ptrig)) & rgpio_inte); +`endif + +// +// Generate interrupt request +// +assign wb_inta = |rgpio_ints ? rgpio_ctrl[`GPIO_RGPIO_CTRL_INTE] : 1'b0; + +// +// Optional registration of WB interrupt +// +`ifdef GPIO_REGISTERED_WB_OUTPUTS +always @(posedge wb_clk_i or posedge wb_rst_i) + if (wb_rst_i) + wb_inta_o <= #1 1'b0; + else + wb_inta_o <= #1 wb_inta; +`else +assign wb_inta_o = wb_inta; +`endif // GPIO_REGISTERED_WB_OUTPUTS + +// +// Output enables are RGPIO_OE bits +// +assign ext_padoe_o = rgpio_oe; + +// +// Generate GPIO outputs +// +`ifdef GPIO_AUX_IMPLEMENT +assign out_pad = rgpio_out & ~rgpio_aux | aux_i & rgpio_aux; +`else +assign out_pad = rgpio_out ; +`endif // GPIO_AUX_IMPLEMENT + +// +// Optional registration of GPIO outputs +// +`ifdef GPIO_REGISTERED_IO_OUTPUTS +always @(posedge wb_clk_i or posedge wb_rst_i) + if (wb_rst_i) + ext_pad_o <= #1 {gw{1'b0}}; + else + ext_pad_o <= #1 out_pad; +`else +assign ext_pad_o = out_pad; +`endif // GPIO_REGISTERED_IO_OUTPUTS + + +`else + +// +// When GPIO is not implemented, drive all outputs as would when RGPIO_CTRL +// is cleared and WISHBONE transfers complete with errors +// +assign wb_inta_o = 1'b0; +assign wb_ack_o = 1'b0; +assign wb_err_o = wb_cyc_i & wb_stb_i; +assign ext_padoe_o = {gw{1'b1}}; +assign ext_pad_o = {gw{1'b0}}; + +// +// Read GPIO registers +// +assign wb_dat_o = {dw{1'b0}}; + +`endif // GPIO_IMPLEMENTED + +endmodule + Index: release-1.0/utils/contributions/gpio/rtl/minsoc_top.ucf =================================================================== --- release-1.0/utils/contributions/gpio/rtl/minsoc_top.ucf (nonexistent) +++ release-1.0/utils/contributions/gpio/rtl/minsoc_top.ucf (revision 151) @@ -0,0 +1,36 @@ + +NET "clk" LOC = E12; # 50 MHz on-board clock oscillator +NET "reset" LOC = T14; # Push Button BTN_NORTH + +# UART Peripheral +NET "uart_stx" LOC = E15; # RS232 Serial port ( DTE Connector ) +NET "uart_srx" LOC = F16; # + +# GPIO +NET "io_pins<0>" LOC = R20; +NET "io_pins<1>" LOC = T19; +NET "io_pins<2>" LOC = U20; +NET "io_pins<3>" LOC = U19; +NET "io_pins<4>" LOC = V19; +NET "io_pins<5>" LOC = V20; +NET "io_pins<6>" LOC = Y22; +NET "io_pins<7>" LOC = W21; + +NET "i_pins<0>" LOC = V8; +NET "i_pins<1>" LOC = U10; +NET "i_pins<2>" LOC = U8; +NET "i_pins<3>" LOC = T9; +NET "i_pins<4>" LOC = T16; +NET "i_pins<5>" LOC = U15; +#NET "i_pins<6>" LOC = ; +NET "i_pins<7>" LOC = T15; + +################################################################################# +# Pin constraints including the IOSTANDARD and DRIVE +# Reference : Spartan-3A/3AN FPGA Starter Kit Board User Guide ( UG334 v1.1 ) +################################################################################# + +#NET "clk" LOC = E12 | IOSTANDARD = LVCMOS33; +#NET "uart_stx" LOC = E15 | IOSTANDARD = LVCMOS33 | DRIVE = 8 | SLEW = SLOW ; +#NET "uart_srx" LOC = F16 | IOSTANDARD = LVCMOS33; +#NET "reset" LOC = T14 | IOSTANDARD = LVCMOS33 | PULLDOWN ; Index: release-1.0/utils/contributions/gpio/rtl/minsoc_defines.v =================================================================== --- release-1.0/utils/contributions/gpio/rtl/minsoc_defines.v (nonexistent) +++ release-1.0/utils/contributions/gpio/rtl/minsoc_defines.v (revision 151) @@ -0,0 +1,130 @@ +// +// Define FPGA manufacturer +// +//`define GENERIC_FPGA +//`define ALTERA_FPGA +`define XILINX_FPGA + +// +// Define FPGA Model (comment all out for ALTERA) +// +//`define SPARTAN2 +//`define SPARTAN3 +//`define SPARTAN3E +`define SPARTAN3A +//`define VIRTEX +//`define VIRTEX2 +//`define VIRTEX4 +//`define VIRTEX5 + + +// +// Memory +// +`define MEMORY_ADR_WIDTH 13 //MEMORY_ADR_WIDTH IS NOT ALLOWED TO BE LESS THAN 12, memory is composed by blocks of address width 11 + //Address width of memory -> select memory depth, 2 powers MEMORY_ADR_WIDTH defines the memory depth + //the memory data width is 32 bit, memory amount in Bytes = 4*memory depth + +// +// Memory type (uncomment something if ASIC or generic memory) +// +//`define GENERIC_MEMORY +//`define AVANT_ATP +//`define VIRAGE_SSP +//`define VIRTUALSILICON_SSP + + +// +// TAP selection +// +//`define GENERIC_TAP +`define FPGA_TAP + +// +// Clock Division selection +// +//`define NO_CLOCK_DIVISION +//`define GENERIC_CLOCK_DIVISION +`define FPGA_CLOCK_DIVISION //Altera ALTPLL is not implemented, didn't find the code for its verilog instantiation + //if you selected altera and this, the GENERIC_CLOCK_DIVISION will be automatically taken + +// +// Define division +// +`define CLOCK_DIVISOR 5 //in case of GENERIC_CLOCK_DIVISION the real value will be rounded down to an even value + //in FPGA case, check minsoc_clock_manager for allowed divisors + //DO NOT USE CLOCK_DIVISOR = 1 COMMENT THE CLOCK DIVISION SELECTION INSTEAD + +// +// Reset polarity +// +//`define NEGATIVE_RESET; //rstn +`define POSITIVE_RESET; //rst + +// +// Start-up circuit (only necessary later to load firmware automatically from SPI memory) +// +//`define START_UP + +// +// Connected modules +// +`define UART +//`define ETHERNET +`define GPIO + +// +// Ethernet reset +// +//`define ETH_RESET 1'b0 +`define ETH_RESET 1'b1 + +// +// GPIO Pins +// +`define GPIO_HAS_INPUT_PINS +//`define GPIO_HAS_OUTPUT_PINS +`define GPIO_HAS_BIDIR_PINS + +`define GPIO_NUM_INPUT 4'd8 +`define GPIO_NUM_OUTPUT 4'd0 +`define GPIO_NUM_BIDIR 4'd8 + +// +// Interrupts +// +`define APP_INT_RES1 1:0 +`define APP_INT_UART 2 +`define APP_INT_RES2 3 +`define APP_INT_ETH 4 +`define APP_INT_PS2 5 +`define APP_INT_GPIO 6 +`define APP_INT_RES3 19:7 + +// +// Address map +// +`define APP_ADDR_DEC_W 8 +`define APP_ADDR_SRAM `APP_ADDR_DEC_W'h00 +`define APP_ADDR_FLASH `APP_ADDR_DEC_W'h04 +`define APP_ADDR_DECP_W 4 +`define APP_ADDR_PERIP `APP_ADDR_DECP_W'h9 +`define APP_ADDR_SPI `APP_ADDR_DEC_W'h97 +`define APP_ADDR_ETH `APP_ADDR_DEC_W'h92 +`define APP_ADDR_AUDIO `APP_ADDR_DEC_W'h9d +`define APP_ADDR_UART `APP_ADDR_DEC_W'h90 +`define APP_ADDR_PS2 `APP_ADDR_DEC_W'h94 +`define APP_ADDR_GPIO `APP_ADDR_DEC_W'h9e +`define APP_ADDR_RES2 `APP_ADDR_DEC_W'h9f + +// +// Set-up GENERIC_TAP, GENERIC_MEMORY if GENERIC_FPGA was chosen +// and GENERIC_CLOCK_DIVISION if NO_CLOCK_DIVISION was not set +// +`ifdef GENERIC_FPGA + `define GENERIC_TAP + `define GENERIC_MEMORY + `ifndef NO_CLOCK_DIVISION + `define GENERIC_CLOCK_DIVISION + `endif +`endif Index: release-1.0/utils/contributions/gpio/rtl/minsoc_spartan_3a_starter_kit_ios.v =================================================================== --- release-1.0/utils/contributions/gpio/rtl/minsoc_spartan_3a_starter_kit_ios.v (nonexistent) +++ release-1.0/utils/contributions/gpio/rtl/minsoc_spartan_3a_starter_kit_ios.v (revision 151) @@ -0,0 +1,224 @@ +////////////////////////////////////////////////////////////////////////////////// +// Company: +// Engineer: +// +// Create Date: 11:51:27 10/29/2009 +// Design Name: +// Module Name: minsoc_spartan_3a_starter_kit_ios +// Project Name: +// Target Devices: +// Tool versions: +// Description: +// +// Dependencies: +// +// Revision: +// Revision 0.01 - File Created +// Additional Comments: +// +////////////////////////////////////////////////////////////////////////////////// + +module minsoc_spartan_3a_starter_kit_ios +( + // Signals from GPIO Core + ext_pad_o, + ext_pad_oe, + ext_pad_i, + + // Signals driving external pins + i_pins, + o_pins, + io_pins +); + parameter gpio_num = 32; + parameter i_line_num = 8; + parameter o_line_num = 8; + parameter io_line_num= 8; + + input [gpio_num-1:0] ext_pad_o; + input [gpio_num-1:0] ext_pad_oe; + output [gpio_num-1:0] ext_pad_i; + + input [i_line_num-1:0] i_pins; + output [o_line_num-1:0] o_pins; + inout [io_line_num-1:0] io_pins; + + IOBUF #( + .DRIVE(12), // Specify the output drive strength + .IBUF_DELAY_VALUE("0"), // Specify the amount of added input delay for the buffer, "0"-"16" (Spartan-3E only) + .IFD_DELAY_VALUE("AUTO"), // Specify the amount of added delay for input register, "AUTO", "0"-"8" (Spartan-3E only) + .IOSTANDARD("DEFAULT"), // Specify the I/O standard + .SLEW("SLOW") // Specify the output slew rate + ) IOBUF_inst_0 ( + .O(ext_pad_i[0]), // Buffer output + .IO(io_pins[0]), // Buffer inout port (connect directly to top-level port) + .I(ext_pad_o[0]), // Buffer input + .T(~ext_pad_oe[0]) // 3-state enable input + ); + + IOBUF #( + .DRIVE(12), // Specify the output drive strength + .IBUF_DELAY_VALUE("0"), // Specify the amount of added input delay for the buffer, "0"-"16" (Spartan-3E only) + .IFD_DELAY_VALUE("AUTO"), // Specify the amount of added delay for input register, "AUTO", "0"-"8" (Spartan-3E only) + .IOSTANDARD("DEFAULT"), // Specify the I/O standard + .SLEW("SLOW") // Specify the output slew rate + ) IOBUF_inst_1 ( + .O(ext_pad_i[1]), // Buffer output + .IO(io_pins[1]), // Buffer inout port (connect directly to top-level port) + .I(ext_pad_o[1]), // Buffer input + .T(~ext_pad_oe[1]) // 3-state enable input + ); + + IOBUF #( + .DRIVE(12), // Specify the output drive strength + .IBUF_DELAY_VALUE("0"), // Specify the amount of added input delay for the buffer, "0"-"16" (Spartan-3E only) + .IFD_DELAY_VALUE("AUTO"), // Specify the amount of added delay for input register, "AUTO", "0"-"8" (Spartan-3E only) + .IOSTANDARD("DEFAULT"), // Specify the I/O standard + .SLEW("SLOW") // Specify the output slew rate + ) IOBUF_inst_2 ( + .O(ext_pad_i[2]), // Buffer output + .IO(io_pins[2]), // Buffer inout port (connect directly to top-level port) + .I(ext_pad_o[2]), // Buffer input + .T(~ext_pad_oe[2]) // 3-state enable input + ); + + IOBUF #( + .DRIVE(12), // Specify the output drive strength + .IBUF_DELAY_VALUE("0"), // Specify the amount of added input delay for the buffer, "0"-"16" (Spartan-3E only) + .IFD_DELAY_VALUE("AUTO"), // Specify the amount of added delay for input register, "AUTO", "0"-"8" (Spartan-3E only) + .IOSTANDARD("DEFAULT"), // Specify the I/O standard + .SLEW("SLOW") // Specify the output slew rate + ) IOBUF_inst_3 ( + .O(ext_pad_i[3]), // Buffer output + .IO(io_pins[3]), // Buffer inout port (connect directly to top-level port) + .I(ext_pad_o[3]), // Buffer input + .T(~ext_pad_oe[3]) // 3-state enable input + ); + + IOBUF #( + .DRIVE(12), // Specify the output drive strength + .IBUF_DELAY_VALUE("0"), // Specify the amount of added input delay for the buffer, "0"-"16" (Spartan-3E only) + .IFD_DELAY_VALUE("AUTO"), // Specify the amount of added delay for input register, "AUTO", "0"-"8" (Spartan-3E only) + .IOSTANDARD("DEFAULT"), // Specify the I/O standard + .SLEW("SLOW") // Specify the output slew rate + ) IOBUF_inst_4 ( + .O(ext_pad_i[4]), // Buffer output + .IO(io_pins[4]), // Buffer inout port (connect directly to top-level port) + .I(ext_pad_o[4]), // Buffer input + .T(~ext_pad_oe[4]) // 3-state enable input + ); + + IOBUF #( + .DRIVE(12), // Specify the output drive strength + .IBUF_DELAY_VALUE("0"), // Specify the amount of added input delay for the buffer, "0"-"16" (Spartan-3E only) + .IFD_DELAY_VALUE("AUTO"), // Specify the amount of added delay for input register, "AUTO", "0"-"8" (Spartan-3E only) + .IOSTANDARD("DEFAULT"), // Specify the I/O standard + .SLEW("SLOW") // Specify the output slew rate + ) IOBUF_inst_5 ( + .O(ext_pad_i[5]), // Buffer output + .IO(io_pins[5]), // Buffer inout port (connect directly to top-level port) + .I(ext_pad_o[5]), // Buffer input + .T(~ext_pad_oe[5]) // 3-state enable input + ); + + IOBUF #( + .DRIVE(12), // Specify the output drive strength + .IBUF_DELAY_VALUE("0"), // Specify the amount of added input delay for the buffer, "0"-"16" (Spartan-3E only) + .IFD_DELAY_VALUE("AUTO"), // Specify the amount of added delay for input register, "AUTO", "0"-"8" (Spartan-3E only) + .IOSTANDARD("DEFAULT"), // Specify the I/O standard + .SLEW("SLOW") // Specify the output slew rate + ) IOBUF_inst_6 ( + .O(ext_pad_i[6]), // Buffer output + .IO(io_pins[6]), // Buffer inout port (connect directly to top-level port) + .I(ext_pad_o[6]), // Buffer input + .T(~ext_pad_oe[6]) // 3-state enable input + ); + + IOBUF #( + .DRIVE(12), // Specify the output drive strength + .IBUF_DELAY_VALUE("0"), // Specify the amount of added input delay for the buffer, "0"-"16" (Spartan-3E only) + .IFD_DELAY_VALUE("AUTO"), // Specify the amount of added delay for input register, "AUTO", "0"-"8" (Spartan-3E only) + .IOSTANDARD("DEFAULT"), // Specify the I/O standard + .SLEW("SLOW") // Specify the output slew rate + ) IOBUF_inst_7 ( + .O(ext_pad_i[7]), // Buffer output + .IO(io_pins[7]), // Buffer inout port (connect directly to top-level port) + .I(ext_pad_o[7]), // Buffer input + .T(~ext_pad_oe[7]) // 3-state enable input + ); + + + IBUF #( + .IBUF_DELAY_VALUE("0"), // Specify the amount of added input delay for // the buffer, "0"-"16" (Spartan-3E/3A only) + .IFD_DELAY_VALUE("AUTO"), // Specify the amount of added delay for input // register, "AUTO", "0"-"8" (Spartan-3E/3A only) + .IOSTANDARD("DEFAULT") // Specify the input I/O standard + )IBUF_inst_0 ( + .O(ext_pad_i[8]), // Buffer output + .I(i_pins[0]) // Buffer input (connect directly to top-level port) + ); + + IBUF #( + .IBUF_DELAY_VALUE("0"), // Specify the amount of added input delay for // the buffer, "0"-"16" (Spartan-3E/3A only) + .IFD_DELAY_VALUE("AUTO"), // Specify the amount of added delay for input // register, "AUTO", "0"-"8" (Spartan-3E/3A only) + .IOSTANDARD("DEFAULT") // Specify the input I/O standard + )IBUF_inst_1 ( + .O(ext_pad_i[9]), // Buffer output + .I(i_pins[1]) // Buffer input (connect directly to top-level port) + ); + + IBUF #( + .IBUF_DELAY_VALUE("0"), // Specify the amount of added input delay for // the buffer, "0"-"16" (Spartan-3E/3A only) + .IFD_DELAY_VALUE("AUTO"), // Specify the amount of added delay for input // register, "AUTO", "0"-"8" (Spartan-3E/3A only) + .IOSTANDARD("DEFAULT") // Specify the input I/O standard + )IBUF_inst_2 ( + .O(ext_pad_i[10]), // Buffer output + .I(i_pins[2]) // Buffer input (connect directly to top-level port) + ); + + IBUF #( + .IBUF_DELAY_VALUE("0"), // Specify the amount of added input delay for // the buffer, "0"-"16" (Spartan-3E/3A only) + .IFD_DELAY_VALUE("AUTO"), // Specify the amount of added delay for input // register, "AUTO", "0"-"8" (Spartan-3E/3A only) + .IOSTANDARD("DEFAULT") // Specify the input I/O standard + )IBUF_inst_3 ( + .O(ext_pad_i[11]), // Buffer output + .I(i_pins[3]) // Buffer input (connect directly to top-level port) + ); + + IBUF #( + .IBUF_DELAY_VALUE("0"), // Specify the amount of added input delay for // the buffer, "0"-"16" (Spartan-3E/3A only) + .IFD_DELAY_VALUE("AUTO"), // Specify the amount of added delay for input // register, "AUTO", "0"-"8" (Spartan-3E/3A only) + .IOSTANDARD("DEFAULT") // Specify the input I/O standard + )IBUF_inst_4 ( + .O(ext_pad_i[12]), // Buffer output + .I(i_pins[4]) // Buffer input (connect directly to top-level port) + ); + + IBUF #( + .IBUF_DELAY_VALUE("0"), // Specify the amount of added input delay for // the buffer, "0"-"16" (Spartan-3E/3A only) + .IFD_DELAY_VALUE("AUTO"), // Specify the amount of added delay for input // register, "AUTO", "0"-"8" (Spartan-3E/3A only) + .IOSTANDARD("DEFAULT") // Specify the input I/O standard + )IBUF_inst_5 ( + .O(ext_pad_i[13]), // Buffer output + .I(i_pins[5]) // Buffer input (connect directly to top-level port) + ); + + /* PUSH Button NORTH is RESET. + IBUF #( + .IBUF_DELAY_VALUE("0"), // Specify the amount of added input delay for // the buffer, "0"-"16" (Spartan-3E/3A only) + .IFD_DELAY_VALUE("AUTO"), // Specify the amount of added delay for input // register, "AUTO", "0"-"8" (Spartan-3E/3A only) + .IOSTANDARD("DEFAULT") // Specify the input I/O standard + )IBUF_inst_6 ( + .O(ext_pad_i[14]), // Buffer output + .I(i_pins[6]) // Buffer input (connect directly to top-level port) + ); + */ + + IBUF #( + .IBUF_DELAY_VALUE("0"), // Specify the amount of added input delay for // the buffer, "0"-"16" (Spartan-3E/3A only) + .IFD_DELAY_VALUE("AUTO"), // Specify the amount of added delay for input // register, "AUTO", "0"-"8" (Spartan-3E/3A only) + .IOSTANDARD("DEFAULT") // Specify the input I/O standard + )IBUF_inst_7 ( + .O(ext_pad_i[15]), // Buffer output + .I(i_pins[7]) // Buffer input (connect directly to top-level port) + ); +endmodule Index: release-1.0/utils/contributions/gpio/rtl/minsoc_top.v =================================================================== --- release-1.0/utils/contributions/gpio/rtl/minsoc_top.v (nonexistent) +++ release-1.0/utils/contributions/gpio/rtl/minsoc_top.v (revision 151) @@ -0,0 +1,1105 @@ +`include "minsoc_defines.v" +`include "or1200_defines.v" + +`include "gpio_defines.v" + +module minsoc_top ( + clk,reset + + //JTAG ports +`ifdef GENERIC_TAP + , jtag_tdi,jtag_tms,jtag_tck, + jtag_tdo,jtag_vref,jtag_gnd +`endif + + //SPI ports +`ifdef START_UP + , spi_flash_mosi, spi_flash_miso, spi_flash_sclk, spi_flash_ss +`endif + + //UART ports +`ifdef UART + , uart_stx,uart_srx +`endif + + // Ethernet ports +`ifdef ETHERNET + , eth_col, eth_crs, eth_trste, eth_tx_clk, + eth_tx_en, eth_tx_er, eth_txd, eth_rx_clk, + eth_rx_dv, eth_rx_er, eth_rxd, eth_fds_mdint, + eth_mdc, eth_mdio +`endif + + // GPIO ports +`ifdef GPIO + `ifdef GPIO_HAS_INPUT_PINS + ,i_pins + `endif + `ifdef GPIO_HAS_OUTPUT_PINS + ,o_pins + `endif + `ifdef GPIO_HAS_BIDIR_PINS + ,io_pins + `endif +`endif +); + +// +// I/O Ports +// + + input clk; + input reset; + +// +// SPI controller external i/f wires +// +`ifdef START_UP +output spi_flash_mosi; +input spi_flash_miso; +output spi_flash_sclk; +output [1:0] spi_flash_ss; +`endif + +// +// UART +// +`ifdef UART + output uart_stx; + input uart_srx; +`endif + +// +// Ethernet +// +`ifdef ETHERNET +output eth_tx_er; +input eth_tx_clk; +output eth_tx_en; +output [3:0] eth_txd; +input eth_rx_er; +input eth_rx_clk; +input eth_rx_dv; +input [3:0] eth_rxd; +input eth_col; +input eth_crs; +output eth_trste; +input eth_fds_mdint; +inout eth_mdio; +output eth_mdc; +`endif + +// +// GPIO +// +`ifdef GPIO + `ifdef GPIO_HAS_INPUT_PINS + input [`GPIO_NUM_INPUT-1:0] i_pins; + `endif + `ifdef GPIO_HAS_OUTPUT_PINS + output [`GPIO_NUM_OUTPUT-1:0] o_pins; + `endif + `ifdef GPIO_HAS_BIDIR_PINS + inout [`GPIO_NUM_BIDIR-1:0] io_pins; + `endif +`endif + +// +// JTAG +// +`ifdef GENERIC_TAP + input jtag_tdi; + input jtag_tms; + input jtag_tck; + output jtag_tdo; + output jtag_vref; + output jtag_gnd; + + +assign jtag_vref = 1'b1; +assign jtag_gnd = 1'b0; +`endif + +wire rstn; + +`ifdef POSITIVE_RESET +assign rstn = ~reset; +`elsif NEGATIVE_RESET +assign rstn = reset; +`endif + +// +// Internal wires +// + +// +// Debug core master i/f wires +// +wire [31:0] wb_dm_adr_o; +wire [31:0] wb_dm_dat_i; +wire [31:0] wb_dm_dat_o; +wire [3:0] wb_dm_sel_o; +wire wb_dm_we_o; +wire wb_dm_stb_o; +wire wb_dm_cyc_o; +wire wb_dm_ack_i; +wire wb_dm_err_i; + +// +// Debug <-> RISC wires +// +wire [3:0] dbg_lss; +wire [1:0] dbg_is; +wire [10:0] dbg_wp; +wire dbg_bp; +wire [31:0] dbg_dat_dbg; +wire [31:0] dbg_dat_risc; +wire [31:0] dbg_adr; +wire dbg_ewt; +wire dbg_stall; +wire [2:0] dbg_op; //dbg_op[0] = dbg_we //dbg_op[2] = dbg_stb (didn't change for backward compatibility with DBG_IF_MODEL +wire dbg_ack; + +// +// RISC instruction master i/f wires +// +wire [31:0] wb_rim_adr_o; +wire wb_rim_cyc_o; +wire [31:0] wb_rim_dat_i; +wire [31:0] wb_rim_dat_o; +wire [3:0] wb_rim_sel_o; +wire wb_rim_ack_i; +wire wb_rim_err_i; +wire wb_rim_rty_i = 1'b0; +wire wb_rim_we_o; +wire wb_rim_stb_o; +wire [31:0] wb_rif_dat_i; +wire wb_rif_ack_i; + +// +// RISC data master i/f wires +// +wire [31:0] wb_rdm_adr_o; +wire wb_rdm_cyc_o; +wire [31:0] wb_rdm_dat_i; +wire [31:0] wb_rdm_dat_o; +wire [3:0] wb_rdm_sel_o; +wire wb_rdm_ack_i; +wire wb_rdm_err_i; +wire wb_rdm_rty_i = 1'b0; +wire wb_rdm_we_o; +wire wb_rdm_stb_o; + +// +// RISC misc +// +wire [19:0] pic_ints; + +// +// Flash controller slave i/f wires +// +wire [31:0] wb_fs_dat_i; +wire [31:0] wb_fs_dat_o; +wire [31:0] wb_fs_adr_i; +wire [3:0] wb_fs_sel_i; +wire wb_fs_we_i; +wire wb_fs_cyc_i; +wire wb_fs_stb_i; +wire wb_fs_ack_o; +wire wb_fs_err_o; + +// +// SPI controller slave i/f wires +// +wire [31:0] wb_sp_dat_i; +wire [31:0] wb_sp_dat_o; +wire [31:0] wb_sp_adr_i; +wire [3:0] wb_sp_sel_i; +wire wb_sp_we_i; +wire wb_sp_cyc_i; +wire wb_sp_stb_i; +wire wb_sp_ack_o; +wire wb_sp_err_o; + +// +// SPI controller external i/f wires +// +wire spi_flash_mosi; +wire spi_flash_miso; +wire spi_flash_sclk; +wire [1:0] spi_flash_ss; + +// +// SRAM controller slave i/f wires +// +wire [31:0] wb_ss_dat_i; +wire [31:0] wb_ss_dat_o; +wire [31:0] wb_ss_adr_i; +wire [3:0] wb_ss_sel_i; +wire wb_ss_we_i; +wire wb_ss_cyc_i; +wire wb_ss_stb_i; +wire wb_ss_ack_o; +wire wb_ss_err_o; + +// +// Ethernet core master i/f wires +// +wire [31:0] wb_em_adr_o; +wire [31:0] wb_em_dat_i; +wire [31:0] wb_em_dat_o; +wire [3:0] wb_em_sel_o; +wire wb_em_we_o; +wire wb_em_stb_o; +wire wb_em_cyc_o; +wire wb_em_ack_i; +wire wb_em_err_i; + +// +// Ethernet core slave i/f wires +// +wire [31:0] wb_es_dat_i; +wire [31:0] wb_es_dat_o; +wire [31:0] wb_es_adr_i; +wire [3:0] wb_es_sel_i; +wire wb_es_we_i; +wire wb_es_cyc_i; +wire wb_es_stb_i; +wire wb_es_ack_o; +wire wb_es_err_o; + +// +// Ethernet external i/f wires +// +wire eth_mdo; +wire eth_mdoe; + +// +// UART16550 core slave i/f wires +// +wire [31:0] wb_us_dat_i; +wire [31:0] wb_us_dat_o; +wire [31:0] wb_us_adr_i; +wire [3:0] wb_us_sel_i; +wire wb_us_we_i; +wire wb_us_cyc_i; +wire wb_us_stb_i; +wire wb_us_ack_o; +wire wb_us_err_o; + +// +// UART external i/f wires +// +wire uart_stx; +wire uart_srx; + +// +// GPIO core slave i/f wires +// +wire [31:0] wb_gpio_dat_i; +wire [31:0] wb_gpio_dat_o; +wire [31:0] wb_gpio_adr_i; +wire [3:0] wb_gpio_sel_i; +wire wb_gpio_we_i; +wire wb_gpio_cyc_i; +wire wb_gpio_stb_i; +wire wb_gpio_ack_o; +wire wb_gpio_err_o; + +// +// Interface to GPIO core - Device specific core +// +wire [`GPIO_IOS:0] ext_pad_o; +wire [`GPIO_IOS:0] ext_pad_i; +wire [`GPIO_IOS:0] ext_pad_oe_o; + +// +// Reset debounce +// +reg rst_r; +reg wb_rst; + +// +// Global clock +// +wire wb_clk; + +// +// Reset debounce +// +always @(posedge wb_clk or negedge rstn) + if (~rstn) + rst_r <= 1'b1; + else + rst_r <= #1 1'b0; + +// +// Reset debounce +// +always @(posedge wb_clk) + wb_rst <= #1 rst_r; + +// +// Clock Divider +// +minsoc_clock_manager # +( + .divisor(`CLOCK_DIVISOR) +) +clk_adjust ( + .clk_i(clk), + .clk_o(wb_clk) +); + +// +// Unused WISHBONE signals +// +assign wb_us_err_o = 1'b0; +assign wb_fs_err_o = 1'b0; +assign wb_sp_err_o = 1'b0; + +// +// Unused interrupts +// +assign pic_ints[`APP_INT_RES1] = 'b0; +assign pic_ints[`APP_INT_RES2] = 'b0; +assign pic_ints[`APP_INT_RES3] = 'b0; +assign pic_ints[`APP_INT_PS2] = 'b0; + +// +// Ethernet tri-state +// +`ifdef ETHERNET +assign eth_mdio = eth_mdoe ? eth_mdo : 1'bz; +assign eth_trste = `ETH_RESET; +`endif + + +// +// RISC Instruction address for Flash +// +// Until first access to real Flash area, +// CPU instruction is fixed to jump to the Flash area. +// After Flash area is accessed, CPU instructions +// come from the tc_top (wishbone "switch"). +// +`ifdef START_UP +reg jump_flash; +reg [3:0] rif_counter; +reg [31:0] rif_dat_int; +reg rif_ack_int; + +always @(posedge wb_clk or negedge rstn) +begin + if (!rstn) begin + jump_flash <= #1 1'b1; + rif_counter <= 4'h0; + rif_ack_int <= 1'b0; + end + else begin + rif_ack_int <= 1'b0; + + if (wb_rim_cyc_o && (wb_rim_adr_o[31:32-`APP_ADDR_DEC_W] == `APP_ADDR_FLASH)) + jump_flash <= #1 1'b0; + + if ( jump_flash == 1'b1 ) begin + if ( wb_rim_cyc_o && wb_rim_stb_o && ~wb_rim_we_o ) begin + rif_counter <= rif_counter + 1'b1; + rif_ack_int <= 1'b1; + end + end + end +end + +always @ (rif_counter) +begin + case ( rif_counter ) + 4'h0: rif_dat_int = { `OR1200_OR32_MOVHI , 5'h01 , 4'h0 , 1'b0 , `APP_ADDR_FLASH , 8'h00 }; + 4'h1: rif_dat_int = { `OR1200_OR32_ORI , 5'h01 , 5'h01 , 16'h0000 }; + 4'h2: rif_dat_int = { `OR1200_OR32_JR , 10'h000 , 5'h01 , 11'h000 }; + 4'h3: rif_dat_int = { `OR1200_OR32_NOP , 10'h000 , 16'h0000 }; + default: rif_dat_int = 32'h0000_0000; + endcase +end + +assign wb_rif_dat_i = jump_flash ? rif_dat_int : wb_rim_dat_i; + +assign wb_rif_ack_i = jump_flash ? rif_ack_int : wb_rim_ack_i; + +`else +assign wb_rif_dat_i = wb_rim_dat_i; +assign wb_rif_ack_i = wb_rim_ack_i; +`endif + + +// +// TAP<->dbg_interface +// +wire jtag_tck; +wire debug_tdi; +wire debug_tdo; +wire capture_dr; +wire shift_dr; +wire pause_dr; +wire update_dr; + +wire debug_select; +wire test_logic_reset; + +// +// Instantiation of the development i/f +// +adbg_top dbg_top ( + + // JTAG pins + .tck_i ( jtag_tck ), + .tdi_i ( debug_tdi ), + .tdo_o ( debug_tdo ), + .rst_i ( test_logic_reset ), //cable without rst + + // Boundary Scan signals + .capture_dr_i ( capture_dr ), + .shift_dr_i ( shift_dr ), + .pause_dr_i ( pause_dr ), + .update_dr_i ( update_dr ), + + .debug_select_i( debug_select ), + // WISHBONE common + .wb_clk_i ( wb_clk ), + + // WISHBONE master interface + .wb_adr_o ( wb_dm_adr_o ), + .wb_dat_i ( wb_dm_dat_i ), + .wb_dat_o ( wb_dm_dat_o ), + .wb_sel_o ( wb_dm_sel_o ), + .wb_we_o ( wb_dm_we_o ), + .wb_stb_o ( wb_dm_stb_o ), + .wb_cyc_o ( wb_dm_cyc_o ), + .wb_ack_i ( wb_dm_ack_i ), + .wb_err_i ( wb_dm_err_i ), + .wb_cti_o ( ), + .wb_bte_o ( ), + + // RISC signals + .cpu0_clk_i ( wb_clk ), + .cpu0_addr_o ( dbg_adr ), + .cpu0_data_i ( dbg_dat_risc ), + .cpu0_data_o ( dbg_dat_dbg ), + .cpu0_bp_i ( dbg_bp ), + .cpu0_stall_o( dbg_stall ), + .cpu0_stb_o ( dbg_op[2] ), + .cpu0_we_o ( dbg_op[0] ), + .cpu0_ack_i ( dbg_ack ), + .cpu0_rst_o ( ) + +); + +// +// JTAG TAP controller instantiation +// +`ifdef GENERIC_TAP +tap_top tap_top( + // JTAG pads + .tms_pad_i(jtag_tms), + .tck_pad_i(jtag_tck), + .trstn_pad_i(rstn), + .tdi_pad_i(jtag_tdi), + .tdo_pad_o(jtag_tdo), + .tdo_padoe_o( ), + + // TAP states + .test_logic_reset_o( test_logic_reset ), + .run_test_idle_o(), + .shift_dr_o(shift_dr), + .pause_dr_o(pause_dr), + .update_dr_o(update_dr), + .capture_dr_o(capture_dr), + + // Select signals for boundary scan or mbist + .extest_select_o(), + .sample_preload_select_o(), + .mbist_select_o(), + .debug_select_o(debug_select), + + // TDO signal that is connected to TDI of sub-modules. + .tdi_o(debug_tdi), + + // TDI signals from sub-modules + .debug_tdo_i(debug_tdo), // from debug module + .bs_chain_tdo_i(1'b0), // from Boundary Scan Chain + .mbist_tdo_i(1'b0) // from Mbist Chain +); +`elsif FPGA_TAP +`ifdef ALTERA_FPGA +altera_virtual_jtag tap_top( + .tck_o(jtag_tck), + .debug_tdo_o(debug_tdo), + .tdi_o(debug_tdi), + .test_logic_reset_o(test_logic_reset), + .run_test_idle_o(), + .shift_dr_o(shift_dr), + .capture_dr_o(capture_dr), + .pause_dr_o(pause_dr), + .update_dr_o(update_dr), + .debug_select_o(debug_select) +); +`elsif XILINX_FPGA +minsoc_xilinx_internal_jtag tap_top( + .tck_o( jtag_tck ), + .debug_tdo_i( debug_tdo ), + .tdi_o( debug_tdi ), + + .test_logic_reset_o( test_logic_reset ), + .run_test_idle_o( ), + + .shift_dr_o( shift_dr ), + .capture_dr_o( capture_dr ), + .pause_dr_o( pause_dr ), + .update_dr_o( update_dr ), + .debug_select_o( debug_select ) +); +`endif // !FPGA_TAP + +`endif // !GENERIC_TAP + +// +// Instantiation of the OR1200 RISC +// +or1200_top or1200_top ( + + // Common + .rst_i ( wb_rst ), + .clk_i ( wb_clk ), +`ifdef OR1200_CLMODE_1TO2 + .clmode_i ( 2'b01 ), +`else +`ifdef OR1200_CLMODE_1TO4 + .clmode_i ( 2'b11 ), +`else + .clmode_i ( 2'b00 ), +`endif +`endif + + // WISHBONE Instruction Master + .iwb_clk_i ( wb_clk ), + .iwb_rst_i ( wb_rst ), + .iwb_cyc_o ( wb_rim_cyc_o ), + .iwb_adr_o ( wb_rim_adr_o ), + .iwb_dat_i ( wb_rif_dat_i ), + .iwb_dat_o ( wb_rim_dat_o ), + .iwb_sel_o ( wb_rim_sel_o ), + .iwb_ack_i ( wb_rif_ack_i ), + .iwb_err_i ( wb_rim_err_i ), + .iwb_rty_i ( wb_rim_rty_i ), + .iwb_we_o ( wb_rim_we_o ), + .iwb_stb_o ( wb_rim_stb_o ), + + // WISHBONE Data Master + .dwb_clk_i ( wb_clk ), + .dwb_rst_i ( wb_rst ), + .dwb_cyc_o ( wb_rdm_cyc_o ), + .dwb_adr_o ( wb_rdm_adr_o ), + .dwb_dat_i ( wb_rdm_dat_i ), + .dwb_dat_o ( wb_rdm_dat_o ), + .dwb_sel_o ( wb_rdm_sel_o ), + .dwb_ack_i ( wb_rdm_ack_i ), + .dwb_err_i ( wb_rdm_err_i ), + .dwb_rty_i ( wb_rdm_rty_i ), + .dwb_we_o ( wb_rdm_we_o ), + .dwb_stb_o ( wb_rdm_stb_o ), + + // Debug + .dbg_stall_i ( dbg_stall ), + .dbg_dat_i ( dbg_dat_dbg ), + .dbg_adr_i ( dbg_adr ), + .dbg_ewt_i ( 1'b0 ), + .dbg_lss_o ( dbg_lss ), + .dbg_is_o ( dbg_is ), + .dbg_wp_o ( dbg_wp ), + .dbg_bp_o ( dbg_bp ), + .dbg_dat_o ( dbg_dat_risc ), + .dbg_ack_o ( dbg_ack ), + .dbg_stb_i ( dbg_op[2] ), + .dbg_we_i ( dbg_op[0] ), + + // Power Management + .pm_clksd_o ( ), + .pm_cpustall_i ( 1'b0 ), + .pm_dc_gate_o ( ), + .pm_ic_gate_o ( ), + .pm_dmmu_gate_o ( ), + .pm_immu_gate_o ( ), + .pm_tt_gate_o ( ), + .pm_cpu_gate_o ( ), + .pm_wakeup_o ( ), + .pm_lvolt_o ( ), + + // Interrupts + .pic_ints_i ( pic_ints ) +); + +// +// Startup OR1k +// +`ifdef START_UP +OR1K_startup OR1K_startup0 +( + .wb_adr_i(wb_fs_adr_i[6:2]), + .wb_stb_i(wb_fs_stb_i), + .wb_cyc_i(wb_fs_cyc_i), + .wb_dat_o(wb_fs_dat_o), + .wb_ack_o(wb_fs_ack_o), + .wb_clk(wb_clk), + .wb_rst(wb_rst) +); + +spi_flash_top # +( + .divider(0), + .divider_len(2) +) +spi_flash_top0 +( + .wb_clk_i(wb_clk), + .wb_rst_i(wb_rst), + .wb_adr_i(wb_sp_adr_i[4:2]), + .wb_dat_i(wb_sp_dat_i), + .wb_dat_o(wb_sp_dat_o), + .wb_sel_i(wb_sp_sel_i), + .wb_we_i(wb_sp_we_i), + .wb_stb_i(wb_sp_stb_i), + .wb_cyc_i(wb_sp_cyc_i), + .wb_ack_o(wb_sp_ack_o), + + .mosi_pad_o(spi_flash_mosi), + .miso_pad_i(spi_flash_miso), + .sclk_pad_o(spi_flash_sclk), + .ss_pad_o(spi_flash_ss) +); +`else +assign wb_fs_dat_o = 32'h0000_0000; +assign wb_fs_ack_o = 1'b0; +assign wb_sp_dat_o = 32'h0000_0000; +assign wb_sp_ack_o = 1'b0; +`endif + +// +// Instantiation of the SRAM controller +// +minsoc_onchip_ram_top # +( + .adr_width(`MEMORY_ADR_WIDTH) //16 blocks of 2048 bytes memory 32768 +) +onchip_ram_top ( + + // WISHBONE common + .wb_clk_i ( wb_clk ), + .wb_rst_i ( wb_rst ), + + // WISHBONE slave + .wb_dat_i ( wb_ss_dat_i ), + .wb_dat_o ( wb_ss_dat_o ), + .wb_adr_i ( wb_ss_adr_i ), + .wb_sel_i ( wb_ss_sel_i ), + .wb_we_i ( wb_ss_we_i ), + .wb_cyc_i ( wb_ss_cyc_i ), + .wb_stb_i ( wb_ss_stb_i ), + .wb_ack_o ( wb_ss_ack_o ), + .wb_err_o ( wb_ss_err_o ) +); + +// +// Instantiation of the UART16550 +// +`ifdef UART +uart_top uart_top ( + + // WISHBONE common + .wb_clk_i ( wb_clk ), + .wb_rst_i ( wb_rst ), + + // WISHBONE slave + .wb_adr_i ( wb_us_adr_i[4:0] ), + .wb_dat_i ( wb_us_dat_i ), + .wb_dat_o ( wb_us_dat_o ), + .wb_we_i ( wb_us_we_i ), + .wb_stb_i ( wb_us_stb_i ), + .wb_cyc_i ( wb_us_cyc_i ), + .wb_ack_o ( wb_us_ack_o ), + .wb_sel_i ( wb_us_sel_i ), + + // Interrupt request + .int_o ( pic_ints[`APP_INT_UART] ), + + // UART signals + // serial input/output + .stx_pad_o ( uart_stx ), + .srx_pad_i ( uart_srx ), + + // modem signals + .rts_pad_o ( ), + .cts_pad_i ( 1'b0 ), + .dtr_pad_o ( ), + .dsr_pad_i ( 1'b0 ), + .ri_pad_i ( 1'b0 ), + .dcd_pad_i ( 1'b0 ) +); +`else +assign wb_us_dat_o = 32'h0000_0000; +assign wb_us_ack_o = 1'b0; +`endif + + +// +// Instantiation of the GPIO +// +`ifdef GPIO +gpio_top #( .gw(`GPIO_IOS + 1) ) +gpio_top_inst ( + + // WISHBONE common + .wb_clk_i ( wb_clk ), + .wb_rst_i ( wb_rst ), + + // WISHBONE slave + .wb_adr_i ( wb_gpio_adr_i[4:0] ), + .wb_dat_i ( wb_gpio_dat_i ), + .wb_dat_o ( wb_gpio_dat_o ), + .wb_we_i ( wb_gpio_we_i ), + .wb_stb_i ( wb_gpio_stb_i ), + .wb_cyc_i ( wb_gpio_cyc_i ), + .wb_ack_o ( wb_gpio_ack_o ), + .wb_sel_i ( wb_gpio_sel_i ), + + // Interrupt request + .wb_inta_o ( pic_ints[`APP_INT_GPIO] ), + + // GPIO external signals + .ext_pad_o ( ext_pad_o ), + .ext_pad_i ( ext_pad_i ), + .ext_padoe_o( ext_pad_oe_o ) + +); + +minsoc_spartan_3a_starter_kit_ios #( .gpio_num(`GPIO_IOS + 1), + `ifdef GPIO_HAS_INPUT_PINS + .i_line_num(`GPIO_NUM_INPUT), + `endif + `ifdef GPIO_HAS_OUTPUT_PINS + .o_line_num(`GPIO_NUM_OUTPUT), + `endif + `ifdef GPIO_HAS_BIDIR_PINS + .io_line_num(`GPIO_NUM_BIDIR) + `endif +) minsoc_spartan_3a_starter_kit_ios_inst_0 ( + .ext_pad_o( ext_pad_o ), + .ext_pad_oe( ext_pad_oe_o ), + .ext_pad_i( ext_pad_i ), + `ifdef GPIO_HAS_INPUT_PINS + .i_pins( i_pins ), + `else + .i_pins( ), + `endif + `ifdef GPIO_HAS_OUTPUT_PINS + .o_pins( o_pins ), + `else + .o_pins( ), + `endif + `ifdef GPIO_HAS_BIDIR_PINS + .io_pins( io_pins ) + `else + .io_pins( ) + `endif +); + +`else +assign wb_gpio_dat_o = 32'h0000_0000; +assign wb_gpio_ack_o = 1'b0; +`endif + + + +// +// Instantiation of the Ethernet 10/100 MAC +// +`ifdef ETHERNET +eth_top eth_top ( + + // WISHBONE common + .wb_clk_i ( wb_clk ), + .wb_rst_i ( wb_rst ), + + // WISHBONE slave + .wb_dat_i ( wb_es_dat_i ), + .wb_dat_o ( wb_es_dat_o ), + .wb_adr_i ( wb_es_adr_i[11:2] ), + .wb_sel_i ( wb_es_sel_i ), + .wb_we_i ( wb_es_we_i ), + .wb_cyc_i ( wb_es_cyc_i ), + .wb_stb_i ( wb_es_stb_i ), + .wb_ack_o ( wb_es_ack_o ), + .wb_err_o ( wb_es_err_o ), + + // WISHBONE master + .m_wb_adr_o ( wb_em_adr_o ), + .m_wb_sel_o ( wb_em_sel_o ), + .m_wb_we_o ( wb_em_we_o ), + .m_wb_dat_o ( wb_em_dat_o ), + .m_wb_dat_i ( wb_em_dat_i ), + .m_wb_cyc_o ( wb_em_cyc_o ), + .m_wb_stb_o ( wb_em_stb_o ), + .m_wb_ack_i ( wb_em_ack_i ), + .m_wb_err_i ( wb_em_err_i ), + + // TX + .mtx_clk_pad_i ( eth_tx_clk ), + .mtxd_pad_o ( eth_txd ), + .mtxen_pad_o ( eth_tx_en ), + .mtxerr_pad_o ( eth_tx_er ), + + // RX + .mrx_clk_pad_i ( eth_rx_clk ), + .mrxd_pad_i ( eth_rxd ), + .mrxdv_pad_i ( eth_rx_dv ), + .mrxerr_pad_i ( eth_rx_er ), + .mcoll_pad_i ( eth_col ), + .mcrs_pad_i ( eth_crs ), + + // MIIM + .mdc_pad_o ( eth_mdc ), + .md_pad_i ( eth_mdio ), + .md_pad_o ( eth_mdo ), + .md_padoe_o ( eth_mdoe ), + + // Interrupt + .int_o ( pic_ints[`APP_INT_ETH] ) +); +`else +assign wb_es_dat_o = 32'h0000_0000; +assign wb_es_ack_o = 1'b0; + +assign wb_em_adr_o = 32'h0000_0000; +assign wb_em_sel_o = 4'h0; +assign wb_em_we_o = 1'b0; +assign wb_em_dat_o = 32'h0000_0000; +assign wb_em_cyc_o = 1'b0; +assign wb_em_stb_o = 1'b0; +`endif + +// +// Instantiation of the Traffic COP +// +minsoc_tc_top #(`APP_ADDR_DEC_W, + `APP_ADDR_SRAM, + `APP_ADDR_DEC_W, + `APP_ADDR_FLASH, + `APP_ADDR_DECP_W, + `APP_ADDR_PERIP, + `APP_ADDR_DEC_W, + `APP_ADDR_SPI, + `APP_ADDR_ETH, + `APP_ADDR_AUDIO, + `APP_ADDR_UART, + `APP_ADDR_PS2, + `APP_ADDR_GPIO, + `APP_ADDR_RES2 + ) tc_top ( + + // WISHBONE common + .wb_clk_i ( wb_clk ), + .wb_rst_i ( wb_rst ), + + // WISHBONE Initiator 0 + .i0_wb_cyc_i ( 1'b0 ), + .i0_wb_stb_i ( 1'b0 ), + .i0_wb_adr_i ( 32'h0000_0000 ), + .i0_wb_sel_i ( 4'b0000 ), + .i0_wb_we_i ( 1'b0 ), + .i0_wb_dat_i ( 32'h0000_0000 ), + .i0_wb_dat_o ( ), + .i0_wb_ack_o ( ), + .i0_wb_err_o ( ), + + // WISHBONE Initiator 1 + .i1_wb_cyc_i ( wb_em_cyc_o ), + .i1_wb_stb_i ( wb_em_stb_o ), + .i1_wb_adr_i ( wb_em_adr_o ), + .i1_wb_sel_i ( wb_em_sel_o ), + .i1_wb_we_i ( wb_em_we_o ), + .i1_wb_dat_i ( wb_em_dat_o ), + .i1_wb_dat_o ( wb_em_dat_i ), + .i1_wb_ack_o ( wb_em_ack_i ), + .i1_wb_err_o ( wb_em_err_i ), + + // WISHBONE Initiator 2 + .i2_wb_cyc_i ( 1'b0 ), + .i2_wb_stb_i ( 1'b0 ), + .i2_wb_adr_i ( 32'h0000_0000 ), + .i2_wb_sel_i ( 4'b0000 ), + .i2_wb_we_i ( 1'b0 ), + .i2_wb_dat_i ( 32'h0000_0000 ), + .i2_wb_dat_o ( ), + .i2_wb_ack_o ( ), + .i2_wb_err_o ( ), + + // WISHBONE Initiator 3 + .i3_wb_cyc_i ( wb_dm_cyc_o ), + .i3_wb_stb_i ( wb_dm_stb_o ), + .i3_wb_adr_i ( wb_dm_adr_o ), + .i3_wb_sel_i ( wb_dm_sel_o ), + .i3_wb_we_i ( wb_dm_we_o ), + .i3_wb_dat_i ( wb_dm_dat_o ), + .i3_wb_dat_o ( wb_dm_dat_i ), + .i3_wb_ack_o ( wb_dm_ack_i ), + .i3_wb_err_o ( wb_dm_err_i ), + + // WISHBONE Initiator 4 + .i4_wb_cyc_i ( wb_rdm_cyc_o ), + .i4_wb_stb_i ( wb_rdm_stb_o ), + .i4_wb_adr_i ( wb_rdm_adr_o ), + .i4_wb_sel_i ( wb_rdm_sel_o ), + .i4_wb_we_i ( wb_rdm_we_o ), + .i4_wb_dat_i ( wb_rdm_dat_o ), + .i4_wb_dat_o ( wb_rdm_dat_i ), + .i4_wb_ack_o ( wb_rdm_ack_i ), + .i4_wb_err_o ( wb_rdm_err_i ), + + // WISHBONE Initiator 5 + .i5_wb_cyc_i ( wb_rim_cyc_o ), + .i5_wb_stb_i ( wb_rim_stb_o ), + .i5_wb_adr_i ( wb_rim_adr_o ), + .i5_wb_sel_i ( wb_rim_sel_o ), + .i5_wb_we_i ( wb_rim_we_o ), + .i5_wb_dat_i ( wb_rim_dat_o ), + .i5_wb_dat_o ( wb_rim_dat_i ), + .i5_wb_ack_o ( wb_rim_ack_i ), + .i5_wb_err_o ( wb_rim_err_i ), + + // WISHBONE Initiator 6 + .i6_wb_cyc_i ( 1'b0 ), + .i6_wb_stb_i ( 1'b0 ), + .i6_wb_adr_i ( 32'h0000_0000 ), + .i6_wb_sel_i ( 4'b0000 ), + .i6_wb_we_i ( 1'b0 ), + .i6_wb_dat_i ( 32'h0000_0000 ), + .i6_wb_dat_o ( ), + .i6_wb_ack_o ( ), + .i6_wb_err_o ( ), + + // WISHBONE Initiator 7 + .i7_wb_cyc_i ( 1'b0 ), + .i7_wb_stb_i ( 1'b0 ), + .i7_wb_adr_i ( 32'h0000_0000 ), + .i7_wb_sel_i ( 4'b0000 ), + .i7_wb_we_i ( 1'b0 ), + .i7_wb_dat_i ( 32'h0000_0000 ), + .i7_wb_dat_o ( ), + .i7_wb_ack_o ( ), + .i7_wb_err_o ( ), + + // WISHBONE Target 0 + .t0_wb_cyc_o ( wb_ss_cyc_i ), + .t0_wb_stb_o ( wb_ss_stb_i ), + .t0_wb_adr_o ( wb_ss_adr_i ), + .t0_wb_sel_o ( wb_ss_sel_i ), + .t0_wb_we_o ( wb_ss_we_i ), + .t0_wb_dat_o ( wb_ss_dat_i ), + .t0_wb_dat_i ( wb_ss_dat_o ), + .t0_wb_ack_i ( wb_ss_ack_o ), + .t0_wb_err_i ( wb_ss_err_o ), + + // WISHBONE Target 1 + .t1_wb_cyc_o ( wb_fs_cyc_i ), + .t1_wb_stb_o ( wb_fs_stb_i ), + .t1_wb_adr_o ( wb_fs_adr_i ), + .t1_wb_sel_o ( wb_fs_sel_i ), + .t1_wb_we_o ( wb_fs_we_i ), + .t1_wb_dat_o ( wb_fs_dat_i ), + .t1_wb_dat_i ( wb_fs_dat_o ), + .t1_wb_ack_i ( wb_fs_ack_o ), + .t1_wb_err_i ( wb_fs_err_o ), + + // WISHBONE Target 2 + .t2_wb_cyc_o ( wb_sp_cyc_i ), + .t2_wb_stb_o ( wb_sp_stb_i ), + .t2_wb_adr_o ( wb_sp_adr_i ), + .t2_wb_sel_o ( wb_sp_sel_i ), + .t2_wb_we_o ( wb_sp_we_i ), + .t2_wb_dat_o ( wb_sp_dat_i ), + .t2_wb_dat_i ( wb_sp_dat_o ), + .t2_wb_ack_i ( wb_sp_ack_o ), + .t2_wb_err_i ( wb_sp_err_o ), + + // WISHBONE Target 3 + .t3_wb_cyc_o ( wb_es_cyc_i ), + .t3_wb_stb_o ( wb_es_stb_i ), + .t3_wb_adr_o ( wb_es_adr_i ), + .t3_wb_sel_o ( wb_es_sel_i ), + .t3_wb_we_o ( wb_es_we_i ), + .t3_wb_dat_o ( wb_es_dat_i ), + .t3_wb_dat_i ( wb_es_dat_o ), + .t3_wb_ack_i ( wb_es_ack_o ), + .t3_wb_err_i ( wb_es_err_o ), + + // WISHBONE Target 4 + .t4_wb_cyc_o ( ), + .t4_wb_stb_o ( ), + .t4_wb_adr_o ( ), + .t4_wb_sel_o ( ), + .t4_wb_we_o ( ), + .t4_wb_dat_o ( ), + .t4_wb_dat_i ( 32'h0000_0000 ), + .t4_wb_ack_i ( 1'b0 ), + .t4_wb_err_i ( 1'b1 ), + + // WISHBONE Target 5 + .t5_wb_cyc_o ( wb_us_cyc_i ), + .t5_wb_stb_o ( wb_us_stb_i ), + .t5_wb_adr_o ( wb_us_adr_i ), + .t5_wb_sel_o ( wb_us_sel_i ), + .t5_wb_we_o ( wb_us_we_i ), + .t5_wb_dat_o ( wb_us_dat_i ), + .t5_wb_dat_i ( wb_us_dat_o ), + .t5_wb_ack_i ( wb_us_ack_o ), + .t5_wb_err_i ( wb_us_err_o ), + + // WISHBONE Target 6 + .t6_wb_cyc_o ( ), + .t6_wb_stb_o ( ), + .t6_wb_adr_o ( ), + .t6_wb_sel_o ( ), + .t6_wb_we_o ( ), + .t6_wb_dat_o ( ), + .t6_wb_dat_i ( 32'h0000_0000 ), + .t6_wb_ack_i ( 1'b0 ), + .t6_wb_err_i ( 1'b1 ), + + // WISHBONE Target 7 + .t7_wb_cyc_o ( wb_gpio_cyc_i ), + .t7_wb_stb_o ( wb_gpio_stb_i ), + .t7_wb_adr_o ( wb_gpio_adr_i ), + .t7_wb_sel_o ( wb_gpio_sel_i ), + .t7_wb_we_o ( wb_gpio_we_i ), + .t7_wb_dat_o ( wb_gpio_dat_i ), + .t7_wb_dat_i ( wb_gpio_dat_o ), + .t7_wb_ack_i ( wb_gpio_ack_o ), + .t7_wb_err_i ( wb_gpio_err_o ), + + // WISHBONE Target 8 + .t8_wb_cyc_o ( ), + .t8_wb_stb_o ( ), + .t8_wb_adr_o ( ), + .t8_wb_sel_o ( ), + .t8_wb_we_o ( ), + .t8_wb_dat_o ( ), + .t8_wb_dat_i ( 32'h0000_0000 ), + .t8_wb_ack_i ( 1'b0 ), + .t8_wb_err_i ( 1'b1 ) +); + +//initial begin +// $dumpvars(0); +// $dumpfile("dump.vcd"); +//end + +endmodule Index: release-1.0/utils/contributions/gpio/sw/gpio.c =================================================================== --- release-1.0/utils/contributions/gpio/sw/gpio.c (nonexistent) +++ release-1.0/utils/contributions/gpio/sw/gpio.c (revision 151) @@ -0,0 +1,225 @@ +#include "../support/support.h" +#include "../support/board.h" + +#include "../support/spr_defs.h" + +#include "../drivers/uart.h" + +#include "gpio.h" + +void gpio_init(gpio_t *gpio, long instance_num, unsigned long base_addr) +{ + int i = MIN_GPIO_BIT; + + if ( gpio != NULL ) { + gpio->instance_num = instance_num; + gpio->base_addr = (unsigned char*)base_addr; + for ( ;i<=MAX_GPIO_BIT;i++) + gpio->vectors[i].vec = NULL; + return; + } else { + // Print the error msgs here + // + uart_print_str("gpio inst in NULL.\n"); + return; + } +} + +void gpio_config_bit(gpio_t *gpio, unsigned long bit, iotype_t io) +{ + if ( gpio != NULL ) { + if ( io == IO_INPUT ) { + gpio->io_config |= (1 << bit); + *(unsigned long*)(gpio->base_addr + OE_REG_OFFSET) &= (~(1 << bit)); + } else { + gpio->io_config &= (~(1 << bit)); + *(unsigned long*)(gpio->base_addr + OE_REG_OFFSET) |= (1 << bit); + } + return; + } else { + // Print the error msgs here + // + uart_print_str("gpio inst in NULL.\n"); + return; + } +} + +void gpio_set_bit(gpio_t *gpio, unsigned long bit, unsigned long val) +{ + if ( gpio != NULL ) { + if ( val != 0 ) + *(unsigned long*)(gpio->base_addr + OUT_REG_OFFSET) |= (1 << bit); + else + *(unsigned long*)(gpio->base_addr + OUT_REG_OFFSET) &= (~(1 << bit)); + return; + } else { + // Print the error msgs here + // + uart_print_str("gpio inst in NULL.\n"); + return; + } +} + +void gpio_get_bit(gpio_t *gpio, unsigned long bit, unsigned long *val) +{ + unsigned long temp; + + if ( gpio != NULL ) { + temp = *(unsigned long*)(gpio->base_addr + IN_REG_OFFSET); + *val = (temp & (1 << bit))? 1 : 0; + return; + } else { + // Print the error msgs here + // + uart_print_str("gpio inst in NULL.\n"); + return; + } +} + + +void gpio_add_interrupt(gpio_t *gpio, unsigned int bit, edge_t edge,void (*func)() ) +{ + if ( gpio != NULL ) { + if ( ( gpio->io_config &(1 << bit)) != 0 ) { // Port bit is configured as IO_INPUT + // + // Disable the interrupts + // + *(unsigned long*)(gpio->base_addr + CTRL_REG_OFFSET) &= (~0x01); + + // Enable the interrupt bit + // + *(unsigned long*)(gpio->base_addr + INTE_REG_OFFSET) |= (1 << bit); + + // Enable the edge type + // + if ( edge == POS_EDGE ) + *(unsigned long*)(gpio->base_addr + PTRIG_REG_OFFSET) |= (1 << bit); + else + *(unsigned long*)(gpio->base_addr + PTRIG_REG_OFFSET) &= (~(1 << bit)); + + // Set the function vector + // + gpio->vectors[bit].vec = func; + + int_add( 6, gpio_interrupt, gpio ); + + // Re-enable the global control bit + // + *(unsigned long*)(gpio->base_addr + CTRL_REG_OFFSET) |= 0x01; + } else { + // Port is configured as IO_OUTPUT + uart_print_str("gpio pin is not an input pin.\n"); + return; + } + + } else { + // Print the error msgs here + // + uart_print_str("gpio inst in NULL.\n"); + return; + } + +} + +void gpio_interrupt(gpio_t *gpio) +{ + int i; + unsigned long int interrupt_status; + + if ( (*(unsigned long*)(gpio->base_addr + CTRL_REG_OFFSET)) & 0x02 ) + { + // Interrupt is pending here + // + interrupt_status = *(unsigned long*)(gpio->base_addr + INTS_REG_OFFSET); + + // Prioritize from lower bits(0) to higher ones(31) + // + + for ( i=MIN_GPIO_BIT; i<=MAX_GPIO_BIT; i++ ) { + if ( (interrupt_status & (1<base_addr + INTS_REG_OFFSET) &= (~( 1 << i )); + (gpio->vectors[i].vec)(); + } + } + + *(unsigned long*)(gpio->base_addr + CTRL_REG_OFFSET) &= (~0x02); + + } +} + +void hello_east() +{ + uart_print_str("Hello from PUSH Button EAST.\n"); +} + + +void hello_west() +{ + uart_print_str("Hello from PUSH Button WEST.\n"); +} + + +void hello_south() +{ + uart_print_str("Hello from PUSH Button SOUTH.\n"); +} + + + + +#define MAX_COUNT 10 + +int main() +{ + gpio_t gpio_1; + unsigned long t0, t1, t2, t3; + unsigned long count = 0; + + tick_init(); + uart_init(); + int_init(); + int_add(2,&uart_interrupt); + + gpio_init( &gpio_1, 1, GPIO_BASE ); + + gpio_config_bit( &gpio_1, LED_0, IO_OUTPUT); + gpio_config_bit( &gpio_1, LED_1, IO_OUTPUT); + gpio_config_bit( &gpio_1, LED_2, IO_OUTPUT); + gpio_config_bit( &gpio_1, LED_3, IO_OUTPUT); + gpio_config_bit( &gpio_1, LED_4, IO_OUTPUT); + gpio_config_bit( &gpio_1, LED_5, IO_OUTPUT); + gpio_config_bit( &gpio_1, LED_6, IO_OUTPUT); + gpio_config_bit( &gpio_1, LED_7, IO_OUTPUT); + + while ( count++ < MAX_COUNT ) { + gpio_set_bit( &gpio_1, LED_7, 0 ); + gpio_set_bit( &gpio_1, LED_0, 1 ); + udelay(); + gpio_set_bit( &gpio_1, LED_0, 0 ); + gpio_set_bit( &gpio_1, LED_1, 1 ); + udelay(); + gpio_set_bit( &gpio_1, LED_1, 0 ); + gpio_set_bit( &gpio_1, LED_2, 1 ); + udelay(); + gpio_set_bit( &gpio_1, LED_2, 0 ); + gpio_set_bit( &gpio_1, LED_3, 1 ); + udelay(); + gpio_set_bit( &gpio_1, LED_3, 0 ); + gpio_set_bit( &gpio_1, LED_4, 1 ); + udelay(); + gpio_set_bit( &gpio_1, LED_4, 0 ); + gpio_set_bit( &gpio_1, LED_5, 1 ); + udelay(); + gpio_set_bit( &gpio_1, LED_5, 0 ); + gpio_set_bit( &gpio_1, LED_6, 1 ); + udelay(); + gpio_set_bit( &gpio_1, LED_6, 0 ); + gpio_set_bit( &gpio_1, LED_7, 1 ); + udelay(); + } + + gpio_set_bit( &gpio_1, LED_7, 0 ); + + report(0xdeaddead); + or32_exit(0); +} Index: release-1.0/utils/contributions/gpio/sw/udelay.c =================================================================== --- release-1.0/utils/contributions/gpio/sw/udelay.c (nonexistent) +++ release-1.0/utils/contributions/gpio/sw/udelay.c (revision 151) @@ -0,0 +1,13 @@ +#include "../support/support.h" +#include "../support/board.h" + +#include "../drivers/tick.h" + +extern int tick_int; + +void udelay(void) +{ + while (!tick_int); + tick_ack(); +} + Index: release-1.0/utils/contributions/gpio/sw/gpio.h =================================================================== --- release-1.0/utils/contributions/gpio/sw/gpio.h (nonexistent) +++ release-1.0/utils/contributions/gpio/sw/gpio.h (revision 151) @@ -0,0 +1,76 @@ +#ifndef __GPIO_H__ + +#define __GPIO_H__ + +#define MIN_GPIO_BIT 0 +#define MAX_GPIO_BIT 31 + +#define TOTAL_GPIO_BITS ((MAX_GPIO_BIT-MIN_GPIO_BIT+1)) + + +#define IN_REG_OFFSET 0x00 +#define OUT_REG_OFFSET 0x04 +#define OE_REG_OFFSET 0x08 +#define INTE_REG_OFFSET 0x0C +#define PTRIG_REG_OFFSET 0x10 +#define AUX_REG_OFFSET 0x14 +#define CTRL_REG_OFFSET 0x18 +#define INTS_REG_OFFSET 0x1C +#define ECLK_REG_OFFSET 0x20 +#define NEC_REG_OFFSET 0x24 + + +typedef struct vector_t_ +{ + void (*vec)(); +} vector_t; + +typedef struct gpio_t_ +{ + volatile unsigned char *base_addr; + unsigned int instance_num; + unsigned int io_config; + vector_t vectors[TOTAL_GPIO_BITS]; +} gpio_t; + +typedef enum iotype_t_ +{ + IO_OUTPUT = 0, + IO_INPUT = 1 +} iotype_t; + +typedef enum edge_t_ +{ + NEG_EDGE = 0, + POS_EDGE = 1 +} edge_t; + + +#define LED_0 0x00 +#define LED_1 0x01 +#define LED_2 0x02 +#define LED_3 0x03 +#define LED_4 0x04 +#define LED_5 0x05 +#define LED_6 0x06 +#define LED_7 0x07 + +#define DIP_0 0x08 +#define DIP_1 0x09 +#define DIP_2 0x0A +#define DIP_3 0x0B + +#define PUSH_EAST 0x0C +#define PUSH_WEST 0x0D +#define PUSH_NORTH 0x0E +#define PUSH_SOUTH 0x0F + + +void gpio_init(gpio_t *, long, unsigned long); +void gpio_config_bit(gpio_t *, unsigned long, iotype_t); +void gpio_set_bit(gpio_t *, unsigned long, unsigned long); +void gpio_get_bit(gpio_t *, unsigned long, unsigned long *); +void gpio_add_interrupt(gpio_t *, unsigned int, edge_t,void (*func)() ); +void gpio_interrupt(gpio_t *gpio); + +#endif Index: release-1.0/utils/contributions/gpio/sw/Makefile =================================================================== --- release-1.0/utils/contributions/gpio/sw/Makefile (nonexistent) +++ release-1.0/utils/contributions/gpio/sw/Makefile (revision 151) @@ -0,0 +1,26 @@ +include ../support/Makefile.inc +drivers = ../drivers/libdrivers.a +cases = gpio-nocache gpio-icdc +common = ../support/libsupport.a ../support/except.o + +all: $(cases) + +gpio-nocache: gpio.o udelay.o ../support/reset-nocache.o $(common) $(drivers) + $(OR32_TOOL_PREFIX)-gcc $(GCC_OPT) $(GCC_LIB_OPTS) -T ../support/orp.ld $? -o $@.or32 + $(OR32_TOOL_PREFIX)-objcopy -O binary $@.or32 $@.bin + ../utils/bin2hex $@.bin 1 -size_word > $@$(FLASH_MEM_HEX_FILE_SUFFIX).hex + ../utils/bin2vmem $@.bin > $@.vmem + + +gpio-icdc: gpio.o udelay.o ../support/reset-icdc.o $(common) $(drivers) + $(OR32_TOOL_PREFIX)-gcc $(GCC_OPT) $(GCC_LIB_OPTS) -T ../support/orp.ld $? -o $@.or32 + $(OR32_TOOL_PREFIX)-objcopy -O binary $@.or32 $@.bin + ../utils/bin2hex $@.bin 1 -size_word > $@$(FLASH_MEM_HEX_FILE_SUFFIX).hex + ../utils/bin2vmem $@.bin > $@.vmem + + +gpio.o: gpio.c + $(OR32_TOOL_PREFIX)-gcc $(GCC_OPT) $? -c -o $@ + +udelay.o: udelay.c + $(OR32_TOOL_PREFIX)-gcc $(GCC_OPT) $? -c -o $@ Index: release-1.0/utils/contributions/gpio/sw/old/gpio.c =================================================================== --- release-1.0/utils/contributions/gpio/sw/old/gpio.c (nonexistent) +++ release-1.0/utils/contributions/gpio/sw/old/gpio.c (revision 151) @@ -0,0 +1,351 @@ +#include "../support/support.h" +#include "../support/board.h" +#include "../support/uart.h" + +#include "../support/spr_defs.h" + +#include "gpio.h" + + +void uart_print_str(char *); +void uart_print_long(unsigned long); + +// Dummy or32 except vectors +void buserr_except(){} +void dpf_except(){} +void ipf_except(){} +void lpint_except(){} +void align_except(){} +void illegal_except(){} +/*void hpint_except(){ + +}*/ +void dtlbmiss_except(){} +void itlbmiss_except(){} +void range_except(){} +void syscall_except(){} +void res1_except(){} +void trap_except(){} +void res2_except(){} + + +void uart_interrupt() +{ + char lala; + unsigned char interrupt_id; + interrupt_id = REG8(UART_BASE + UART_IIR); + if ( interrupt_id & UART_IIR_RDI ) + { + lala = uart_getc(); + uart_putc(lala+1); + } +} + + +void uart_print_str(char *p) +{ + while(*p != 0) { + uart_putc(*p); + p++; + } +} + +void uart_print_long(unsigned long ul) +{ + int i; + char c; + + + uart_print_str("0x"); + for(i=0; i<8; i++) { + + c = (char) (ul>>((7-i)*4)) & 0xf; + if(c >= 0x0 && c<=0x9) + c += '0'; + else + c += 'a' - 10; + uart_putc(c); + } + +} + +void uart_print_short(unsigned long ul) +{ + int i; + char c; + char flag=0; + + + uart_print_str("0x"); + for(i=0; i<8; i++) { + + c = (char) (ul>>((7-i)*4)) & 0xf; + if(c >= 0x0 && c<=0x9) + c += '0'; + else + c += 'a' - 10; + if ((c != '0') || (i==7)) + flag=1; + if(flag) + uart_putc(c); + } + +} + +/* + * + * + * + * + * + * + * + * + * + */ + +void gpio_init(gpio_t *gpio, long instance_num, unsigned long base_addr) +{ + int i = MIN_GPIO_BIT; + + if ( gpio != NULL ) { + gpio->instance_num = instance_num; + gpio->base_addr = (unsigned char*)base_addr; + for ( ;i<=MAX_GPIO_BIT;i++) + gpio->vectors[i].vec = NULL; + return; + } else { + // Print the error msgs here + // + uart_print_str("gpio inst in NULL.\n"); + return; + } +} + +void gpio_config_bit(gpio_t *gpio, unsigned long bit, iotype_t io) +{ + if ( gpio != NULL ) { + if ( io == IO_INPUT ) { + gpio->io_config |= (1 << bit); + *(unsigned long*)(gpio->base_addr + OE_REG_OFFSET) &= (~(1 << bit)); + } else { + gpio->io_config &= (~(1 << bit)); + *(unsigned long*)(gpio->base_addr + OE_REG_OFFSET) |= (1 << bit); + } + return; + } else { + // Print the error msgs here + // + uart_print_str("gpio inst in NULL.\n"); + return; + } +} + +void gpio_set_bit(gpio_t *gpio, unsigned long bit, unsigned long val) +{ + if ( gpio != NULL ) { + if ( val != 0 ) + *(unsigned long*)(gpio->base_addr + OUT_REG_OFFSET) |= (1 << bit); + else + *(unsigned long*)(gpio->base_addr + OUT_REG_OFFSET) &= (~(1 << bit)); + return; + } else { + // Print the error msgs here + // + uart_print_str("gpio inst in NULL.\n"); + return; + } +} + +void gpio_get_bit(gpio_t *gpio, unsigned long bit, unsigned long *val) +{ + unsigned long temp; + + if ( gpio != NULL ) { + temp = *(unsigned long*)(gpio->base_addr + IN_REG_OFFSET); + *val = (temp & (1 << bit))? 1 : 0; + return; + } else { + // Print the error msgs here + // + uart_print_str("gpio inst in NULL.\n"); + return; + } +} + + +void gpio_add_interrupt(gpio_t *gpio, unsigned int bit, edge_t edge,void (*func)() ) +{ + if ( gpio != NULL ) { + if ( ( gpio->io_config &(1 << bit)) != 0 ) { // Port bit is configured as IO_INPUT + // + // Disable the interrupts + // + *(unsigned long*)(gpio->base_addr + CTRL_REG_OFFSET) &= (~0x01); + + // Enable the interrupt bit + // + *(unsigned long*)(gpio->base_addr + INTE_REG_OFFSET) |= (1 << bit); + + // Enable the edge type + // + if ( edge == POS_EDGE ) + *(unsigned long*)(gpio->base_addr + PTRIG_REG_OFFSET) |= (1 << bit); + else + *(unsigned long*)(gpio->base_addr + PTRIG_REG_OFFSET) &= (~(1 << bit)); + + // Set the function vector + // + gpio->vectors[bit].vec = func; + + int_add( 6, gpio_interrupt, gpio ); + + // Re-enable the global control bit + // + *(unsigned long*)(gpio->base_addr + CTRL_REG_OFFSET) |= 0x01; + } else { + // Port is configured as IO_OUTPUT + uart_print_str("gpio pin is not an input pin.\n"); + return; + } + + } else { + // Print the error msgs here + // + uart_print_str("gpio inst in NULL.\n"); + return; + } + +} + +void gpio_interrupt(gpio_t *gpio) +{ + int i; + unsigned long int interrupt_status; + + if ( (*(unsigned long*)(gpio->base_addr + CTRL_REG_OFFSET)) & 0x02 ) + { + // Interrupt is pending here + // + interrupt_status = *(unsigned long*)(gpio->base_addr + INTS_REG_OFFSET); + + // Prioritize from lower bits(0) to higher ones(31) + // + + for ( i=MIN_GPIO_BIT; i<=MAX_GPIO_BIT; i++ ) { + if ( (interrupt_status & (1<base_addr + INTS_REG_OFFSET) &= (~( 1 << i )); + (gpio->vectors[i].vec)(); + } + } + + *(unsigned long*)(gpio->base_addr + CTRL_REG_OFFSET) &= (~0x02); + + } +} + +void hello_east() +{ + uart_print_str("Hello from PUSH Button EAST.\n"); +} + + +void hello_west() +{ + uart_print_str("Hello from PUSH Button WEST.\n"); +} + + +void hello_south() +{ + uart_print_str("Hello from PUSH Button SOUTH.\n"); +} + + + + +#define MAX_COUNT 10 + +int main() +{ + gpio_t gpio_1; + unsigned long t0, t1, t2, t3; + unsigned long count = 0; + + uart_init(); + int_init(); + int_add(2,&uart_interrupt); + + gpio_init( &gpio_1, 1, GPIO_BASE ); + + gpio_config_bit( &gpio_1, LED_0, IO_OUTPUT); + gpio_config_bit( &gpio_1, LED_1, IO_OUTPUT); + gpio_config_bit( &gpio_1, LED_2, IO_OUTPUT); + gpio_config_bit( &gpio_1, LED_3, IO_OUTPUT); + gpio_config_bit( &gpio_1, LED_4, IO_OUTPUT); + gpio_config_bit( &gpio_1, LED_5, IO_OUTPUT); + gpio_config_bit( &gpio_1, LED_6, IO_OUTPUT); + gpio_config_bit( &gpio_1, LED_7, IO_OUTPUT); + + gpio_config_bit( &gpio_1, DIP_0, IO_INPUT); + gpio_config_bit( &gpio_1, DIP_1, IO_INPUT); + gpio_config_bit( &gpio_1, DIP_2, IO_INPUT); + gpio_config_bit( &gpio_1, DIP_3, IO_INPUT); + + uart_print_str("Demo 1 : Check for running LED patterns on board ...\n"); + + while ( count++ < MAX_COUNT ) { + gpio_set_bit( &gpio_1, LED_7, 0 ); + gpio_set_bit( &gpio_1, LED_0, 1 ); + udelay( 100000 ); + gpio_set_bit( &gpio_1, LED_0, 0 ); + gpio_set_bit( &gpio_1, LED_1, 1 ); + udelay( 100000 ); + gpio_set_bit( &gpio_1, LED_1, 0 ); + gpio_set_bit( &gpio_1, LED_2, 1 ); + udelay( 100000 ); + gpio_set_bit( &gpio_1, LED_2, 0 ); + gpio_set_bit( &gpio_1, LED_3, 1 ); + udelay( 100000 ); + gpio_set_bit( &gpio_1, LED_3, 0 ); + gpio_set_bit( &gpio_1, LED_4, 1 ); + udelay( 100000 ); + gpio_set_bit( &gpio_1, LED_4, 0 ); + gpio_set_bit( &gpio_1, LED_5, 1 ); + udelay( 100000 ); + gpio_set_bit( &gpio_1, LED_5, 0 ); + gpio_set_bit( &gpio_1, LED_6, 1 ); + udelay( 100000 ); + gpio_set_bit( &gpio_1, LED_6, 0 ); + gpio_set_bit( &gpio_1, LED_7, 1 ); + udelay( 100000 ); + } + + gpio_set_bit( &gpio_1, LED_7, 0 ); + + gpio_config_bit( &gpio_1, PUSH_EAST, IO_INPUT); + gpio_add_interrupt( &gpio_1, PUSH_EAST, POS_EDGE, hello_east ); + gpio_config_bit( &gpio_1, PUSH_WEST, IO_INPUT); + gpio_add_interrupt( &gpio_1, PUSH_WEST, POS_EDGE, hello_west ); + gpio_config_bit( &gpio_1, PUSH_SOUTH, IO_INPUT); + gpio_add_interrupt( &gpio_1, PUSH_SOUTH, POS_EDGE, hello_south ); + + uart_print_str("Demo 2 : Press the DIP switches and watch corresponding LED glow ...\n"); + + + while (1) { + gpio_get_bit( &gpio_1, DIP_0, &t0 ); + gpio_get_bit( &gpio_1, DIP_1, &t1 ); + gpio_get_bit( &gpio_1, DIP_2, &t2 ); + gpio_get_bit( &gpio_1, DIP_3, &t3 ); + // + gpio_set_bit( &gpio_1, LED_0, t0 ); + gpio_set_bit( &gpio_1, LED_1, t1 ); + gpio_set_bit( &gpio_1, LED_2, t2 ); + gpio_set_bit( &gpio_1, LED_3, t3 ); + } + + + report(0xdeaddead); + or32_exit(0); +} Index: release-1.0/utils/contributions/gpio/sw/old/udelay.c =================================================================== --- release-1.0/utils/contributions/gpio/sw/old/udelay.c (nonexistent) +++ release-1.0/utils/contributions/gpio/sw/old/udelay.c (revision 151) @@ -0,0 +1,17 @@ +#include "../support/support.h" +#include "../support/board.h" + + +void udelay(unsigned long); + +void udelay(unsigned long usecs) +{ + unsigned long i; + unsigned long cycles = usecs / (IN_CLK / 1000000 ); + unsigned long mem_dummy; + volatile unsigned long* ptr = &mem_dummy; + + for ( i=0; i< cycles; i++) + *ptr = 0xABCD; +} + Index: release-1.0/utils/contributions/gpio/sw/old/gpio.h =================================================================== --- release-1.0/utils/contributions/gpio/sw/old/gpio.h (nonexistent) +++ release-1.0/utils/contributions/gpio/sw/old/gpio.h (revision 151) @@ -0,0 +1,76 @@ +#ifndef __GPIO_H__ + +#define __GPIO_H__ + +#define MIN_GPIO_BIT 0 +#define MAX_GPIO_BIT 31 + +#define TOTAL_GPIO_BITS ((MAX_GPIO_BIT-MIN_GPIO_BIT+1)) + + +#define IN_REG_OFFSET 0x00 +#define OUT_REG_OFFSET 0x04 +#define OE_REG_OFFSET 0x08 +#define INTE_REG_OFFSET 0x0C +#define PTRIG_REG_OFFSET 0x10 +#define AUX_REG_OFFSET 0x14 +#define CTRL_REG_OFFSET 0x18 +#define INTS_REG_OFFSET 0x1C +#define ECLK_REG_OFFSET 0x20 +#define NEC_REG_OFFSET 0x24 + + +typedef struct vector_t_ +{ + void (*vec)(); +} vector_t; + +typedef struct gpio_t_ +{ + volatile unsigned char *base_addr; + unsigned int instance_num; + unsigned int io_config; + vector_t vectors[TOTAL_GPIO_BITS]; +} gpio_t; + +typedef enum iotype_t_ +{ + IO_OUTPUT = 0, + IO_INPUT = 1 +} iotype_t; + +typedef enum edge_t_ +{ + NEG_EDGE = 0, + POS_EDGE = 1 +} edge_t; + + +#define LED_0 0x00 +#define LED_1 0x01 +#define LED_2 0x02 +#define LED_3 0x03 +#define LED_4 0x04 +#define LED_5 0x05 +#define LED_6 0x06 +#define LED_7 0x07 + +#define DIP_0 0x08 +#define DIP_1 0x09 +#define DIP_2 0x0A +#define DIP_3 0x0B + +#define PUSH_EAST 0x0C +#define PUSH_WEST 0x0D +#define PUSH_NORTH 0x0E +#define PUSH_SOUTH 0x0F + + +void gpio_init(gpio_t *, long, unsigned long); +void gpio_config_bit(gpio_t *, unsigned long, iotype_t); +void gpio_set_bit(gpio_t *, unsigned long, unsigned long); +void gpio_get_bit(gpio_t *, unsigned long, unsigned long *); +void gpio_add_interrupt(gpio_t *, unsigned int, edge_t,void (*func)() ); +void gpio_interrupt(gpio_t *gpio); + +#endif Index: release-1.0/utils/contributions/gpio/sw/old/Makefile =================================================================== --- release-1.0/utils/contributions/gpio/sw/old/Makefile (nonexistent) +++ release-1.0/utils/contributions/gpio/sw/old/Makefile (revision 151) @@ -0,0 +1,26 @@ +include ../support/Makefile.inc +cases = gpio-nocache gpio-icdc +common = ../support/libsupport.a ../support/except.o + +all: $(cases) + +gpio-nocache: gpio.o udelay.o ../support/reset-nocache.o $(common) + $(OR32_TOOL_PREFIX)-gcc $(GCC_OPT) $(GCC_LIB_OPTS) -T ../support/orp.ld $? -o $@.or32 + $(OR32_TOOL_PREFIX)-objcopy -O binary $@.or32 $@.bin + ../utils/bin2hex $@.bin 1 -size_word > $@$(FLASH_MEM_HEX_FILE_SUFFIX).hex + ../utils/bin2vmem $@.bin > $@.vmem + + +gpio-icdc: gpio.o udelay.o ../support/reset-icdc.o + $(OR32_TOOL_PREFIX)-gcc $(GCC_OPT) $(GCC_LIB_OPTS) -T ../support/orp.ld $? -o $@.or32 $(common) + $(OR32_TOOL_PREFIX)-objcopy -O binary $@.or32 $@.bin + ../utils/bin2hex $@.bin 1 -size_word > $@$(FLASH_MEM_HEX_FILE_SUFFIX).hex + ../utils/bin2vmem $@.bin > $@.vmem + + +gpio.o: gpio.c + $(OR32_TOOL_PREFIX)-gcc $(GCC_OPT) $? -c -o $@ + +udelay.o: udelay.c + $(OR32_TOOL_PREFIX)-gcc $(GCC_OPT) $? -c -o $@ + Index: release-1.0/utils/contributions/setup/beautify.sh =================================================================== --- release-1.0/utils/contributions/setup/beautify.sh (nonexistent) +++ release-1.0/utils/contributions/setup/beautify.sh (revision 151) @@ -0,0 +1,45 @@ +#!/bin/bash +# Xanthopoulos Constantinos +# Some useful function for my scripts + +function cecho +{ + echo -e "\033[1m\033[33m$1\033[0m" +} + +function cnecho +{ + echo -e -n "\033[0m\033[33m$1\033[0m" +} + +function errormsg +{ + echo -e "\033[1m\033[31mError: $1\033[0m\n"; + exit 1; +} + +function execcmd +{ + # Print Message + echo -e "\033[35m$1\033[0m" + # Execute command + echo $2 + if [ $DEBUG -ne 1 ]; + then + eval $2; + fi; + # Check Execution + if [ $? -eq 0 ] + then + echo -e "\033[32mSuccessfully \"$1\"\033[0m\n"; + else + errormsg "$1"; + exit 1; + + fi +} + +if [ $DEBUG -eq 1 ] +then + cecho "Debug mode on! Nothing will actually run"; +fi Index: release-1.0/utils/contributions/setup/TODO.txt =================================================================== --- release-1.0/utils/contributions/setup/TODO.txt (nonexistent) +++ release-1.0/utils/contributions/setup/TODO.txt (revision 151) @@ -0,0 +1,4 @@ +# TODO list for the setup script + + * Install ftdi drivers according to the $ENV + * Test it in cygwin and freebsd. Index: release-1.0/utils/contributions/setup/minsoc-install.sh =================================================================== --- release-1.0/utils/contributions/setup/minsoc-install.sh (nonexistent) +++ release-1.0/utils/contributions/setup/minsoc-install.sh (revision 151) @@ -0,0 +1,132 @@ +#!/bin/bash +# Author: Constantinos Xanthopoulos +# This script install MinSOC tree +# under a specific directory. + +# ===== CONFIGURATIONS ===== +# ========================== + +# Where should I put the dir. minsoc? +# ex. /home/conx/Thesis/ +DIR_TO_INSTALL="" + +# This variable should be set to trunk +# or to stable. +VERSION="" + +# This variable should take one of +# the following values depending +# to your system: linux, cygwin, freebsd +ENV="" + +# !!! DO NOT EDIT BELLOW THIS LINE !!! +# =================================== + +# ===== SCRIPT ====== +# =================== + +# Debug ? +export DEBUG=0; +. beautify.sh + +# User check! +if [ `whoami` = "root" ]; +then + errormsg "You shouldn't be root for this script to run."; +fi; + +# Wizard +if [ -z ${DIR_TO_INSTALL} ] +then + cnecho "Give full path (ex. /home/foo/): "; + read DIR_TO_INSTALL; +fi + +# Directory exists? +if [ ! -d ${DIR_TO_INSTALL} ] +then + errormsg "Directory doesn't exist. Please create it"; +fi; + +cd ${DIR_TO_INSTALL} + +# Which Version? +if [ -z ${VERSION} ] +then + while [ "$VERSION" != "trunk" -a "$VERSION" != "stable" ] + do + cnecho "Select MinSOC Version [stable/trunk]: " + read VERSION; + done +fi + +if [ -z ${ENV} ] +then + while [ "$ENV" != "linux" -a "$ENV" != "cygwin" -a "$ENV" != "freebsd" ] + do + cnecho "Select build environment [linux/cygwin/freebsd]: " + read ENV; + done +fi + + + +# Checkout MinSOC +if [ "${VERSION}" = "trunk" ] +then + execcmd "Download minsoc" "svn co -q http://opencores.org/ocsvn/minsoc/minsoc/trunk/ minsoc" +else + execcmd "Download minsoc" "svn co -q http://opencores.org/ocsvn/minsoc/minsoc/tags/release-0.9/ minsoc" +fi + +cd minsoc/rtl/verilog + +execcmd "Checkout adv_jtag_bridge" "svn co -q http://opencores.org/ocsvn/adv_debug_sys/adv_debug_sys/trunk adv_debug_sys" +execcmd "Checkout ethmac" "svn co -q http://opencores.org/ocsvn/ethmac/ethmac/trunk ethmac" +execcmd "Checkout openrisc" "svn co -q http://opencores.org/ocsvn/openrisc/openrisc/trunk/or1200 or1200" +execcmd "Checkout uart" "svn co -q http://opencores.org/ocsvn/uart16550/uart16550/trunk uart16550" + +cecho "I will now start to compile everything that's needed"; + +cd ${DIR_TO_INSTALL}/minsoc/sw/utils + +echo $PWD + +execcmd "Make utils" "make" + +cd ../support + +execcmd "Make support tools" "make" + +cd ../drivers + +execcmd "Make drivers" "make" + + +cd ../uart + +execcmd "Make UART" "make" + +# adv_jtag_bridge install +cd ${DIR_TO_INSTALL}/minsoc/rtl/verilog/adv_debug_sys/Software/adv_jtag_bridge + +# FIXME: install FTDI headers for all build environments +#cecho "Installing FTDI headers! You will be asked to give root pass" + +#execcmd "Install FTDI headers" "su -c \"aptitude install libftdi-dev\""; + +if [ `grep "INCLUDE_JSP_SERVER=true" Makefile` != "" ] +then + cecho "Switching off the adv_jtag_bridge JSP_SERVER option"; + sed 's/INCLUDE_JSP_SERVER=true/INCLUDE_JSP_SERVER=false/' Makefile > TMPFILE && mv TMPFILE Makefile +fi + +if [ "${ENV}" != "cygwin" ] +then + cecho "Setting the right build environment"; + sed "s/BUILD_ENVIRONMENT=cygwin/BUILD_ENVIRONMENT=${ENV}/" Makefile > TMPFILE && mv TMPFILE Makefile +fi + +execcmd "Make adv_jtag_bridge" "make" + +cecho "Installation Finised"
release-1.0/utils/contributions/setup/minsoc-install.sh Property changes : Added: svn:executable ## -0,0 +1 ## +* \ No newline at end of property Index: release-1.0/utils/contributions/setup/toolchain-install.sh =================================================================== --- release-1.0/utils/contributions/setup/toolchain-install.sh (nonexistent) +++ release-1.0/utils/contributions/setup/toolchain-install.sh (revision 151) @@ -0,0 +1,51 @@ +#!/bin/bash +# Xanthopoulos Constantinos +# Installing OR GNU Toolchain. +# Only tested in Debian Squeeze. + + +# ===== CONFIGURATIONS ===== +# ========================== + +# Where will I put the binaries? +# ex. /opt/openrisc/bin +DIR_TO_INSTALL=""; + +# Debian's kernel architecture {32,64} +# ex. KERNEL_ARCH="32" +KERNEL_ARCH="" + +# ===== SCRIPT ====== +# =================== +export DEBUG=0; +. conxshlib.sh + +if [ `whoami` == "root" ]; +then + errormsg "You shouldn't be root for this script to run."; +fi; + +if [ ! -d $DIR_TO_INSTALL ] +then + errormsg "Directory doesn't exist. Please create it"; +fi; + +execcmd "Change permissions" "chmod 777 $DIR_TO_INSTALL"; + +cd $DIR_TO_INSTALL; + +if [ $KERNEL_ARCH == "32" ]; +then + execcmd "Download toolchain (it may take a while)" "wget ftp://ocuser:oc@opencores.org/toolchain/or32-elf-linux-x86.tar.bz2"; +elif [ $KERNEL_ARCH == "64"]; +then + execcmd "Download toolchain (it may take a while)" "wget ftp://ocuser:oc@opencores.org/toolchain/or32-elf-linux-x86_64.tar.bz2"; +else + errormsg "Not a correct architecture. Check Configurations"; +fi + +execcmd "Un-tar" "tar xf *bz2"; + +execcmd "Adding toolchain to PATH" "echo \"PATH=\\\$PATH:$DIR_TO_INSTALL/or32-elf/bin/\" >> /home/$(whoami)/.bashrc;"; + +cecho "Install completed"
release-1.0/utils/contributions/setup/toolchain-install.sh Property changes : Added: svn:executable ## -0,0 +1 ## +* \ No newline at end of property Index: release-1.0/utils/contributions/initialized_onchip_ram/minsoc_onchip_ram_top_altera.v =================================================================== --- release-1.0/utils/contributions/initialized_onchip_ram/minsoc_onchip_ram_top_altera.v (nonexistent) +++ release-1.0/utils/contributions/initialized_onchip_ram/minsoc_onchip_ram_top_altera.v (revision 151) @@ -0,0 +1,310 @@ +////////////////////////////////////////////////////////////////////// +//// //// +//// Generic Wishbone controller for //// +//// Single-Port Synchronous RAM //// +//// //// +//// This file is part of memory library available from //// +//// http://www.opencores.org/cvsweb.shtml/minsoc/ //// +//// //// +//// Description //// +//// This Wishbone controller connects to the wrapper of //// +//// the single-port synchronous memory interface. //// +//// Besides universal memory due to onchip_ram it provides a //// +//// generic way to set the depth of the memory. //// +//// //// +//// To Do: //// +//// //// +//// Author(s): //// +//// - Raul Fajardo, rfajardo@gmail.com //// +//// //// +////////////////////////////////////////////////////////////////////// +//// //// +//// Copyright (C) 2000 Authors and OPENCORES.ORG //// +//// //// +//// This source file may be used and distributed without //// +//// restriction provided that this copyright statement is not //// +//// removed from the file and that any derivative work contains //// +//// the original copyright notice and the associated disclaimer. //// +//// //// +//// This source file is free software; you can redistribute it //// +//// and/or modify it under the terms of the GNU Lesser General //// +//// Public License as published by the Free Software Foundation; //// +//// either version 2.1 of the License, or (at your option) any //// +//// later version. //// +//// //// +//// This source is distributed in the hope that it will be //// +//// useful, but WITHOUT ANY WARRANTY; without even the implied //// +//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR //// +//// PURPOSE. See the GNU Lesser General Public License for more //// +//// details. //// +//// //// +//// You should have received a copy of the GNU Lesser General //// +//// Public License along with this source; if not, download it //// +//// from http://www.gnu.org/licenses/lgpl.html //// +//// //// +////////////////////////////////////////////////////////////////////// +// +// Revision History +// +// Revision 1.1 2009/10/02 16:49 fajardo +// Not using the oe signal (output enable) from +// memories, instead multiplexing the outputs +// between the different instantiated blocks +// +// +// Revision 1.0 2009/08/18 15:15:00 fajardo +// Created interface and tested +// +`include "minsoc_defines.v" + +`define mem_init_file "uart-nocache.mif" //specific memory initalization file name, which can be intel hex(.hex) or Altera mif file + //if no initalization file used, give a name of "UNUSED" + +module minsoc_onchip_ram_top ( + wb_clk_i, wb_rst_i, + + wb_dat_i, wb_dat_o, wb_adr_i, wb_sel_i, wb_we_i, wb_cyc_i, + wb_stb_i, wb_ack_o, wb_err_o +); + +// +// Parameters +// +parameter adr_width = 13; //Memory address width, is composed by blocks of aw_int, is not allowed to be less than 12 +localparam aw_int = 11; //11 = 2048 +localparam blocks = (1<<(adr_width-aw_int)); //generated memory contains "blocks" memory blocks of 2048x32 2048 depth x32 bit data + +// +// I/O Ports +// +input wb_clk_i; +input wb_rst_i; + +// +// WB slave i/f +// +input [31:0] wb_dat_i; +output [31:0] wb_dat_o; +input [31:0] wb_adr_i; +input [3:0] wb_sel_i; +input wb_we_i; +input wb_cyc_i; +input wb_stb_i; +output wb_ack_o; +output wb_err_o; + +// +// Internal regs and wires +// +wire we; +wire [3:0] be_i; +wire [31:0] wb_dat_o; +reg ack_we; +reg ack_re; +// +// Aliases and simple assignments +// +assign wb_ack_o = ack_re | ack_we; +assign wb_err_o = wb_cyc_i & wb_stb_i & (|wb_adr_i[23:adr_width+2]); // If Access to > (8-bit leading prefix ignored) +assign we = wb_cyc_i & wb_stb_i & wb_we_i & (|wb_sel_i[3:0]); +assign be_i = (wb_cyc_i & wb_stb_i) * wb_sel_i; + +// +// Write acknowledge +// +always @ (negedge wb_clk_i or posedge wb_rst_i) +begin +if (wb_rst_i) + ack_we <= 1'b0; + else + if (wb_cyc_i & wb_stb_i & wb_we_i & ~ack_we) + ack_we <= #1 1'b1; + else + ack_we <= #1 1'b0; +end + +// +// read acknowledge +// +always @ (posedge wb_clk_i or posedge wb_rst_i) +begin + if (wb_rst_i) + ack_re <= 1'b0; + else + if (wb_cyc_i & wb_stb_i & ~wb_err_o & ~wb_we_i & ~ack_re) + ack_re <= #1 1'b1; + else + ack_re <= #1 1'b0; +end + +`ifdef ALTERA_FPGA //only for altera memory initialization + +//2^adr_width x 32bit single-port ram. +altsyncram altsyncram_component ( + .wren_a (we), + .clock0 (wb_clk_i), + .byteena_a (be_i), + .address_a (wb_adr_i[adr_width+1:2]), + .data_a (wb_dat_i), + .q_a (wb_dat_o), + .aclr0 (1'b0), + .aclr1 (1'b0), + .address_b (1'b1), + .addressstall_a (1'b0), + .addressstall_b (1'b0), + .byteena_b (1'b1), + .clock1 (1'b1), + .clocken0 (1'b1), + .clocken1 (1'b1), + .clocken2 (1'b1), + .clocken3 (1'b1), + .data_b (1'b1), + .eccstatus (), + .q_b (), + .rden_a (1'b1), + .rden_b (1'b1), + .wren_b (1'b0)); + defparam + altsyncram_component.clock_enable_input_a = "BYPASS", + altsyncram_component.clock_enable_output_a = "BYPASS", + altsyncram_component.init_file = `mem_init_file, + altsyncram_component.intended_device_family = "Stratix III", + altsyncram_component.lpm_hint = "ENABLE_RUNTIME_MOD=NO", + altsyncram_component.lpm_type = "altsyncram", + altsyncram_component.operation_mode = "SINGLE_PORT", + altsyncram_component.outdata_aclr_a = "NONE", + altsyncram_component.outdata_reg_a = "UNREGISTERED", + altsyncram_component.power_up_uninitialized = "FALSE", + altsyncram_component.read_during_write_mode_port_a = "NEW_DATA_NO_NBE_READ", + altsyncram_component.numwords_a = (1<>(j+1)); k=k+1) begin : MUX + if (j==0) begin + mux2 # + ( + .dw(32) + ) + mux_int( + .sel( wb_adr_i[aw_int+2+j] ), + .in1( int_dat_o[k*2] ), + .in2( int_dat_o[k*2+1] ), + .out( mux_out[k] ) + ); + end + else begin + mux2 # + ( + .dw(32) + ) + mux_int( + .sel( wb_adr_i[aw_int+2+j] ), + .in1( mux_out[(mux_in_nr-(mux_in_nr>>(j-1)))+k*2] ), + .in2( mux_out[(mux_in_nr-(mux_in_nr>>(j-1)))+k*2+1] ), + .out( mux_out[(mux_in_nr-(mux_in_nr>>j))+k] ) + ); + end + end + end +endgenerate + +//last output = total output +assign wb_dat_o = mux_out[mux_out_nr-1]; + +//(mux_in_nr-(mux_in_nr>>j)): +//-Given sum of 2^i | i = x -> y series can be resumed to 2^(y+1)-2^x +//so, with this expression I'm evaluating how many times the internal loop has been run + +wire [blocks-1:0] bank; + +generate +genvar i; + for (i=0; i < blocks; i=i+1) begin : MEM + + assign bank[i] = wb_adr_i[adr_width+1:aw_int+2] == i; + + //BANK0 + minsoc_onchip_ram block_ram_0 ( + .clk(wb_clk_i), + .rst(wb_rst_i), + .addr(wb_adr_i[aw_int+1:2]), + .di(wb_dat_i[7:0]), + .doq(int_dat_o[i][7:0]), + .we(we & bank[i]), + .oe(1'b1), + .ce(be_i[0]) + ); + + + minsoc_onchip_ram block_ram_1 ( + .clk(wb_clk_i), + .rst(wb_rst_i), + .addr(wb_adr_i[aw_int+1:2]), + .di(wb_dat_i[15:8]), + .doq(int_dat_o[i][15:8]), + .we(we & bank[i]), + .oe(1'b1), + .ce(be_i[1]) + ); + + minsoc_onchip_ram block_ram_2 ( + .clk(wb_clk_i), + .rst(wb_rst_i), + .addr(wb_adr_i[aw_int+1:2]), + .di(wb_dat_i[23:16]), + .doq(int_dat_o[i][23:16]), + .we(we & bank[i]), + .oe(1'b1), + .ce(be_i[2]) + ); + + minsoc_onchip_ram block_ram_3 ( + .clk(wb_clk_i), + .rst(wb_rst_i), + .addr(wb_adr_i[aw_int+1:2]), + .di(wb_dat_i[31:24]), + .doq(int_dat_o[i][31:24]), + .we(we & bank[i]), + .oe(1'b1), + .ce(be_i[3]) + ); + + end +endgenerate +`endif + +endmodule + +module mux2(sel,in1,in2,out); + +parameter dw = 32; + +input sel; +input [dw-1:0] in1, in2; +output reg [dw-1:0] out; + +always @ (sel or in1 or in2) +begin + case (sel) + 1'b0: out = in1; + 1'b1: out = in2; + endcase +end + +endmodule Index: release-1.0/utils/contributions/initialized_onchip_ram/bin2init.py =================================================================== --- release-1.0/utils/contributions/initialized_onchip_ram/bin2init.py (nonexistent) +++ release-1.0/utils/contributions/initialized_onchip_ram/bin2init.py (revision 151) @@ -0,0 +1,212 @@ +""" +***************************************************************************** + * + H E A D E R I N F O R M A T I O N * + * +***************************************************************************** +Project Name : SysPy (System Python) + http://cgi.di.uoa.gr/~evlog/syspy.html + +File Name : bin2init.py + +Created by : Evangelos Logaras + + +***************************************************************************** + * + C O P Y R I G H T N O T I C E * + * +***************************************************************************** + + This library is free software; you can redistribute it and/or + modify it under the terms of the GNU Lesser General Public + License as published by the Free Software Foundation; + version 2.1 of the License, a copy of which is available from + http://www.gnu.org/licenses/old-licenses/lgpl-2.1.txt. + + This library is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + Lesser General Public License for more details. + + You should have received a copy of the GNU Lesser General Public + License along with this library; if not, write to the Free Software + Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA + + +***************************************************************************** + * + D E S C R I P T I O N * + * +***************************************************************************** + + Generates block_ram.init file from binary images. Binary images are first converted in hex files + using bin2hex.c file, provided with the ORPSoC v2 project. bin2hex executable must exist in the same folder with this script. + + Currently init file is generated for Xilinx's RAMB16_S9 BRAMs + + Usage: python bin2init.py (Python 2.6) +""" + +import commands +import sys + + +# Python's variable declarations +#---------------------------------------------------------------------------------------------------------------------------------- +y = ' ' +mem_arr = [] +block_ram_num = 4 +block0 = [] +block1 = [] +block2 = [] +block3 = [] +block_ram = [block3, block2, block1, block0] +init_arr = [] +mem_size2 = 8192 +mem_count = 0 +bram_count = -1 +init_count = -1 +hex_count = 0 +zero_pad = '' +filename = '' +#---------------------------------------------------------------------------------------------------------------------------------- + +# Exceptions' class +#---------------------------------------------------------------------------------------------------------------------------------- +class MyExceptions(Exception): + def __init__(self, value): + self.value = value + def __str__(self): + return repr(self.value) +#---------------------------------------------------------------------------------------------------------------------------------- + +# Raising exception if a *.bin file is not provided as an argument +#---------------------------------------------------------------------------------------------------------------------------------- +filename = sys.argv[len(sys.argv) - 1] + +if (filename.find(".bin") == -1): + raise MyExceptions("*.bin file required") +#---------------------------------------------------------------------------------------------------------------------------------- + +i = filename.find(".bin") + +filename = filename[:i] + +# Deleting old *.hex and *.bin files +#---------------------------------------------------------------------------------------------------------------------------------- +commands.getoutput("rm " + filename + ".hex") +commands.getoutput("rm " + filename + ".init") +#---------------------------------------------------------------------------------------------------------------------------------- + +## Calling bin2hex executable to convert *.bin file to *.hex +commands.getoutput("./bin2hex " + filename + ".bin 4 > "+ filename + ".hex") + +# Opening the *.hex and the *.init file +#---------------------------------------------------------------------------------------------------------------------------------- +hexFile = open(filename + ".hex", 'r') +initFile = open(filename + ".init", 'w') +#---------------------------------------------------------------------------------------------------------------------------------- + +# Reading the *.hex file and appending its contents to mem_arr[] +#---------------------------------------------------------------------------------------------------------------------------------- +y = ' ' +hex_count = 0 +while(y): + hex_count = hex_count + 1 + if (hex_count == 127): + mem_arr.append("00000000") + + y = hexFile.readline() + mem_arr.append(y) +#---------------------------------------------------------------------------------------------------------------------------------- + +# Reading mem_arr[] and creating the contents of BRAMs +#---------------------------------------------------------------------------------------------------------------------------------- +for i in range(len(mem_arr)): + bram_count = bram_count + 1 + if (bram_count < 32): + block_ram[0].append(mem_arr[i][6:8]) + block_ram[1].append(mem_arr[i][4:6]) + block_ram[2].append(mem_arr[i][2:4]) + block_ram[3].append(mem_arr[i][0:2]) + + elif (bram_count >= 32): + bram_count = 0 + + init_count = init_count + 1 + + if (init_count >= 64): + init_count = 0 + mem_count = mem_count + 1 + + hex_init_count = str(hex(init_count)) + hex_init_count = hex_init_count[2:] + hex_init_count = hex_init_count.upper() + if (init_count < 16): + hex_init_count = '0' + hex_init_count + + + for j in range((block_ram_num - 1), -1, -1): + if (j == (block_ram_num - 1)): + init_arr.append(";\ndefparam MEM[" + str(mem_count) + "].block_ram_" + str(j) + ".INIT_" + hex_init_count + " = 256'h") + block_ram[j].reverse() + for k in range(len(block_ram[j])): + init_arr.append(block_ram[j][k].replace("\n", '')) + else: + init_arr.append(";\ndefparam MEM[" + str(mem_count) + "].block_ram_" + str(j) + ".INIT_" + hex_init_count + " = 256'h") + block_ram[j].reverse() + for k in range(len(block_ram[j])): + init_arr.append(block_ram[j][k].replace("\n", '')) + + block_ram[0] = [] + block_ram[1] = [] + block_ram[2] = [] + block_ram[3] = [] + + block_ram[0].append(mem_arr[i][6:8]) + block_ram[1].append(mem_arr[i][4:6]) + block_ram[2].append(mem_arr[i][2:4]) + block_ram[3].append(mem_arr[i][0:2]) + + +if (bram_count != -1): + init_count = init_count + 1 + hex_init_count = str(hex(init_count)) + hex_init_count = hex_init_count[2:] + hex_init_count = hex_init_count.upper() + if (init_count < 16): + hex_init_count = '0' + hex_init_count + + if (init_count == 0): + for j in range(64 - 2 * bram_count): + zero_pad = zero_pad + '0' + else: + for j in range(64 - 2 * bram_count): + zero_pad = zero_pad + '0' + + for j in range((block_ram_num - 1), -1, -1): + init_arr.append(";\ndefparam MEM[" + str(mem_count) + "].block_ram_" + str(j) + ".INIT_" + hex_init_count + " = 256'h") + block_ram[j].reverse() + init_arr.append(zero_pad) + for k in range(len(block_ram[j])): + init_arr.append(block_ram[j][k].replace("\n", '')) + +init_arr.append(';') +#---------------------------------------------------------------------------------------------------------------------------------- + +# Writing BRAMs contetns to *.init file +#---------------------------------------------------------------------------------------------------------------------------------- +i = init_arr[0].find(";/n") + +init_arr[0] = init_arr[0][i + 2:] + +for i in range(len(init_arr)): + initFile.write(init_arr[i]) +#---------------------------------------------------------------------------------------------------------------------------------- + +# Closing the *.hex and the *.init file +#---------------------------------------------------------------------------------------------------------------------------------- +hexFile.close() +initFile.close() +#---------------------------------------------------------------------------------------------------------------------------------- Index: release-1.0/utils/contributions/initialized_onchip_ram/minsoc_onchip_ram_top_xilinx.v =================================================================== --- release-1.0/utils/contributions/initialized_onchip_ram/minsoc_onchip_ram_top_xilinx.v (nonexistent) +++ release-1.0/utils/contributions/initialized_onchip_ram/minsoc_onchip_ram_top_xilinx.v (revision 151) @@ -0,0 +1,312 @@ +////////////////////////////////////////////////////////////////////// +//// //// +//// Generic Wishbone controller for //// +//// Single-Port Synchronous RAM //// +//// //// +//// This file is part of memory library available from //// +//// http://www.opencores.org/cvsweb.shtml/minsoc/ //// +//// //// +//// Description //// +//// This Wishbone controller connects to the wrapper of //// +//// the single-port synchronous memory interface. //// +//// Besides universal memory due to onchip_ram it provides a //// +//// generic way to set the depth of the memory. //// +//// //// +//// To Do: //// +//// //// +//// Author(s): //// +//// - Raul Fajardo, rfajardo@gmail.com //// +//// //// +////////////////////////////////////////////////////////////////////// +//// //// +//// Copyright (C) 2000 Authors and OPENCORES.ORG //// +//// //// +//// This source file may be used and distributed without //// +//// restriction provided that this copyright statement is not //// +//// removed from the file and that any derivative work contains //// +//// the original copyright notice and the associated disclaimer. //// +//// //// +//// This source file is free software; you can redistribute it //// +//// and/or modify it under the terms of the GNU Lesser General //// +//// Public License as published by the Free Software Foundation; //// +//// either version 2.1 of the License, or (at your option) any //// +//// later version. //// +//// //// +//// This source is distributed in the hope that it will be //// +//// useful, but WITHOUT ANY WARRANTY; without even the implied //// +//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR //// +//// PURPOSE. See the GNU Lesser General Public License for more //// +//// details. //// +//// //// +//// You should have received a copy of the GNU Lesser General //// +//// Public License along with this source; if not, download it //// +//// from http://www.gnu.org/licenses/lgpl.html //// +//// //// +////////////////////////////////////////////////////////////////////// +// +// Revision History +// +// Revision 1.1 2009/10/02 16:49 fajardo +// Not using the oe signal (output enable) from +// memories, instead multiplexing the outputs +// between the different instantiated blocks +// +// +// Revision 1.0 2009/08/18 15:15:00 fajardo +// Created interface and tested +// +`include "minsoc_defines.v" + +module minsoc_onchip_ram_top ( + wb_clk_i, wb_rst_i, + + wb_dat_i, wb_dat_o, wb_adr_i, wb_sel_i, wb_we_i, wb_cyc_i, + wb_stb_i, wb_ack_o, wb_err_o +); + +// +// Parameters +// +parameter adr_width = 13; //Memory address width, is composed by blocks of aw_int, is not allowed to be less than 12 +localparam aw_int = 11; //11 = 2048 +localparam blocks = (1<<(adr_width-aw_int)); //generated memory contains "blocks" memory blocks of 2048x32 2048 depth x32 bit data + +// +// I/O Ports +// +input wb_clk_i; +input wb_rst_i; + +// +// WB slave i/f +// +input [31:0] wb_dat_i; +output [31:0] wb_dat_o; +input [31:0] wb_adr_i; +input [3:0] wb_sel_i; +input wb_we_i; +input wb_cyc_i; +input wb_stb_i; +output wb_ack_o; +output wb_err_o; + +// +// Internal regs and wires +// +wire we; +wire [3:0] be_i; +wire [31:0] wb_dat_o; +reg ack_we; +reg ack_re; +// +// Aliases and simple assignments +// +assign wb_ack_o = ack_re | ack_we; +assign wb_err_o = wb_cyc_i & wb_stb_i & (|wb_adr_i[23:adr_width+2]); // If Access to > (8-bit leading prefix ignored) +assign we = wb_cyc_i & wb_stb_i & wb_we_i & (|wb_sel_i[3:0]); +assign be_i = (wb_cyc_i & wb_stb_i) * wb_sel_i; + +// +// Write acknowledge +// +always @ (negedge wb_clk_i or posedge wb_rst_i) +begin +if (wb_rst_i) + ack_we <= 1'b0; + else + if (wb_cyc_i & wb_stb_i & wb_we_i & ~ack_we) + ack_we <= #1 1'b1; + else + ack_we <= #1 1'b0; +end + +// +// read acknowledge +// +always @ (posedge wb_clk_i or posedge wb_rst_i) +begin + if (wb_rst_i) + ack_re <= 1'b0; + else + if (wb_cyc_i & wb_stb_i & ~wb_err_o & ~wb_we_i & ~ack_re) + ack_re <= #1 1'b1; + else + ack_re <= #1 1'b0; +end + +//Generic (multiple inputs x 1 output) MUX +localparam mux_in_nr = blocks; +localparam slices = adr_width-aw_int; +localparam mux_out_nr = blocks-1; + +wire [31:0] int_dat_o[0:mux_in_nr-1]; +wire [31:0] mux_out[0:mux_out_nr-1]; + +generate +genvar j, k; + for (j=0; j>(j+1)); k=k+1) begin : MUX + if (j==0) begin + mux21 # + ( + .dw(32) + ) + mux_int( + .sel( wb_adr_i[aw_int+2+j] ), + .in1( int_dat_o[k*2] ), + .in2( int_dat_o[k*2+1] ), + .out( mux_out[k] ) + ); + end + else begin + mux21 # + ( + .dw(32) + ) + mux_int( + .sel( wb_adr_i[aw_int+2+j] ), + .in1( mux_out[(mux_in_nr-(mux_in_nr>>(j-1)))+k*2] ), + .in2( mux_out[(mux_in_nr-(mux_in_nr>>(j-1)))+k*2+1] ), + .out( mux_out[(mux_in_nr-(mux_in_nr>>j))+k] ) + ); + end + end + end +endgenerate + +//last output = total output +assign wb_dat_o = mux_out[mux_out_nr-1]; + +//(mux_in_nr-(mux_in_nr>>j)): +//-Given sum of 2^i | i = x -> y series can be resumed to 2^(y+1)-2^x +//so, with this expression I'm evaluating how many times the internal loop has been run + +wire [blocks-1:0] bank; + +generate +genvar i; + for (i=0; i < blocks; i=i+1) begin : MEM + + assign bank[i] = wb_adr_i[adr_width+1:aw_int+2] == i; + + //BANK0 +/* minsoc_onchip_ram block_ram_0 ( + .clk(wb_clk_i), + .rst(wb_rst_i), + .addr(wb_adr_i[aw_int+1:2]), + .di(wb_dat_i[7:0]), + .doq(int_dat_o[i][7:0]), + .we(we & bank[i]), + .oe(1'b1), + .ce(be_i[0]) + ); +*/ + RAMB16_S9 block_ram_0( + .CLK(wb_clk_i), + .SSR(wb_rst_i), + .ADDR(wb_adr_i[aw_int+1:2]), + .DI(wb_dat_i[7:0]), + .DIP(1'b0), + .EN(be_i[0]), + .WE(we & bank[i]), + .DO(int_dat_o[i][7:0]), + .DOP() + ); + +/* + minsoc_onchip_ram block_ram_1 ( + .clk(wb_clk_i), + .rst(wb_rst_i), + .addr(wb_adr_i[aw_int+1:2]), + .di(wb_dat_i[15:8]), + .doq(int_dat_o[i][15:8]), + .we(we & bank[i]), + .oe(1'b1), + .ce(be_i[1]) + ); +*/ + RAMB16_S9 block_ram_1( + .CLK(wb_clk_i), + .SSR(wb_rst_i), + .ADDR(wb_adr_i[aw_int+1:2]), + .DI(wb_dat_i[15:8]), + .DIP(1'b0), + .EN(be_i[1]), + .WE(we & bank[i]), + .DO(int_dat_o[i][15:8]), + .DOP() + ); +/* + minsoc_onchip_ram block_ram_2 ( + .clk(wb_clk_i), + .rst(wb_rst_i), + .addr(wb_adr_i[aw_int+1:2]), + .di(wb_dat_i[23:16]), + .doq(int_dat_o[i][23:16]), + .we(we & bank[i]), + .oe(1'b1), + .ce(be_i[2]) + ); +*/ + RAMB16_S9 block_ram_2( + .CLK(wb_clk_i), + .SSR(wb_rst_i), + .ADDR(wb_adr_i[aw_int+1:2]), + .DI(wb_dat_i[23:16]), + .DIP(1'b0), + .EN(be_i[2]), + .WE(we & bank[i]), + .DO(int_dat_o[i][23:16]), + .DOP() + ); + +/* + minsoc_onchip_ram block_ram_3 ( + .clk(wb_clk_i), + .rst(wb_rst_i), + .addr(wb_adr_i[aw_int+1:2]), + .di(wb_dat_i[31:24]), + .doq(int_dat_o[i][31:24]), + .we(we & bank[i]), + .oe(1'b1), + .ce(be_i[3]) + ); +*/ + RAMB16_S9 block_ram_3( + .CLK(wb_clk_i), + .SSR(wb_rst_i), + .ADDR(wb_adr_i[aw_int+1:2]), + .DI(wb_dat_i[31:24]), + .DIP(1'b0), + .EN(be_i[3]), + .WE(we & bank[i]), + .DO(int_dat_o[i][31:24]), + .DOP() + ); + + end +endgenerate + +`ifdef BLOCK_RAM_INIT +`include "block_ram.init" +`endif + +endmodule + +module mux21(sel,in1,in2,out); + +parameter dw = 32; + +input sel; +input [dw-1:0] in1, in2; +output reg [dw-1:0] out; + +always @ (sel or in1 or in2) +begin + case (sel) + 1'b0: out = in1; + 1'b1: out = in2; + endcase +end + +endmodule Index: release-1.0/utils/contributions/synthesis_makefile/guideTop.pdf =================================================================== Cannot display: file marked as a binary type. svn:mime-type = application/octet-stream Index: release-1.0/utils/contributions/synthesis_makefile/guideTop.pdf =================================================================== --- release-1.0/utils/contributions/synthesis_makefile/guideTop.pdf (nonexistent) +++ release-1.0/utils/contributions/synthesis_makefile/guideTop.pdf (revision 151)
release-1.0/utils/contributions/synthesis_makefile/guideTop.pdf Property changes : Added: svn:mime-type ## -0,0 +1 ## +application/octet-stream \ No newline at end of property Index: release-1.0/utils/contributions/synthesis_makefile/Makefile =================================================================== --- release-1.0/utils/contributions/synthesis_makefile/Makefile (nonexistent) +++ release-1.0/utils/contributions/synthesis_makefile/Makefile (revision 151) @@ -0,0 +1,107 @@ +ROOT = /home/mdhicks2/Desktop/softPatch/baseSoC +MINSOC = $(ROOT)/minsoc +MINSOC_RTL = $(MINSOC)/rtl/verilog +UART_RTL = $(ROOT)/uart16550/rtl/verilog +ADV_DEBUG_ROOT = $(ROOT)/adv_debug_sys/Hardware +DEBUG_RTL = $(ADV_DEBUG_ROOT)/adv_dbg_if/rtl/verilog +XIL_DEBUG_RTL = $(ADV_DEBUG_ROOT)/xilinx_internal_jtag/rtl/verilog +OR1200_RTL = $(ROOT)/or1200/rtl/verilog + +help: + @echo " all: Synthesize and implement the SoC, then generate a bit stream" + @echo " soc: Synthesize the SoC" + @echo " translate: Convert the SoC's ngc file to an ngd file for mapping" + @echo " map: Express the SoC netlist in the target hardware" + @echo " par: Place the target hardware, then route the wires" + @echo " bitgen: Generate a programming file for the target FPGA" + @echo " clean: Delete all superfluous files generated by Xilinx tools" + @echo " distclean: Delete all generated files" + @echo " uart: Synthesize the UART" + @echo " debug: Synthesize the debug interface" + @echo " xilDebug: Synthesize the Xilinx JTAG user interface" + @echo " or1200: Synthesize the OR1200 processor" +all: minsoc_top.ngc minsoc.ngd minsoc.ncd minsoc_par.ncd minsoc.bit +soc: minsoc_top.ngc +translate: minsoc.ngd +map: minsoc.ncd +par: minsoc_par.ncd +bitgen: minsoc.bit + +distclean: + rm -f _xmsgs xst *.{ngc,ncd,ngd,bit,xst,xrpt,srp,lso,log} +clean: + rm -f _xmsgs xst *.{xst,xrpt,srp,lso,log} + +minsoc_top.ngc: $(MINSOC_RTL)/*.v buildSupport/*.xst buildSupport/*.prj #uart_top.ngc adbg_top.ngc xilinx_internal_jtag.ngc or1200_top.ngc + xst -ifn "buildSupport/minsoc_top.xst" + rm -f minsoc_top_xst.xrpt + rm -f minsoc_top.srp + rm -f minsoc_top.lso + rm -rf _xmsgs + rm -rf xst +uart: uart_top.ngc +uart_top.ngc: $(UART_RTL)/*.v buildSupport/uart_top.xst buildSupport/uart_top.prj + xst -ifn "buildSupport/uart_top.xst" + rm -f uart_top_xst.xrpt + rm -f uart_top.srp + rm -f uart_top.lso + rm -rf _xmsgs + rm -rf xst +debug: adbg_top.ngc +adbg_top.ngc: $(DEBUG_RTL)/*.v buildSupport/adbg_top.xst buildSupport/adbg_top.prj + xst -ifn "buildSupport/adbg_top.xst" + rm -f adbg_top_xst.xrpt + rm -f adbg_top.srp + rm -f adbg_top.lso + rm -rf _xmsgs + rm -rf xst +xilDebug: xilinx_internal_jtag.ngc +xilinx_internal_jtag.ngc: $(XIL_DEBUG_RTL)/*.v buildSupport/xilinx_internal_jtag.xst buildSupport/xilinx_internal_jtag.prj + xst -ifn "buildSupport/xilinx_internal_jtag.xst" + rm -f xilinx_internal_jtag_xst.xrpt + rm -f xilinx_internal_jtag.srp + rm -f xilinx_internal_jtag.lso + rm -rf _xmsgs + rm -rf xst +or1200: or1200_top.ngc +or1200_top.ngc: $(OR1200_RTL)/*.v buildSupport/or1200_top.xst buildSupport/or1200_top.prj + xst -ifn "buildSupport/or1200_top.xst" + rm -f or1200_top_xst.xrpt + rm -f or1200_top.srp + rm -f or1200_top.lso + rm -rf _xmsgs + rm -rf xst +minsoc.ngd: $(MINSOC)/backend/ml509.ucf minsoc_top.ngc + ngdbuild -p xc5vlx110t-ff1136-3 -uc $(MINSOC)/backend/ml509.ucf -aul -aut minsoc_top.ngc minsoc.ngd + rm -rf netlist.lst + rm -rf minsoc.bld + rm -rf minsoc*.xrpt + rm -rf xlnx_auto_0_xdb + rm -rf _xmsgs +minsoc.ncd : minsoc.ngd + map -bp -timing -cm speed -equivalent_register_removal on -global_opt speed -logic_opt on -mt 2 -ol high -power off -register_duplication on -retiming on -w -xe n minsoc.ngd + rm -rf minsoc.map + rm -rf minsoc.mrp + rm -rf minsoc.ngm + rm -rf minsoc.pcf + rm -rf minsoc.psr + rm -rf minsoc*.xml + rm -rf minsoc_top*.xrpt + rm -rf _xmsgs +minsoc_par.ncd: minsoc.ncd + par -mt 4 -ol high -w -xe n minsoc.ncd minsoc_par.ncd + rm -rf minsoc_par.pad + rm -rf minsoc_par.par + rm -rf minsoc_par.ptwx + rm -rf minsoc_par.unroutes + rm -rf minsoc_par.xpi + rm -rf minsoc_par_pad* + rm -rf minsoc_top*.xrpt + rm -rf _xmsgs +minsoc.bit: minsoc_par.ncd + bitgen -d -w minsoc_par.ncd minsoc.bit + rm -rf minsoc.bgn + rm -rf *.xwbt + rm -rf *.xml + rm -rf *.log + rm -rf _xmsgs Index: release-1.0/utils/contributions/minsoc_tc_top_B3.v =================================================================== --- release-1.0/utils/contributions/minsoc_tc_top_B3.v (nonexistent) +++ release-1.0/utils/contributions/minsoc_tc_top_B3.v (revision 151) @@ -0,0 +1,1883 @@ +////////////////////////////////////////////////////////////////////// +//// //// +//// Xess Traffic Cop //// +//// //// +//// This file is part of the OR1K test application //// +//// http://www.opencores.org/cores/or1k/ //// +//// //// +//// Description //// +//// This block connectes the RISC and peripheral controller //// +//// cores together. //// +//// //// +//// To Do: //// +//// - nothing really //// +//// //// +//// Author(s): //// +//// - Damjan Lampret, lampret@opencores.org //// +//// //// +////////////////////////////////////////////////////////////////////// +//// //// +//// Copyright (C) 2002 OpenCores //// +//// //// +//// This source file may be used and distributed without //// +//// restriction provided that this copyright statement is not //// +//// removed from the file and that any derivative work contains //// +//// the original copyright notice and the associated disclaimer. //// +//// //// +//// This source file is free software; you can redistribute it //// +//// and/or modify it under the terms of the GNU Lesser General //// +//// Public License as published by the Free Software Foundation; //// +//// either version 2.1 of the License, or (at your option) any //// +//// later version. //// +//// //// +//// This source is distributed in the hope that it will be //// +//// useful, but WITHOUT ANY WARRANTY; without even the implied //// +//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR //// +//// PURPOSE. See the GNU Lesser General Public License for more //// +//// details. //// +//// //// +//// You should have received a copy of the GNU Lesser General //// +//// Public License along with this source; if not, download it //// +//// from http://www.opencores.org/lgpl.shtml //// +//// //// +////////////////////////////////////////////////////////////////////// +// +// CVS Revision History +// +// $Log: tc_top.v,v $ +// Revision 1.4 2004/04/05 08:44:34 lampret +// Merged branch_qmem into main tree. +// +// Revision 1.2 2002/03/29 20:57:30 lampret +// Removed unused ports wb_clki and wb_rst_i +// +// Revision 1.1.1.1 2002/03/21 16:55:44 lampret +// First import of the "new" XESS XSV environment. +// +// +// + +// synopsys translate_off +`include "timescale.v" +// synopsys translate_on + +// +// Width of address bus +// +`define TC_AW 32 + +// +// Width of data bus +// +`define TC_DW 32 + +// +// Width of byte select bus +// +`define TC_BSW 4 + +// +// Width of WB target inputs (coming from WB slave) +// +// data bus width + ack + err +// +`define TC_TIN_W `TC_DW+1+1 + +// +// Width of WB initiator inputs (coming from WB masters) +// +// cyc + stb + address bus width + +// byte select bus width + we + data bus width +// +`define TC_IIN_W 1+1+1+`TC_AW+`TC_BSW+1+`TC_DW + +// +// Traffic Cop Top +// +module minsoc_tc_top ( + wb_clk_i, + wb_rst_i, + + i0_wb_cyc_i, + i0_wb_stb_i, + i0_wb_adr_i, + i0_wb_sel_i, + i0_wb_we_i, + i0_wb_dat_i, + i0_wb_dat_o, + i0_wb_ack_o, + i0_wb_err_o, + i0_wb_cti_i, + i0_wb_bte_i, + + i1_wb_cyc_i, + i1_wb_stb_i, + i1_wb_adr_i, + i1_wb_sel_i, + i1_wb_we_i, + i1_wb_dat_i, + i1_wb_dat_o, + i1_wb_ack_o, + i1_wb_err_o, + i1_wb_cti_i, + i1_wb_bte_i, + + i2_wb_cyc_i, + i2_wb_stb_i, + i2_wb_adr_i, + i2_wb_sel_i, + i2_wb_we_i, + i2_wb_dat_i, + i2_wb_dat_o, + i2_wb_ack_o, + i2_wb_err_o, + i2_wb_cti_i, + i2_wb_bte_i, + + i3_wb_cyc_i, + i3_wb_stb_i, + i3_wb_adr_i, + i3_wb_sel_i, + i3_wb_we_i, + i3_wb_dat_i, + i3_wb_dat_o, + i3_wb_ack_o, + i3_wb_err_o, + i3_wb_cti_i, + i3_wb_bte_i, + + i4_wb_cyc_i, + i4_wb_stb_i, + i4_wb_adr_i, + i4_wb_sel_i, + i4_wb_we_i, + i4_wb_dat_i, + i4_wb_dat_o, + i4_wb_ack_o, + i4_wb_err_o, + i4_wb_cti_i, + i4_wb_bte_i, + + i5_wb_cyc_i, + i5_wb_stb_i, + i5_wb_adr_i, + i5_wb_sel_i, + i5_wb_we_i, + i5_wb_dat_i, + i5_wb_dat_o, + i5_wb_ack_o, + i5_wb_err_o, + i5_wb_cti_i, + i5_wb_bte_i, + + i6_wb_cyc_i, + i6_wb_stb_i, + i6_wb_adr_i, + i6_wb_sel_i, + i6_wb_we_i, + i6_wb_dat_i, + i6_wb_dat_o, + i6_wb_ack_o, + i6_wb_err_o, + i6_wb_cti_i, + i6_wb_bte_i, + + i7_wb_cyc_i, + i7_wb_stb_i, + i7_wb_adr_i, + i7_wb_sel_i, + i7_wb_we_i, + i7_wb_dat_i, + i7_wb_dat_o, + i7_wb_ack_o, + i7_wb_err_o, + i7_wb_cti_i, + i7_wb_bte_i, + + t0_wb_cyc_o, + t0_wb_stb_o, + t0_wb_adr_o, + t0_wb_sel_o, + t0_wb_we_o, + t0_wb_dat_o, + t0_wb_dat_i, + t0_wb_ack_i, + t0_wb_err_i, + t0_wb_cti_o, + t0_wb_bte_o, + + t1_wb_cyc_o, + t1_wb_stb_o, + t1_wb_adr_o, + t1_wb_sel_o, + t1_wb_we_o, + t1_wb_dat_o, + t1_wb_dat_i, + t1_wb_ack_i, + t1_wb_err_i, + t1_wb_cti_o, + t1_wb_bte_o, + + t2_wb_cyc_o, + t2_wb_stb_o, + t2_wb_adr_o, + t2_wb_sel_o, + t2_wb_we_o, + t2_wb_dat_o, + t2_wb_dat_i, + t2_wb_ack_i, + t2_wb_err_i, + t2_wb_cti_o, + t2_wb_bte_o, + + t3_wb_cyc_o, + t3_wb_stb_o, + t3_wb_adr_o, + t3_wb_sel_o, + t3_wb_we_o, + t3_wb_dat_o, + t3_wb_dat_i, + t3_wb_ack_i, + t3_wb_err_i, + t3_wb_cti_o, + t3_wb_bte_o, + + t4_wb_cyc_o, + t4_wb_stb_o, + t4_wb_adr_o, + t4_wb_sel_o, + t4_wb_we_o, + t4_wb_dat_o, + t4_wb_dat_i, + t4_wb_ack_i, + t4_wb_err_i, + t4_wb_cti_o, + t4_wb_bte_o, + + t5_wb_cyc_o, + t5_wb_stb_o, + t5_wb_adr_o, + t5_wb_sel_o, + t5_wb_we_o, + t5_wb_dat_o, + t5_wb_dat_i, + t5_wb_ack_i, + t5_wb_err_i, + t5_wb_cti_o, + t5_wb_bte_o, + + t6_wb_cyc_o, + t6_wb_stb_o, + t6_wb_adr_o, + t6_wb_sel_o, + t6_wb_we_o, + t6_wb_dat_o, + t6_wb_dat_i, + t6_wb_ack_i, + t6_wb_err_i, + t6_wb_cti_o, + t6_wb_bte_o, + + t7_wb_cyc_o, + t7_wb_stb_o, + t7_wb_adr_o, + t7_wb_sel_o, + t7_wb_we_o, + t7_wb_dat_o, + t7_wb_dat_i, + t7_wb_ack_i, + t7_wb_err_i, + t7_wb_cti_o, + t7_wb_bte_o, + + t8_wb_cyc_o, + t8_wb_stb_o, + t8_wb_adr_o, + t8_wb_sel_o, + t8_wb_we_o, + t8_wb_dat_o, + t8_wb_dat_i, + t8_wb_ack_i, + t8_wb_err_i, + t8_wb_cti_o, + t8_wb_bte_o + + +); + +// +// Parameters +// +parameter t0_addr_w = 4; +parameter t0_addr = 4'd8; +parameter t1_addr_w = 4; +parameter t1_addr = 4'd0; +parameter t28c_addr_w = 4; +parameter t28_addr = 4'd0; +parameter t28i_addr_w = 4; +parameter t2_addr = 4'd1; +parameter t3_addr = 4'd2; +parameter t4_addr = 4'd3; +parameter t5_addr = 4'd4; +parameter t6_addr = 4'd5; +parameter t7_addr = 4'd6; +parameter t8_addr = 4'd7; + +// +// I/O Ports +// +input wb_clk_i; +input wb_rst_i; +// +// WB slave i/f connecting initiator 0 +// +input i0_wb_cyc_i; +input i0_wb_stb_i; +input [`TC_AW-1:0] i0_wb_adr_i; +input [`TC_BSW-1:0] i0_wb_sel_i; +input i0_wb_we_i; +input [`TC_DW-1:0] i0_wb_dat_i; +output [`TC_DW-1:0] i0_wb_dat_o; +output i0_wb_ack_o; +output i0_wb_err_o; +input [2:0] i0_wb_cti_i; +input [1:0] i0_wb_bte_i; + +// +// WB slave i/f connecting initiator 1 +// +input i1_wb_cyc_i; +input i1_wb_stb_i; +input [`TC_AW-1:0] i1_wb_adr_i; +input [`TC_BSW-1:0] i1_wb_sel_i; +input i1_wb_we_i; +input [`TC_DW-1:0] i1_wb_dat_i; +output [`TC_DW-1:0] i1_wb_dat_o; +output i1_wb_ack_o; +output i1_wb_err_o; +input [2:0] i1_wb_cti_i; +input [1:0] i1_wb_bte_i; + +// +// WB slave i/f connecting initiator 2 +// +input i2_wb_cyc_i; +input i2_wb_stb_i; +input [`TC_AW-1:0] i2_wb_adr_i; +input [`TC_BSW-1:0] i2_wb_sel_i; +input i2_wb_we_i; +input [`TC_DW-1:0] i2_wb_dat_i; +output [`TC_DW-1:0] i2_wb_dat_o; +output i2_wb_ack_o; +output i2_wb_err_o; +input [2:0] i2_wb_cti_i; +input [1:0] i2_wb_bte_i; + +// +// WB slave i/f connecting initiator 3 +// +input i3_wb_cyc_i; +input i3_wb_stb_i; +input [`TC_AW-1:0] i3_wb_adr_i; +input [`TC_BSW-1:0] i3_wb_sel_i; +input i3_wb_we_i; +input [`TC_DW-1:0] i3_wb_dat_i; +output [`TC_DW-1:0] i3_wb_dat_o; +output i3_wb_ack_o; +output i3_wb_err_o; +input [2:0] i3_wb_cti_i; +input [1:0] i3_wb_bte_i; + +// +// WB slave i/f connecting initiator 4 +// +input i4_wb_cyc_i; +input i4_wb_stb_i; +input [`TC_AW-1:0] i4_wb_adr_i; +input [`TC_BSW-1:0] i4_wb_sel_i; +input i4_wb_we_i; +input [`TC_DW-1:0] i4_wb_dat_i; +output [`TC_DW-1:0] i4_wb_dat_o; +output i4_wb_ack_o; +output i4_wb_err_o; +input [2:0] i4_wb_cti_i; +input [1:0] i4_wb_bte_i; + +// +// WB slave i/f connecting initiator 5 +// +input i5_wb_cyc_i; +input i5_wb_stb_i; +input [`TC_AW-1:0] i5_wb_adr_i; +input [`TC_BSW-1:0] i5_wb_sel_i; +input i5_wb_we_i; +input [`TC_DW-1:0] i5_wb_dat_i; +output [`TC_DW-1:0] i5_wb_dat_o; +output i5_wb_ack_o; +output i5_wb_err_o; +input [2:0] i5_wb_cti_i; +input [1:0] i5_wb_bte_i; + +// +// WB slave i/f connecting initiator 6 +// +input i6_wb_cyc_i; +input i6_wb_stb_i; +input [`TC_AW-1:0] i6_wb_adr_i; +input [`TC_BSW-1:0] i6_wb_sel_i; +input i6_wb_we_i; +input [`TC_DW-1:0] i6_wb_dat_i; +output [`TC_DW-1:0] i6_wb_dat_o; +output i6_wb_ack_o; +output i6_wb_err_o; +input [2:0] i6_wb_cti_i; +input [1:0] i6_wb_bte_i; + +// +// WB slave i/f connecting initiator 7 +// +input i7_wb_cyc_i; +input i7_wb_stb_i; +input [`TC_AW-1:0] i7_wb_adr_i; +input [`TC_BSW-1:0] i7_wb_sel_i; +input i7_wb_we_i; +input [`TC_DW-1:0] i7_wb_dat_i; +output [`TC_DW-1:0] i7_wb_dat_o; +output i7_wb_ack_o; +output i7_wb_err_o; +input [2:0] i7_wb_cti_i; +input [1:0] i7_wb_bte_i; + +// +// WB master i/f connecting target 0 +// +output t0_wb_cyc_o; +output t0_wb_stb_o; +output [`TC_AW-1:0] t0_wb_adr_o; +output [`TC_BSW-1:0] t0_wb_sel_o; +output t0_wb_we_o; +output [`TC_DW-1:0] t0_wb_dat_o; +input [`TC_DW-1:0] t0_wb_dat_i; +input t0_wb_ack_i; +input t0_wb_err_i; +output [2:0] t0_wb_cti_o; +output [1:0] t0_wb_bte_o; + +// +// WB master i/f connecting target 1 +// +output t1_wb_cyc_o; +output t1_wb_stb_o; +output [`TC_AW-1:0] t1_wb_adr_o; +output [`TC_BSW-1:0] t1_wb_sel_o; +output t1_wb_we_o; +output [`TC_DW-1:0] t1_wb_dat_o; +input [`TC_DW-1:0] t1_wb_dat_i; +input t1_wb_ack_i; +input t1_wb_err_i; +output [2:0] t1_wb_cti_o; +output [1:0] t1_wb_bte_o; + +// +// WB master i/f connecting target 2 +// +output t2_wb_cyc_o; +output t2_wb_stb_o; +output [`TC_AW-1:0] t2_wb_adr_o; +output [`TC_BSW-1:0] t2_wb_sel_o; +output t2_wb_we_o; +output [`TC_DW-1:0] t2_wb_dat_o; +input [`TC_DW-1:0] t2_wb_dat_i; +input t2_wb_ack_i; +input t2_wb_err_i; +output [2:0] t2_wb_cti_o; +output [1:0] t2_wb_bte_o; + +// +// WB master i/f connecting target 3 +// +output t3_wb_cyc_o; +output t3_wb_stb_o; +output [`TC_AW-1:0] t3_wb_adr_o; +output [`TC_BSW-1:0] t3_wb_sel_o; +output t3_wb_we_o; +output [`TC_DW-1:0] t3_wb_dat_o; +input [`TC_DW-1:0] t3_wb_dat_i; +input t3_wb_ack_i; +input t3_wb_err_i; +output [2:0] t3_wb_cti_o; +output [1:0] t3_wb_bte_o; + +// +// WB master i/f connecting target 4 +// +output t4_wb_cyc_o; +output t4_wb_stb_o; +output [`TC_AW-1:0] t4_wb_adr_o; +output [`TC_BSW-1:0] t4_wb_sel_o; +output t4_wb_we_o; +output [`TC_DW-1:0] t4_wb_dat_o; +input [`TC_DW-1:0] t4_wb_dat_i; +input t4_wb_ack_i; +input t4_wb_err_i; +output [2:0] t4_wb_cti_o; +output [1:0] t4_wb_bte_o; + +// +// WB master i/f connecting target 5 +// +output t5_wb_cyc_o; +output t5_wb_stb_o; +output [`TC_AW-1:0] t5_wb_adr_o; +output [`TC_BSW-1:0] t5_wb_sel_o; +output t5_wb_we_o; +output [`TC_DW-1:0] t5_wb_dat_o; +input [`TC_DW-1:0] t5_wb_dat_i; +input t5_wb_ack_i; +input t5_wb_err_i; +output [2:0] t5_wb_cti_o; +output [1:0] t5_wb_bte_o; + +// +// WB master i/f connecting target 6 +// +output t6_wb_cyc_o; +output t6_wb_stb_o; +output [`TC_AW-1:0] t6_wb_adr_o; +output [`TC_BSW-1:0] t6_wb_sel_o; +output t6_wb_we_o; +output [`TC_DW-1:0] t6_wb_dat_o; +input [`TC_DW-1:0] t6_wb_dat_i; +input t6_wb_ack_i; +input t6_wb_err_i; +output [2:0] t6_wb_cti_o; +output [1:0] t6_wb_bte_o; + +// +// WB master i/f connecting target 7 +// +output t7_wb_cyc_o; +output t7_wb_stb_o; +output [`TC_AW-1:0] t7_wb_adr_o; +output [`TC_BSW-1:0] t7_wb_sel_o; +output t7_wb_we_o; +output [`TC_DW-1:0] t7_wb_dat_o; +input [`TC_DW-1:0] t7_wb_dat_i; +input t7_wb_ack_i; +input t7_wb_err_i; +output [2:0] t7_wb_cti_o; +output [1:0] t7_wb_bte_o; + +// +// WB master i/f connecting target 8 +// +output t8_wb_cyc_o; +output t8_wb_stb_o; +output [`TC_AW-1:0] t8_wb_adr_o; +output [`TC_BSW-1:0] t8_wb_sel_o; +output t8_wb_we_o; +output [`TC_DW-1:0] t8_wb_dat_o; +input [`TC_DW-1:0] t8_wb_dat_i; +input t8_wb_ack_i; +input t8_wb_err_i; +output [2:0] t8_wb_cti_o; +output [1:0] t8_wb_bte_o; + + +// +// Internal wires & registers +// + +// +// Outputs for initiators from both mi_to_st blocks +// +wire [`TC_DW-1:0] xi0_wb_dat_o; +wire xi0_wb_ack_o; +wire xi0_wb_err_o; +wire [`TC_DW-1:0] xi1_wb_dat_o; +wire xi1_wb_ack_o; +wire xi1_wb_err_o; +wire [`TC_DW-1:0] xi2_wb_dat_o; +wire xi2_wb_ack_o; +wire xi2_wb_err_o; +wire [`TC_DW-1:0] xi3_wb_dat_o; +wire xi3_wb_ack_o; +wire xi3_wb_err_o; +wire [`TC_DW-1:0] xi4_wb_dat_o; +wire xi4_wb_ack_o; +wire xi4_wb_err_o; +wire [`TC_DW-1:0] xi5_wb_dat_o; +wire xi5_wb_ack_o; +wire xi5_wb_err_o; +wire [`TC_DW-1:0] xi6_wb_dat_o; +wire xi6_wb_ack_o; +wire xi6_wb_err_o; +wire [`TC_DW-1:0] xi7_wb_dat_o; +wire xi7_wb_ack_o; +wire xi7_wb_err_o; +wire [`TC_DW-1:0] yi0_wb_dat_o; +wire yi0_wb_ack_o; +wire yi0_wb_err_o; +wire [`TC_DW-1:0] yi1_wb_dat_o; +wire yi1_wb_ack_o; +wire yi1_wb_err_o; +wire [`TC_DW-1:0] yi2_wb_dat_o; +wire yi2_wb_ack_o; +wire yi2_wb_err_o; +wire [`TC_DW-1:0] yi3_wb_dat_o; +wire yi3_wb_ack_o; +wire yi3_wb_err_o; +wire [`TC_DW-1:0] yi4_wb_dat_o; +wire yi4_wb_ack_o; +wire yi4_wb_err_o; +wire [`TC_DW-1:0] yi5_wb_dat_o; +wire yi5_wb_ack_o; +wire yi5_wb_err_o; +wire [`TC_DW-1:0] yi6_wb_dat_o; +wire yi6_wb_ack_o; +wire yi6_wb_err_o; +wire [`TC_DW-1:0] yi7_wb_dat_o; +wire yi7_wb_ack_o; +wire yi7_wb_err_o; + +// +// Intermediate signals connecting peripheral channel's +// mi_to_st and si_to_mt blocks. +// +wire z_wb_cyc_i; +wire z_wb_stb_i; +wire [`TC_AW-1:0] z_wb_adr_i; +wire [`TC_BSW-1:0] z_wb_sel_i; +wire z_wb_we_i; +wire [`TC_DW-1:0] z_wb_dat_i; +wire [`TC_DW-1:0] z_wb_dat_t; +wire z_wb_ack_t; +wire z_wb_err_t; +wire [2:0] z_wb_cti_i; +wire [1:0] z_wb_bte_i; + +// +// Outputs for initiators are ORed from both mi_to_st blocks +// +assign i0_wb_dat_o = xi0_wb_dat_o | yi0_wb_dat_o; +assign i0_wb_ack_o = xi0_wb_ack_o | yi0_wb_ack_o; +assign i0_wb_err_o = xi0_wb_err_o | yi0_wb_err_o; +assign i1_wb_dat_o = xi1_wb_dat_o | yi1_wb_dat_o; +assign i1_wb_ack_o = xi1_wb_ack_o | yi1_wb_ack_o; +assign i1_wb_err_o = xi1_wb_err_o | yi1_wb_err_o; +assign i2_wb_dat_o = xi2_wb_dat_o | yi2_wb_dat_o; +assign i2_wb_ack_o = xi2_wb_ack_o | yi2_wb_ack_o; +assign i2_wb_err_o = xi2_wb_err_o | yi2_wb_err_o; +assign i3_wb_dat_o = xi3_wb_dat_o | yi3_wb_dat_o; +assign i3_wb_ack_o = xi3_wb_ack_o | yi3_wb_ack_o; +assign i3_wb_err_o = xi3_wb_err_o | yi3_wb_err_o; +assign i4_wb_dat_o = xi4_wb_dat_o | yi4_wb_dat_o; +assign i4_wb_ack_o = xi4_wb_ack_o | yi4_wb_ack_o; +assign i4_wb_err_o = xi4_wb_err_o | yi4_wb_err_o; +assign i5_wb_dat_o = xi5_wb_dat_o | yi5_wb_dat_o; +assign i5_wb_ack_o = xi5_wb_ack_o | yi5_wb_ack_o; +assign i5_wb_err_o = xi5_wb_err_o | yi5_wb_err_o; +assign i6_wb_dat_o = xi6_wb_dat_o | yi6_wb_dat_o; +assign i6_wb_ack_o = xi6_wb_ack_o | yi6_wb_ack_o; +assign i6_wb_err_o = xi6_wb_err_o | yi6_wb_err_o; +assign i7_wb_dat_o = xi7_wb_dat_o | yi7_wb_dat_o; +assign i7_wb_ack_o = xi7_wb_ack_o | yi7_wb_ack_o; +assign i7_wb_err_o = xi7_wb_err_o | yi7_wb_err_o; + +// +// From initiators to target 0 +// +tc_mi_to_st #(t0_addr_w, t0_addr, + 0, t0_addr_w, t0_addr) t0_ch( + .wb_clk_i(wb_clk_i), + .wb_rst_i(wb_rst_i), + .i0_wb_cyc_i(i0_wb_cyc_i), + .i0_wb_stb_i(i0_wb_stb_i), + .i0_wb_adr_i(i0_wb_adr_i), + .i0_wb_sel_i(i0_wb_sel_i), + .i0_wb_we_i(i0_wb_we_i), + .i0_wb_dat_i(i0_wb_dat_i), + .i0_wb_dat_o(xi0_wb_dat_o), + .i0_wb_ack_o(xi0_wb_ack_o), + .i0_wb_err_o(xi0_wb_err_o), + .i0_wb_cti_i(i0_wb_cti_i), + .i0_wb_bte_i(i0_wb_bte_i), + + .i1_wb_cyc_i(i1_wb_cyc_i), + .i1_wb_stb_i(i1_wb_stb_i), + .i1_wb_adr_i(i1_wb_adr_i), + .i1_wb_sel_i(i1_wb_sel_i), + .i1_wb_we_i(i1_wb_we_i), + .i1_wb_dat_i(i1_wb_dat_i), + .i1_wb_dat_o(xi1_wb_dat_o), + .i1_wb_ack_o(xi1_wb_ack_o), + .i1_wb_err_o(xi1_wb_err_o), + .i1_wb_cti_i(i1_wb_cti_i), + .i1_wb_bte_i(i1_wb_bte_i), + + .i2_wb_cyc_i(i2_wb_cyc_i), + .i2_wb_stb_i(i2_wb_stb_i), + .i2_wb_adr_i(i2_wb_adr_i), + .i2_wb_sel_i(i2_wb_sel_i), + .i2_wb_we_i(i2_wb_we_i), + .i2_wb_dat_i(i2_wb_dat_i), + .i2_wb_dat_o(xi2_wb_dat_o), + .i2_wb_ack_o(xi2_wb_ack_o), + .i2_wb_err_o(xi2_wb_err_o), + .i2_wb_cti_i(i2_wb_cti_i), + .i2_wb_bte_i(i2_wb_bte_i), + + .i3_wb_cyc_i(i3_wb_cyc_i), + .i3_wb_stb_i(i3_wb_stb_i), + .i3_wb_adr_i(i3_wb_adr_i), + .i3_wb_sel_i(i3_wb_sel_i), + .i3_wb_we_i(i3_wb_we_i), + .i3_wb_dat_i(i3_wb_dat_i), + .i3_wb_dat_o(xi3_wb_dat_o), + .i3_wb_ack_o(xi3_wb_ack_o), + .i3_wb_err_o(xi3_wb_err_o), + .i3_wb_cti_i(i3_wb_cti_i), + .i3_wb_bte_i(i3_wb_bte_i), + + .i4_wb_cyc_i(i4_wb_cyc_i), + .i4_wb_stb_i(i4_wb_stb_i), + .i4_wb_adr_i(i4_wb_adr_i), + .i4_wb_sel_i(i4_wb_sel_i), + .i4_wb_we_i(i4_wb_we_i), + .i4_wb_dat_i(i4_wb_dat_i), + .i4_wb_dat_o(xi4_wb_dat_o), + .i4_wb_ack_o(xi4_wb_ack_o), + .i4_wb_err_o(xi4_wb_err_o), + .i4_wb_cti_i(i4_wb_cti_i), + .i4_wb_bte_i(i4_wb_bte_i), + + .i5_wb_cyc_i(i5_wb_cyc_i), + .i5_wb_stb_i(i5_wb_stb_i), + .i5_wb_adr_i(i5_wb_adr_i), + .i5_wb_sel_i(i5_wb_sel_i), + .i5_wb_we_i(i5_wb_we_i), + .i5_wb_dat_i(i5_wb_dat_i), + .i5_wb_dat_o(xi5_wb_dat_o), + .i5_wb_ack_o(xi5_wb_ack_o), + .i5_wb_err_o(xi5_wb_err_o), + .i5_wb_cti_i(i5_wb_cti_i), + .i5_wb_bte_i(i5_wb_bte_i), + + .i6_wb_cyc_i(i6_wb_cyc_i), + .i6_wb_stb_i(i6_wb_stb_i), + .i6_wb_adr_i(i6_wb_adr_i), + .i6_wb_sel_i(i6_wb_sel_i), + .i6_wb_we_i(i6_wb_we_i), + .i6_wb_dat_i(i6_wb_dat_i), + .i6_wb_dat_o(xi6_wb_dat_o), + .i6_wb_ack_o(xi6_wb_ack_o), + .i6_wb_err_o(xi6_wb_err_o), + .i6_wb_cti_i(i6_wb_cti_i), + .i6_wb_bte_i(i6_wb_bte_i), + + .i7_wb_cyc_i(i7_wb_cyc_i), + .i7_wb_stb_i(i7_wb_stb_i), + .i7_wb_adr_i(i7_wb_adr_i), + .i7_wb_sel_i(i7_wb_sel_i), + .i7_wb_we_i(i7_wb_we_i), + .i7_wb_dat_i(i7_wb_dat_i), + .i7_wb_dat_o(xi7_wb_dat_o), + .i7_wb_ack_o(xi7_wb_ack_o), + .i7_wb_err_o(xi7_wb_err_o), + .i7_wb_cti_i(i7_wb_cti_i), + .i7_wb_bte_i(i7_wb_bte_i), + + + .t0_wb_cyc_o(t0_wb_cyc_o), + .t0_wb_stb_o(t0_wb_stb_o), + .t0_wb_adr_o(t0_wb_adr_o), + .t0_wb_sel_o(t0_wb_sel_o), + .t0_wb_we_o(t0_wb_we_o), + .t0_wb_dat_o(t0_wb_dat_o), + .t0_wb_dat_i(t0_wb_dat_i), + .t0_wb_ack_i(t0_wb_ack_i), + .t0_wb_err_i(t0_wb_err_i), + .t0_wb_cti_o(t0_wb_cti_o), + .t0_wb_bte_o(t0_wb_bte_o) + +); + +// +// From initiators to targets 1-8 (upper part) +// +tc_mi_to_st #(t1_addr_w, t1_addr, + 1, t28c_addr_w, t28_addr) t18_ch_upper( + .wb_clk_i(wb_clk_i), + .wb_rst_i(wb_rst_i), + .i0_wb_cyc_i(i0_wb_cyc_i), + .i0_wb_stb_i(i0_wb_stb_i), + .i0_wb_adr_i(i0_wb_adr_i), + .i0_wb_sel_i(i0_wb_sel_i), + .i0_wb_we_i(i0_wb_we_i), + .i0_wb_dat_i(i0_wb_dat_i), + .i0_wb_dat_o(yi0_wb_dat_o), + .i0_wb_ack_o(yi0_wb_ack_o), + .i0_wb_err_o(yi0_wb_err_o), + .i0_wb_cti_i(i0_wb_cti_i), + .i0_wb_bte_i(i0_wb_bte_i), + + .i1_wb_cyc_i(i1_wb_cyc_i), + .i1_wb_stb_i(i1_wb_stb_i), + .i1_wb_adr_i(i1_wb_adr_i), + .i1_wb_sel_i(i1_wb_sel_i), + .i1_wb_we_i(i1_wb_we_i), + .i1_wb_dat_i(i1_wb_dat_i), + .i1_wb_dat_o(yi1_wb_dat_o), + .i1_wb_ack_o(yi1_wb_ack_o), + .i1_wb_err_o(yi1_wb_err_o), + .i1_wb_cti_i(i1_wb_cti_i), + .i1_wb_bte_i(i1_wb_bte_i), + + .i2_wb_cyc_i(i2_wb_cyc_i), + .i2_wb_stb_i(i2_wb_stb_i), + .i2_wb_adr_i(i2_wb_adr_i), + .i2_wb_sel_i(i2_wb_sel_i), + .i2_wb_we_i(i2_wb_we_i), + .i2_wb_dat_i(i2_wb_dat_i), + .i2_wb_dat_o(yi2_wb_dat_o), + .i2_wb_ack_o(yi2_wb_ack_o), + .i2_wb_err_o(yi2_wb_err_o), + .i2_wb_cti_i(i2_wb_cti_i), + .i2_wb_bte_i(i2_wb_bte_i), + + .i3_wb_cyc_i(i3_wb_cyc_i), + .i3_wb_stb_i(i3_wb_stb_i), + .i3_wb_adr_i(i3_wb_adr_i), + .i3_wb_sel_i(i3_wb_sel_i), + .i3_wb_we_i(i3_wb_we_i), + .i3_wb_dat_i(i3_wb_dat_i), + .i3_wb_dat_o(yi3_wb_dat_o), + .i3_wb_ack_o(yi3_wb_ack_o), + .i3_wb_err_o(yi3_wb_err_o), + .i3_wb_cti_i(i3_wb_cti_i), + .i3_wb_bte_i(i3_wb_bte_i), + + .i4_wb_cyc_i(i4_wb_cyc_i), + .i4_wb_stb_i(i4_wb_stb_i), + .i4_wb_adr_i(i4_wb_adr_i), + .i4_wb_sel_i(i4_wb_sel_i), + .i4_wb_we_i(i4_wb_we_i), + .i4_wb_dat_i(i4_wb_dat_i), + .i4_wb_dat_o(yi4_wb_dat_o), + .i4_wb_ack_o(yi4_wb_ack_o), + .i4_wb_err_o(yi4_wb_err_o), + .i4_wb_cti_i(i4_wb_cti_i), + .i4_wb_bte_i(i4_wb_bte_i), + + .i5_wb_cyc_i(i5_wb_cyc_i), + .i5_wb_stb_i(i5_wb_stb_i), + .i5_wb_adr_i(i5_wb_adr_i), + .i5_wb_sel_i(i5_wb_sel_i), + .i5_wb_we_i(i5_wb_we_i), + .i5_wb_dat_i(i5_wb_dat_i), + .i5_wb_dat_o(yi5_wb_dat_o), + .i5_wb_ack_o(yi5_wb_ack_o), + .i5_wb_err_o(yi5_wb_err_o), + .i5_wb_cti_i(i5_wb_cti_i), + .i5_wb_bte_i(i5_wb_bte_i), + + .i6_wb_cyc_i(i6_wb_cyc_i), + .i6_wb_stb_i(i6_wb_stb_i), + .i6_wb_adr_i(i6_wb_adr_i), + .i6_wb_sel_i(i6_wb_sel_i), + .i6_wb_we_i(i6_wb_we_i), + .i6_wb_dat_i(i6_wb_dat_i), + .i6_wb_dat_o(yi6_wb_dat_o), + .i6_wb_ack_o(yi6_wb_ack_o), + .i6_wb_err_o(yi6_wb_err_o), + .i6_wb_cti_i(i6_wb_cti_i), + .i6_wb_bte_i(i6_wb_bte_i), + + .i7_wb_cyc_i(i7_wb_cyc_i), + .i7_wb_stb_i(i7_wb_stb_i), + .i7_wb_adr_i(i7_wb_adr_i), + .i7_wb_sel_i(i7_wb_sel_i), + .i7_wb_we_i(i7_wb_we_i), + .i7_wb_dat_i(i7_wb_dat_i), + .i7_wb_dat_o(yi7_wb_dat_o), + .i7_wb_ack_o(yi7_wb_ack_o), + .i7_wb_err_o(yi7_wb_err_o), + .i7_wb_cti_i(i7_wb_cti_i), + .i7_wb_bte_i(i7_wb_bte_i), + + + .t0_wb_cyc_o(z_wb_cyc_i), + .t0_wb_stb_o(z_wb_stb_i), + .t0_wb_adr_o(z_wb_adr_i), + .t0_wb_sel_o(z_wb_sel_i), + .t0_wb_we_o(z_wb_we_i), + .t0_wb_dat_o(z_wb_dat_i), + .t0_wb_dat_i(z_wb_dat_t), + .t0_wb_ack_i(z_wb_ack_t), + .t0_wb_err_i(z_wb_err_t), + .t0_wb_cti_o(z_wb_cti_i), + .t0_wb_bte_o(z_wb_bte_i) + +); + +// +// From initiators to targets 1-8 (lower part) +// +tc_si_to_mt #(t1_addr_w, t1_addr, t28i_addr_w, t2_addr, t3_addr, + t4_addr, t5_addr, t6_addr, t7_addr, t8_addr) t18_ch_lower( + + + .i0_wb_cyc_i(z_wb_cyc_i), + .i0_wb_stb_i(z_wb_stb_i), + .i0_wb_adr_i(z_wb_adr_i), + .i0_wb_sel_i(z_wb_sel_i), + .i0_wb_we_i(z_wb_we_i), + .i0_wb_dat_i(z_wb_dat_i), + .i0_wb_dat_o(z_wb_dat_t), + .i0_wb_ack_o(z_wb_ack_t), + .i0_wb_err_o(z_wb_err_t), + .i0_wb_cti_i(z_wb_cti_i), + .i0_wb_bte_i(z_wb_bte_i), + + .t0_wb_cyc_o(t1_wb_cyc_o), + .t0_wb_stb_o(t1_wb_stb_o), + .t0_wb_adr_o(t1_wb_adr_o), + .t0_wb_sel_o(t1_wb_sel_o), + .t0_wb_we_o(t1_wb_we_o), + .t0_wb_dat_o(t1_wb_dat_o), + .t0_wb_dat_i(t1_wb_dat_i), + .t0_wb_ack_i(t1_wb_ack_i), + .t0_wb_err_i(t1_wb_err_i), + .t0_wb_cti_o(t1_wb_cti_o), + .t0_wb_bte_o(t1_wb_bte_o), + + .t1_wb_cyc_o(t2_wb_cyc_o), + .t1_wb_stb_o(t2_wb_stb_o), + .t1_wb_adr_o(t2_wb_adr_o), + .t1_wb_sel_o(t2_wb_sel_o), + .t1_wb_we_o(t2_wb_we_o), + .t1_wb_dat_o(t2_wb_dat_o), + .t1_wb_dat_i(t2_wb_dat_i), + .t1_wb_ack_i(t2_wb_ack_i), + .t1_wb_err_i(t2_wb_err_i), + .t1_wb_cti_o(t2_wb_cti_o), + .t1_wb_bte_o(t2_wb_bte_o), + + .t2_wb_cyc_o(t3_wb_cyc_o), + .t2_wb_stb_o(t3_wb_stb_o), + .t2_wb_adr_o(t3_wb_adr_o), + .t2_wb_sel_o(t3_wb_sel_o), + .t2_wb_we_o(t3_wb_we_o), + .t2_wb_dat_o(t3_wb_dat_o), + .t2_wb_dat_i(t3_wb_dat_i), + .t2_wb_ack_i(t3_wb_ack_i), + .t2_wb_err_i(t3_wb_err_i), + .t2_wb_cti_o(t3_wb_cti_o), + .t2_wb_bte_o(t3_wb_bte_o), + + .t3_wb_cyc_o(t4_wb_cyc_o), + .t3_wb_stb_o(t4_wb_stb_o), + .t3_wb_adr_o(t4_wb_adr_o), + .t3_wb_sel_o(t4_wb_sel_o), + .t3_wb_we_o(t4_wb_we_o), + .t3_wb_dat_o(t4_wb_dat_o), + .t3_wb_dat_i(t4_wb_dat_i), + .t3_wb_ack_i(t4_wb_ack_i), + .t3_wb_err_i(t4_wb_err_i), + .t3_wb_cti_o(t4_wb_cti_o), + .t3_wb_bte_o(t4_wb_bte_o), + + .t4_wb_cyc_o(t5_wb_cyc_o), + .t4_wb_stb_o(t5_wb_stb_o), + .t4_wb_adr_o(t5_wb_adr_o), + .t4_wb_sel_o(t5_wb_sel_o), + .t4_wb_we_o(t5_wb_we_o), + .t4_wb_dat_o(t5_wb_dat_o), + .t4_wb_dat_i(t5_wb_dat_i), + .t4_wb_ack_i(t5_wb_ack_i), + .t4_wb_err_i(t5_wb_err_i), + .t4_wb_cti_o(t5_wb_cti_o), + .t4_wb_bte_o(t5_wb_bte_o), + + .t5_wb_cyc_o(t6_wb_cyc_o), + .t5_wb_stb_o(t6_wb_stb_o), + .t5_wb_adr_o(t6_wb_adr_o), + .t5_wb_sel_o(t6_wb_sel_o), + .t5_wb_we_o(t6_wb_we_o), + .t5_wb_dat_o(t6_wb_dat_o), + .t5_wb_dat_i(t6_wb_dat_i), + .t5_wb_ack_i(t6_wb_ack_i), + .t5_wb_err_i(t6_wb_err_i), + .t5_wb_cti_o(t6_wb_cti_o), + .t5_wb_bte_o(t6_wb_bte_o), + + .t6_wb_cyc_o(t7_wb_cyc_o), + .t6_wb_stb_o(t7_wb_stb_o), + .t6_wb_adr_o(t7_wb_adr_o), + .t6_wb_sel_o(t7_wb_sel_o), + .t6_wb_we_o(t7_wb_we_o), + .t6_wb_dat_o(t7_wb_dat_o), + .t6_wb_dat_i(t7_wb_dat_i), + .t6_wb_ack_i(t7_wb_ack_i), + .t6_wb_err_i(t7_wb_err_i), + .t6_wb_cti_o(t7_wb_cti_o), + .t6_wb_bte_o(t7_wb_bte_o), + + .t7_wb_cyc_o(t8_wb_cyc_o), + .t7_wb_stb_o(t8_wb_stb_o), + .t7_wb_adr_o(t8_wb_adr_o), + .t7_wb_sel_o(t8_wb_sel_o), + .t7_wb_we_o(t8_wb_we_o), + .t7_wb_dat_o(t8_wb_dat_o), + .t7_wb_dat_i(t8_wb_dat_i), + .t7_wb_ack_i(t8_wb_ack_i), + .t7_wb_err_i(t8_wb_err_i), + .t7_wb_cti_o(t8_wb_cti_o), + .t7_wb_bte_o(t8_wb_bte_o), + + +); + +endmodule + +// +// Multiple initiator to single target +// +module tc_mi_to_st ( + wb_clk_i, + wb_rst_i, + i0_wb_cyc_i, + i0_wb_stb_i, + i0_wb_adr_i, + i0_wb_sel_i, + i0_wb_we_i, + i0_wb_dat_i, + i0_wb_dat_o, + i0_wb_ack_o, + i0_wb_err_o, + i0_wb_cti_i, + i0_wb_bte_i, + + i1_wb_cyc_i, + i1_wb_stb_i, + i1_wb_adr_i, + i1_wb_sel_i, + i1_wb_we_i, + i1_wb_dat_i, + i1_wb_dat_o, + i1_wb_ack_o, + i1_wb_err_o, + i1_wb_cti_i, + i1_wb_bte_i, + + i2_wb_cyc_i, + i2_wb_stb_i, + i2_wb_adr_i, + i2_wb_sel_i, + i2_wb_we_i, + i2_wb_dat_i, + i2_wb_dat_o, + i2_wb_ack_o, + i2_wb_err_o, + i2_wb_cti_i, + i2_wb_bte_i, + + i3_wb_cyc_i, + i3_wb_stb_i, + i3_wb_adr_i, + i3_wb_sel_i, + i3_wb_we_i, + i3_wb_dat_i, + i3_wb_dat_o, + i3_wb_ack_o, + i3_wb_err_o, + i3_wb_cti_i, + i3_wb_bte_i, + + i4_wb_cyc_i, + i4_wb_stb_i, + i4_wb_adr_i, + i4_wb_sel_i, + i4_wb_we_i, + i4_wb_dat_i, + i4_wb_dat_o, + i4_wb_ack_o, + i4_wb_err_o, + i4_wb_cti_i, + i4_wb_bte_i, + + i5_wb_cyc_i, + i5_wb_stb_i, + i5_wb_adr_i, + i5_wb_sel_i, + i5_wb_we_i, + i5_wb_dat_i, + i5_wb_dat_o, + i5_wb_ack_o, + i5_wb_err_o, + i5_wb_cti_i, + i5_wb_bte_i, + + i6_wb_cyc_i, + i6_wb_stb_i, + i6_wb_adr_i, + i6_wb_sel_i, + i6_wb_we_i, + i6_wb_dat_i, + i6_wb_dat_o, + i6_wb_ack_o, + i6_wb_err_o, + i6_wb_cti_i, + i6_wb_bte_i, + + i7_wb_cyc_i, + i7_wb_stb_i, + i7_wb_adr_i, + i7_wb_sel_i, + i7_wb_we_i, + i7_wb_dat_i, + i7_wb_dat_o, + i7_wb_ack_o, + i7_wb_err_o, + i7_wb_cti_i, + i7_wb_bte_i, + + + t0_wb_cyc_o, + t0_wb_stb_o, + t0_wb_adr_o, + t0_wb_sel_o, + t0_wb_we_o, + t0_wb_dat_o, + t0_wb_dat_i, + t0_wb_ack_i, + t0_wb_err_i, + t0_wb_cti_o, + t0_wb_bte_o + +); + +// +// Parameters +// +parameter t0_addr_w = 2; +parameter t0_addr = 2'b00; +parameter multitarg = 1'b0; +parameter t17_addr_w = 2; +parameter t17_addr = 2'b00; + +// +// I/O Ports +// +input wb_clk_i; +input wb_rst_i; +// +// WB slave i/f connecting initiator 0 +// +input i0_wb_cyc_i; +input i0_wb_stb_i; +input [`TC_AW-1:0] i0_wb_adr_i; +input [`TC_BSW-1:0] i0_wb_sel_i; +input i0_wb_we_i; +input [`TC_DW-1:0] i0_wb_dat_i; +output [`TC_DW-1:0] i0_wb_dat_o; +output i0_wb_ack_o; +output i0_wb_err_o; +input [2:0] i0_wb_cti_i; +input [1:0] i0_wb_bte_i; + +// +// WB slave i/f connecting initiator 1 +// +input i1_wb_cyc_i; +input i1_wb_stb_i; +input [`TC_AW-1:0] i1_wb_adr_i; +input [`TC_BSW-1:0] i1_wb_sel_i; +input i1_wb_we_i; +input [`TC_DW-1:0] i1_wb_dat_i; +output [`TC_DW-1:0] i1_wb_dat_o; +output i1_wb_ack_o; +output i1_wb_err_o; +input [2:0] i1_wb_cti_i; +input [1:0] i1_wb_bte_i; + +// +// WB slave i/f connecting initiator 2 +// +input i2_wb_cyc_i; +input i2_wb_stb_i; +input [`TC_AW-1:0] i2_wb_adr_i; +input [`TC_BSW-1:0] i2_wb_sel_i; +input i2_wb_we_i; +input [`TC_DW-1:0] i2_wb_dat_i; +output [`TC_DW-1:0] i2_wb_dat_o; +output i2_wb_ack_o; +output i2_wb_err_o; +input [2:0] i2_wb_cti_i; +input [1:0] i2_wb_bte_i; + +// +// WB slave i/f connecting initiator 3 +// +input i3_wb_cyc_i; +input i3_wb_stb_i; +input [`TC_AW-1:0] i3_wb_adr_i; +input [`TC_BSW-1:0] i3_wb_sel_i; +input i3_wb_we_i; +input [`TC_DW-1:0] i3_wb_dat_i; +output [`TC_DW-1:0] i3_wb_dat_o; +output i3_wb_ack_o; +output i3_wb_err_o; +input [2:0] i3_wb_cti_i; +input [1:0] i3_wb_bte_i; + +// +// WB slave i/f connecting initiator 4 +// +input i4_wb_cyc_i; +input i4_wb_stb_i; +input [`TC_AW-1:0] i4_wb_adr_i; +input [`TC_BSW-1:0] i4_wb_sel_i; +input i4_wb_we_i; +input [`TC_DW-1:0] i4_wb_dat_i; +output [`TC_DW-1:0] i4_wb_dat_o; +output i4_wb_ack_o; +output i4_wb_err_o; +input [2:0] i4_wb_cti_i; +input [1:0] i4_wb_bte_i; + +// +// WB slave i/f connecting initiator 5 +// +input i5_wb_cyc_i; +input i5_wb_stb_i; +input [`TC_AW-1:0] i5_wb_adr_i; +input [`TC_BSW-1:0] i5_wb_sel_i; +input i5_wb_we_i; +input [`TC_DW-1:0] i5_wb_dat_i; +output [`TC_DW-1:0] i5_wb_dat_o; +output i5_wb_ack_o; +output i5_wb_err_o; +input [2:0] i5_wb_cti_i; +input [1:0] i5_wb_bte_i; + +// +// WB slave i/f connecting initiator 6 +// +input i6_wb_cyc_i; +input i6_wb_stb_i; +input [`TC_AW-1:0] i6_wb_adr_i; +input [`TC_BSW-1:0] i6_wb_sel_i; +input i6_wb_we_i; +input [`TC_DW-1:0] i6_wb_dat_i; +output [`TC_DW-1:0] i6_wb_dat_o; +output i6_wb_ack_o; +output i6_wb_err_o; +input [2:0] i6_wb_cti_i; +input [1:0] i6_wb_bte_i; + +// +// WB slave i/f connecting initiator 7 +// +input i7_wb_cyc_i; +input i7_wb_stb_i; +input [`TC_AW-1:0] i7_wb_adr_i; +input [`TC_BSW-1:0] i7_wb_sel_i; +input i7_wb_we_i; +input [`TC_DW-1:0] i7_wb_dat_i; +output [`TC_DW-1:0] i7_wb_dat_o; +output i7_wb_ack_o; +output i7_wb_err_o; +input [2:0] i7_wb_cti_i; +input [1:0] i7_wb_bte_i; + + +// +// WB master i/f connecting target +// +output t0_wb_cyc_o; +output t0_wb_stb_o; +output [`TC_AW-1:0] t0_wb_adr_o; +output [`TC_BSW-1:0] t0_wb_sel_o; +output t0_wb_we_o; +output [`TC_DW-1:0] t0_wb_dat_o; +input [`TC_DW-1:0] t0_wb_dat_i; +input t0_wb_ack_i; +input t0_wb_err_i; +output [2:0] t0_wb_cti_o; +output [1:0] t0_wb_bte_o; + +// +// Internal wires & registers +// +wire [`TC_IIN_W-1:0] i0_in, i1_in, + i2_in, i3_in, + i4_in, i5_in, + i6_in, i7_in; +wire [`TC_TIN_W-1:0] i0_out, i1_out, + i2_out, i3_out, + i4_out, i5_out, + i6_out, i7_out; +wire [`TC_IIN_W-1:0] t0_out; +wire [`TC_TIN_W-1:0] t0_in; +wire [7:0] req_i; +wire [2:0] req_won; +reg req_cont; +reg [2:0] req_r; +// +// Group WB initiator 0 i/f inputs and outputs +// +assign i0_in = {i0_wb_cyc_i, i0_wb_stb_i, i0_wb_adr_i, + i0_wb_sel_i, i0_wb_we_i, i0_wb_dat_i, i0_wb_cti_i, i0_wb_bte_i}; +assign {i0_wb_dat_o, i0_wb_ack_o, i0_wb_err_o} = i0_out; + +// +// Group WB initiator 1 i/f inputs and outputs +// +assign i1_in = {i1_wb_cyc_i, i1_wb_stb_i, i1_wb_adr_i, + i1_wb_sel_i, i1_wb_we_i, i1_wb_dat_i, i1_wb_cti_i, i1_wb_bte_i}; +assign {i1_wb_dat_o, i1_wb_ack_o, i1_wb_err_o} = i1_out; + +// +// Group WB initiator 2 i/f inputs and outputs +// +assign i2_in = {i2_wb_cyc_i, i2_wb_stb_i, i2_wb_adr_i, + i2_wb_sel_i, i2_wb_we_i, i2_wb_dat_i, i2_wb_cti_i, i2_wb_bte_i}; +assign {i2_wb_dat_o, i2_wb_ack_o, i2_wb_err_o} = i2_out; + +// +// Group WB initiator 3 i/f inputs and outputs +// +assign i3_in = {i3_wb_cyc_i, i3_wb_stb_i, i3_wb_adr_i, + i3_wb_sel_i, i3_wb_we_i, i3_wb_dat_i, i3_wb_cti_i, i3_wb_bte_i}; +assign {i3_wb_dat_o, i3_wb_ack_o, i3_wb_err_o} = i3_out; + +// +// Group WB initiator 4 i/f inputs and outputs +// +assign i4_in = {i4_wb_cyc_i, i4_wb_stb_i, i4_wb_adr_i, + i4_wb_sel_i, i4_wb_we_i, i4_wb_dat_i, i4_wb_cti_i, i4_wb_bte_i}; +assign {i4_wb_dat_o, i4_wb_ack_o, i4_wb_err_o} = i4_out; + +// +// Group WB initiator 5 i/f inputs and outputs +// +assign i5_in = {i5_wb_cyc_i, i5_wb_stb_i, i5_wb_adr_i, + i5_wb_sel_i, i5_wb_we_i, i5_wb_dat_i, i5_wb_cti_i, i5_wb_bte_i}; +assign {i5_wb_dat_o, i5_wb_ack_o, i5_wb_err_o} = i5_out; + +// +// Group WB initiator 6 i/f inputs and outputs +// +assign i6_in = {i6_wb_cyc_i, i6_wb_stb_i, i6_wb_adr_i, + i6_wb_sel_i, i6_wb_we_i, i6_wb_dat_i, i6_wb_cti_i, i6_wb_bte_i}; +assign {i6_wb_dat_o, i6_wb_ack_o, i6_wb_err_o} = i6_out; + +// +// Group WB initiator 7 i/f inputs and outputs +// +assign i7_in = {i7_wb_cyc_i, i7_wb_stb_i, i7_wb_adr_i, + i7_wb_sel_i, i7_wb_we_i, i7_wb_dat_i, i7_wb_cti_i, i7_wb_bte_i}; +assign {i7_wb_dat_o, i7_wb_ack_o, i7_wb_err_o} = i7_out; + + +// +// Group WB target 0 i/f inputs and outputs +// +assign {t0_wb_cyc_o, t0_wb_stb_o, t0_wb_adr_o, + t0_wb_sel_o, t0_wb_we_o, t0_wb_dat_o, t0_wb_cti_o, t0_wb_bte_o} = t0_out; +assign t0_in = {t0_wb_dat_i, t0_wb_ack_i, t0_wb_err_i}; + +// +// Assign to WB initiator i/f outputs +// +// Either inputs from the target are assigned or zeros. +// +assign i0_out = (req_won == 3'd0) ? t0_in : {`TC_TIN_W{1'b0}}; +assign i1_out = (req_won == 3'd1) ? t0_in : {`TC_TIN_W{1'b0}}; +assign i2_out = (req_won == 3'd2) ? t0_in : {`TC_TIN_W{1'b0}}; +assign i3_out = (req_won == 3'd3) ? t0_in : {`TC_TIN_W{1'b0}}; +assign i4_out = (req_won == 3'd4) ? t0_in : {`TC_TIN_W{1'b0}}; +assign i5_out = (req_won == 3'd5) ? t0_in : {`TC_TIN_W{1'b0}}; +assign i6_out = (req_won == 3'd6) ? t0_in : {`TC_TIN_W{1'b0}}; +assign i7_out = (req_won == 3'd7) ? t0_in : {`TC_TIN_W{1'b0}}; + +// +// Assign to WB target i/f outputs +// +// Assign inputs from initiator to target outputs according to +// which initiator has won. If there is no request for the target, +// assign zeros. +// +assign t0_out = (req_won == 3'd0) ? i0_in : + (req_won == 3'd1) ? i1_in : + (req_won == 3'd2) ? i2_in : + (req_won == 3'd3) ? i3_in : + (req_won == 3'd4) ? i4_in : + (req_won == 3'd5) ? i5_in : + (req_won == 3'd6) ? i6_in : + (req_won == 3'd7) ? i7_in : {`TC_IIN_W{1'b0}}; + +// +// Determine if an initiator has address of the target. +// +assign req_i[0] = i0_wb_cyc_i & + ((i0_wb_adr_i[`TC_AW-1:`TC_AW-t0_addr_w] == t0_addr) | + multitarg & (i0_wb_adr_i[`TC_AW-1:`TC_AW-t17_addr_w] == t17_addr)); +assign req_i[1] = i1_wb_cyc_i & + ((i1_wb_adr_i[`TC_AW-1:`TC_AW-t0_addr_w] == t0_addr) | + multitarg & (i1_wb_adr_i[`TC_AW-1:`TC_AW-t17_addr_w] == t17_addr)); +assign req_i[2] = i2_wb_cyc_i & + ((i2_wb_adr_i[`TC_AW-1:`TC_AW-t0_addr_w] == t0_addr) | + multitarg & (i2_wb_adr_i[`TC_AW-1:`TC_AW-t17_addr_w] == t17_addr)); +assign req_i[3] = i3_wb_cyc_i & + ((i3_wb_adr_i[`TC_AW-1:`TC_AW-t0_addr_w] == t0_addr) | + multitarg & (i3_wb_adr_i[`TC_AW-1:`TC_AW-t17_addr_w] == t17_addr)); +assign req_i[4] = i4_wb_cyc_i & + ((i4_wb_adr_i[`TC_AW-1:`TC_AW-t0_addr_w] == t0_addr) | + multitarg & (i4_wb_adr_i[`TC_AW-1:`TC_AW-t17_addr_w] == t17_addr)); +assign req_i[5] = i5_wb_cyc_i & + ((i5_wb_adr_i[`TC_AW-1:`TC_AW-t0_addr_w] == t0_addr) | + multitarg & (i5_wb_adr_i[`TC_AW-1:`TC_AW-t17_addr_w] == t17_addr)); +assign req_i[6] = i6_wb_cyc_i & + ((i6_wb_adr_i[`TC_AW-1:`TC_AW-t0_addr_w] == t0_addr) | + multitarg & (i6_wb_adr_i[`TC_AW-1:`TC_AW-t17_addr_w] == t17_addr)); +assign req_i[7] = i7_wb_cyc_i & + ((i7_wb_adr_i[`TC_AW-1:`TC_AW-t0_addr_w] == t0_addr) | + multitarg & (i7_wb_adr_i[`TC_AW-1:`TC_AW-t17_addr_w] == t17_addr)); + +// +// Determine who gets current access to the target. +// +// If current initiator still asserts request, do nothing +// (keep current initiator). +// Otherwise check each initiator's request, starting from initiator 0 +// (highest priority). +// If there is no requests from initiators, park initiator 0. +// +assign req_won = req_cont ? req_r : + req_i[0] ? 3'd0 : + req_i[1] ? 3'd1 : + req_i[2] ? 3'd2 : + req_i[3] ? 3'd3 : + req_i[4] ? 3'd4 : + req_i[5] ? 3'd5 : + req_i[6] ? 3'd6 : + req_i[7] ? 3'd7 : 3'd0; + +// +// Check if current initiator still wants access to the target and if +// it does, assert req_cont. +// +always @(req_r or req_i) + case (req_r) // synopsys parallel_case + 3'd0: req_cont = req_i[0]; + 3'd1: req_cont = req_i[1]; + 3'd2: req_cont = req_i[2]; + 3'd3: req_cont = req_i[3]; + 3'd4: req_cont = req_i[4]; + 3'd5: req_cont = req_i[5]; + 3'd6: req_cont = req_i[6]; + 3'd7: req_cont = req_i[7]; + endcase + +// +// Register who has current access to the target. +// +always @(posedge wb_clk_i or posedge wb_rst_i) + if (wb_rst_i) + req_r <= #1 3'd0; + else + req_r <= #1 req_won; + +endmodule + +// +// Single initiator to multiple targets +// +module tc_si_to_mt ( + + i0_wb_cyc_i, + i0_wb_stb_i, + i0_wb_adr_i, + i0_wb_sel_i, + i0_wb_we_i, + i0_wb_dat_i, + i0_wb_dat_o, + i0_wb_ack_o, + i0_wb_err_o, + i0_wb_cti_i, + i0_wb_bte_i, + + t0_wb_cyc_o, + t0_wb_stb_o, + t0_wb_adr_o, + t0_wb_sel_o, + t0_wb_we_o, + t0_wb_dat_o, + t0_wb_dat_i, + t0_wb_ack_i, + t0_wb_err_i, + t0_wb_cti_o, + t0_wb_bte_o, + + t1_wb_cyc_o, + t1_wb_stb_o, + t1_wb_adr_o, + t1_wb_sel_o, + t1_wb_we_o, + t1_wb_dat_o, + t1_wb_dat_i, + t1_wb_ack_i, + t1_wb_err_i, + t1_wb_cti_o, + t1_wb_bte_o, + + t2_wb_cyc_o, + t2_wb_stb_o, + t2_wb_adr_o, + t2_wb_sel_o, + t2_wb_we_o, + t2_wb_dat_o, + t2_wb_dat_i, + t2_wb_ack_i, + t2_wb_err_i, + t2_wb_cti_o, + t2_wb_bte_o, + + t3_wb_cyc_o, + t3_wb_stb_o, + t3_wb_adr_o, + t3_wb_sel_o, + t3_wb_we_o, + t3_wb_dat_o, + t3_wb_dat_i, + t3_wb_ack_i, + t3_wb_err_i, + t3_wb_cti_o, + t3_wb_bte_o, + + t4_wb_cyc_o, + t4_wb_stb_o, + t4_wb_adr_o, + t4_wb_sel_o, + t4_wb_we_o, + t4_wb_dat_o, + t4_wb_dat_i, + t4_wb_ack_i, + t4_wb_err_i, + t4_wb_cti_o, + t4_wb_bte_o, + + t5_wb_cyc_o, + t5_wb_stb_o, + t5_wb_adr_o, + t5_wb_sel_o, + t5_wb_we_o, + t5_wb_dat_o, + t5_wb_dat_i, + t5_wb_ack_i, + t5_wb_err_i, + t5_wb_cti_o, + t5_wb_bte_o, + + t6_wb_cyc_o, + t6_wb_stb_o, + t6_wb_adr_o, + t6_wb_sel_o, + t6_wb_we_o, + t6_wb_dat_o, + t6_wb_dat_i, + t6_wb_ack_i, + t6_wb_err_i, + t6_wb_cti_o, + t6_wb_bte_o, + + t7_wb_cyc_o, + t7_wb_stb_o, + t7_wb_adr_o, + t7_wb_sel_o, + t7_wb_we_o, + t7_wb_dat_o, + t7_wb_dat_i, + t7_wb_ack_i, + t7_wb_err_i, + t7_wb_cti_o, + t7_wb_bte_o + + +); + +// +// Parameters +// +parameter t0_addr_w = 3; +parameter t0_addr = 3'd0; +parameter t17_addr_w = 3; +parameter t1_addr = 3'd1; +parameter t2_addr = 3'd2; +parameter t3_addr = 3'd3; +parameter t4_addr = 3'd4; +parameter t5_addr = 3'd5; +parameter t6_addr = 3'd6; +parameter t7_addr = 3'd7; + +// +// I/O Ports +// + +// +// WB slave i/f connecting initiator 0 +// +input i0_wb_cyc_i; +input i0_wb_stb_i; +input [`TC_AW-1:0] i0_wb_adr_i; +input [`TC_BSW-1:0] i0_wb_sel_i; +input i0_wb_we_i; +input [`TC_DW-1:0] i0_wb_dat_i; +output [`TC_DW-1:0] i0_wb_dat_o; +output i0_wb_ack_o; +output i0_wb_err_o; +input [2:0] i0_wb_cti_i; +input [1:0] i0_wb_bte_i; +// +// WB master i/f connecting target 0 +// +output t0_wb_cyc_o; +output t0_wb_stb_o; +output [`TC_AW-1:0] t0_wb_adr_o; +output [`TC_BSW-1:0] t0_wb_sel_o; +output t0_wb_we_o; +output [`TC_DW-1:0] t0_wb_dat_o; +input [`TC_DW-1:0] t0_wb_dat_i; +input t0_wb_ack_i; +input t0_wb_err_i; +output [2:0] t0_wb_cti_o; +output [1:0] t0_wb_bte_o; + +// +// WB master i/f connecting target 1 +// +output t1_wb_cyc_o; +output t1_wb_stb_o; +output [`TC_AW-1:0] t1_wb_adr_o; +output [`TC_BSW-1:0] t1_wb_sel_o; +output t1_wb_we_o; +output [`TC_DW-1:0] t1_wb_dat_o; +input [`TC_DW-1:0] t1_wb_dat_i; +input t1_wb_ack_i; +input t1_wb_err_i; +output [2:0] t1_wb_cti_o; +output [1:0] t1_wb_bte_o; + +// +// WB master i/f connecting target 2 +// +output t2_wb_cyc_o; +output t2_wb_stb_o; +output [`TC_AW-1:0] t2_wb_adr_o; +output [`TC_BSW-1:0] t2_wb_sel_o; +output t2_wb_we_o; +output [`TC_DW-1:0] t2_wb_dat_o; +input [`TC_DW-1:0] t2_wb_dat_i; +input t2_wb_ack_i; +input t2_wb_err_i; +output [2:0] t2_wb_cti_o; +output [1:0] t2_wb_bte_o; + +// +// WB master i/f connecting target 3 +// +output t3_wb_cyc_o; +output t3_wb_stb_o; +output [`TC_AW-1:0] t3_wb_adr_o; +output [`TC_BSW-1:0] t3_wb_sel_o; +output t3_wb_we_o; +output [`TC_DW-1:0] t3_wb_dat_o; +input [`TC_DW-1:0] t3_wb_dat_i; +input t3_wb_ack_i; +input t3_wb_err_i; +output [2:0] t3_wb_cti_o; +output [1:0] t3_wb_bte_o; + +// +// WB master i/f connecting target 4 +// +output t4_wb_cyc_o; +output t4_wb_stb_o; +output [`TC_AW-1:0] t4_wb_adr_o; +output [`TC_BSW-1:0] t4_wb_sel_o; +output t4_wb_we_o; +output [`TC_DW-1:0] t4_wb_dat_o; +input [`TC_DW-1:0] t4_wb_dat_i; +input t4_wb_ack_i; +input t4_wb_err_i; +output [2:0] t4_wb_cti_o; +output [1:0] t4_wb_bte_o; + +// +// WB master i/f connecting target 5 +// +output t5_wb_cyc_o; +output t5_wb_stb_o; +output [`TC_AW-1:0] t5_wb_adr_o; +output [`TC_BSW-1:0] t5_wb_sel_o; +output t5_wb_we_o; +output [`TC_DW-1:0] t5_wb_dat_o; +input [`TC_DW-1:0] t5_wb_dat_i; +input t5_wb_ack_i; +input t5_wb_err_i; +output [2:0] t5_wb_cti_o; +output [1:0] t5_wb_bte_o; + +// +// WB master i/f connecting target 6 +// +output t6_wb_cyc_o; +output t6_wb_stb_o; +output [`TC_AW-1:0] t6_wb_adr_o; +output [`TC_BSW-1:0] t6_wb_sel_o; +output t6_wb_we_o; +output [`TC_DW-1:0] t6_wb_dat_o; +input [`TC_DW-1:0] t6_wb_dat_i; +input t6_wb_ack_i; +input t6_wb_err_i; +output [2:0] t6_wb_cti_o; +output [1:0] t6_wb_bte_o; + +// +// WB master i/f connecting target 7 +// +output t7_wb_cyc_o; +output t7_wb_stb_o; +output [`TC_AW-1:0] t7_wb_adr_o; +output [`TC_BSW-1:0] t7_wb_sel_o; +output t7_wb_we_o; +output [`TC_DW-1:0] t7_wb_dat_o; +input [`TC_DW-1:0] t7_wb_dat_i; +input t7_wb_ack_i; +input t7_wb_err_i; +output [2:0] t7_wb_cti_o; +output [1:0] t7_wb_bte_o; + + +// +// Internal wires & registers +// +wire [`TC_IIN_W-1:0] i0_in; +wire [`TC_TIN_W-1:0] i0_out; +wire [`TC_IIN_W-1:0] t0_out, t1_out, + t2_out, t3_out, + t4_out, t5_out, + t6_out, t7_out; +wire [`TC_TIN_W-1:0] t0_in, t1_in, + t2_in, t3_in, + t4_in, t5_in, + t6_in, t7_in; +wire [7:0] req_t; + +// +// Group WB initiator 0 i/f inputs and outputs +// +assign i0_in = {i0_wb_cyc_i, i0_wb_stb_i, i0_wb_adr_i, + i0_wb_sel_i, i0_wb_we_i, i0_wb_dat_i, i0_wb_cti_i, i0_wb_bte_i}; +assign {i0_wb_dat_o, i0_wb_ack_o, i0_wb_err_o} = i0_out; +// +// Group WB target 0 i/f inputs and outputs +// +assign {t0_wb_cyc_o, t0_wb_stb_o, t0_wb_adr_o, +t0_wb_sel_o, t0_wb_we_o, t0_wb_dat_o, t0_wb_cti_o, t0_wb_bte_o} = t0_out; +assign t0_in = {t0_wb_dat_i, t0_wb_ack_i, t0_wb_err_i}; + +// +// Group WB target 1 i/f inputs and outputs +// +assign {t1_wb_cyc_o, t1_wb_stb_o, t1_wb_adr_o, +t1_wb_sel_o, t1_wb_we_o, t1_wb_dat_o, t1_wb_cti_o, t1_wb_bte_o} = t1_out; +assign t1_in = {t1_wb_dat_i, t1_wb_ack_i, t1_wb_err_i}; + +// +// Group WB target 2 i/f inputs and outputs +// +assign {t2_wb_cyc_o, t2_wb_stb_o, t2_wb_adr_o, +t2_wb_sel_o, t2_wb_we_o, t2_wb_dat_o, t2_wb_cti_o, t2_wb_bte_o} = t2_out; +assign t2_in = {t2_wb_dat_i, t2_wb_ack_i, t2_wb_err_i}; + +// +// Group WB target 3 i/f inputs and outputs +// +assign {t3_wb_cyc_o, t3_wb_stb_o, t3_wb_adr_o, +t3_wb_sel_o, t3_wb_we_o, t3_wb_dat_o, t3_wb_cti_o, t3_wb_bte_o} = t3_out; +assign t3_in = {t3_wb_dat_i, t3_wb_ack_i, t3_wb_err_i}; + +// +// Group WB target 4 i/f inputs and outputs +// +assign {t4_wb_cyc_o, t4_wb_stb_o, t4_wb_adr_o, +t4_wb_sel_o, t4_wb_we_o, t4_wb_dat_o, t4_wb_cti_o, t4_wb_bte_o} = t4_out; +assign t4_in = {t4_wb_dat_i, t4_wb_ack_i, t4_wb_err_i}; + +// +// Group WB target 5 i/f inputs and outputs +// +assign {t5_wb_cyc_o, t5_wb_stb_o, t5_wb_adr_o, +t5_wb_sel_o, t5_wb_we_o, t5_wb_dat_o, t5_wb_cti_o, t5_wb_bte_o} = t5_out; +assign t5_in = {t5_wb_dat_i, t5_wb_ack_i, t5_wb_err_i}; + +// +// Group WB target 6 i/f inputs and outputs +// +assign {t6_wb_cyc_o, t6_wb_stb_o, t6_wb_adr_o, +t6_wb_sel_o, t6_wb_we_o, t6_wb_dat_o, t6_wb_cti_o, t6_wb_bte_o} = t6_out; +assign t6_in = {t6_wb_dat_i, t6_wb_ack_i, t6_wb_err_i}; + +// +// Group WB target 7 i/f inputs and outputs +// +assign {t7_wb_cyc_o, t7_wb_stb_o, t7_wb_adr_o, +t7_wb_sel_o, t7_wb_we_o, t7_wb_dat_o, t7_wb_cti_o, t7_wb_bte_o} = t7_out; +assign t7_in = {t7_wb_dat_i, t7_wb_ack_i, t7_wb_err_i}; + +// +// Assign to WB target i/f outputs +// +// Either inputs from the initiator are assigned or zeros. +// +assign t0_out = req_t[0] ? i0_in : {`TC_IIN_W{1'b0}}; +assign t1_out = req_t[1] ? i0_in : {`TC_IIN_W{1'b0}}; +assign t2_out = req_t[2] ? i0_in : {`TC_IIN_W{1'b0}}; +assign t3_out = req_t[3] ? i0_in : {`TC_IIN_W{1'b0}}; +assign t4_out = req_t[4] ? i0_in : {`TC_IIN_W{1'b0}}; +assign t5_out = req_t[5] ? i0_in : {`TC_IIN_W{1'b0}}; +assign t6_out = req_t[6] ? i0_in : {`TC_IIN_W{1'b0}}; +assign t7_out = req_t[7] ? i0_in : {`TC_IIN_W{1'b0}}; + +// +// Assign to WB initiator i/f outputs +// +// Assign inputs from target to initiator outputs according to +// which target is accessed. If there is no request for a target, +// assign zeros. +// +assign i0_out = req_t[0] ? t0_in : + req_t[1] ? t1_in : + req_t[2] ? t2_in : + req_t[3] ? t3_in : + req_t[4] ? t4_in : + req_t[5] ? t5_in : + req_t[6] ? t6_in : + req_t[7] ? t7_in : {`TC_TIN_W{1'b0}}; + +// +// Determine which target is being accessed. +// +assign req_t[0] = i0_wb_cyc_i & (i0_wb_adr_i[`TC_AW-1:`TC_AW-t0_addr_w] == t0_addr); +assign req_t[1] = i0_wb_cyc_i & (i0_wb_adr_i[`TC_AW-1:`TC_AW-t17_addr_w] == t1_addr); +assign req_t[2] = i0_wb_cyc_i & (i0_wb_adr_i[`TC_AW-1:`TC_AW-t17_addr_w] == t2_addr); +assign req_t[3] = i0_wb_cyc_i & (i0_wb_adr_i[`TC_AW-1:`TC_AW-t17_addr_w] == t3_addr); +assign req_t[4] = i0_wb_cyc_i & (i0_wb_adr_i[`TC_AW-1:`TC_AW-t17_addr_w] == t4_addr); +assign req_t[5] = i0_wb_cyc_i & (i0_wb_adr_i[`TC_AW-1:`TC_AW-t17_addr_w] == t5_addr); +assign req_t[6] = i0_wb_cyc_i & (i0_wb_adr_i[`TC_AW-1:`TC_AW-t17_addr_w] == t6_addr); +assign req_t[7] = i0_wb_cyc_i & (i0_wb_adr_i[`TC_AW-1:`TC_AW-t17_addr_w] == t7_addr); + +endmodule Index: release-1.0/utils/contributions/eth_transf_linux/eth1_mac_recv.c =================================================================== --- release-1.0/utils/contributions/eth_transf_linux/eth1_mac_recv.c (nonexistent) +++ release-1.0/utils/contributions/eth_transf_linux/eth1_mac_recv.c (revision 151) @@ -0,0 +1,118 @@ +#include + +#include + +//packet socket +#include +#include +#include + +//protocol +#include + +//netdevice stuff +#include +#include + +//file open stuff +#include +#include +#include + +//arp stuff +//#include + +#define MAC_ADDR_LEN 6 +typedef unsigned char MacAddress[MAC_ADDR_LEN]; + +int main() +{ + int socket_id, new_sock, iRet = -1; + int addrlen, bytesread, nfound =0; + + int i = 0; + + MacAddress localMac = {0x00, 0x00, 0xC0, 0x41, 0x36, 0xD3}; +// MacAddress localMac = {0xD3, 0x36, 0x41, 0xC0, 0x00, 0x00}; + + char buf[256]; + + struct sockaddr_ll my_addr; + + struct ifreq ethreq; + + int if_index; + + //create packet socket from type sock_dgram where headers are automatically thrown out + if ( ( socket_id = socket(PF_PACKET, SOCK_DGRAM, htons(ETH_P_ALL) ) ) < 0 ) + { + perror("socket"); + exit(1); + } + else + { + printf("Socket has been created: socket_number %d\n", socket_id); + } + + + //GET ethreq for if "eth1" + strncpy(ethreq.ifr_name,"eth1",IFNAMSIZ); + ioctl(socket_id, SIOCGIFFLAGS, ðreq); + //SET promisc mode for if ethreq +// ethreq.ifr_flags |= IFF_PROMISC; +// ioctl(socket_id, SIOCSIFFLAGS, ðreq); + //request index + ioctl(socket_id, SIOCGIFINDEX, ðreq); + + if_index = ethreq.ifr_ifindex; + + printf("This is the index of the interface: %d\n", if_index ); + + memset(&my_addr, '0', sizeof(my_addr) ); + + my_addr.sll_family = AF_PACKET; + my_addr.sll_protocol = htons(ETH_P_ALL); //defaults to socket protocol + my_addr.sll_ifindex = if_index; +// my_addr.sll_hatype = htons(ARPHRD_ETHER); +// my_addr.sll_pkttype = PACKET_OTHERHOST; + my_addr.sll_halen = 6; + memcpy( &(my_addr.sll_addr), localMac, MAC_ADDR_LEN ); + + //request hw_addres + ioctl(socket_id, SIOCGIFHWADDR, ðreq); + + printf("This is the address of my card: %d\n", my_addr.sll_addr[5] ); + + //bind to interface goten from ioctl SIOCGIFHWADDR directive (otherwise all packets are recved) + if ( bind( socket_id, (struct sockaddr *) &my_addr, sizeof(my_addr) ) ) + { + perror("bind"); + exit(1); + } + + struct sockaddr_ll from; + int fromlen; + + fromlen = sizeof(from); + + for (;;) + { + iRet = recvfrom(socket_id, buf, 256, 0, &from, &fromlen); + if ( iRet == -1 ) + { + perror("recvfrom"); + exit(1); + } + else + { + printf("Received %d bytes of data.\n", iRet); + printf("This is the received data:\n"); + for ( i = 0; i < iRet; i++) + printf("Byte %d: %X\n", i, (int)buf[i]); + printf("End of transmission!\n"); + } + } + + return 0; +} + Index: release-1.0/utils/contributions/eth_transf_linux/eth1_mac_snd.c =================================================================== --- release-1.0/utils/contributions/eth_transf_linux/eth1_mac_snd.c (nonexistent) +++ release-1.0/utils/contributions/eth_transf_linux/eth1_mac_snd.c (revision 151) @@ -0,0 +1,139 @@ +#include + +#include + +//packet socket +#include +#include +#include + +//protocol +#include + +//netdevice stuff +#include +#include + +//file open stuff +#include +#include +#include + +//arp stuff +//#include + +#define MAC_ADDR_LEN 6 +typedef unsigned char MacAddress[MAC_ADDR_LEN]; + +int main() +{ + int socket_id, new_sock, iRet = -1; + int addrlen, bytesread, nfound =0; + + int i = 0; + + MacAddress localMac = {0x00, 0x00, 0xC0, 0x41, 0x36, 0xD3}; + MacAddress extMac = {0x55, 0x47, 0x34, 0x22, 0x88, 0x92}; +// MacAddress extMac = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00}; + + char buf[256]; + + struct sockaddr_ll my_addr; + + struct ifreq ethreq; + + int if_index; + + if ( ( socket_id = socket(PF_PACKET, SOCK_DGRAM, htons(ETH_P_ALL) ) ) < 0 ) + { + perror("socket"); + exit(1); + } + else + { + printf("Socket has been created: socket_number %d\n", socket_id); + } + + + //GET ethreq for if "eth1" + strncpy(ethreq.ifr_name,"eth1",IFNAMSIZ); + ioctl(socket_id, SIOCGIFFLAGS, ðreq); + //SET promisc mode for if ethreq +// ethreq.ifr_flags |= IFF_PROMISC; +// ioctl(socket_id, SIOCSIFFLAGS, ðreq); + //request index + ioctl(socket_id, SIOCGIFINDEX, ðreq); + if_index = ethreq.ifr_ifindex; + + printf("This is the index of the interface: %d\n", if_index ); + + memset(&my_addr, '0', sizeof(my_addr) ); + + my_addr.sll_family = AF_PACKET; + my_addr.sll_protocol = htons(ETH_P_ALL); //defaults to socket protocol + my_addr.sll_ifindex = if_index; +// my_addr.sll_hatype = htons(ARPHRD_ETHER); +// my_addr.sll_pkttype = PACKET_OTHERHOST; + my_addr.sll_halen = 6; + memcpy( &(my_addr.sll_addr), localMac, MAC_ADDR_LEN ); + + //request hw_addres + ioctl(socket_id, SIOCGIFHWADDR, ðreq); + + printf("This is the address of my card: %d\n", my_addr.sll_addr[5] ); + + if ( bind( socket_id, (struct sockaddr *) &my_addr, sizeof(my_addr) ) ) + { + perror("bind"); + exit(1); + } + + struct sockaddr_ll addr_to; + int addr_toLen; + + addr_toLen = sizeof(addr_to); + + memset(&addr_to, '0', sizeof(addr_to) ); + + addr_to.sll_family = AF_PACKET; + addr_to.sll_ifindex = if_index; + addr_to.sll_halen = 6; + memcpy( &(addr_to.sll_addr), extMac, MAC_ADDR_LEN ); + + for (i=0; i<256 ; i++ ) + buf[i] = 0; + + //first 2 bytes are gathered with length and are ignored + buf[0] = 0xAA; + buf[1] = 0xAA; + //now it gets to fpga: send opcode 0xBA8 + buf[2] = 0xBA; + buf[3] = 0x87; + //opcode sent + buf[4] = 0xAA; + buf[5] = 0xAA; + buf[6] = 0xAA; + buf[7] = 0xAA; + buf[8] = 0xAA; + buf[9] = 0xAA; + buf[10] = 0xAA; + buf[11] = 0xAA; + +// for (;;) +// { + iRet = sendto(socket_id, buf, 46, 0, (struct sockaddr *) &addr_to, addr_toLen); + if ( iRet == -1 ) + { + perror("sendto"); + exit(1); + } + else + { +// printf("%s\n", buf); + printf("Data sent!\nExiting...\n"); + } +// } + + return 0; +} + Index: release-1.0/utils/cable_parallel.c =================================================================== --- release-1.0/utils/cable_parallel.c (nonexistent) +++ release-1.0/utils/cable_parallel.c (revision 151) @@ -0,0 +1,219 @@ +/* cable_parallel.c - Parallel cable drivers (XPC3 and XESS) for the Advanced JTAG Bridge + Copyright (C) 2001 Marko Mlinar, markom@opencores.org + Copyright (C) 2004 György Jeney, nog@sdf.lonestar.org + + + This program is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 2 of the License, or + (at your option) any later version. + + This program is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program; if not, write to the Free Software + Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. */ + + + +#include +#include + +#include +#include +#include +#include +#include +#include + +#include "cable_common.h" +#include "errcodes.h" + + +// Common functions used by both cable types +static int cable_parallel_out(uint8_t value); +static int cable_parallel_inout(uint8_t value, uint8_t *inval); + + +int fd; + + + +///////////////////////////////////////////////////////////////////////////////// +/*-------------------------------------[ Parallel port specific functions ]---*/ +/////////////////////////////////////////////////////////////////////////////// + +int cable_parallel_init() +{ +/* + //#ifndef WIN32 + if (ioperm(base, 3, 1)) { + fprintf(stderr, "Couldn't get the port at %x\n", base); + perror("Root privileges are required.\n"); + return APP_ERR_INIT_FAILED; + } + printf("Connected to parallel port at %x\n", base); + printf("Dropping root privileges.\n"); + setreuid(getuid(), getuid()); + //#endif +*/ + int mode = IEEE1284_MODE_COMPAT; + fd = open("/dev/parport0", O_RDWR | O_NONBLOCK); + if (fd == -1) + { + perror("Not able to acquire the device desriptor\n"); + return APP_ERR_INIT_FAILED; + } + if (ioctl(fd, PPCLAIM) == -1) + { + perror("Fail to claim the interface for itself.\n"); + return APP_ERR_INIT_FAILED; + } + if (ioctl(fd, PPSETMODE, &mode) == -1) + { + perror("Setting compatibility mode failed.\n"); + return APP_ERR_INIT_FAILED; + } + + return APP_ERR_NONE; +} + + +int cable_parallel_opt(int c, char *str) +{ + switch(c) { + case 'p': +// if(!sscanf(str, "%x", &base)) { +// fprintf(stderr, "p parameter must have a hex number as parameter\n"); + return APP_ERR_BAD_PARAM; +// } + break; + default: + fprintf(stderr, "Unknown parameter '%c'\n", c); + return APP_ERR_BAD_PARAM; + } + return APP_ERR_NONE; +} + +/*-----------------------------------------[ Physical board wait function ]---*/ +void cable_parallel_phys_wait() +{ + /* Multiple users have reported poor performance of parallel cables, + * which has been traced to usleep() sleeping much longer than + * microseconds. The same users have reported error-free functionality + * and an order of magnitude improvement in upload speed. + * If you get strange data errors while running, add this sleep back + * in, or perhaps a busy-wait delay. + */ + /* usleep(10); */ +} + +/*----------------------------------------------[ xpc3 specific functions ]---*/ +int cable_xpc3_out(uint8_t value) +{ + uint8_t out = 0; + + /* First convert the bits in value byte to the ones that the cable wants */ + if(value & TCLK_BIT) + out |= 0x02; /* D1 pin 3 */ + if(value & TRST_BIT) + out |= 0x10; /* Not used */ + if(value & TDI_BIT) + out |= 0x01; /* D0 pin 2 */ + if(value & TMS_BIT) + out |= 0x04; /* D2 pin 4 */ + + return cable_parallel_out(out); +} + +int cable_xpc3_inout(uint8_t value, uint8_t *inval) +{ + uint8_t in; + int retval; + uint8_t out = 0; + + /* First convert the bits in value byte to the ones that the cable wants */ + if(value & TCLK_BIT) + out |= 0x02; /* D1 pin 3 */ + if(value & TRST_BIT) + out |= 0x10; /* Not used */ + if(value & TDI_BIT) + out |= 0x01; /* D0 pin 2 */ + if(value & TMS_BIT) + out |= 0x04; /* D2 pin 4 */ + + retval = cable_parallel_inout(out, &in); + + if(in & 0x10) /* S6 pin 13 */ + *inval = 1; + else + *inval = 0; + + return retval; +} + +/*----------------------------------------------[ xess specific functions ]---*/ +int cable_xess_out(uint8_t value) +{ + uint8_t out = 0; + + /* First convert the bits in value byte to the ones that the cable wants */ + if(value & TCLK_BIT) + out |= 0x04; /* D2 pin 4 */ + if(value & TRST_BIT) + out |= 0x08; /* D3 pin 5 */ + if(value & TDI_BIT) + out |= 0x10; /* D4 pin 6 */ + if(value & TMS_BIT) + out |= 0x20; /* D3 pin 5 */ + + return cable_parallel_out(out); +} + +uint8_t cable_xess_inout(uint8_t value, uint8_t *inval) +{ + uint8_t in; + int retval; + uint8_t out = 0; + + /* First convert the bits in value byte to the ones that the cable wants */ + if(value & TCLK_BIT) + out |= 0x04; /* D2 pin 4 */ + if(value & TRST_BIT) + out |= 0x08; /* D3 pin 5 */ + if(value & TDI_BIT) + out |= 0x10; /* D4 pin 6 */ + if(value & TMS_BIT) + out |= 0x20; /* D3 pin 5 */ + + retval = cable_parallel_inout(out, &in); + + if(in & 0x20) /* S5 pin 12*/ + *inval = 1; + else + *inval = 0; + + return retval; +} + + +/*----------------------------------------------[ common helper functions ]---*/ +// 'static' for internal access only + +static int cable_parallel_out(uint8_t value) +{ + ioctl(fd, PPWDATA, &value); + + return APP_ERR_NONE; +} + +static int cable_parallel_inout(uint8_t value, uint8_t *inval) +{ + ioctl(fd, PPRSTATUS, inval); + ioctl(fd, PPWDATA, &value); + + return APP_ERR_NONE; +}
release-1.0/utils/cable_parallel.c Property changes : Added: svn:executable ## -0,0 +1 ## +* \ No newline at end of property Index: release-1.0/utils/minsoc_wb_32_8_bridge.v =================================================================== --- release-1.0/utils/minsoc_wb_32_8_bridge.v (nonexistent) +++ release-1.0/utils/minsoc_wb_32_8_bridge.v (revision 151) @@ -0,0 +1,52 @@ + +module minsoc_wb_32_8_bridge( + wb_32_sel_i, + wb_32_dat_i, wb_32_dat_o, wb_32_adr_i, + + wb_8_dat_i, wb_8_dat_o, wb_8_adr_i +); + +input [3:0] wb_32_sel_i; + +input [31:0] wb_32_dat_i; +output reg [31:0] wb_32_dat_o; +input [31:0] wb_32_adr_i; + +output reg [7:0] wb_8_dat_i; +input [7:0] wb_8_dat_o; +output [31:0] wb_8_adr_i; + +reg [1:0] wb_8_adr; + +// put output to the correct byte in 32 bits using select line +always @(wb_32_sel_i or wb_8_dat_o) + case (wb_32_sel_i) + 4'b0001: wb_32_dat_o <= #1 {24'b0, wb_8_dat_o}; + 4'b0010: wb_32_dat_o <= #1 {16'b0, wb_8_dat_o , 8'b0}; + 4'b0100: wb_32_dat_o <= #1 {8'b0, wb_8_dat_o , 16'b0}; + 4'b1000: wb_32_dat_o <= #1 {wb_8_dat_o , 24'b0}; + 4'b1111: wb_32_dat_o <= #1 {24'b0, wb_8_dat_o}; + default: wb_32_dat_o <= #1 0; + endcase // case(wb_sel_i) + +always @(wb_32_sel_i or wb_32_dat_i) +begin + case (wb_32_sel_i) + 4'b0001 : wb_8_dat_i = wb_32_dat_i[7:0]; + 4'b0010 : wb_8_dat_i = wb_32_dat_i[15:8]; + 4'b0100 : wb_8_dat_i = wb_32_dat_i[23:16]; + 4'b1000 : wb_8_dat_i = wb_32_dat_i[31:24]; + default : wb_8_dat_i = wb_32_dat_i[7:0]; + endcase // case(wb_sel_i) + case (wb_32_sel_i) + 4'b0001 : wb_8_adr = 2'h3; + 4'b0010 : wb_8_adr = 2'h2; + 4'b0100 : wb_8_adr = 2'h1; + 4'b1000 : wb_8_adr = 2'h0; + default : wb_8_adr = 2'h0; + endcase // case(wb_sel_i) +end + +assign wb_8_adr_i = { wb_32_adr_i[31:2] , wb_8_adr }; + +endmodule Index: release-1.0/bench/verilog/minsoc_bench.v =================================================================== --- release-1.0/bench/verilog/minsoc_bench.v (nonexistent) +++ release-1.0/bench/verilog/minsoc_bench.v (revision 151) @@ -0,0 +1,953 @@ +`include "minsoc_bench_defines.v" +`include "minsoc_defines.v" +`include "or1200_defines.v" + +`include "timescale.v" + +module minsoc_bench(); + +`ifdef POSITIVE_RESET + localparam RESET_LEVEL = 1'b1; +`elsif NEGATIVE_RESET + localparam RESET_LEVEL = 1'b0; +`else + localparam RESET_LEVEL = 1'b1; +`endif + +reg clock, reset; + +//Debug interface +wire dbg_tms_i; +wire dbg_tck_i; +wire dbg_tdi_i; +wire dbg_tdo_o; +wire jtag_vref; +wire jtag_gnd; + +//SPI wires +wire spi_mosi; +reg spi_miso; +wire spi_sclk; +wire [1:0] spi_ss; + +//UART wires +wire uart_stx; +reg uart_srx; + +//ETH wires +reg eth_col; +reg eth_crs; +wire eth_trst; +reg eth_tx_clk; +wire eth_tx_en; +wire eth_tx_er; +wire [3:0] eth_txd; +reg eth_rx_clk; +reg eth_rx_dv; +reg eth_rx_er; +reg [3:0] eth_rxd; +reg eth_fds_mdint; +wire eth_mdc; +wire eth_mdio; + +// +// TASKS registers to communicate with interfaces +// +reg design_ready; +reg uart_echo; +`ifdef UART +reg [40*8-1:0] line; +reg [12*8-1:0] hello; +reg new_line; +reg new_char; +reg flush_line; +`endif +`ifdef ETHERNET +reg [7:0] eth_rx_data [0:1535]; //receive buffer ETH (max packet 1536) +reg [7:0] eth_tx_data [0:1535]; //send buffer ETH (max packet 1536) +localparam ETH_HDR = 14; +localparam ETH_PAYLOAD_MAX_LENGTH = 1518;//only able to send up to 1536 bytes with header (14 bytes) and CRC (4 bytes) +`endif + + +// +// Testbench mechanics +// +reg [7:0] program_mem[(1<<(`MEMORY_ADR_WIDTH+2))-1:0]; +integer initialize, ptr; +reg [8*64:0] file_name; +integer firmware_size; // Note that the .hex file size is greater than this, as each byte in the file needs 2 hex characters. +integer firmware_size_in_header; +reg load_file; + +initial begin + reset = ~RESET_LEVEL; + clock = 1'b0; + eth_tx_clk = 1'b0; + eth_rx_clk = 1'b0; + + design_ready = 1'b0; + uart_echo = 1'b1; + +`ifndef NO_CLOCK_DIVISION + minsoc_top_0.clk_adjust.clk_int = 1'b0; + minsoc_top_0.clk_adjust.clock_divisor = 32'h0000_0000; +`endif + + uart_srx = 1'b1; + + eth_col = 1'b0; + eth_crs = 1'b0; + eth_fds_mdint = 1'b1; + eth_rx_er = 1'b0; + eth_rxd = 4'h0; + eth_rx_dv = 1'b0; + + +//dual and two port rams from FPGA memory instances have to be initialized to 0 + init_fpga_memory(); + + load_file = 1'b0; +`ifdef INITIALIZE_MEMORY_MODEL + load_file = 1'b1; +`endif +`ifdef START_UP + load_file = 1'b1; +`endif + + //get firmware hex file from command line input + if ( load_file ) begin + if ( ! $value$plusargs("file_name=%s", file_name) || file_name == 0 ) begin + $display("ERROR: Please specify the name of the firmware file to load on start-up."); + $finish; + end + + // We are passing the firmware size separately as a command-line argument in order + // to avoid this kind of Icarus Verilog warnings: + // WARNING: minsoc_bench_core.v:111: $readmemh: Standard inconsistency, following 1364-2005. + // WARNING: minsoc_bench_core.v:111: $readmemh(../../sw/uart/uart.hex): Not enough words in the file for the requested range [0:32767]. + // Apparently, some of the $readmemh() warnigns are even required by the standard. The trouble is, + // Verilog's $fread() is not widely implemented in the simulators, so from Verilog alone + // it's not easy to read the firmware file header without getting such warnings. + if ( ! $value$plusargs("firmware_size=%d", firmware_size) ) begin + $display("ERROR: Please specify the size of the firmware (in bytes) contained in the hex firmware file."); + $finish; + end + + $readmemh(file_name, program_mem, 0, firmware_size - 1); + + firmware_size_in_header = { program_mem[0] , program_mem[1] , program_mem[2] , program_mem[3] }; + + if ( firmware_size != firmware_size_in_header ) begin + $display("ERROR: The firmware size in the file header does not match the firmware size given as command-line argument. Did you forget bin2hex's -size_word flag when generating the firmware file?"); + $finish; + end + + end + +`ifdef INITIALIZE_MEMORY_MODEL + // Initialize memory with firmware + initialize = 0; + while ( initialize < firmware_size ) begin + minsoc_top_0.onchip_ram_top.block_ram_3.mem[initialize/4] = program_mem[initialize]; + minsoc_top_0.onchip_ram_top.block_ram_2.mem[initialize/4] = program_mem[initialize+1]; + minsoc_top_0.onchip_ram_top.block_ram_1.mem[initialize/4] = program_mem[initialize+2]; + minsoc_top_0.onchip_ram_top.block_ram_0.mem[initialize/4] = program_mem[initialize+3]; + initialize = initialize + 4; + end + $display("Memory model initialized with firmware:"); + $display("%s", file_name); + $display("%d Bytes loaded from %d ...", initialize , firmware_size); +`endif + + // Reset controller + repeat (2) @ (negedge clock); + reset = RESET_LEVEL; + repeat (16) @ (negedge clock); + reset = ~RESET_LEVEL; + +`ifdef START_UP + // Pass firmware over spi to or1k_startup + ptr = 0; + //read dummy + send_spi(program_mem[ptr]); + send_spi(program_mem[ptr]); + send_spi(program_mem[ptr]); + send_spi(program_mem[ptr]); + //~read dummy + while ( ptr < firmware_size ) begin + send_spi(program_mem[ptr]); + ptr = ptr + 1; + end + $display("Memory start-up completed..."); + $display("Loaded firmware:"); + $display("%s", file_name); +`endif + + + // + // Testbench START + // + design_ready = 1'b1; + $display("Running simulation: if you want to stop it, type ctrl+c and type in finish afterwards."); + fork + begin +`ifdef UART + +`ifdef ETHERNET +`ifdef TEST_ETHERNET + $display("Testing Ethernet firmware, this takes long (~15 min. @ 2.53 GHz dual-core)..."); + $display("Ethernet firmware encloses UART firmware, testing UART firmware first..."); + test_uart(); + test_eth(); + $display("Stopping simulation."); + $finish; +`endif +`endif + +`ifdef TEST_UART + $display("Testing UART firmware, this takes a while (~1 min. @ 2.53 GHz dual-core)..."); + test_uart(); + $display("Stopping simulation."); + $finish; +`endif + +`endif + end + begin +`ifdef ETHERNET +`ifdef TEST_ETHERNET + get_mac(); + if ( { eth_rx_data[ETH_HDR] , eth_rx_data[ETH_HDR+1] , eth_rx_data[ETH_HDR+2] , eth_rx_data[ETH_HDR+3] } == 32'hFF2B4050 ) + $display("Ethernet firmware started correctly."); +`endif +`endif + end + join + +end + + +// +// Modules instantiations +// +minsoc_top minsoc_top_0( + .clk(clock), + .reset(reset) + + //JTAG ports +`ifdef GENERIC_TAP + , .jtag_tdi(dbg_tdi_i), + .jtag_tms(dbg_tms_i), + .jtag_tck(dbg_tck_i), + .jtag_tdo(dbg_tdo_o), + .jtag_vref(jtag_vref), + .jtag_gnd(jtag_gnd) +`endif + + //SPI ports +`ifdef START_UP + , .spi_flash_mosi(spi_mosi), + .spi_flash_miso(spi_miso), + .spi_flash_sclk(spi_sclk), + .spi_flash_ss(spi_ss) +`endif + + //UART ports +`ifdef UART + , .uart_stx(uart_stx), + .uart_srx(uart_srx) +`endif // !UART + + // Ethernet ports +`ifdef ETHERNET + , .eth_col(eth_col), + .eth_crs(eth_crs), + .eth_trste(eth_trst), + .eth_tx_clk(eth_tx_clk), + .eth_tx_en(eth_tx_en), + .eth_tx_er(eth_tx_er), + .eth_txd(eth_txd), + .eth_rx_clk(eth_rx_clk), + .eth_rx_dv(eth_rx_dv), + .eth_rx_er(eth_rx_er), + .eth_rxd(eth_rxd), + .eth_fds_mdint(eth_fds_mdint), + .eth_mdc(eth_mdc), + .eth_mdio(eth_mdio) +`endif // !ETHERNET +); + +`ifdef VPI_DEBUG + dbg_comm_vpi dbg_if( + .SYS_CLK(clock), + .P_TMS(dbg_tms_i), + .P_TCK(dbg_tck_i), + .P_TRST(), + .P_TDI(dbg_tdi_i), + .P_TDO(dbg_tdo_o) + ); +`else + assign dbg_tdi_i = 1; + assign dbg_tck_i = 0; + assign dbg_tms_i = 1; +`endif + + +// +// Firmware testers +// +`ifdef UART +task test_uart(); + begin + @ (posedge new_line); + $display("UART data received."); + hello = line[12*8-1:0]; + //sending character A to UART, B expected + $display("Testing UART interrupt..."); + uart_echo = 1'b0; + uart_send(8'h41); //Character A + @ (posedge new_char); + if ( line[7:0] == "B" ) + $display("UART interrupt working."); + else + $display("UART interrupt failed. B was expected, %c was received.", line[7:0]); + uart_echo = 1'b1; + + if ( hello == "Hello World." ) + $display("UART firmware test completed, behaving correctly."); + else + $display("UART firmware test completed, failed."); + end +endtask +`endif + +`ifdef ETHERNET +task test_eth(); + begin + eth_tx_data[ETH_HDR+0] = 8'hBA; + eth_tx_data[ETH_HDR+1] = 8'h87; + eth_tx_data[ETH_HDR+2] = 8'hAA; + eth_tx_data[ETH_HDR+3] = 8'hBB; + eth_tx_data[ETH_HDR+4] = 8'hCC; + eth_tx_data[ETH_HDR+5] = 8'hDD; + + $display("Sending an Ethernet package to the system and waiting for the data to be output through UART..."); + send_mac(6); + repeat(3+40) @ (posedge new_line); + $display("Ethernet test completed."); + end +endtask +`endif + + +// +// Regular clocking and output +// +always begin + #((`CLK_PERIOD)/2) clock <= ~clock; +end + +`ifdef WAVEFORM_OUTPUT +initial begin + $dumpfile("../results/minsoc_wave.lxt2"); + $dumpvars(); +end +`endif + + +// +// Functionalities tasks: SPI Startup and UART Monitor +// +//SPI START_UP +`ifdef START_UP +task send_spi; + input [7:0] data_in; + integer i; + begin + i = 7; + for ( i = 7 ; i >= 0; i = i - 1 ) begin + spi_miso = data_in[i]; + @ (posedge spi_sclk); + end + end +endtask +`endif +//~SPI START_UP + +//UART +`ifdef UART +localparam UART_TX_WAIT = (`FREQ_NUM_FOR_NS / `UART_BAUDRATE); + +task uart_send; + input [7:0] data; + integer i; + begin + uart_srx = 1'b0; + #UART_TX_WAIT; + for ( i = 0; i < 8 ; i = i + 1 ) begin + uart_srx = data[i]; + #UART_TX_WAIT; + end + uart_srx = 1'b0; + #UART_TX_WAIT; + uart_srx = 1'b1; + end +endtask + +//UART Monitor (prints uart output on the terminal) +// Something to trigger the task +initial +begin + new_line = 1'b0; + new_char = 1'b0; + flush_line = 1'b0; +end + +always @ (posedge clock) + if ( design_ready ) + uart_decoder; + +task uart_decoder; + integer i; + reg [7:0] tx_byte; + begin + new_char = 1'b0; + new_line = 1'b0; + // Wait for start bit + while (uart_stx == 1'b1) + @(uart_stx); + + #(UART_TX_WAIT + (UART_TX_WAIT/2)); + + for ( i = 0; i < 8 ; i = i + 1 ) begin + tx_byte[i] = uart_stx; + #UART_TX_WAIT; + end + + //Check for stop bit + if (uart_stx == 1'b0) begin + //$display("* WARNING: user stop bit not received when expected at time %d__", $time); + // Wait for return to idle + while (uart_stx == 1'b0) + @(uart_stx); + //$display("* USER UART returned to idle at time %d",$time); + end + // display the char + if ( uart_echo ) + $write("%c", tx_byte); + if ( flush_line ) begin + line = ""; + flush_line = 1'b0; + end + if ( tx_byte == "\n" ) begin + new_line = 1'b1; + flush_line = 1'b1; + end + else begin + line = { line[39*8-1:0], tx_byte}; + new_char = 1'b1; + end + end +endtask +//~UART Monitor +`endif // !UART +//~UART + + +// +// TASKS to communicate with interfaces +// +//MAC_DATA +// +`ifdef ETHERNET +reg [31:0] crc32_result; + +task get_mac; + integer conta; + reg LSB; + begin + conta = 0; + LSB = 1; + @ ( posedge eth_tx_en); + + repeat (16) @ (negedge eth_tx_clk); //8 bytes, preamble (7 bytes) + start of frame (1 byte) + + while ( eth_tx_en == 1'b1 ) begin + @ (negedge eth_tx_clk) begin + if ( LSB == 1'b1 ) + eth_rx_data[conta][3:0] = eth_txd; + else begin + eth_rx_data[conta][7:4] = eth_txd; + conta = conta + 1; + end + LSB = ~LSB; + end + end + end +endtask + +task send_mac; //only able to send up to 1536 bytes with header (14 bytes) and CRC (4 bytes) + input [31:0] length; //ETH_PAYLOAD_MAX_LENGTH 1518 + integer conta; + begin + if ( length <= ETH_PAYLOAD_MAX_LENGTH ) begin + //DEST MAC + eth_tx_data[0] = 8'h55; + eth_tx_data[1] = 8'h47; + eth_tx_data[2] = 8'h34; + eth_tx_data[3] = 8'h22; + eth_tx_data[4] = 8'h88; + eth_tx_data[5] = 8'h92; + + //SOURCE MAC + eth_tx_data[6] = 8'h3D; + eth_tx_data[7] = 8'h4F; + eth_tx_data[8] = 8'h1A; + eth_tx_data[9] = 8'hBE; + eth_tx_data[10] = 8'h68; + eth_tx_data[11] = 8'h72; + + //LEN + eth_tx_data[12] = length[7:4]; + eth_tx_data[13] = length[3:0]; + + //DATA input by task caller + + //PAD + for ( conta = length+14; conta < 60; conta = conta + 1 ) begin + eth_tx_data[conta] = 8'h00; + end + + gencrc32(conta); + + eth_tx_data[conta] = crc32_result[31:24]; + eth_tx_data[conta+1] = crc32_result[23:16]; + eth_tx_data[conta+2] = crc32_result[15:8]; + eth_tx_data[conta+3] = crc32_result[7:0]; + + send_rx_packet( 64'h0055_5555_5555_5555, 4'h7, 8'hD5, 32'h0000_0000, conta+4, 1'b0 ); + end + else + $display("Warning: Ethernet packet is to big to be sent."); + end + +endtask + +task send_rx_packet; + input [(8*8)-1:0] preamble_data; // preamble data to be sent - correct is 64'h0055_5555_5555_5555 + input [3:0] preamble_len; // length of preamble in bytes - max is 4'h8, correct is 4'h7 + input [7:0] sfd_data; // SFD data to be sent - correct is 8'hD5 + input [31:0] start_addr; // start address + input [31:0] len; // length of frame in Bytes (without preamble and SFD) + input plus_drible_nibble; // if length is longer for one nibble + integer rx_cnt; + reg [31:0] eth_tx_data_addr_in; // address for reading from RX memory + reg [7:0] eth_tx_data_data_out; // data for reading from RX memory +begin + @(posedge eth_rx_clk); + eth_rx_dv = 1; + + // set initial rx memory address + eth_tx_data_addr_in = start_addr; + + // send preamble + for (rx_cnt = 0; (rx_cnt < (preamble_len << 1)) && (rx_cnt < 16); rx_cnt = rx_cnt + 1) + begin + eth_rxd = preamble_data[3:0]; + preamble_data = preamble_data >> 4; + @(posedge eth_rx_clk); + end + + // send SFD + for (rx_cnt = 0; rx_cnt < 2; rx_cnt = rx_cnt + 1) + begin + eth_rxd = sfd_data[3:0]; + sfd_data = sfd_data >> 4; + @(posedge eth_rx_clk); + end + + // send packet's addresses, type/length, data and FCS + for (rx_cnt = 0; rx_cnt < len; rx_cnt = rx_cnt + 1) + begin + eth_tx_data_data_out = eth_tx_data[eth_tx_data_addr_in[21:0]]; + eth_rxd = eth_tx_data_data_out[3:0]; + @(posedge eth_rx_clk); + eth_rxd = eth_tx_data_data_out[7:4]; + eth_tx_data_addr_in = eth_tx_data_addr_in + 1; + @(posedge eth_rx_clk); + end + if (plus_drible_nibble) + begin + eth_tx_data_data_out = eth_tx_data[eth_tx_data_addr_in[21:0]]; + eth_rxd = eth_tx_data_data_out[3:0]; + @(posedge eth_rx_clk); + end + + eth_rx_dv = 0; + @(posedge eth_rx_clk); + +end +endtask // send_rx_packet + +//CRC32 +localparam [31:0] CRC32_POLY = 32'h04C11DB7; + +task gencrc32; + input [31:0] crc32_length; + + integer byte, bit; + reg msb; + reg [7:0] current_byte; + reg [31:0] temp; + + begin + crc32_result = 32'hffffffff; + for (byte = 0; byte < crc32_length; byte = byte + 1) begin + current_byte = eth_tx_data[byte]; + for (bit = 0; bit < 8; bit = bit + 1) begin + msb = crc32_result[31]; + crc32_result = crc32_result << 1; + if (msb != current_byte[bit]) begin + crc32_result = crc32_result ^ CRC32_POLY; + crc32_result[0] = 1; + end + end + end + + // Last step is to "mirror" every bit, swap the 4 bytes, and then complement each bit. + // + // Mirror: + for (bit = 0; bit < 32; bit = bit + 1) + temp[31-bit] = crc32_result[bit]; + + // Swap and Complement: + crc32_result = ~{temp[7:0], temp[15:8], temp[23:16], temp[31:24]}; + end +endtask +//~CRC32 + +`endif // !ETHERNET +//~MAC_DATA + +//Generate tx and rx clocks +always begin + #((`ETH_PHY_PERIOD)/2) eth_tx_clk <= ~eth_tx_clk; +end +always begin + #((`ETH_PHY_PERIOD)/2) eth_rx_clk <= ~eth_rx_clk; +end +//~Generate tx and rx clocks + + + +// +// TASK to initialize instantiated FPGA dual and two port memory to 0 +// +task init_fpga_memory; + integer i; + begin +`ifdef OR1200_RFRAM_TWOPORT +`ifdef OR1200_XILINX_RAMB4 + for ( i = 0; i < (1<<8); i = i + 1 ) begin + minsoc_top_0.or1200_top.or1200_cpu.or1200_rf.rf_a.ramb4_s16_s16_0.mem[i] = 16'h0000; + minsoc_top_0.or1200_top.or1200_cpu.or1200_rf.rf_a.ramb4_s16_s16_1.mem[i] = 16'h0000; + minsoc_top_0.or1200_top.or1200_cpu.or1200_rf.rf_b.ramb4_s16_s16_0.mem[i] = 16'h0000; + minsoc_top_0.or1200_top.or1200_cpu.or1200_rf.rf_b.ramb4_s16_s16_1.mem[i] = 16'h0000; + end +`elsif OR1200_XILINX_RAMB16 + for ( i = 0; i < (1<<9); i = i + 1 ) begin + minsoc_top_0.or1200_top.or1200_cpu.or1200_rf.rf_a.ramb16_s36_s36.mem[i] = 32'h0000_0000; + minsoc_top_0.or1200_top.or1200_cpu.or1200_rf.rf_b.ramb16_s36_s36.mem[i] = 32'h0000_0000; + end +`elsif OR1200_ALTERA_LPM +`ifndef OR1200_ALTERA_LPM_XXX + $display("Definition OR1200_ALTERA_LPM in or1200_defines.v does not enable ALTERA memory for neither DUAL nor TWO port RFRAM"); + $display("It uses GENERIC memory instead."); + $display("Add '`define OR1200_ALTERA_LPM_XXX' under '`define OR1200_ALTERA_LPM' on or1200_defines.v to use ALTERA memory."); +`endif +`ifdef OR1200_ALTERA_LPM_XXX + $display("...Using ALTERA memory for TWOPORT RFRAM!"); + for ( i = 0; i < (1<<5); i = i + 1 ) begin + minsoc_top_0.or1200_top.or1200_cpu.or1200_rf.rf_a.altqpram_component.mem[i] = 32'h0000_0000; + minsoc_top_0.or1200_top.or1200_cpu.or1200_rf.rf_b.altqpram_component.mem[i] = 32'h0000_0000; + end +`else + $display("...Using GENERIC memory!"); + for ( i = 0; i < (1<<5); i = i + 1 ) begin + minsoc_top_0.or1200_top.or1200_cpu.or1200_rf.rf_a.mem[i] = 32'h0000_0000; + minsoc_top_0.or1200_top.or1200_cpu.or1200_rf.rf_b.mem[i] = 32'h0000_0000; + end +`endif +`elsif OR1200_XILINX_RAM32X1D + $display("Definition OR1200_XILINX_RAM32X1D in or1200_defines.v does not enable FPGA memory for TWO port RFRAM"); + $display("It uses GENERIC memory instead."); + $display("FPGA memory can be used if you choose OR1200_RFRAM_DUALPORT"); + for ( i = 0; i < (1<<5); i = i + 1 ) begin + minsoc_top_0.or1200_top.or1200_cpu.or1200_rf.rf_a.mem[i] = 32'h0000_0000; + minsoc_top_0.or1200_top.or1200_cpu.or1200_rf.rf_b.mem[i] = 32'h0000_0000; + end +`else + for ( i = 0; i < (1<<5); i = i + 1 ) begin + minsoc_top_0.or1200_top.or1200_cpu.or1200_rf.rf_a.mem[i] = 32'h0000_0000; + minsoc_top_0.or1200_top.or1200_cpu.or1200_rf.rf_b.mem[i] = 32'h0000_0000; + end +`endif +`elsif OR1200_RFRAM_DUALPORT +`ifdef OR1200_XILINX_RAMB4 + for ( i = 0; i < (1<<8); i = i + 1 ) begin + minsoc_top_0.or1200_top.or1200_cpu.or1200_rf.rf_a.ramb4_s16_0.mem[i] = 16'h0000; + minsoc_top_0.or1200_top.or1200_cpu.or1200_rf.rf_a.ramb4_s16_1.mem[i] = 16'h0000; + minsoc_top_0.or1200_top.or1200_cpu.or1200_rf.rf_b.ramb4_s16_0.mem[i] = 16'h0000; + minsoc_top_0.or1200_top.or1200_cpu.or1200_rf.rf_b.ramb4_s16_1.mem[i] = 16'h0000; + end +`elsif OR1200_XILINX_RAMB16 + for ( i = 0; i < (1<<9); i = i + 1 ) begin + minsoc_top_0.or1200_top.or1200_cpu.or1200_rf.rf_a.ramb16_s36_s36.mem[i] = 32'h0000_0000; + minsoc_top_0.or1200_top.or1200_cpu.or1200_rf.rf_b.ramb16_s36_s36.mem[i] = 32'h0000_0000; + end +`elsif OR1200_ALTERA_LPM +`ifndef OR1200_ALTERA_LPM_XXX + $display("Definition OR1200_ALTERA_LPM in or1200_defines.v does not enable ALTERA memory for neither DUAL nor TWO port RFRAM"); + $display("It uses GENERIC memory instead."); + $display("Add '`define OR1200_ALTERA_LPM_XXX' under '`define OR1200_ALTERA_LPM' on or1200_defines.v to use ALTERA memory."); +`endif +`ifdef OR1200_ALTERA_LPM_XXX + $display("...Using ALTERA memory for DUALPORT RFRAM!"); + for ( i = 0; i < (1<<5); i = i + 1 ) begin + minsoc_top_0.or1200_top.or1200_cpu.or1200_rf.rf_a.altqpram_component.mem[i] = 32'h0000_0000; + minsoc_top_0.or1200_top.or1200_cpu.or1200_rf.rf_b.altqpram_component.mem[i] = 32'h0000_0000; + end +`else + $display("...Using GENERIC memory!"); + for ( i = 0; i < (1<<5); i = i + 1 ) begin + minsoc_top_0.or1200_top.or1200_cpu.or1200_rf.rf_a.mem[i] = 32'h0000_0000; + minsoc_top_0.or1200_top.or1200_cpu.or1200_rf.rf_b.mem[i] = 32'h0000_0000; + end +`endif +`elsif OR1200_XILINX_RAM32X1D +`ifdef OR1200_USE_RAM16X1D_FOR_RAM32X1D + for ( i = 0; i < (1<<4); i = i + 1 ) begin + minsoc_top_0.or1200_top.or1200_cpu.or1200_rf.rf_a.xcv_ram32x8d_0.ram32x1d_0_0.mem[i] = 1'b0; + minsoc_top_0.or1200_top.or1200_cpu.or1200_rf.rf_a.xcv_ram32x8d_0.ram32x1d_0_1.mem[i] = 1'b0; + minsoc_top_0.or1200_top.or1200_cpu.or1200_rf.rf_a.xcv_ram32x8d_0.ram32x1d_0_2.mem[i] = 1'b0; + minsoc_top_0.or1200_top.or1200_cpu.or1200_rf.rf_a.xcv_ram32x8d_0.ram32x1d_0_3.mem[i] = 1'b0; + minsoc_top_0.or1200_top.or1200_cpu.or1200_rf.rf_a.xcv_ram32x8d_0.ram32x1d_0_4.mem[i] = 1'b0; + minsoc_top_0.or1200_top.or1200_cpu.or1200_rf.rf_a.xcv_ram32x8d_0.ram32x1d_0_5.mem[i] = 1'b0; + minsoc_top_0.or1200_top.or1200_cpu.or1200_rf.rf_a.xcv_ram32x8d_0.ram32x1d_0_6.mem[i] = 1'b0; + minsoc_top_0.or1200_top.or1200_cpu.or1200_rf.rf_a.xcv_ram32x8d_0.ram32x1d_0_7.mem[i] = 1'b0; + minsoc_top_0.or1200_top.or1200_cpu.or1200_rf.rf_a.xcv_ram32x8d_0.ram32x1d_1_0.mem[i] = 1'b0; + minsoc_top_0.or1200_top.or1200_cpu.or1200_rf.rf_a.xcv_ram32x8d_0.ram32x1d_1_1.mem[i] = 1'b0; + minsoc_top_0.or1200_top.or1200_cpu.or1200_rf.rf_a.xcv_ram32x8d_0.ram32x1d_1_2.mem[i] = 1'b0; + minsoc_top_0.or1200_top.or1200_cpu.or1200_rf.rf_a.xcv_ram32x8d_0.ram32x1d_1_3.mem[i] = 1'b0; + minsoc_top_0.or1200_top.or1200_cpu.or1200_rf.rf_a.xcv_ram32x8d_0.ram32x1d_1_4.mem[i] = 1'b0; + minsoc_top_0.or1200_top.or1200_cpu.or1200_rf.rf_a.xcv_ram32x8d_0.ram32x1d_1_5.mem[i] = 1'b0; + minsoc_top_0.or1200_top.or1200_cpu.or1200_rf.rf_a.xcv_ram32x8d_0.ram32x1d_1_6.mem[i] = 1'b0; + minsoc_top_0.or1200_top.or1200_cpu.or1200_rf.rf_a.xcv_ram32x8d_0.ram32x1d_1_7.mem[i] = 1'b0; + + minsoc_top_0.or1200_top.or1200_cpu.or1200_rf.rf_a.xcv_ram32x8d_1.ram32x1d_0_0.mem[i] = 1'b0; + minsoc_top_0.or1200_top.or1200_cpu.or1200_rf.rf_a.xcv_ram32x8d_1.ram32x1d_0_1.mem[i] = 1'b0; + minsoc_top_0.or1200_top.or1200_cpu.or1200_rf.rf_a.xcv_ram32x8d_1.ram32x1d_0_2.mem[i] = 1'b0; + minsoc_top_0.or1200_top.or1200_cpu.or1200_rf.rf_a.xcv_ram32x8d_1.ram32x1d_0_3.mem[i] = 1'b0; + minsoc_top_0.or1200_top.or1200_cpu.or1200_rf.rf_a.xcv_ram32x8d_1.ram32x1d_0_4.mem[i] = 1'b0; + minsoc_top_0.or1200_top.or1200_cpu.or1200_rf.rf_a.xcv_ram32x8d_1.ram32x1d_0_5.mem[i] = 1'b0; + minsoc_top_0.or1200_top.or1200_cpu.or1200_rf.rf_a.xcv_ram32x8d_1.ram32x1d_0_6.mem[i] = 1'b0; + minsoc_top_0.or1200_top.or1200_cpu.or1200_rf.rf_a.xcv_ram32x8d_1.ram32x1d_0_7.mem[i] = 1'b0; + minsoc_top_0.or1200_top.or1200_cpu.or1200_rf.rf_a.xcv_ram32x8d_1.ram32x1d_1_0.mem[i] = 1'b0; + minsoc_top_0.or1200_top.or1200_cpu.or1200_rf.rf_a.xcv_ram32x8d_1.ram32x1d_1_1.mem[i] = 1'b0; + minsoc_top_0.or1200_top.or1200_cpu.or1200_rf.rf_a.xcv_ram32x8d_1.ram32x1d_1_2.mem[i] = 1'b0; + minsoc_top_0.or1200_top.or1200_cpu.or1200_rf.rf_a.xcv_ram32x8d_1.ram32x1d_1_3.mem[i] = 1'b0; + minsoc_top_0.or1200_top.or1200_cpu.or1200_rf.rf_a.xcv_ram32x8d_1.ram32x1d_1_4.mem[i] = 1'b0; + minsoc_top_0.or1200_top.or1200_cpu.or1200_rf.rf_a.xcv_ram32x8d_1.ram32x1d_1_5.mem[i] = 1'b0; + minsoc_top_0.or1200_top.or1200_cpu.or1200_rf.rf_a.xcv_ram32x8d_1.ram32x1d_1_6.mem[i] = 1'b0; + minsoc_top_0.or1200_top.or1200_cpu.or1200_rf.rf_a.xcv_ram32x8d_1.ram32x1d_1_7.mem[i] = 1'b0; + + minsoc_top_0.or1200_top.or1200_cpu.or1200_rf.rf_a.xcv_ram32x8d_2.ram32x1d_0_0.mem[i] = 1'b0; + minsoc_top_0.or1200_top.or1200_cpu.or1200_rf.rf_a.xcv_ram32x8d_2.ram32x1d_0_1.mem[i] = 1'b0; + minsoc_top_0.or1200_top.or1200_cpu.or1200_rf.rf_a.xcv_ram32x8d_2.ram32x1d_0_2.mem[i] = 1'b0; + minsoc_top_0.or1200_top.or1200_cpu.or1200_rf.rf_a.xcv_ram32x8d_2.ram32x1d_0_3.mem[i] = 1'b0; + minsoc_top_0.or1200_top.or1200_cpu.or1200_rf.rf_a.xcv_ram32x8d_2.ram32x1d_0_4.mem[i] = 1'b0; + minsoc_top_0.or1200_top.or1200_cpu.or1200_rf.rf_a.xcv_ram32x8d_2.ram32x1d_0_5.mem[i] = 1'b0; + minsoc_top_0.or1200_top.or1200_cpu.or1200_rf.rf_a.xcv_ram32x8d_2.ram32x1d_0_6.mem[i] = 1'b0; + minsoc_top_0.or1200_top.or1200_cpu.or1200_rf.rf_a.xcv_ram32x8d_2.ram32x1d_0_7.mem[i] = 1'b0; + minsoc_top_0.or1200_top.or1200_cpu.or1200_rf.rf_a.xcv_ram32x8d_2.ram32x1d_1_0.mem[i] = 1'b0; + minsoc_top_0.or1200_top.or1200_cpu.or1200_rf.rf_a.xcv_ram32x8d_2.ram32x1d_1_1.mem[i] = 1'b0; + minsoc_top_0.or1200_top.or1200_cpu.or1200_rf.rf_a.xcv_ram32x8d_2.ram32x1d_1_2.mem[i] = 1'b0; + minsoc_top_0.or1200_top.or1200_cpu.or1200_rf.rf_a.xcv_ram32x8d_2.ram32x1d_1_3.mem[i] = 1'b0; + minsoc_top_0.or1200_top.or1200_cpu.or1200_rf.rf_a.xcv_ram32x8d_2.ram32x1d_1_4.mem[i] = 1'b0; + minsoc_top_0.or1200_top.or1200_cpu.or1200_rf.rf_a.xcv_ram32x8d_2.ram32x1d_1_5.mem[i] = 1'b0; + minsoc_top_0.or1200_top.or1200_cpu.or1200_rf.rf_a.xcv_ram32x8d_2.ram32x1d_1_6.mem[i] = 1'b0; + minsoc_top_0.or1200_top.or1200_cpu.or1200_rf.rf_a.xcv_ram32x8d_2.ram32x1d_1_7.mem[i] = 1'b0; + + minsoc_top_0.or1200_top.or1200_cpu.or1200_rf.rf_a.xcv_ram32x8d_3.ram32x1d_0_0.mem[i] = 1'b0; + minsoc_top_0.or1200_top.or1200_cpu.or1200_rf.rf_a.xcv_ram32x8d_3.ram32x1d_0_1.mem[i] = 1'b0; + minsoc_top_0.or1200_top.or1200_cpu.or1200_rf.rf_a.xcv_ram32x8d_3.ram32x1d_0_2.mem[i] = 1'b0; + minsoc_top_0.or1200_top.or1200_cpu.or1200_rf.rf_a.xcv_ram32x8d_3.ram32x1d_0_3.mem[i] = 1'b0; + minsoc_top_0.or1200_top.or1200_cpu.or1200_rf.rf_a.xcv_ram32x8d_3.ram32x1d_0_4.mem[i] = 1'b0; + minsoc_top_0.or1200_top.or1200_cpu.or1200_rf.rf_a.xcv_ram32x8d_3.ram32x1d_0_5.mem[i] = 1'b0; + minsoc_top_0.or1200_top.or1200_cpu.or1200_rf.rf_a.xcv_ram32x8d_3.ram32x1d_0_6.mem[i] = 1'b0; + minsoc_top_0.or1200_top.or1200_cpu.or1200_rf.rf_a.xcv_ram32x8d_3.ram32x1d_0_7.mem[i] = 1'b0; + minsoc_top_0.or1200_top.or1200_cpu.or1200_rf.rf_a.xcv_ram32x8d_3.ram32x1d_1_0.mem[i] = 1'b0; + minsoc_top_0.or1200_top.or1200_cpu.or1200_rf.rf_a.xcv_ram32x8d_3.ram32x1d_1_1.mem[i] = 1'b0; + minsoc_top_0.or1200_top.or1200_cpu.or1200_rf.rf_a.xcv_ram32x8d_3.ram32x1d_1_2.mem[i] = 1'b0; + minsoc_top_0.or1200_top.or1200_cpu.or1200_rf.rf_a.xcv_ram32x8d_3.ram32x1d_1_3.mem[i] = 1'b0; + minsoc_top_0.or1200_top.or1200_cpu.or1200_rf.rf_a.xcv_ram32x8d_3.ram32x1d_1_4.mem[i] = 1'b0; + minsoc_top_0.or1200_top.or1200_cpu.or1200_rf.rf_a.xcv_ram32x8d_3.ram32x1d_1_5.mem[i] = 1'b0; + minsoc_top_0.or1200_top.or1200_cpu.or1200_rf.rf_a.xcv_ram32x8d_3.ram32x1d_1_6.mem[i] = 1'b0; + minsoc_top_0.or1200_top.or1200_cpu.or1200_rf.rf_a.xcv_ram32x8d_3.ram32x1d_1_7.mem[i] = 1'b0; + + minsoc_top_0.or1200_top.or1200_cpu.or1200_rf.rf_b.xcv_ram32x8d_0.ram32x1d_0_0.mem[i] = 1'b0; + minsoc_top_0.or1200_top.or1200_cpu.or1200_rf.rf_b.xcv_ram32x8d_0.ram32x1d_0_1.mem[i] = 1'b0; + minsoc_top_0.or1200_top.or1200_cpu.or1200_rf.rf_b.xcv_ram32x8d_0.ram32x1d_0_2.mem[i] = 1'b0; + minsoc_top_0.or1200_top.or1200_cpu.or1200_rf.rf_b.xcv_ram32x8d_0.ram32x1d_0_3.mem[i] = 1'b0; + minsoc_top_0.or1200_top.or1200_cpu.or1200_rf.rf_b.xcv_ram32x8d_0.ram32x1d_0_4.mem[i] = 1'b0; + minsoc_top_0.or1200_top.or1200_cpu.or1200_rf.rf_b.xcv_ram32x8d_0.ram32x1d_0_5.mem[i] = 1'b0; + minsoc_top_0.or1200_top.or1200_cpu.or1200_rf.rf_b.xcv_ram32x8d_0.ram32x1d_0_6.mem[i] = 1'b0; + minsoc_top_0.or1200_top.or1200_cpu.or1200_rf.rf_b.xcv_ram32x8d_0.ram32x1d_0_7.mem[i] = 1'b0; + minsoc_top_0.or1200_top.or1200_cpu.or1200_rf.rf_b.xcv_ram32x8d_0.ram32x1d_1_0.mem[i] = 1'b0; + minsoc_top_0.or1200_top.or1200_cpu.or1200_rf.rf_b.xcv_ram32x8d_0.ram32x1d_1_1.mem[i] = 1'b0; + minsoc_top_0.or1200_top.or1200_cpu.or1200_rf.rf_b.xcv_ram32x8d_0.ram32x1d_1_2.mem[i] = 1'b0; + minsoc_top_0.or1200_top.or1200_cpu.or1200_rf.rf_b.xcv_ram32x8d_0.ram32x1d_1_3.mem[i] = 1'b0; + minsoc_top_0.or1200_top.or1200_cpu.or1200_rf.rf_b.xcv_ram32x8d_0.ram32x1d_1_4.mem[i] = 1'b0; + minsoc_top_0.or1200_top.or1200_cpu.or1200_rf.rf_b.xcv_ram32x8d_0.ram32x1d_1_5.mem[i] = 1'b0; + minsoc_top_0.or1200_top.or1200_cpu.or1200_rf.rf_b.xcv_ram32x8d_0.ram32x1d_1_6.mem[i] = 1'b0; + minsoc_top_0.or1200_top.or1200_cpu.or1200_rf.rf_b.xcv_ram32x8d_0.ram32x1d_1_7.mem[i] = 1'b0; + + minsoc_top_0.or1200_top.or1200_cpu.or1200_rf.rf_b.xcv_ram32x8d_1.ram32x1d_0_0.mem[i] = 1'b0; + minsoc_top_0.or1200_top.or1200_cpu.or1200_rf.rf_b.xcv_ram32x8d_1.ram32x1d_0_1.mem[i] = 1'b0; + minsoc_top_0.or1200_top.or1200_cpu.or1200_rf.rf_b.xcv_ram32x8d_1.ram32x1d_0_2.mem[i] = 1'b0; + minsoc_top_0.or1200_top.or1200_cpu.or1200_rf.rf_b.xcv_ram32x8d_1.ram32x1d_0_3.mem[i] = 1'b0; + minsoc_top_0.or1200_top.or1200_cpu.or1200_rf.rf_b.xcv_ram32x8d_1.ram32x1d_0_4.mem[i] = 1'b0; + minsoc_top_0.or1200_top.or1200_cpu.or1200_rf.rf_b.xcv_ram32x8d_1.ram32x1d_0_5.mem[i] = 1'b0; + minsoc_top_0.or1200_top.or1200_cpu.or1200_rf.rf_b.xcv_ram32x8d_1.ram32x1d_0_6.mem[i] = 1'b0; + minsoc_top_0.or1200_top.or1200_cpu.or1200_rf.rf_b.xcv_ram32x8d_1.ram32x1d_0_7.mem[i] = 1'b0; + minsoc_top_0.or1200_top.or1200_cpu.or1200_rf.rf_b.xcv_ram32x8d_1.ram32x1d_1_0.mem[i] = 1'b0; + minsoc_top_0.or1200_top.or1200_cpu.or1200_rf.rf_b.xcv_ram32x8d_1.ram32x1d_1_1.mem[i] = 1'b0; + minsoc_top_0.or1200_top.or1200_cpu.or1200_rf.rf_b.xcv_ram32x8d_1.ram32x1d_1_2.mem[i] = 1'b0; + minsoc_top_0.or1200_top.or1200_cpu.or1200_rf.rf_b.xcv_ram32x8d_1.ram32x1d_1_3.mem[i] = 1'b0; + minsoc_top_0.or1200_top.or1200_cpu.or1200_rf.rf_b.xcv_ram32x8d_1.ram32x1d_1_4.mem[i] = 1'b0; + minsoc_top_0.or1200_top.or1200_cpu.or1200_rf.rf_b.xcv_ram32x8d_1.ram32x1d_1_5.mem[i] = 1'b0; + minsoc_top_0.or1200_top.or1200_cpu.or1200_rf.rf_b.xcv_ram32x8d_1.ram32x1d_1_6.mem[i] = 1'b0; + minsoc_top_0.or1200_top.or1200_cpu.or1200_rf.rf_b.xcv_ram32x8d_1.ram32x1d_1_7.mem[i] = 1'b0; + + minsoc_top_0.or1200_top.or1200_cpu.or1200_rf.rf_b.xcv_ram32x8d_2.ram32x1d_0_0.mem[i] = 1'b0; + minsoc_top_0.or1200_top.or1200_cpu.or1200_rf.rf_b.xcv_ram32x8d_2.ram32x1d_0_1.mem[i] = 1'b0; + minsoc_top_0.or1200_top.or1200_cpu.or1200_rf.rf_b.xcv_ram32x8d_2.ram32x1d_0_2.mem[i] = 1'b0; + minsoc_top_0.or1200_top.or1200_cpu.or1200_rf.rf_b.xcv_ram32x8d_2.ram32x1d_0_3.mem[i] = 1'b0; + minsoc_top_0.or1200_top.or1200_cpu.or1200_rf.rf_b.xcv_ram32x8d_2.ram32x1d_0_4.mem[i] = 1'b0; + minsoc_top_0.or1200_top.or1200_cpu.or1200_rf.rf_b.xcv_ram32x8d_2.ram32x1d_0_5.mem[i] = 1'b0; + minsoc_top_0.or1200_top.or1200_cpu.or1200_rf.rf_b.xcv_ram32x8d_2.ram32x1d_0_6.mem[i] = 1'b0; + minsoc_top_0.or1200_top.or1200_cpu.or1200_rf.rf_b.xcv_ram32x8d_2.ram32x1d_0_7.mem[i] = 1'b0; + minsoc_top_0.or1200_top.or1200_cpu.or1200_rf.rf_b.xcv_ram32x8d_2.ram32x1d_1_0.mem[i] = 1'b0; + minsoc_top_0.or1200_top.or1200_cpu.or1200_rf.rf_b.xcv_ram32x8d_2.ram32x1d_1_1.mem[i] = 1'b0; + minsoc_top_0.or1200_top.or1200_cpu.or1200_rf.rf_b.xcv_ram32x8d_2.ram32x1d_1_2.mem[i] = 1'b0; + minsoc_top_0.or1200_top.or1200_cpu.or1200_rf.rf_b.xcv_ram32x8d_2.ram32x1d_1_3.mem[i] = 1'b0; + minsoc_top_0.or1200_top.or1200_cpu.or1200_rf.rf_b.xcv_ram32x8d_2.ram32x1d_1_4.mem[i] = 1'b0; + minsoc_top_0.or1200_top.or1200_cpu.or1200_rf.rf_b.xcv_ram32x8d_2.ram32x1d_1_5.mem[i] = 1'b0; + minsoc_top_0.or1200_top.or1200_cpu.or1200_rf.rf_b.xcv_ram32x8d_2.ram32x1d_1_6.mem[i] = 1'b0; + minsoc_top_0.or1200_top.or1200_cpu.or1200_rf.rf_b.xcv_ram32x8d_2.ram32x1d_1_7.mem[i] = 1'b0; + + minsoc_top_0.or1200_top.or1200_cpu.or1200_rf.rf_b.xcv_ram32x8d_3.ram32x1d_0_0.mem[i] = 1'b0; + minsoc_top_0.or1200_top.or1200_cpu.or1200_rf.rf_b.xcv_ram32x8d_3.ram32x1d_0_1.mem[i] = 1'b0; + minsoc_top_0.or1200_top.or1200_cpu.or1200_rf.rf_b.xcv_ram32x8d_3.ram32x1d_0_2.mem[i] = 1'b0; + minsoc_top_0.or1200_top.or1200_cpu.or1200_rf.rf_b.xcv_ram32x8d_3.ram32x1d_0_3.mem[i] = 1'b0; + minsoc_top_0.or1200_top.or1200_cpu.or1200_rf.rf_b.xcv_ram32x8d_3.ram32x1d_0_4.mem[i] = 1'b0; + minsoc_top_0.or1200_top.or1200_cpu.or1200_rf.rf_b.xcv_ram32x8d_3.ram32x1d_0_5.mem[i] = 1'b0; + minsoc_top_0.or1200_top.or1200_cpu.or1200_rf.rf_b.xcv_ram32x8d_3.ram32x1d_0_6.mem[i] = 1'b0; + minsoc_top_0.or1200_top.or1200_cpu.or1200_rf.rf_b.xcv_ram32x8d_3.ram32x1d_0_7.mem[i] = 1'b0; + minsoc_top_0.or1200_top.or1200_cpu.or1200_rf.rf_b.xcv_ram32x8d_3.ram32x1d_1_0.mem[i] = 1'b0; + minsoc_top_0.or1200_top.or1200_cpu.or1200_rf.rf_b.xcv_ram32x8d_3.ram32x1d_1_1.mem[i] = 1'b0; + minsoc_top_0.or1200_top.or1200_cpu.or1200_rf.rf_b.xcv_ram32x8d_3.ram32x1d_1_2.mem[i] = 1'b0; + minsoc_top_0.or1200_top.or1200_cpu.or1200_rf.rf_b.xcv_ram32x8d_3.ram32x1d_1_3.mem[i] = 1'b0; + minsoc_top_0.or1200_top.or1200_cpu.or1200_rf.rf_b.xcv_ram32x8d_3.ram32x1d_1_4.mem[i] = 1'b0; + minsoc_top_0.or1200_top.or1200_cpu.or1200_rf.rf_b.xcv_ram32x8d_3.ram32x1d_1_5.mem[i] = 1'b0; + minsoc_top_0.or1200_top.or1200_cpu.or1200_rf.rf_b.xcv_ram32x8d_3.ram32x1d_1_6.mem[i] = 1'b0; + minsoc_top_0.or1200_top.or1200_cpu.or1200_rf.rf_b.xcv_ram32x8d_3.ram32x1d_1_7.mem[i] = 1'b0; + end +`else + for ( i = 0; i < (1<<4); i = i + 1 ) begin + minsoc_top_0.or1200_top.or1200_cpu.or1200_rf.rf_a.xcv_ram32x8d_0.ram32x1d_0.mem[i] = 1'b0; + minsoc_top_0.or1200_top.or1200_cpu.or1200_rf.rf_a.xcv_ram32x8d_0.ram32x1d_1.mem[i] = 1'b0; + minsoc_top_0.or1200_top.or1200_cpu.or1200_rf.rf_a.xcv_ram32x8d_0.ram32x1d_2.mem[i] = 1'b0; + minsoc_top_0.or1200_top.or1200_cpu.or1200_rf.rf_a.xcv_ram32x8d_0.ram32x1d_3.mem[i] = 1'b0; + minsoc_top_0.or1200_top.or1200_cpu.or1200_rf.rf_a.xcv_ram32x8d_0.ram32x1d_4.mem[i] = 1'b0; + minsoc_top_0.or1200_top.or1200_cpu.or1200_rf.rf_a.xcv_ram32x8d_0.ram32x1d_5.mem[i] = 1'b0; + minsoc_top_0.or1200_top.or1200_cpu.or1200_rf.rf_a.xcv_ram32x8d_0.ram32x1d_6.mem[i] = 1'b0; + minsoc_top_0.or1200_top.or1200_cpu.or1200_rf.rf_a.xcv_ram32x8d_0.ram32x1d_7.mem[i] = 1'b0; + + minsoc_top_0.or1200_top.or1200_cpu.or1200_rf.rf_a.xcv_ram32x8d_1.ram32x1d_0.mem[i] = 1'b0; + minsoc_top_0.or1200_top.or1200_cpu.or1200_rf.rf_a.xcv_ram32x8d_1.ram32x1d_1.mem[i] = 1'b0; + minsoc_top_0.or1200_top.or1200_cpu.or1200_rf.rf_a.xcv_ram32x8d_1.ram32x1d_2.mem[i] = 1'b0; + minsoc_top_0.or1200_top.or1200_cpu.or1200_rf.rf_a.xcv_ram32x8d_1.ram32x1d_3.mem[i] = 1'b0; + minsoc_top_0.or1200_top.or1200_cpu.or1200_rf.rf_a.xcv_ram32x8d_1.ram32x1d_4.mem[i] = 1'b0; + minsoc_top_0.or1200_top.or1200_cpu.or1200_rf.rf_a.xcv_ram32x8d_1.ram32x1d_5.mem[i] = 1'b0; + minsoc_top_0.or1200_top.or1200_cpu.or1200_rf.rf_a.xcv_ram32x8d_1.ram32x1d_6.mem[i] = 1'b0; + minsoc_top_0.or1200_top.or1200_cpu.or1200_rf.rf_a.xcv_ram32x8d_1.ram32x1d_7.mem[i] = 1'b0; + + minsoc_top_0.or1200_top.or1200_cpu.or1200_rf.rf_a.xcv_ram32x8d_2.ram32x1d_0.mem[i] = 1'b0; + minsoc_top_0.or1200_top.or1200_cpu.or1200_rf.rf_a.xcv_ram32x8d_2.ram32x1d_1.mem[i] = 1'b0; + minsoc_top_0.or1200_top.or1200_cpu.or1200_rf.rf_a.xcv_ram32x8d_2.ram32x1d_2.mem[i] = 1'b0; + minsoc_top_0.or1200_top.or1200_cpu.or1200_rf.rf_a.xcv_ram32x8d_2.ram32x1d_3.mem[i] = 1'b0; + minsoc_top_0.or1200_top.or1200_cpu.or1200_rf.rf_a.xcv_ram32x8d_2.ram32x1d_4.mem[i] = 1'b0; + minsoc_top_0.or1200_top.or1200_cpu.or1200_rf.rf_a.xcv_ram32x8d_2.ram32x1d_5.mem[i] = 1'b0; + minsoc_top_0.or1200_top.or1200_cpu.or1200_rf.rf_a.xcv_ram32x8d_2.ram32x1d_6.mem[i] = 1'b0; + minsoc_top_0.or1200_top.or1200_cpu.or1200_rf.rf_a.xcv_ram32x8d_2.ram32x1d_7.mem[i] = 1'b0; + + minsoc_top_0.or1200_top.or1200_cpu.or1200_rf.rf_a.xcv_ram32x8d_3.ram32x1d_0.mem[i] = 1'b0; + minsoc_top_0.or1200_top.or1200_cpu.or1200_rf.rf_a.xcv_ram32x8d_3.ram32x1d_1.mem[i] = 1'b0; + minsoc_top_0.or1200_top.or1200_cpu.or1200_rf.rf_a.xcv_ram32x8d_3.ram32x1d_2.mem[i] = 1'b0; + minsoc_top_0.or1200_top.or1200_cpu.or1200_rf.rf_a.xcv_ram32x8d_3.ram32x1d_3.mem[i] = 1'b0; + minsoc_top_0.or1200_top.or1200_cpu.or1200_rf.rf_a.xcv_ram32x8d_3.ram32x1d_4.mem[i] = 1'b0; + minsoc_top_0.or1200_top.or1200_cpu.or1200_rf.rf_a.xcv_ram32x8d_3.ram32x1d_5.mem[i] = 1'b0; + minsoc_top_0.or1200_top.or1200_cpu.or1200_rf.rf_a.xcv_ram32x8d_3.ram32x1d_6.mem[i] = 1'b0; + minsoc_top_0.or1200_top.or1200_cpu.or1200_rf.rf_a.xcv_ram32x8d_3.ram32x1d_7.mem[i] = 1'b0; + + minsoc_top_0.or1200_top.or1200_cpu.or1200_rf.rf_b.xcv_ram32x8d_0.ram32x1d_0.mem[i] = 1'b0; + minsoc_top_0.or1200_top.or1200_cpu.or1200_rf.rf_b.xcv_ram32x8d_0.ram32x1d_1.mem[i] = 1'b0; + minsoc_top_0.or1200_top.or1200_cpu.or1200_rf.rf_b.xcv_ram32x8d_0.ram32x1d_2.mem[i] = 1'b0; + minsoc_top_0.or1200_top.or1200_cpu.or1200_rf.rf_b.xcv_ram32x8d_0.ram32x1d_3.mem[i] = 1'b0; + minsoc_top_0.or1200_top.or1200_cpu.or1200_rf.rf_b.xcv_ram32x8d_0.ram32x1d_4.mem[i] = 1'b0; + minsoc_top_0.or1200_top.or1200_cpu.or1200_rf.rf_b.xcv_ram32x8d_0.ram32x1d_5.mem[i] = 1'b0; + minsoc_top_0.or1200_top.or1200_cpu.or1200_rf.rf_b.xcv_ram32x8d_0.ram32x1d_6.mem[i] = 1'b0; + minsoc_top_0.or1200_top.or1200_cpu.or1200_rf.rf_b.xcv_ram32x8d_0.ram32x1d_7.mem[i] = 1'b0; + + minsoc_top_0.or1200_top.or1200_cpu.or1200_rf.rf_b.xcv_ram32x8d_1.ram32x1d_0.mem[i] = 1'b0; + minsoc_top_0.or1200_top.or1200_cpu.or1200_rf.rf_b.xcv_ram32x8d_1.ram32x1d_1.mem[i] = 1'b0; + minsoc_top_0.or1200_top.or1200_cpu.or1200_rf.rf_b.xcv_ram32x8d_1.ram32x1d_2.mem[i] = 1'b0; + minsoc_top_0.or1200_top.or1200_cpu.or1200_rf.rf_b.xcv_ram32x8d_1.ram32x1d_3.mem[i] = 1'b0; + minsoc_top_0.or1200_top.or1200_cpu.or1200_rf.rf_b.xcv_ram32x8d_1.ram32x1d_4.mem[i] = 1'b0; + minsoc_top_0.or1200_top.or1200_cpu.or1200_rf.rf_b.xcv_ram32x8d_1.ram32x1d_5.mem[i] = 1'b0; + minsoc_top_0.or1200_top.or1200_cpu.or1200_rf.rf_b.xcv_ram32x8d_1.ram32x1d_6.mem[i] = 1'b0; + minsoc_top_0.or1200_top.or1200_cpu.or1200_rf.rf_b.xcv_ram32x8d_1.ram32x1d_7.mem[i] = 1'b0; + + minsoc_top_0.or1200_top.or1200_cpu.or1200_rf.rf_b.xcv_ram32x8d_2.ram32x1d_0.mem[i] = 1'b0; + minsoc_top_0.or1200_top.or1200_cpu.or1200_rf.rf_b.xcv_ram32x8d_2.ram32x1d_1.mem[i] = 1'b0; + minsoc_top_0.or1200_top.or1200_cpu.or1200_rf.rf_b.xcv_ram32x8d_2.ram32x1d_2.mem[i] = 1'b0; + minsoc_top_0.or1200_top.or1200_cpu.or1200_rf.rf_b.xcv_ram32x8d_2.ram32x1d_3.mem[i] = 1'b0; + minsoc_top_0.or1200_top.or1200_cpu.or1200_rf.rf_b.xcv_ram32x8d_2.ram32x1d_4.mem[i] = 1'b0; + minsoc_top_0.or1200_top.or1200_cpu.or1200_rf.rf_b.xcv_ram32x8d_2.ram32x1d_5.mem[i] = 1'b0; + minsoc_top_0.or1200_top.or1200_cpu.or1200_rf.rf_b.xcv_ram32x8d_2.ram32x1d_6.mem[i] = 1'b0; + minsoc_top_0.or1200_top.or1200_cpu.or1200_rf.rf_b.xcv_ram32x8d_2.ram32x1d_7.mem[i] = 1'b0; + + minsoc_top_0.or1200_top.or1200_cpu.or1200_rf.rf_b.xcv_ram32x8d_3.ram32x1d_0.mem[i] = 1'b0; + minsoc_top_0.or1200_top.or1200_cpu.or1200_rf.rf_b.xcv_ram32x8d_3.ram32x1d_1.mem[i] = 1'b0; + minsoc_top_0.or1200_top.or1200_cpu.or1200_rf.rf_b.xcv_ram32x8d_3.ram32x1d_2.mem[i] = 1'b0; + minsoc_top_0.or1200_top.or1200_cpu.or1200_rf.rf_b.xcv_ram32x8d_3.ram32x1d_3.mem[i] = 1'b0; + minsoc_top_0.or1200_top.or1200_cpu.or1200_rf.rf_b.xcv_ram32x8d_3.ram32x1d_4.mem[i] = 1'b0; + minsoc_top_0.or1200_top.or1200_cpu.or1200_rf.rf_b.xcv_ram32x8d_3.ram32x1d_5.mem[i] = 1'b0; + minsoc_top_0.or1200_top.or1200_cpu.or1200_rf.rf_b.xcv_ram32x8d_3.ram32x1d_6.mem[i] = 1'b0; + minsoc_top_0.or1200_top.or1200_cpu.or1200_rf.rf_b.xcv_ram32x8d_3.ram32x1d_7.mem[i] = 1'b0; + end +`endif +`else + for ( i = 0; i < (1<<5); i = i + 1 ) begin + minsoc_top_0.or1200_top.or1200_cpu.or1200_rf.rf_a.mem[i] = 32'h0000_0000; + minsoc_top_0.or1200_top.or1200_cpu.or1200_rf.rf_b.mem[i] = 32'h0000_0000; + end +`endif +`endif + end +endtask + +endmodule + Index: release-1.0/bench/verilog/minsoc_memory_model.v =================================================================== --- release-1.0/bench/verilog/minsoc_memory_model.v (nonexistent) +++ release-1.0/bench/verilog/minsoc_memory_model.v (revision 151) @@ -0,0 +1,188 @@ +////////////////////////////////////////////////////////////////////// +//// //// +//// Wishbone Single-Port Synchronous RAM //// +//// Memory Model //// +//// //// +//// This file is part of memory library available from //// +//// http://www.opencores.org/cvsweb.shtml/minsoc/ //// +//// //// +//// Description //// +//// This Wishbone controller connects to the wrapper of //// +//// the single-port synchronous memory interface. //// +//// Besides universal memory due to onchip_ram it provides a //// +//// generic way to set the depth of the memory. //// +//// //// +//// To Do: //// +//// //// +//// Author(s): //// +//// - Raul Fajardo, rfajardo@gmail.com //// +//// //// +////////////////////////////////////////////////////////////////////// +//// //// +//// Copyright (C) 2000 Authors and OPENCORES.ORG //// +//// //// +//// This source file may be used and distributed without //// +//// restriction provided that this copyright statement is not //// +//// removed from the file and that any derivative work contains //// +//// the original copyright notice and the associated disclaimer. //// +//// //// +//// This source file is free software; you can redistribute it //// +//// and/or modify it under the terms of the GNU Lesser General //// +//// Public License as published by the Free Software Foundation; //// +//// either version 2.1 of the License, or (at your option) any //// +//// later version. //// +//// //// +//// This source is distributed in the hope that it will be //// +//// useful, but WITHOUT ANY WARRANTY; without even the implied //// +//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR //// +//// PURPOSE. See the GNU Lesser General Public License for more //// +//// details. //// +//// //// +//// You should have received a copy of the GNU Lesser General //// +//// Public License along with this source; if not, download it //// +//// from http://www.gnu.org/licenses/lgpl.html //// +//// //// +////////////////////////////////////////////////////////////////////// +// +// Revision History +// +// +// Revision 1.0 2009/08/18 15:15:00 fajardo +// Created interface and tested +// + +`include "timescale.v" + +module minsoc_memory_model ( + wb_clk_i, wb_rst_i, + + wb_dat_i, wb_dat_o, wb_adr_i, wb_sel_i, wb_we_i, wb_cyc_i, + wb_stb_i, wb_ack_o, wb_err_o +); + +// +// Parameters +// +parameter adr_width = 2; + +// +// I/O Ports +// +input wb_clk_i; +input wb_rst_i; + +// +// WB slave i/f +// +input [31:0] wb_dat_i; +output [31:0] wb_dat_o; +input [31:0] wb_adr_i; +input [3:0] wb_sel_i; +input wb_we_i; +input wb_cyc_i; +input wb_stb_i; +output wb_ack_o; +output wb_err_o; + +// +// Internal regs and wires +// +wire we; +wire [3:0] be_i; +wire [31:0] wb_dat_o; +reg ack_we; +reg ack_re; +// +// Aliases and simple assignments +// +assign wb_ack_o = ack_re | ack_we; +assign wb_err_o = wb_cyc_i & wb_stb_i & (|wb_adr_i[23:adr_width+2]); // If Access to > (8-bit leading prefix ignored) +assign we = wb_cyc_i & wb_stb_i & wb_we_i & (|wb_sel_i[3:0]); +assign be_i = (wb_cyc_i & wb_stb_i) * wb_sel_i; + +// +// Write acknowledge +// +always @ (negedge wb_clk_i or posedge wb_rst_i) +begin +if (wb_rst_i) + ack_we <= 1'b0; + else + if (wb_cyc_i & wb_stb_i & wb_we_i & ~ack_we) + ack_we <= #1 1'b1; + else + ack_we <= #1 1'b0; +end + +// +// read acknowledge +// +always @ (posedge wb_clk_i or posedge wb_rst_i) +begin + if (wb_rst_i) + ack_re <= 1'b0; + else + if (wb_cyc_i & wb_stb_i & ~wb_err_o & ~wb_we_i & ~ack_re) + ack_re <= #1 1'b1; + else + ack_re <= #1 1'b0; +end + + minsoc_onchip_ram # + ( + .aw(adr_width) + ) + block_ram_0 ( + .clk(wb_clk_i), + .rst(wb_rst_i), + .addr(wb_adr_i[adr_width+1:2]), + .di(wb_dat_i[7:0]), + .doq(wb_dat_o[7:0]), + .we(we), + .oe(1'b1), + .ce(be_i[0])); + + minsoc_onchip_ram # + ( + .aw(adr_width) + ) + block_ram_1 ( + .clk(wb_clk_i), + .rst(wb_rst_i), + .addr(wb_adr_i[adr_width+1:2]), + .di(wb_dat_i[15:8]), + .doq(wb_dat_o[15:8]), + .we(we), + .oe(1'b1), + .ce(be_i[1])); + + minsoc_onchip_ram # + ( + .aw(adr_width) + ) + block_ram_2 ( + .clk(wb_clk_i), + .rst(wb_rst_i), + .addr(wb_adr_i[adr_width+1:2]), + .di(wb_dat_i[23:16]), + .doq(wb_dat_o[23:16]), + .we(we), + .oe(1'b1), + .ce(be_i[2])); + + minsoc_onchip_ram # + ( + .aw(adr_width) + ) + block_ram_3 ( + .clk(wb_clk_i), + .rst(wb_rst_i), + .addr(wb_adr_i[adr_width+1:2]), + .di(wb_dat_i[31:24]), + .doq(wb_dat_o[31:24]), + .we(we), + .oe(1'b1), + .ce(be_i[3])); + +endmodule +
release-1.0/bench/verilog/minsoc_memory_model.v Property changes : Added: svn:executable ## -0,0 +1 ## +* \ No newline at end of property Index: release-1.0/bench/verilog/vpi/dbg_comm_vpi.v =================================================================== --- release-1.0/bench/verilog/vpi/dbg_comm_vpi.v (nonexistent) +++ release-1.0/bench/verilog/vpi/dbg_comm_vpi.v (revision 151) @@ -0,0 +1,162 @@ +////////////////////////////////////////////////////////////////////// +//// //// +//// dbg_comm_vpi.v //// +//// //// +//// //// +//// This file is part of the SoC/OpenRISC Development Interface //// +//// http://www.opencores.org/cores/DebugInterface/ //// +//// //// +//// //// +//// Author(s): //// +//// Igor Mohor (igorm@opencores.org) //// +//// Gyorgy Jeney (nog@sdf.lonestar.net) //// +//// Nathan Yawn (nathan.yawn@opencores.org) //// +//// Raul Fajardo (rfajardo@gmail.com) //// +//// //// +//// //// +////////////////////////////////////////////////////////////////////// +//// //// +//// Copyright (C) 2000-2008 Authors //// +//// //// +//// This source file may be used and distributed without //// +//// restriction provided that this copyright statement is not //// +//// removed from the file and that any derivative work contains //// +//// the original copyright notice and the associated disclaimer. //// +//// //// +//// This source file is free software; you can redistribute it //// +//// and/or modify it under the terms of the GNU Lesser General //// +//// Public License as published by the Free Software Foundation; //// +//// either version 2.1 of the License, or (at your option) any //// +//// later version. //// +//// //// +//// This source is distributed in the hope that it will be //// +//// useful, but WITHOUT ANY WARRANTY; without even the implied //// +//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR //// +//// PURPOSE. See the GNU Lesser General Public License for more //// +//// details. //// +//// //// +//// You should have received a copy of the GNU Lesser General //// +//// Public License along with this source; if not, download it //// +//// from http://www.opencores.org/lgpl.shtml //// +//// //// +////////////////////////////////////////////////////////////////////// +// +// CVS Revision History +// +// $Log: dbg_comm_vpi.v,v $ +// Revision 1.2.1 2009/09/08 14:57 rfajardo +// Changed clock and reset outputs to inputs for minsoc +// +// $Log: dbg_comm_vpi.v,v $ +// Revision 1.2 2009/05/17 20:55:57 Nathan +// Changed email address to opencores.org +// +// Revision 1.1 2008/07/26 17:33:20 Nathan +// Added debug comm module for use with VPI / network communication. +// +// Revision 1.1 2002/03/28 19:59:54 lampret +// Added bench directory +// +// Revision 1.1.1.1 2001/11/04 18:51:07 lampret +// First import. +// +// Revision 1.3 2001/09/24 14:06:13 mohor +// Changes connected to the OpenRISC access (SPR read, SPR write). +// +// Revision 1.2 2001/09/20 10:10:30 mohor +// Working version. Few bugs fixed, comments added. +// +// Revision 1.1.1.1 2001/09/13 13:49:19 mohor +// Initial official release. +// +// +// +// +// + +`include "timescale.v" + +`define JP_PORT "4567" +`define TIMEOUT_COUNT 6'd20 // 1/2 of a TCK clock will be this many SYS_CLK ticks. Must be less than 6 bits. + + module dbg_comm_vpi ( + SYS_CLK, + P_TMS, + P_TCK, + P_TRST, + P_TDI, + P_TDO + ); + + //parameter Tp = 20; + + input SYS_CLK; + output P_TMS; + output P_TCK; + output P_TRST; + output P_TDI; + input P_TDO; + + + reg [4:0] memory; // [0:0]; + + + wire P_TCK; + wire P_TRST; + wire P_TDI; + wire P_TMS; + wire P_TDO; + + reg [3:0] in_word_r; + reg [5:0] clk_count; + + + // Handle commands from the upper level + initial + begin + in_word_r = 5'b0; + memory = 5'b0; + $jp_init(`JP_PORT); + #5500; // Wait until reset is complete + + while(1) + begin + #1; + $jp_in(memory); // This will not change memory[][] if no command has been sent from jp + if(memory[4]) // was memory[0][4] + begin + in_word_r = memory[3:0]; + memory = memory & 4'b1111; + clk_count = 6'b000000; // Reset the timeout clock in case jp wants to wait for a timeout / half TCK period + end + end + end + + + + // Send the output bit to the upper layer + always @ (P_TDO) + begin + $jp_out(P_TDO); + end + + + assign P_TCK = in_word_r[0]; + assign P_TRST = in_word_r[1]; + assign P_TDI = in_word_r[2]; + assign P_TMS = in_word_r[3]; + + + // Send timeouts / wait periods to the upper layer + always @ (posedge SYS_CLK) + begin + if(clk_count < `TIMEOUT_COUNT) clk_count[5:0] = clk_count[5:0] + 1; + else if(clk_count == `TIMEOUT_COUNT) begin + $jp_wait_time(); + clk_count[5:0] = clk_count[5:0] + 1; + end + // else it's already timed out, don't do anything + end + +endmodule +
release-1.0/bench/verilog/vpi/dbg_comm_vpi.v Property changes : Added: svn:executable ## -0,0 +1 ## +* \ No newline at end of property Index: release-1.0/bench/verilog/sim_lib/fpga_memory_primitives.v =================================================================== --- release-1.0/bench/verilog/sim_lib/fpga_memory_primitives.v (nonexistent) +++ release-1.0/bench/verilog/sim_lib/fpga_memory_primitives.v (revision 151) @@ -0,0 +1,705 @@ + +// +//ALTERA_LPM +// +module lpm_ram_dq ( + address, + inclock, + outclock, + data, + we, + q +); + +parameter lpm_width = 8; +parameter lpm_widthad = 11; +parameter lpm_indata = "REGISTERED"; //This 4 parameters are included only to avoid warnings +parameter lpm_address_control = "REGISTERED"; //they are not accessed inside the module. OR1200 uses this +parameter lpm_outdata = "UNREGISTERED"; //configuration set on all its instantiations, so this is fine. +parameter lpm_hint = "USE_EAB=ON"; //It may not be fine, if you are adding this library to your + //own system, which uses this module with another configuration. +localparam dw = lpm_width; +localparam aw = lpm_widthad; + +input [aw-1:0] address; +input inclock; +input outclock; +input [dw-1:0] data; +input we; +output [dw-1:0] q; + +reg [dw-1:0] mem [(1<
release-1.0/backend/spartan3a_dsp_kit/minsoc_bench_defines.v Property changes : Added: svn:executable ## -0,0 +1 ## +* \ No newline at end of property Index: release-1.0/backend/spartan3a_dsp_kit/configure =================================================================== --- release-1.0/backend/spartan3a_dsp_kit/configure (nonexistent) +++ release-1.0/backend/spartan3a_dsp_kit/configure (revision 151) @@ -0,0 +1,130 @@ +#!/bin/bash + +#new boards have to udpate this +BOARD=spartan3a_dsp_kit #this has to have the name of the directory this file is in +DEVICE_PART='xc3sd1800a-4-fg676' +CONSTRAINT_FILE='spartan3a_dsp_kit.ucf' +#~new boards update + +#system workings +MINSOC_DIR=`pwd`/../.. +BACKEND_DIR=$MINSOC_DIR/backend +SYN_DIR=$MINSOC_DIR/syn +SYNSRC_DIR=$MINSOC_DIR/prj/xilinx +SYNSUPPORT_DIR=$SYN_DIR/buildSupport +MAKEFILE_DIR=$SYN_DIR/xilinx + +SYN_FILES=(ethmac.xst uart_top.xst adbg_top.xst or1200_top.xst minsoc_top.xst) +MAKEFILE=Makefile + +FIND_PART='DEVICE_PART' +FIND_CONSTRAINT='CONSTRAINT_FILE' + +BOARD_DIR=$BACKEND_DIR/$BOARD +BOARD_FILES=(board.h orp.ld minsoc_defines.v minsoc_bench_defines.v gcc-opt.mk $CONSTRAINT_FILE) + +in_minsoc=`pwd | grep minsoc/backend/${BOARD}$` +if [ -z $in_minsoc ] +then + echo "" + echo " !!!WARNING!!!" + echo "This script cannot be run if not in a board directory inside minsoc/backend," + echo "because it relies on the directory structure of the minsoc system." + echo "" + echo "Possibly your minsoc directory is named differently, minsoc_trunk for example." + echo "Its name must be minsoc only." + echo "" + exit 1 +fi + +#NON STANDARD SCRIPT PART +echo "THIS SCRIPT HAS A NON-STANDARD BEGINNING." +echo "__________________________________________________________________________" +echo "${BOARD} requires another configuration for or1200_rel1." + +echo "" +echo "Copying or1200_defines.v, to or1200 implementation directory..." +echo "(minsoc/rtl/verilog/or1200/rtl/verilog)" +echo "__________________________________________________________________________" +cp $BOARD_DIR/or1200_defines.v $MINSOC_DIR/rtl/verilog/or1200/rtl/verilog +echo "" +echo "REGULAR SCRIPT STARTS NOW" +echo "__________________________________________________________________________" +#~NON STANDARD SCRIPT PART + +echo "" +echo "This script sets up the SoC for simulations and synthesis." +echo "" +echo "In order to do so, SoC board's specific files for firmware compilation, " +echo "testbench generation and synthesis are configured." +echo "Firmware and testbench looks for board specific files under $BACKEND_DIR." +echo "Synthesis work under $SYN_DIR." +echo "" +echo "" + +echo "Copying board specific SoC files from $BOARD_DIR to $BACKEND_DIR directory." +echo "__________________________________________________________________________" +echo "" +for file in "${BOARD_FILES[@]}" +do + if [ $file != NONE ] + then + echo "Copying $file, to backend directory..." + cp $BOARD_DIR/$file $BACKEND_DIR + fi +done +echo "" +echo "" + +echo "Generating project files for simulation and synthesis..." +echo "__________________________________________________________________________" +echo "" +make -C $MINSOC_DIR/prj +echo "Generation complete." +echo "" +echo "" + +if [ $CONSTRAINT_FILE == 'NONE' ] +then + echo "Skipping synthesis preparation. Standard implementation can only be simulated." + echo "" + echo "" +else + echo "Device part for files under $SYNSRC_DIR will be patched and stored " + echo "temporarily." + echo "Afterwards, they are copied to $SYNSUPPORT_DIR." + echo "__________________________________________________________________________" + echo "" + for file in "${SYN_FILES[@]}" + do + echo "Updating synthesis file, $file..." + echo "Copying $file to synthesis directory..." + echo "" + sed "s/$FIND_PART/$DEVICE_PART/g" $SYNSRC_DIR/$file > TMPFILE + sed "s/$FIND_CONSTRAINT/$CONSTRAINT_FILE/g" TMPFILE > TMPFILE2 && mv TMPFILE2 $SYNSUPPORT_DIR/$file + rm TMPFILE + done + + echo "Updating Makefile file under $MAKEFILE_DIR..." + echo "Copying Makefile to synthesis directory, $SYN_DIR..." + echo "" + sed "s/$FIND_PART/$DEVICE_PART/g" $MAKEFILE_DIR/$MAKEFILE > TMPFILE + sed "s/$FIND_CONSTRAINT/$CONSTRAINT_FILE/g" TMPFILE > TMPFILE2 && mv TMPFILE2 $SYN_DIR/$MAKEFILE + rm TMPFILE + cp $MAKEFILE_DIR/setup.bat $SYN_DIR/setup.bat + echo "" + echo "" +fi + +#Precompiling firmwares +echo "Precompiling delivered libraries and firmwares..." +make -C ../../sw/utils +make -C ../../sw/support +make -C ../../sw/drivers +make -C ../../sw/uart +make -C ../../sw/eth +echo "done." +echo "" +echo "" + +echo "Configuration done."
release-1.0/backend/spartan3a_dsp_kit/configure Property changes : Added: svn:executable ## -0,0 +1 ## +* \ No newline at end of property Index: release-1.0/backend/spartan3a_dsp_kit/or1200_defines.v =================================================================== --- release-1.0/backend/spartan3a_dsp_kit/or1200_defines.v (nonexistent) +++ release-1.0/backend/spartan3a_dsp_kit/or1200_defines.v (revision 151) @@ -0,0 +1,1754 @@ +////////////////////////////////////////////////////////////////////// +//// //// +//// OR1200's definitions //// +//// //// +//// This file is part of the OpenRISC 1200 project //// +//// http://www.opencores.org/cores/or1k/ //// +//// //// +//// Description //// +//// Parameters of the OR1200 core //// +//// //// +//// To Do: //// +//// - add parameters that are missing //// +//// //// +//// Author(s): //// +//// - Damjan Lampret, lampret@opencores.org //// +//// //// +////////////////////////////////////////////////////////////////////// +//// //// +//// Copyright (C) 2000 Authors and OPENCORES.ORG //// +//// //// +//// This source file may be used and distributed without //// +//// restriction provided that this copyright statement is not //// +//// removed from the file and that any derivative work contains //// +//// the original copyright notice and the associated disclaimer. //// +//// //// +//// This source file is free software; you can redistribute it //// +//// and/or modify it under the terms of the GNU Lesser General //// +//// Public License as published by the Free Software Foundation; //// +//// either version 2.1 of the License, or (at your option) any //// +//// later version. //// +//// //// +//// This source is distributed in the hope that it will be //// +//// useful, but WITHOUT ANY WARRANTY; without even the implied //// +//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR //// +//// PURPOSE. See the GNU Lesser General Public License for more //// +//// details. //// +//// //// +//// You should have received a copy of the GNU Lesser General //// +//// Public License along with this source; if not, download it //// +//// from http://www.opencores.org/lgpl.shtml //// +//// //// +////////////////////////////////////////////////////////////////////// +// +// CVS Revision History +// +// $Log: not supported by cvs2svn $ +// Revision 1.44 2005/10/19 11:37:56 jcastillo +// Added support for RAMB16 Xilinx4/Spartan3 primitives +// +// Revision 1.43 2005/01/07 09:23:39 andreje +// l.ff1 and l.cmov instructions added +// +// Revision 1.42 2004/06/08 18:17:36 lampret +// Non-functional changes. Coding style fixes. +// +// Revision 1.41 2004/05/09 20:03:20 lampret +// By default l.cust5 insns are disabled +// +// Revision 1.40 2004/05/09 19:49:04 lampret +// Added some l.cust5 custom instructions as example +// +// Revision 1.39 2004/04/08 11:00:46 simont +// Add support for 512B instruction cache. +// +// Revision 1.38 2004/04/05 08:29:57 lampret +// Merged branch_qmem into main tree. +// +// Revision 1.35.4.6 2004/02/11 01:40:11 lampret +// preliminary HW breakpoints support in debug unit (by default disabled). To enable define OR1200_DU_HWBKPTS. +// +// Revision 1.35.4.5 2004/01/15 06:46:38 markom +// interface to debug changed; no more opselect; stb-ack protocol +// +// Revision 1.35.4.4 2004/01/11 22:45:46 andreje +// Separate instruction and data QMEM decoders, QMEM acknowledge and byte-select added +// +// Revision 1.35.4.3 2003/12/17 13:43:38 simons +// Exception prefix configuration changed. +// +// Revision 1.35.4.2 2003/12/05 00:05:03 lampret +// Static exception prefix. +// +// Revision 1.35.4.1 2003/07/08 15:36:37 lampret +// Added embedded memory QMEM. +// +// Revision 1.35 2003/04/24 00:16:07 lampret +// No functional changes. Added defines to disable implementation of multiplier/MAC +// +// Revision 1.34 2003/04/20 22:23:57 lampret +// No functional change. Only added customization for exception vectors. +// +// Revision 1.33 2003/04/07 20:56:07 lampret +// Fixed OR1200_CLKDIV_x_SUPPORTED defines. Better description. +// +// Revision 1.32 2003/04/07 01:26:57 lampret +// RFRAM defines comments updated. Altera LPM option added. +// +// Revision 1.31 2002/12/08 08:57:56 lampret +// Added optional support for WB B3 specification (xwb_cti_o, xwb_bte_o). Made xwb_cab_o optional. +// +// Revision 1.30 2002/10/28 15:09:22 mohor +// Previous check-in was done by mistake. +// +// Revision 1.29 2002/10/28 15:03:50 mohor +// Signal scanb_sen renamed to scanb_en. +// +// Revision 1.28 2002/10/17 20:04:40 lampret +// Added BIST scan. Special VS RAMs need to be used to implement BIST. +// +// Revision 1.27 2002/09/16 03:13:23 lampret +// Removed obsolete comment. +// +// Revision 1.26 2002/09/08 05:52:16 lampret +// Added optional l.div/l.divu insns. By default they are disabled. +// +// Revision 1.25 2002/09/07 19:16:10 lampret +// If SR[CY] implemented with OR1200_IMPL_ADDC enabled, l.add/l.addi also set SR[CY]. +// +// Revision 1.24 2002/09/07 05:42:02 lampret +// Added optional SR[CY]. Added define to enable additional (compare) flag modifiers. Defines are OR1200_IMPL_ADDC and OR1200_ADDITIONAL_FLAG_MODIFIERS. +// +// Revision 1.23 2002/09/04 00:50:34 lampret +// Now most of the configuration registers are updatded automatically based on defines in or1200_defines.v. +// +// Revision 1.22 2002/09/03 22:28:21 lampret +// As per Taylor Su suggestion all case blocks are full case by default and optionally (OR1200_CASE_DEFAULT) can be disabled to increase clock frequncy. +// +// Revision 1.21 2002/08/22 02:18:55 lampret +// Store buffer has been tested and it works. BY default it is still disabled until uClinux confirms correct operation on FPGA board. +// +// Revision 1.20 2002/08/18 21:59:45 lampret +// Disable SB until it is tested +// +// Revision 1.19 2002/08/18 19:53:08 lampret +// Added store buffer. +// +// Revision 1.18 2002/08/15 06:04:11 lampret +// Fixed Xilinx trace buffer address. REported by Taylor Su. +// +// Revision 1.17 2002/08/12 05:31:44 lampret +// Added OR1200_WB_RETRY. Moved WB registered outsputs / samples inputs into lower section. +// +// Revision 1.16 2002/07/14 22:17:17 lampret +// Added simple trace buffer [only for Xilinx Virtex target]. Fixed instruction fetch abort when new exception is recognized. +// +// Revision 1.15 2002/06/08 16:20:21 lampret +// Added defines for enabling generic FF based memory macro for register file. +// +// Revision 1.14 2002/03/29 16:24:06 lampret +// Changed comment about synopsys to _synopsys_ because synthesis was complaining about unknown directives +// +// Revision 1.13 2002/03/29 15:16:55 lampret +// Some of the warnings fixed. +// +// Revision 1.12 2002/03/28 19:25:42 lampret +// Added second type of Virtual Silicon two-port SRAM (for register file). Changed defines for VS STP RAMs. +// +// Revision 1.11 2002/03/28 19:13:17 lampret +// Updated defines. +// +// Revision 1.10 2002/03/14 00:30:24 lampret +// Added alternative for critical path in DU. +// +// Revision 1.9 2002/03/11 01:26:26 lampret +// Fixed async loop. Changed multiplier type for ASIC. +// +// Revision 1.8 2002/02/11 04:33:17 lampret +// Speed optimizations (removed duplicate _cyc_ and _stb_). Fixed D/IMMU cache-inhibit attr. +// +// Revision 1.7 2002/02/01 19:56:54 lampret +// Fixed combinational loops. +// +// Revision 1.6 2002/01/19 14:10:22 lampret +// Fixed OR1200_XILINX_RAM32X1D. +// +// Revision 1.5 2002/01/18 07:56:00 lampret +// No more low/high priority interrupts (PICPR removed). Added tick timer exception. Added exception prefix (SR[EPH]). Fixed single-step bug whenreading NPC. +// +// Revision 1.4 2002/01/14 09:44:12 lampret +// Default ASIC configuration does not sample WB inputs. +// +// Revision 1.3 2002/01/08 00:51:08 lampret +// Fixed typo. OR1200_REGISTERED_OUTPUTS was not defined. Should be. +// +// Revision 1.2 2002/01/03 21:23:03 lampret +// Uncommented OR1200_REGISTERED_OUTPUTS for FPGA target. +// +// Revision 1.1 2002/01/03 08:16:15 lampret +// New prefixes for RTL files, prefixed module names. Updated cache controllers and MMUs. +// +// Revision 1.20 2001/12/04 05:02:36 lampret +// Added OR1200_GENERIC_MULTP2_32X32 and OR1200_ASIC_MULTP2_32X32 +// +// Revision 1.19 2001/11/27 19:46:57 lampret +// Now FPGA and ASIC target are separate. +// +// Revision 1.18 2001/11/23 21:42:31 simons +// Program counter divided to PPC and NPC. +// +// Revision 1.17 2001/11/23 08:38:51 lampret +// Changed DSR/DRR behavior and exception detection. +// +// Revision 1.16 2001/11/20 21:30:38 lampret +// Added OR1200_REGISTERED_INPUTS. +// +// Revision 1.15 2001/11/19 14:29:48 simons +// Cashes disabled. +// +// Revision 1.14 2001/11/13 10:02:21 lampret +// Added 'setpc'. Renamed some signals (except_flushpipe into flushpipe etc) +// +// Revision 1.13 2001/11/12 01:45:40 lampret +// Moved flag bit into SR. Changed RF enable from constant enable to dynamic enable for read ports. +// +// Revision 1.12 2001/11/10 03:43:57 lampret +// Fixed exceptions. +// +// Revision 1.11 2001/11/02 18:57:14 lampret +// Modified virtual silicon instantiations. +// +// Revision 1.10 2001/10/21 17:57:16 lampret +// Removed params from generic_XX.v. Added translate_off/on in sprs.v and id.v. Removed spr_addr from dc.v and ic.v. Fixed CR+LF. +// +// Revision 1.9 2001/10/19 23:28:46 lampret +// Fixed some synthesis warnings. Configured with caches and MMUs. +// +// Revision 1.8 2001/10/14 13:12:09 lampret +// MP3 version. +// +// Revision 1.1.1.1 2001/10/06 10:18:36 igorm +// no message +// +// Revision 1.3 2001/08/17 08:01:19 lampret +// IC enable/disable. +// +// Revision 1.2 2001/08/13 03:36:20 lampret +// Added cfg regs. Moved all defines into one defines.v file. More cleanup. +// +// Revision 1.1 2001/08/09 13:39:33 lampret +// Major clean-up. +// +// Revision 1.2 2001/07/22 03:31:54 lampret +// Fixed RAM's oen bug. Cache bypass under development. +// +// Revision 1.1 2001/07/20 00:46:03 lampret +// Development version of RTL. Libraries are missing. +// +// + +// +// Dump VCD +// +//`define OR1200_VCD_DUMP + +// +// Generate debug messages during simulation +// +//`define OR1200_VERBOSE + +// `define OR1200_ASIC +//////////////////////////////////////////////////////// +// +// Typical configuration for an ASIC +// +`ifdef OR1200_ASIC + +// +// Target ASIC memories +// +//`define OR1200_ARTISAN_SSP +//`define OR1200_ARTISAN_SDP +//`define OR1200_ARTISAN_STP +`define OR1200_VIRTUALSILICON_SSP +//`define OR1200_VIRTUALSILICON_STP_T1 +//`define OR1200_VIRTUALSILICON_STP_T2 + +// +// Do not implement Data cache +// +//`define OR1200_NO_DC + +// +// Do not implement Insn cache +// +//`define OR1200_NO_IC + +// +// Do not implement Data MMU +// +//`define OR1200_NO_DMMU + +// +// Do not implement Insn MMU +// +//`define OR1200_NO_IMMU + +// +// Select between ASIC optimized and generic multiplier +// +//`define OR1200_ASIC_MULTP2_32X32 +`define OR1200_GENERIC_MULTP2_32X32 + +// +// Size/type of insn/data cache if implemented +// +// `define OR1200_IC_1W_512B +// `define OR1200_IC_1W_4KB +`define OR1200_IC_1W_8KB +// `define OR1200_DC_1W_4KB +`define OR1200_DC_1W_8KB + +`else + + +///////////////////////////////////////////////////////// +// +// Typical configuration for an FPGA +// + +// +// Target FPGA memories +// +//`define OR1200_ALTERA_LPM +`define OR1200_XILINX_RAMB16 +//`define OR1200_XILINX_RAMB4 +//`define OR1200_XILINX_RAM32X1D +//`define OR1200_USE_RAM16X1D_FOR_RAM32X1D + +// +// Do not implement Data cache +// +`define OR1200_NO_DC + +// +// Do not implement Insn cache +// +`define OR1200_NO_IC + +// +// Do not implement Data MMU +// +`define OR1200_NO_DMMU + +// +// Do not implement Insn MMU +// +`define OR1200_NO_IMMU + +// +// Select between ASIC and generic multiplier +// +// (Generic seems to trigger a bug in the Cadence Ncsim simulator) +// +//`define OR1200_ASIC_MULTP2_32X32 +`define OR1200_GENERIC_MULTP2_32X32 + +// +// Size/type of insn/data cache if implemented +// (consider available FPGA memory resources) +// +//`define OR1200_IC_1W_512B +`define OR1200_IC_1W_4KB +//`define OR1200_IC_1W_8KB +`define OR1200_DC_1W_4KB +//`define OR1200_DC_1W_8KB + +`endif + + +////////////////////////////////////////////////////////// +// +// Do not change below unless you know what you are doing +// + +// +// Enable RAM BIST +// +// At the moment this only works for Virtual Silicon +// single port RAMs. For other RAMs it has not effect. +// Special wrapper for VS RAMs needs to be provided +// with scan flops to facilitate bist scan. +// +//`define OR1200_BIST + +// +// Register OR1200 WISHBONE outputs +// (must be defined/enabled) +// +`define OR1200_REGISTERED_OUTPUTS + +// +// Register OR1200 WISHBONE inputs +// +// (must be undefined/disabled) +// +//`define OR1200_REGISTERED_INPUTS + +// +// Disable bursts if they are not supported by the +// memory subsystem (only affect cache line fill) +// +//`define OR1200_NO_BURSTS +// + +// +// WISHBONE retry counter range +// +// 2^value range for retry counter. Retry counter +// is activated whenever *wb_rty_i is asserted and +// until retry counter expires, corresponding +// WISHBONE interface is deactivated. +// +// To disable retry counters and *wb_rty_i all together, +// undefine this macro. +// +//`define OR1200_WB_RETRY 7 + +// +// WISHBONE Consecutive Address Burst +// +// This was used prior to WISHBONE B3 specification +// to identify bursts. It is no longer needed but +// remains enabled for compatibility with old designs. +// +// To remove *wb_cab_o ports undefine this macro. +// +`define OR1200_WB_CAB + +// +// WISHBONE B3 compatible interface +// +// This follows the WISHBONE B3 specification. +// It is not enabled by default because most +// designs still don't use WB b3. +// +// To enable *wb_cti_o/*wb_bte_o ports, +// define this macro. +// +//`define OR1200_WB_B3 + +// +// Enable additional synthesis directives if using +// _Synopsys_ synthesis tool +// +//`define OR1200_ADDITIONAL_SYNOPSYS_DIRECTIVES + +// +// Enables default statement in some case blocks +// and disables Synopsys synthesis directive full_case +// +// By default it is enabled. When disabled it +// can increase clock frequency. +// +`define OR1200_CASE_DEFAULT + +// +// Operand width / register file address width +// +// (DO NOT CHANGE) +// +`define OR1200_OPERAND_WIDTH 32 +`define OR1200_REGFILE_ADDR_WIDTH 5 + +// +// l.add/l.addi/l.and and optional l.addc/l.addic +// also set (compare) flag when result of their +// operation equals zero +// +// At the time of writing this, default or32 +// C/C++ compiler doesn't generate code that +// would benefit from this optimization. +// +// By default this optimization is disabled to +// save area. +// +//`define OR1200_ADDITIONAL_FLAG_MODIFIERS + +// +// Implement l.addc/l.addic instructions +// +// By default implementation of l.addc/l.addic +// instructions is enabled in case you need them. +// If you don't use them, then disable implementation +// to save area. +// +`define OR1200_IMPL_ADDC + +// +// Implement carry bit SR[CY] +// +// By default implementation of SR[CY] is enabled +// to be compliant with the simulator. However +// SR[CY] is explicitly only used by l.addc/l.addic +// instructions and if these two insns are not +// implemented there is not much point having SR[CY]. +// +`define OR1200_IMPL_CY + +// +// Implement optional l.div/l.divu instructions +// +// By default divide instructions are not implemented +// to save area and increase clock frequency. or32 C/C++ +// compiler can use soft library for division. +// +// To implement divide, multiplier needs to be implemented. +// +//`define OR1200_IMPL_DIV + +// +// Implement rotate in the ALU +// +// At the time of writing this, or32 +// C/C++ compiler doesn't generate rotate +// instructions. However or32 assembler +// can assemble code that uses rotate insn. +// This means that rotate instructions +// must be used manually inserted. +// +// By default implementation of rotate +// is disabled to save area and increase +// clock frequency. +// +//`define OR1200_IMPL_ALU_ROTATE + +// +// Type of ALU compare to implement +// +// Try either one to find what yields +// higher clock frequencyin your case. +// +//`define OR1200_IMPL_ALU_COMP1 +`define OR1200_IMPL_ALU_COMP2 + +// +// Implement multiplier +// +// By default multiplier is implemented +// +`define OR1200_MULT_IMPLEMENTED + +// +// Implement multiply-and-accumulate +// +// By default MAC is implemented. To +// implement MAC, multiplier needs to be +// implemented. +// +`define OR1200_MAC_IMPLEMENTED + +// +// Low power, slower multiplier +// +// Select between low-power (larger) multiplier +// and faster multiplier. The actual difference +// is only AND logic that prevents distribution +// of operands into the multiplier when instruction +// in execution is not multiply instruction +// +//`define OR1200_LOWPWR_MULT + +// +// Clock ratio RISC clock versus WB clock +// +// If you plan to run WB:RISC clock fixed to 1:1, disable +// both defines +// +// For WB:RISC 1:2 or 1:1, enable OR1200_CLKDIV_2_SUPPORTED +// and use clmode to set ratio +// +// For WB:RISC 1:4, 1:2 or 1:1, enable both defines and use +// clmode to set ratio +// +`define OR1200_CLKDIV_2_SUPPORTED +//`define OR1200_CLKDIV_4_SUPPORTED + +// +// Type of register file RAM +// +// Memory macro w/ two ports (see or1200_tpram_32x32.v) +//`define OR1200_RFRAM_TWOPORT +// +// Memory macro dual port (see or1200_dpram_32x32.v) +`define OR1200_RFRAM_DUALPORT +// +// Generic (flip-flop based) register file (see or1200_rfram_generic.v) +//`define OR1200_RFRAM_GENERIC + +// +// Type of mem2reg aligner to implement. +// +// Once OR1200_IMPL_MEM2REG2 yielded faster +// circuit, however with today tools it will +// most probably give you slower circuit. +// +`define OR1200_IMPL_MEM2REG1 +//`define OR1200_IMPL_MEM2REG2 + +// +// ALUOPs +// +`define OR1200_ALUOP_WIDTH 4 +`define OR1200_ALUOP_NOP 4'd4 +/* Order defined by arith insns that have two source operands both in regs + (see binutils/include/opcode/or32.h) */ +`define OR1200_ALUOP_ADD 4'd0 +`define OR1200_ALUOP_ADDC 4'd1 +`define OR1200_ALUOP_SUB 4'd2 +`define OR1200_ALUOP_AND 4'd3 +`define OR1200_ALUOP_OR 4'd4 +`define OR1200_ALUOP_XOR 4'd5 +`define OR1200_ALUOP_MUL 4'd6 +`define OR1200_ALUOP_CUST5 4'd7 +`define OR1200_ALUOP_SHROT 4'd8 +`define OR1200_ALUOP_DIV 4'd9 +`define OR1200_ALUOP_DIVU 4'd10 +/* Order not specifically defined. */ +`define OR1200_ALUOP_IMM 4'd11 +`define OR1200_ALUOP_MOVHI 4'd12 +`define OR1200_ALUOP_COMP 4'd13 +`define OR1200_ALUOP_MTSR 4'd14 +`define OR1200_ALUOP_MFSR 4'd15 +`define OR1200_ALUOP_CMOV 4'd14 +`define OR1200_ALUOP_FF1 4'd15 +// +// MACOPs +// +`define OR1200_MACOP_WIDTH 2 +`define OR1200_MACOP_NOP 2'b00 +`define OR1200_MACOP_MAC 2'b01 +`define OR1200_MACOP_MSB 2'b10 + +// +// Shift/rotate ops +// +`define OR1200_SHROTOP_WIDTH 2 +`define OR1200_SHROTOP_NOP 2'd0 +`define OR1200_SHROTOP_SLL 2'd0 +`define OR1200_SHROTOP_SRL 2'd1 +`define OR1200_SHROTOP_SRA 2'd2 +`define OR1200_SHROTOP_ROR 2'd3 + +// Execution cycles per instruction +`define OR1200_MULTICYCLE_WIDTH 2 +`define OR1200_ONE_CYCLE 2'd0 +`define OR1200_TWO_CYCLES 2'd1 + +// Operand MUX selects +`define OR1200_SEL_WIDTH 2 +`define OR1200_SEL_RF 2'd0 +`define OR1200_SEL_IMM 2'd1 +`define OR1200_SEL_EX_FORW 2'd2 +`define OR1200_SEL_WB_FORW 2'd3 + +// +// BRANCHOPs +// +`define OR1200_BRANCHOP_WIDTH 3 +`define OR1200_BRANCHOP_NOP 3'd0 +`define OR1200_BRANCHOP_J 3'd1 +`define OR1200_BRANCHOP_JR 3'd2 +`define OR1200_BRANCHOP_BAL 3'd3 +`define OR1200_BRANCHOP_BF 3'd4 +`define OR1200_BRANCHOP_BNF 3'd5 +`define OR1200_BRANCHOP_RFE 3'd6 + +// +// LSUOPs +// +// Bit 0: sign extend +// Bits 1-2: 00 doubleword, 01 byte, 10 halfword, 11 singleword +// Bit 3: 0 load, 1 store +`define OR1200_LSUOP_WIDTH 4 +`define OR1200_LSUOP_NOP 4'b0000 +`define OR1200_LSUOP_LBZ 4'b0010 +`define OR1200_LSUOP_LBS 4'b0011 +`define OR1200_LSUOP_LHZ 4'b0100 +`define OR1200_LSUOP_LHS 4'b0101 +`define OR1200_LSUOP_LWZ 4'b0110 +`define OR1200_LSUOP_LWS 4'b0111 +`define OR1200_LSUOP_LD 4'b0001 +`define OR1200_LSUOP_SD 4'b1000 +`define OR1200_LSUOP_SB 4'b1010 +`define OR1200_LSUOP_SH 4'b1100 +`define OR1200_LSUOP_SW 4'b1110 + +// FETCHOPs +`define OR1200_FETCHOP_WIDTH 1 +`define OR1200_FETCHOP_NOP 1'b0 +`define OR1200_FETCHOP_LW 1'b1 + +// +// Register File Write-Back OPs +// +// Bit 0: register file write enable +// Bits 2-1: write-back mux selects +`define OR1200_RFWBOP_WIDTH 3 +`define OR1200_RFWBOP_NOP 3'b000 +`define OR1200_RFWBOP_ALU 3'b001 +`define OR1200_RFWBOP_LSU 3'b011 +`define OR1200_RFWBOP_SPRS 3'b101 +`define OR1200_RFWBOP_LR 3'b111 + +// Compare instructions +`define OR1200_COP_SFEQ 3'b000 +`define OR1200_COP_SFNE 3'b001 +`define OR1200_COP_SFGT 3'b010 +`define OR1200_COP_SFGE 3'b011 +`define OR1200_COP_SFLT 3'b100 +`define OR1200_COP_SFLE 3'b101 +`define OR1200_COP_X 3'b111 +`define OR1200_SIGNED_COMPARE 'd3 +`define OR1200_COMPOP_WIDTH 4 + +// +// TAGs for instruction bus +// +`define OR1200_ITAG_IDLE 4'h0 // idle bus +`define OR1200_ITAG_NI 4'h1 // normal insn +`define OR1200_ITAG_BE 4'hb // Bus error exception +`define OR1200_ITAG_PE 4'hc // Page fault exception +`define OR1200_ITAG_TE 4'hd // TLB miss exception + +// +// TAGs for data bus +// +`define OR1200_DTAG_IDLE 4'h0 // idle bus +`define OR1200_DTAG_ND 4'h1 // normal data +`define OR1200_DTAG_AE 4'ha // Alignment exception +`define OR1200_DTAG_BE 4'hb // Bus error exception +`define OR1200_DTAG_PE 4'hc // Page fault exception +`define OR1200_DTAG_TE 4'hd // TLB miss exception + + +////////////////////////////////////////////// +// +// ORBIS32 ISA specifics +// + +// SHROT_OP position in machine word +`define OR1200_SHROTOP_POS 7:6 + +// ALU instructions multicycle field in machine word +`define OR1200_ALUMCYC_POS 9:8 + +// +// Instruction opcode groups (basic) +// +`define OR1200_OR32_J 6'b000000 +`define OR1200_OR32_JAL 6'b000001 +`define OR1200_OR32_BNF 6'b000011 +`define OR1200_OR32_BF 6'b000100 +`define OR1200_OR32_NOP 6'b000101 +`define OR1200_OR32_MOVHI 6'b000110 +`define OR1200_OR32_XSYNC 6'b001000 +`define OR1200_OR32_RFE 6'b001001 +/* */ +`define OR1200_OR32_JR 6'b010001 +`define OR1200_OR32_JALR 6'b010010 +`define OR1200_OR32_MACI 6'b010011 +/* */ +`define OR1200_OR32_LWZ 6'b100001 +`define OR1200_OR32_LBZ 6'b100011 +`define OR1200_OR32_LBS 6'b100100 +`define OR1200_OR32_LHZ 6'b100101 +`define OR1200_OR32_LHS 6'b100110 +`define OR1200_OR32_ADDI 6'b100111 +`define OR1200_OR32_ADDIC 6'b101000 +`define OR1200_OR32_ANDI 6'b101001 +`define OR1200_OR32_ORI 6'b101010 +`define OR1200_OR32_XORI 6'b101011 +`define OR1200_OR32_MULI 6'b101100 +`define OR1200_OR32_MFSPR 6'b101101 +`define OR1200_OR32_SH_ROTI 6'b101110 +`define OR1200_OR32_SFXXI 6'b101111 +/* */ +`define OR1200_OR32_MTSPR 6'b110000 +`define OR1200_OR32_MACMSB 6'b110001 +/* */ +`define OR1200_OR32_SW 6'b110101 +`define OR1200_OR32_SB 6'b110110 +`define OR1200_OR32_SH 6'b110111 +`define OR1200_OR32_ALU 6'b111000 +`define OR1200_OR32_SFXX 6'b111001 +//`define OR1200_OR32_CUST5 6'b111100 + + +///////////////////////////////////////////////////// +// +// Exceptions +// + +// +// Exception vectors per OR1K architecture: +// 0xPPPPP100 - reset +// 0xPPPPP200 - bus error +// ... etc +// where P represents exception prefix. +// +// Exception vectors can be customized as per +// the following formula: +// 0xPPPPPNVV - exception N +// +// P represents exception prefix +// N represents exception N +// VV represents length of the individual vector space, +// usually it is 8 bits wide and starts with all bits zero +// + +// +// PPPPP and VV parts +// +// Sum of these two defines needs to be 28 +// +`define OR1200_EXCEPT_EPH0_P 20'h00000 +`define OR1200_EXCEPT_EPH1_P 20'hF0000 +`define OR1200_EXCEPT_V 8'h00 + +// +// N part width +// +`define OR1200_EXCEPT_WIDTH 4 + +// +// Definition of exception vectors +// +// To avoid implementation of a certain exception, +// simply comment out corresponding line +// +`define OR1200_EXCEPT_UNUSED `OR1200_EXCEPT_WIDTH'hf +`define OR1200_EXCEPT_TRAP `OR1200_EXCEPT_WIDTH'he +`define OR1200_EXCEPT_BREAK `OR1200_EXCEPT_WIDTH'hd +`define OR1200_EXCEPT_SYSCALL `OR1200_EXCEPT_WIDTH'hc +`define OR1200_EXCEPT_RANGE `OR1200_EXCEPT_WIDTH'hb +`define OR1200_EXCEPT_ITLBMISS `OR1200_EXCEPT_WIDTH'ha +`define OR1200_EXCEPT_DTLBMISS `OR1200_EXCEPT_WIDTH'h9 +`define OR1200_EXCEPT_INT `OR1200_EXCEPT_WIDTH'h8 +`define OR1200_EXCEPT_ILLEGAL `OR1200_EXCEPT_WIDTH'h7 +`define OR1200_EXCEPT_ALIGN `OR1200_EXCEPT_WIDTH'h6 +`define OR1200_EXCEPT_TICK `OR1200_EXCEPT_WIDTH'h5 +`define OR1200_EXCEPT_IPF `OR1200_EXCEPT_WIDTH'h4 +`define OR1200_EXCEPT_DPF `OR1200_EXCEPT_WIDTH'h3 +`define OR1200_EXCEPT_BUSERR `OR1200_EXCEPT_WIDTH'h2 +`define OR1200_EXCEPT_RESET `OR1200_EXCEPT_WIDTH'h1 +`define OR1200_EXCEPT_NONE `OR1200_EXCEPT_WIDTH'h0 + + +///////////////////////////////////////////////////// +// +// SPR groups +// + +// Bits that define the group +`define OR1200_SPR_GROUP_BITS 15:11 + +// Width of the group bits +`define OR1200_SPR_GROUP_WIDTH 5 + +// Bits that define offset inside the group +`define OR1200_SPR_OFS_BITS 10:0 + +// List of groups +`define OR1200_SPR_GROUP_SYS 5'd00 +`define OR1200_SPR_GROUP_DMMU 5'd01 +`define OR1200_SPR_GROUP_IMMU 5'd02 +`define OR1200_SPR_GROUP_DC 5'd03 +`define OR1200_SPR_GROUP_IC 5'd04 +`define OR1200_SPR_GROUP_MAC 5'd05 +`define OR1200_SPR_GROUP_DU 5'd06 +`define OR1200_SPR_GROUP_PM 5'd08 +`define OR1200_SPR_GROUP_PIC 5'd09 +`define OR1200_SPR_GROUP_TT 5'd10 + + +///////////////////////////////////////////////////// +// +// System group +// + +// +// System registers +// +`define OR1200_SPR_CFGR 7'd0 +`define OR1200_SPR_RF 6'd32 // 1024 >> 5 +`define OR1200_SPR_NPC 11'd16 +`define OR1200_SPR_SR 11'd17 +`define OR1200_SPR_PPC 11'd18 +`define OR1200_SPR_EPCR 11'd32 +`define OR1200_SPR_EEAR 11'd48 +`define OR1200_SPR_ESR 11'd64 + +// +// SR bits +// +`define OR1200_SR_WIDTH 16 +`define OR1200_SR_SM 0 +`define OR1200_SR_TEE 1 +`define OR1200_SR_IEE 2 +`define OR1200_SR_DCE 3 +`define OR1200_SR_ICE 4 +`define OR1200_SR_DME 5 +`define OR1200_SR_IME 6 +`define OR1200_SR_LEE 7 +`define OR1200_SR_CE 8 +`define OR1200_SR_F 9 +`define OR1200_SR_CY 10 // Unused +`define OR1200_SR_OV 11 // Unused +`define OR1200_SR_OVE 12 // Unused +`define OR1200_SR_DSX 13 // Unused +`define OR1200_SR_EPH 14 +`define OR1200_SR_FO 15 +`define OR1200_SR_CID 31:28 // Unimplemented + +// +// Bits that define offset inside the group +// +`define OR1200_SPROFS_BITS 10:0 + +// +// Default Exception Prefix +// +// 1'b0 - OR1200_EXCEPT_EPH0_P (0x0000_0000) +// 1'b1 - OR1200_EXCEPT_EPH1_P (0xF000_0000) +// +`define OR1200_SR_EPH_DEF 1'b0 + +///////////////////////////////////////////////////// +// +// Power Management (PM) +// + +// Define it if you want PM implemented +//`define OR1200_PM_IMPLEMENTED + +// Bit positions inside PMR (don't change) +`define OR1200_PM_PMR_SDF 3:0 +`define OR1200_PM_PMR_DME 4 +`define OR1200_PM_PMR_SME 5 +`define OR1200_PM_PMR_DCGE 6 +`define OR1200_PM_PMR_UNUSED 31:7 + +// PMR offset inside PM group of registers +`define OR1200_PM_OFS_PMR 11'b0 + +// PM group +`define OR1200_SPRGRP_PM 5'd8 + +// Define if PMR can be read/written at any address inside PM group +`define OR1200_PM_PARTIAL_DECODING + +// Define if reading PMR is allowed +`define OR1200_PM_READREGS + +// Define if unused PMR bits should be zero +`define OR1200_PM_UNUSED_ZERO + + +///////////////////////////////////////////////////// +// +// Debug Unit (DU) +// + +// Define it if you want DU implemented +`define OR1200_DU_IMPLEMENTED + +// +// Define if you want HW Breakpoints +// (if HW breakpoints are not implemented +// only default software trapping is +// possible with l.trap insn - this is +// however already enough for use +// with or32 gdb) +// +`define OR1200_DU_HWBKPTS + +// Number of DVR/DCR pairs if HW breakpoints enabled +`define OR1200_DU_DVRDCR_PAIRS 8 + +// Define if you want trace buffer +//`define OR1200_DU_TB_IMPLEMENTED + +// +// Address offsets of DU registers inside DU group +// +// To not implement a register, doq not define its address +// +`ifdef OR1200_DU_HWBKPTS +`define OR1200_DU_DVR0 11'd0 +`define OR1200_DU_DVR1 11'd1 +`define OR1200_DU_DVR2 11'd2 +`define OR1200_DU_DVR3 11'd3 +`define OR1200_DU_DVR4 11'd4 +`define OR1200_DU_DVR5 11'd5 +`define OR1200_DU_DVR6 11'd6 +`define OR1200_DU_DVR7 11'd7 +`define OR1200_DU_DCR0 11'd8 +`define OR1200_DU_DCR1 11'd9 +`define OR1200_DU_DCR2 11'd10 +`define OR1200_DU_DCR3 11'd11 +`define OR1200_DU_DCR4 11'd12 +`define OR1200_DU_DCR5 11'd13 +`define OR1200_DU_DCR6 11'd14 +`define OR1200_DU_DCR7 11'd15 +`endif +`define OR1200_DU_DMR1 11'd16 +`ifdef OR1200_DU_HWBKPTS +`define OR1200_DU_DMR2 11'd17 +`define OR1200_DU_DWCR0 11'd18 +`define OR1200_DU_DWCR1 11'd19 +`endif +`define OR1200_DU_DSR 11'd20 +`define OR1200_DU_DRR 11'd21 +`ifdef OR1200_DU_TB_IMPLEMENTED +`define OR1200_DU_TBADR 11'h0ff +`define OR1200_DU_TBIA 11'h1xx +`define OR1200_DU_TBIM 11'h2xx +`define OR1200_DU_TBAR 11'h3xx +`define OR1200_DU_TBTS 11'h4xx +`endif + +// Position of offset bits inside SPR address +`define OR1200_DUOFS_BITS 10:0 + +// DCR bits +`define OR1200_DU_DCR_DP 0 +`define OR1200_DU_DCR_CC 3:1 +`define OR1200_DU_DCR_SC 4 +`define OR1200_DU_DCR_CT 7:5 + +// DMR1 bits +`define OR1200_DU_DMR1_CW0 1:0 +`define OR1200_DU_DMR1_CW1 3:2 +`define OR1200_DU_DMR1_CW2 5:4 +`define OR1200_DU_DMR1_CW3 7:6 +`define OR1200_DU_DMR1_CW4 9:8 +`define OR1200_DU_DMR1_CW5 11:10 +`define OR1200_DU_DMR1_CW6 13:12 +`define OR1200_DU_DMR1_CW7 15:14 +`define OR1200_DU_DMR1_CW8 17:16 +`define OR1200_DU_DMR1_CW9 19:18 +`define OR1200_DU_DMR1_RES 21:20 +`define OR1200_DU_DMR1_ST 22 +`define OR1200_DU_DMR1_BT 23 + +// DMR2 bits +`define OR1200_DU_DMR2_WCE0 0 +`define OR1200_DU_DMR2_WCE1 1 +`define OR1200_DU_DMR2_AWTC 11:2 +`define OR1200_DU_DMR2_WGB 21:12 + +// DWCR bits +`define OR1200_DU_DWCR_COUNT 15:0 +`define OR1200_DU_DWCR_MATCH 31:16 + +// DSR bits +`define OR1200_DU_DSR_WIDTH 14 +`define OR1200_DU_DSR_RSTE 0 +`define OR1200_DU_DSR_BUSEE 1 +`define OR1200_DU_DSR_DPFE 2 +`define OR1200_DU_DSR_IPFE 3 +`define OR1200_DU_DSR_TTE 4 +`define OR1200_DU_DSR_AE 5 +`define OR1200_DU_DSR_IIE 6 +`define OR1200_DU_DSR_IE 7 +`define OR1200_DU_DSR_DME 8 +`define OR1200_DU_DSR_IME 9 +`define OR1200_DU_DSR_RE 10 +`define OR1200_DU_DSR_SCE 11 +`define OR1200_DU_DSR_BE 12 +`define OR1200_DU_DSR_TE 13 + +// DRR bits +`define OR1200_DU_DRR_RSTE 0 +`define OR1200_DU_DRR_BUSEE 1 +`define OR1200_DU_DRR_DPFE 2 +`define OR1200_DU_DRR_IPFE 3 +`define OR1200_DU_DRR_TTE 4 +`define OR1200_DU_DRR_AE 5 +`define OR1200_DU_DRR_IIE 6 +`define OR1200_DU_DRR_IE 7 +`define OR1200_DU_DRR_DME 8 +`define OR1200_DU_DRR_IME 9 +`define OR1200_DU_DRR_RE 10 +`define OR1200_DU_DRR_SCE 11 +`define OR1200_DU_DRR_BE 12 +`define OR1200_DU_DRR_TE 13 + +// Define if reading DU regs is allowed +`define OR1200_DU_READREGS + +// Define if unused DU registers bits should be zero +`define OR1200_DU_UNUSED_ZERO + +// Define if IF/LSU status is not needed by devel i/f +`define OR1200_DU_STATUS_UNIMPLEMENTED + +///////////////////////////////////////////////////// +// +// Programmable Interrupt Controller (PIC) +// + +// Define it if you want PIC implemented +`define OR1200_PIC_IMPLEMENTED + +// Define number of interrupt inputs (2-31) +`define OR1200_PIC_INTS 20 + +// Address offsets of PIC registers inside PIC group +`define OR1200_PIC_OFS_PICMR 2'd0 +`define OR1200_PIC_OFS_PICSR 2'd2 + +// Position of offset bits inside SPR address +`define OR1200_PICOFS_BITS 1:0 + +// Define if you want these PIC registers to be implemented +`define OR1200_PIC_PICMR +`define OR1200_PIC_PICSR + +// Define if reading PIC registers is allowed +`define OR1200_PIC_READREGS + +// Define if unused PIC register bits should be zero +`define OR1200_PIC_UNUSED_ZERO + + +///////////////////////////////////////////////////// +// +// Tick Timer (TT) +// + +// Define it if you want TT implemented +`define OR1200_TT_IMPLEMENTED + +// Address offsets of TT registers inside TT group +`define OR1200_TT_OFS_TTMR 1'd0 +`define OR1200_TT_OFS_TTCR 1'd1 + +// Position of offset bits inside SPR group +`define OR1200_TTOFS_BITS 0 + +// Define if you want these TT registers to be implemented +`define OR1200_TT_TTMR +`define OR1200_TT_TTCR + +// TTMR bits +`define OR1200_TT_TTMR_TP 27:0 +`define OR1200_TT_TTMR_IP 28 +`define OR1200_TT_TTMR_IE 29 +`define OR1200_TT_TTMR_M 31:30 + +// Define if reading TT registers is allowed +`define OR1200_TT_READREGS + + +////////////////////////////////////////////// +// +// MAC +// +`define OR1200_MAC_ADDR 0 // MACLO 0xxxxxxxx1, MACHI 0xxxxxxxx0 +`define OR1200_MAC_SPR_WE // Define if MACLO/MACHI are SPR writable + +// +// Shift {MACHI,MACLO} into destination register when executing l.macrc +// +// According to architecture manual there is no shift, so default value is 0. +// +// However the implementation has deviated in this from the arch manual and had hard coded shift by 28 bits which +// is a useful optimization for MP3 decoding (if using libmad fixed point library). Shifts are no longer +// default setup, but if you need to remain backward compatible, define your shift bits, which were normally +// dest_GPR = {MACHI,MACLO}[59:28] +`define OR1200_MAC_SHIFTBY 0 // 0 = According to arch manual, 28 = obsolete backward compatibility + + +////////////////////////////////////////////// +// +// Data MMU (DMMU) +// + +// +// Address that selects between TLB TR and MR +// +`define OR1200_DTLB_TM_ADDR 7 + +// +// DTLBMR fields +// +`define OR1200_DTLBMR_V_BITS 0 +`define OR1200_DTLBMR_CID_BITS 4:1 +`define OR1200_DTLBMR_RES_BITS 11:5 +`define OR1200_DTLBMR_VPN_BITS 31:13 + +// +// DTLBTR fields +// +`define OR1200_DTLBTR_CC_BITS 0 +`define OR1200_DTLBTR_CI_BITS 1 +`define OR1200_DTLBTR_WBC_BITS 2 +`define OR1200_DTLBTR_WOM_BITS 3 +`define OR1200_DTLBTR_A_BITS 4 +`define OR1200_DTLBTR_D_BITS 5 +`define OR1200_DTLBTR_URE_BITS 6 +`define OR1200_DTLBTR_UWE_BITS 7 +`define OR1200_DTLBTR_SRE_BITS 8 +`define OR1200_DTLBTR_SWE_BITS 9 +`define OR1200_DTLBTR_RES_BITS 11:10 +`define OR1200_DTLBTR_PPN_BITS 31:13 + +// +// DTLB configuration +// +`define OR1200_DMMU_PS 13 // 13 for 8KB page size +`define OR1200_DTLB_INDXW 6 // 6 for 64 entry DTLB 7 for 128 entries +`define OR1200_DTLB_INDXL `OR1200_DMMU_PS // 13 13 +`define OR1200_DTLB_INDXH `OR1200_DMMU_PS+`OR1200_DTLB_INDXW-1 // 18 19 +`define OR1200_DTLB_INDX `OR1200_DTLB_INDXH:`OR1200_DTLB_INDXL // 18:13 19:13 +`define OR1200_DTLB_TAGW 32-`OR1200_DTLB_INDXW-`OR1200_DMMU_PS // 13 12 +`define OR1200_DTLB_TAGL `OR1200_DTLB_INDXH+1 // 19 20 +`define OR1200_DTLB_TAG 31:`OR1200_DTLB_TAGL // 31:19 31:20 +`define OR1200_DTLBMRW `OR1200_DTLB_TAGW+1 // +1 because of V bit +`define OR1200_DTLBTRW 32-`OR1200_DMMU_PS+5 // +5 because of protection bits and CI + +// +// Cache inhibit while DMMU is not enabled/implemented +// +// cache inhibited 0GB-4GB 1'b1 +// cache inhibited 0GB-2GB !dcpu_adr_i[31] +// cache inhibited 0GB-1GB 2GB-3GB !dcpu_adr_i[30] +// cache inhibited 1GB-2GB 3GB-4GB dcpu_adr_i[30] +// cache inhibited 2GB-4GB (default) dcpu_adr_i[31] +// cached 0GB-4GB 1'b0 +// +`define OR1200_DMMU_CI dcpu_adr_i[31] + + +////////////////////////////////////////////// +// +// Insn MMU (IMMU) +// + +// +// Address that selects between TLB TR and MR +// +`define OR1200_ITLB_TM_ADDR 7 + +// +// ITLBMR fields +// +`define OR1200_ITLBMR_V_BITS 0 +`define OR1200_ITLBMR_CID_BITS 4:1 +`define OR1200_ITLBMR_RES_BITS 11:5 +`define OR1200_ITLBMR_VPN_BITS 31:13 + +// +// ITLBTR fields +// +`define OR1200_ITLBTR_CC_BITS 0 +`define OR1200_ITLBTR_CI_BITS 1 +`define OR1200_ITLBTR_WBC_BITS 2 +`define OR1200_ITLBTR_WOM_BITS 3 +`define OR1200_ITLBTR_A_BITS 4 +`define OR1200_ITLBTR_D_BITS 5 +`define OR1200_ITLBTR_SXE_BITS 6 +`define OR1200_ITLBTR_UXE_BITS 7 +`define OR1200_ITLBTR_RES_BITS 11:8 +`define OR1200_ITLBTR_PPN_BITS 31:13 + +// +// ITLB configuration +// +`define OR1200_IMMU_PS 13 // 13 for 8KB page size +`define OR1200_ITLB_INDXW 6 // 6 for 64 entry ITLB 7 for 128 entries +`define OR1200_ITLB_INDXL `OR1200_IMMU_PS // 13 13 +`define OR1200_ITLB_INDXH `OR1200_IMMU_PS+`OR1200_ITLB_INDXW-1 // 18 19 +`define OR1200_ITLB_INDX `OR1200_ITLB_INDXH:`OR1200_ITLB_INDXL // 18:13 19:13 +`define OR1200_ITLB_TAGW 32-`OR1200_ITLB_INDXW-`OR1200_IMMU_PS // 13 12 +`define OR1200_ITLB_TAGL `OR1200_ITLB_INDXH+1 // 19 20 +`define OR1200_ITLB_TAG 31:`OR1200_ITLB_TAGL // 31:19 31:20 +`define OR1200_ITLBMRW `OR1200_ITLB_TAGW+1 // +1 because of V bit +`define OR1200_ITLBTRW 32-`OR1200_IMMU_PS+3 // +3 because of protection bits and CI + +// +// Cache inhibit while IMMU is not enabled/implemented +// Note: all combinations that use icpu_adr_i cause async loop +// +// cache inhibited 0GB-4GB 1'b1 +// cache inhibited 0GB-2GB !icpu_adr_i[31] +// cache inhibited 0GB-1GB 2GB-3GB !icpu_adr_i[30] +// cache inhibited 1GB-2GB 3GB-4GB icpu_adr_i[30] +// cache inhibited 2GB-4GB (default) icpu_adr_i[31] +// cached 0GB-4GB 1'b0 +// +`define OR1200_IMMU_CI 1'b0 + + +///////////////////////////////////////////////// +// +// Insn cache (IC) +// + +// 3 for 8 bytes, 4 for 16 bytes etc +`define OR1200_ICLS 4 + +// +// IC configurations +// +`ifdef OR1200_IC_1W_512B +`define OR1200_ICSIZE 9 // 512 +`define OR1200_ICINDX `OR1200_ICSIZE-2 // 7 +`define OR1200_ICINDXH `OR1200_ICSIZE-1 // 8 +`define OR1200_ICTAGL `OR1200_ICINDXH+1 // 9 +`define OR1200_ICTAG `OR1200_ICSIZE-`OR1200_ICLS // 5 +`define OR1200_ICTAG_W 24 +`endif +`ifdef OR1200_IC_1W_4KB +`define OR1200_ICSIZE 12 // 4096 +`define OR1200_ICINDX `OR1200_ICSIZE-2 // 10 +`define OR1200_ICINDXH `OR1200_ICSIZE-1 // 11 +`define OR1200_ICTAGL `OR1200_ICINDXH+1 // 12 +`define OR1200_ICTAG `OR1200_ICSIZE-`OR1200_ICLS // 8 +`define OR1200_ICTAG_W 21 +`endif +`ifdef OR1200_IC_1W_8KB +`define OR1200_ICSIZE 13 // 8192 +`define OR1200_ICINDX `OR1200_ICSIZE-2 // 11 +`define OR1200_ICINDXH `OR1200_ICSIZE-1 // 12 +`define OR1200_ICTAGL `OR1200_ICINDXH+1 // 13 +`define OR1200_ICTAG `OR1200_ICSIZE-`OR1200_ICLS // 9 +`define OR1200_ICTAG_W 20 +`endif + + +///////////////////////////////////////////////// +// +// Data cache (DC) +// + +// 3 for 8 bytes, 4 for 16 bytes etc +`define OR1200_DCLS 4 + +// Define to perform store refill (potential performance penalty) +// `define OR1200_DC_STORE_REFILL + +// +// DC configurations +// +`ifdef OR1200_DC_1W_4KB +`define OR1200_DCSIZE 12 // 4096 +`define OR1200_DCINDX `OR1200_DCSIZE-2 // 10 +`define OR1200_DCINDXH `OR1200_DCSIZE-1 // 11 +`define OR1200_DCTAGL `OR1200_DCINDXH+1 // 12 +`define OR1200_DCTAG `OR1200_DCSIZE-`OR1200_DCLS // 8 +`define OR1200_DCTAG_W 21 +`endif +`ifdef OR1200_DC_1W_8KB +`define OR1200_DCSIZE 13 // 8192 +`define OR1200_DCINDX `OR1200_DCSIZE-2 // 11 +`define OR1200_DCINDXH `OR1200_DCSIZE-1 // 12 +`define OR1200_DCTAGL `OR1200_DCINDXH+1 // 13 +`define OR1200_DCTAG `OR1200_DCSIZE-`OR1200_DCLS // 9 +`define OR1200_DCTAG_W 20 +`endif + +///////////////////////////////////////////////// +// +// Store buffer (SB) +// + +// +// Store buffer +// +// It will improve performance by "caching" CPU stores +// using store buffer. This is most important for function +// prologues because DC can only work in write though mode +// and all stores would have to complete external WB writes +// to memory. +// Store buffer is between DC and data BIU. +// All stores will be stored into store buffer and immediately +// completed by the CPU, even though actual external writes +// will be performed later. As a consequence store buffer masks +// all data bus errors related to stores (data bus errors +// related to loads are delivered normally). +// All pending CPU loads will wait until store buffer is empty to +// ensure strict memory model. Right now this is necessary because +// we don't make destinction between cached and cache inhibited +// address space, so we simply empty store buffer until loads +// can begin. +// +// It makes design a bit bigger, depending what is the number of +// entries in SB FIFO. Number of entries can be changed further +// down. +// +//`define OR1200_SB_IMPLEMENTED + +// +// Number of store buffer entries +// +// Verified number of entries are 4 and 8 entries +// (2 and 3 for OR1200_SB_LOG). OR1200_SB_ENTRIES must +// always match 2**OR1200_SB_LOG. +// To disable store buffer, undefine +// OR1200_SB_IMPLEMENTED. +// +`define OR1200_SB_LOG 2 // 2 or 3 +`define OR1200_SB_ENTRIES 4 // 4 or 8 + + +///////////////////////////////////////////////// +// +// Quick Embedded Memory (QMEM) +// + +// +// Quick Embedded Memory +// +// Instantiation of dedicated insn/data memory (RAM or ROM). +// Insn fetch has effective throughput 1insn / clock cycle. +// Data load takes two clock cycles / access, data store +// takes 1 clock cycle / access (if there is no insn fetch)). +// Memory instantiation is shared between insn and data, +// meaning if insn fetch are performed, data load/store +// performance will be lower. +// +// Main reason for QMEM is to put some time critical functions +// into this memory and to have predictable and fast access +// to these functions. (soft fpu, context switch, exception +// handlers, stack, etc) +// +// It makes design a bit bigger and slower. QMEM sits behind +// IMMU/DMMU so all addresses are physical (so the MMUs can be +// used with QMEM and QMEM is seen by the CPU just like any other +// memory in the system). IC/DC are sitting behind QMEM so the +// whole design timing might be worse with QMEM implemented. +// +//`define OR1200_QMEM_IMPLEMENTED + +// +// Base address and mask of QMEM +// +// Base address defines first address of QMEM. Mask defines +// QMEM range in address space. Actual size of QMEM is however +// determined with instantiated RAM/ROM. However bigger +// mask will reserve more address space for QMEM, but also +// make design faster, while more tight mask will take +// less address space but also make design slower. If +// instantiated RAM/ROM is smaller than space reserved with +// the mask, instatiated RAM/ROM will also be shadowed +// at higher addresses in reserved space. +// +`define OR1200_QMEM_IADDR 32'h0080_0000 +`define OR1200_QMEM_IMASK 32'hfff0_0000 // Max QMEM size 1MB +`define OR1200_QMEM_DADDR 32'h0080_0000 +`define OR1200_QMEM_DMASK 32'hfff0_0000 // Max QMEM size 1MB + +// +// QMEM interface byte-select capability +// +// To enable qmem_sel* ports, define this macro. +// +//`define OR1200_QMEM_BSEL + +// +// QMEM interface acknowledge +// +// To enable qmem_ack port, define this macro. +// +//`define OR1200_QMEM_ACK + +///////////////////////////////////////////////////// +// +// VR, UPR and Configuration Registers +// +// +// VR, UPR and configuration registers are optional. If +// implemented, operating system can automatically figure +// out how to use the processor because it knows +// what units are available in the processor and how they +// are configured. +// +// This section must be last in or1200_defines.v file so +// that all units are already configured and thus +// configuration registers are properly set. +// + +// Define if you want configuration registers implemented +//`define OR1200_CFGR_IMPLEMENTED + +// Define if you want full address decode inside SYS group +`define OR1200_SYS_FULL_DECODE + +// Offsets of VR, UPR and CFGR registers +`define OR1200_SPRGRP_SYS_VR 4'h0 +`define OR1200_SPRGRP_SYS_UPR 4'h1 +`define OR1200_SPRGRP_SYS_CPUCFGR 4'h2 +`define OR1200_SPRGRP_SYS_DMMUCFGR 4'h3 +`define OR1200_SPRGRP_SYS_IMMUCFGR 4'h4 +`define OR1200_SPRGRP_SYS_DCCFGR 4'h5 +`define OR1200_SPRGRP_SYS_ICCFGR 4'h6 +`define OR1200_SPRGRP_SYS_DCFGR 4'h7 + +// VR fields +`define OR1200_VR_REV_BITS 5:0 +`define OR1200_VR_RES1_BITS 15:6 +`define OR1200_VR_CFG_BITS 23:16 +`define OR1200_VR_VER_BITS 31:24 + +// VR values +`define OR1200_VR_REV 6'h01 +`define OR1200_VR_RES1 10'h000 +`define OR1200_VR_CFG 8'h00 +`define OR1200_VR_VER 8'h12 + +// UPR fields +`define OR1200_UPR_UP_BITS 0 +`define OR1200_UPR_DCP_BITS 1 +`define OR1200_UPR_ICP_BITS 2 +`define OR1200_UPR_DMP_BITS 3 +`define OR1200_UPR_IMP_BITS 4 +`define OR1200_UPR_MP_BITS 5 +`define OR1200_UPR_DUP_BITS 6 +`define OR1200_UPR_PCUP_BITS 7 +`define OR1200_UPR_PMP_BITS 8 +`define OR1200_UPR_PICP_BITS 9 +`define OR1200_UPR_TTP_BITS 10 +`define OR1200_UPR_RES1_BITS 23:11 +`define OR1200_UPR_CUP_BITS 31:24 + +// UPR values +`define OR1200_UPR_UP 1'b1 +`ifdef OR1200_NO_DC +`define OR1200_UPR_DCP 1'b0 +`else +`define OR1200_UPR_DCP 1'b1 +`endif +`ifdef OR1200_NO_IC +`define OR1200_UPR_ICP 1'b0 +`else +`define OR1200_UPR_ICP 1'b1 +`endif +`ifdef OR1200_NO_DMMU +`define OR1200_UPR_DMP 1'b0 +`else +`define OR1200_UPR_DMP 1'b1 +`endif +`ifdef OR1200_NO_IMMU +`define OR1200_UPR_IMP 1'b0 +`else +`define OR1200_UPR_IMP 1'b1 +`endif +`define OR1200_UPR_MP 1'b1 // MAC always present +`ifdef OR1200_DU_IMPLEMENTED +`define OR1200_UPR_DUP 1'b1 +`else +`define OR1200_UPR_DUP 1'b0 +`endif +`define OR1200_UPR_PCUP 1'b0 // Performance counters not present +`ifdef OR1200_DU_IMPLEMENTED +`define OR1200_UPR_PMP 1'b1 +`else +`define OR1200_UPR_PMP 1'b0 +`endif +`ifdef OR1200_DU_IMPLEMENTED +`define OR1200_UPR_PICP 1'b1 +`else +`define OR1200_UPR_PICP 1'b0 +`endif +`ifdef OR1200_DU_IMPLEMENTED +`define OR1200_UPR_TTP 1'b1 +`else +`define OR1200_UPR_TTP 1'b0 +`endif +`define OR1200_UPR_RES1 13'h0000 +`define OR1200_UPR_CUP 8'h00 + +// CPUCFGR fields +`define OR1200_CPUCFGR_NSGF_BITS 3:0 +`define OR1200_CPUCFGR_HGF_BITS 4 +`define OR1200_CPUCFGR_OB32S_BITS 5 +`define OR1200_CPUCFGR_OB64S_BITS 6 +`define OR1200_CPUCFGR_OF32S_BITS 7 +`define OR1200_CPUCFGR_OF64S_BITS 8 +`define OR1200_CPUCFGR_OV64S_BITS 9 +`define OR1200_CPUCFGR_RES1_BITS 31:10 + +// CPUCFGR values +`define OR1200_CPUCFGR_NSGF 4'h0 +`define OR1200_CPUCFGR_HGF 1'b0 +`define OR1200_CPUCFGR_OB32S 1'b1 +`define OR1200_CPUCFGR_OB64S 1'b0 +`define OR1200_CPUCFGR_OF32S 1'b0 +`define OR1200_CPUCFGR_OF64S 1'b0 +`define OR1200_CPUCFGR_OV64S 1'b0 +`define OR1200_CPUCFGR_RES1 22'h000000 + +// DMMUCFGR fields +`define OR1200_DMMUCFGR_NTW_BITS 1:0 +`define OR1200_DMMUCFGR_NTS_BITS 4:2 +`define OR1200_DMMUCFGR_NAE_BITS 7:5 +`define OR1200_DMMUCFGR_CRI_BITS 8 +`define OR1200_DMMUCFGR_PRI_BITS 9 +`define OR1200_DMMUCFGR_TEIRI_BITS 10 +`define OR1200_DMMUCFGR_HTR_BITS 11 +`define OR1200_DMMUCFGR_RES1_BITS 31:12 + +// DMMUCFGR values +`ifdef OR1200_NO_DMMU +`define OR1200_DMMUCFGR_NTW 2'h0 // Irrelevant +`define OR1200_DMMUCFGR_NTS 3'h0 // Irrelevant +`define OR1200_DMMUCFGR_NAE 3'h0 // Irrelevant +`define OR1200_DMMUCFGR_CRI 1'b0 // Irrelevant +`define OR1200_DMMUCFGR_PRI 1'b0 // Irrelevant +`define OR1200_DMMUCFGR_TEIRI 1'b0 // Irrelevant +`define OR1200_DMMUCFGR_HTR 1'b0 // Irrelevant +`define OR1200_DMMUCFGR_RES1 20'h00000 +`else +`define OR1200_DMMUCFGR_NTW 2'h0 // 1 TLB way +`define OR1200_DMMUCFGR_NTS 3'h`OR1200_DTLB_INDXW // Num TLB sets +`define OR1200_DMMUCFGR_NAE 3'h0 // No ATB entries +`define OR1200_DMMUCFGR_CRI 1'b0 // No control register +`define OR1200_DMMUCFGR_PRI 1'b0 // No protection reg +`define OR1200_DMMUCFGR_TEIRI 1'b1 // TLB entry inv reg impl. +`define OR1200_DMMUCFGR_HTR 1'b0 // No HW TLB reload +`define OR1200_DMMUCFGR_RES1 20'h00000 +`endif + +// IMMUCFGR fields +`define OR1200_IMMUCFGR_NTW_BITS 1:0 +`define OR1200_IMMUCFGR_NTS_BITS 4:2 +`define OR1200_IMMUCFGR_NAE_BITS 7:5 +`define OR1200_IMMUCFGR_CRI_BITS 8 +`define OR1200_IMMUCFGR_PRI_BITS 9 +`define OR1200_IMMUCFGR_TEIRI_BITS 10 +`define OR1200_IMMUCFGR_HTR_BITS 11 +`define OR1200_IMMUCFGR_RES1_BITS 31:12 + +// IMMUCFGR values +`ifdef OR1200_NO_IMMU +`define OR1200_IMMUCFGR_NTW 2'h0 // Irrelevant +`define OR1200_IMMUCFGR_NTS 3'h0 // Irrelevant +`define OR1200_IMMUCFGR_NAE 3'h0 // Irrelevant +`define OR1200_IMMUCFGR_CRI 1'b0 // Irrelevant +`define OR1200_IMMUCFGR_PRI 1'b0 // Irrelevant +`define OR1200_IMMUCFGR_TEIRI 1'b0 // Irrelevant +`define OR1200_IMMUCFGR_HTR 1'b0 // Irrelevant +`define OR1200_IMMUCFGR_RES1 20'h00000 +`else +`define OR1200_IMMUCFGR_NTW 2'h0 // 1 TLB way +`define OR1200_IMMUCFGR_NTS 3'h`OR1200_ITLB_INDXW // Num TLB sets +`define OR1200_IMMUCFGR_NAE 3'h0 // No ATB entry +`define OR1200_IMMUCFGR_CRI 1'b0 // No control reg +`define OR1200_IMMUCFGR_PRI 1'b0 // No protection reg +`define OR1200_IMMUCFGR_TEIRI 1'b1 // TLB entry inv reg impl +`define OR1200_IMMUCFGR_HTR 1'b0 // No HW TLB reload +`define OR1200_IMMUCFGR_RES1 20'h00000 +`endif + +// DCCFGR fields +`define OR1200_DCCFGR_NCW_BITS 2:0 +`define OR1200_DCCFGR_NCS_BITS 6:3 +`define OR1200_DCCFGR_CBS_BITS 7 +`define OR1200_DCCFGR_CWS_BITS 8 +`define OR1200_DCCFGR_CCRI_BITS 9 +`define OR1200_DCCFGR_CBIRI_BITS 10 +`define OR1200_DCCFGR_CBPRI_BITS 11 +`define OR1200_DCCFGR_CBLRI_BITS 12 +`define OR1200_DCCFGR_CBFRI_BITS 13 +`define OR1200_DCCFGR_CBWBRI_BITS 14 +`define OR1200_DCCFGR_RES1_BITS 31:15 + +// DCCFGR values +`ifdef OR1200_NO_DC +`define OR1200_DCCFGR_NCW 3'h0 // Irrelevant +`define OR1200_DCCFGR_NCS 4'h0 // Irrelevant +`define OR1200_DCCFGR_CBS 1'b0 // Irrelevant +`define OR1200_DCCFGR_CWS 1'b0 // Irrelevant +`define OR1200_DCCFGR_CCRI 1'b1 // Irrelevant +`define OR1200_DCCFGR_CBIRI 1'b1 // Irrelevant +`define OR1200_DCCFGR_CBPRI 1'b0 // Irrelevant +`define OR1200_DCCFGR_CBLRI 1'b0 // Irrelevant +`define OR1200_DCCFGR_CBFRI 1'b1 // Irrelevant +`define OR1200_DCCFGR_CBWBRI 1'b0 // Irrelevant +`define OR1200_DCCFGR_RES1 17'h00000 +`else +`define OR1200_DCCFGR_NCW 3'h0 // 1 cache way +`define OR1200_DCCFGR_NCS (`OR1200_DCTAG) // Num cache sets +`define OR1200_DCCFGR_CBS (`OR1200_DCLS-4) // 16 byte cache block +`define OR1200_DCCFGR_CWS 1'b0 // Write-through strategy +`define OR1200_DCCFGR_CCRI 1'b1 // Cache control reg impl. +`define OR1200_DCCFGR_CBIRI 1'b1 // Cache block inv reg impl. +`define OR1200_DCCFGR_CBPRI 1'b0 // Cache block prefetch reg not impl. +`define OR1200_DCCFGR_CBLRI 1'b0 // Cache block lock reg not impl. +`define OR1200_DCCFGR_CBFRI 1'b1 // Cache block flush reg impl. +`define OR1200_DCCFGR_CBWBRI 1'b0 // Cache block WB reg not impl. +`define OR1200_DCCFGR_RES1 17'h00000 +`endif + +// ICCFGR fields +`define OR1200_ICCFGR_NCW_BITS 2:0 +`define OR1200_ICCFGR_NCS_BITS 6:3 +`define OR1200_ICCFGR_CBS_BITS 7 +`define OR1200_ICCFGR_CWS_BITS 8 +`define OR1200_ICCFGR_CCRI_BITS 9 +`define OR1200_ICCFGR_CBIRI_BITS 10 +`define OR1200_ICCFGR_CBPRI_BITS 11 +`define OR1200_ICCFGR_CBLRI_BITS 12 +`define OR1200_ICCFGR_CBFRI_BITS 13 +`define OR1200_ICCFGR_CBWBRI_BITS 14 +`define OR1200_ICCFGR_RES1_BITS 31:15 + +// ICCFGR values +`ifdef OR1200_NO_IC +`define OR1200_ICCFGR_NCW 3'h0 // Irrelevant +`define OR1200_ICCFGR_NCS 4'h0 // Irrelevant +`define OR1200_ICCFGR_CBS 1'b0 // Irrelevant +`define OR1200_ICCFGR_CWS 1'b0 // Irrelevant +`define OR1200_ICCFGR_CCRI 1'b0 // Irrelevant +`define OR1200_ICCFGR_CBIRI 1'b0 // Irrelevant +`define OR1200_ICCFGR_CBPRI 1'b0 // Irrelevant +`define OR1200_ICCFGR_CBLRI 1'b0 // Irrelevant +`define OR1200_ICCFGR_CBFRI 1'b0 // Irrelevant +`define OR1200_ICCFGR_CBWBRI 1'b0 // Irrelevant +`define OR1200_ICCFGR_RES1 17'h00000 +`else +`define OR1200_ICCFGR_NCW 3'h0 // 1 cache way +`define OR1200_ICCFGR_NCS (`OR1200_ICTAG) // Num cache sets +`define OR1200_ICCFGR_CBS (`OR1200_ICLS-4) // 16 byte cache block +`define OR1200_ICCFGR_CWS 1'b0 // Irrelevant +`define OR1200_ICCFGR_CCRI 1'b1 // Cache control reg impl. +`define OR1200_ICCFGR_CBIRI 1'b1 // Cache block inv reg impl. +`define OR1200_ICCFGR_CBPRI 1'b0 // Cache block prefetch reg not impl. +`define OR1200_ICCFGR_CBLRI 1'b0 // Cache block lock reg not impl. +`define OR1200_ICCFGR_CBFRI 1'b1 // Cache block flush reg impl. +`define OR1200_ICCFGR_CBWBRI 1'b0 // Irrelevant +`define OR1200_ICCFGR_RES1 17'h00000 +`endif + +// DCFGR fields +`define OR1200_DCFGR_NDP_BITS 2:0 +`define OR1200_DCFGR_WPCI_BITS 3 +`define OR1200_DCFGR_RES1_BITS 31:4 + +// DCFGR values +`ifdef OR1200_DU_HWBKPTS +`define OR1200_DCFGR_NDP 3'h`OR1200_DU_DVRDCR_PAIRS // # of DVR/DCR pairs +`ifdef OR1200_DU_DWCR0 +`define OR1200_DCFGR_WPCI 1'b1 +`else +`define OR1200_DCFGR_WPCI 1'b0 // WP counters not impl. +`endif +`else +`define OR1200_DCFGR_NDP 3'h0 // Zero DVR/DCR pairs +`define OR1200_DCFGR_WPCI 1'b0 // WP counters not impl. +`endif +`define OR1200_DCFGR_RES1 28'h0000000 + Index: release-1.0/backend/spartan3a_dsp_kit/minsoc_defines.v =================================================================== --- release-1.0/backend/spartan3a_dsp_kit/minsoc_defines.v (nonexistent) +++ release-1.0/backend/spartan3a_dsp_kit/minsoc_defines.v (revision 151) @@ -0,0 +1,150 @@ +// +// Define FPGA manufacturer +// +//`define GENERIC_FPGA +//`define ALTERA_FPGA +`define XILINX_FPGA + +// +// Define Xilinx FPGA family +// +`ifdef XILINX_FPGA +//`define SPARTAN2 +//`define SPARTAN3 +//`define SPARTAN3E +`define SPARTAN3A +//`define VIRTEX +//`define VIRTEX2 +//`define VIRTEX4 +//`define VIRTEX5 + +// +// Define Altera FPGA family +// +`elsif ALTERA_FPGA +//`define ARRIA_GX +//`define ARRIA_II_GX +//`define CYCLONE_I +//`define CYCLONE_II +`define CYCLONE_III +//`define CYCLONE_III_LS +//`define CYCLONE_IV_E +//`define CYCLONE_IV_GS +//`define MAX_II +//`define MAX_V +//`define MAX3000A +//`define MAX7000AE +//`define MAX7000B +//`define MAX7000S +//`define STRATIX +//`define STRATIX_II +//`define STRATIX_II_GX +//`define STRATIX_III +`endif + +// +// Memory +// +`define MEMORY_ADR_WIDTH 15 //MEMORY_ADR_WIDTH IS NOT ALLOWED TO BE LESS THAN 12, + //memory is composed by blocks of address width 11 + //Address width of memory -> select memory depth, + //2 powers MEMORY_ADR_WIDTH defines the memory depth + //the memory data width is 32 bit, + //memory amount in Bytes = 4*memory depth + +// +// Memory type (uncomment something if ASIC or generic memory) +// +//`define GENERIC_MEMORY +//`define AVANT_ATP +//`define VIRAGE_SSP +//`define VIRTUALSILICON_SSP + + +// +// TAP selection +// +//`define GENERIC_TAP +`define FPGA_TAP + +// +// Clock Division selection +// +//`define NO_CLOCK_DIVISION +//`define GENERIC_CLOCK_DIVISION +`define FPGA_CLOCK_DIVISION // For Altera ALTPLL, only CYCLONE_III family has been tested. + +// +// Define division +// +`define CLOCK_DIVISOR 5 //in case of GENERIC_CLOCK_DIVISION the real value will be rounded + //down to an even value in FPGA case, check minsoc_clock_manager + //for allowed divisors. + //DO NOT USE CLOCK_DIVISOR = 1 COMMENT THE CLOCK DIVISION SELECTION + //INSTEAD. + +// +// Reset polarity +// +//`define NEGATIVE_RESET //rstn +`define POSITIVE_RESET //rst + +// +// Start-up circuit (only necessary later to load firmware automatically from SPI memory) +// +//`define START_UP + +// +// Connected modules +// +`define UART +`define ETHERNET + +// +// Ethernet reset +// +//`define ETH_RESET 1'b0 +`define ETH_RESET 1'b1 + +// +// Interrupts +// +`define APP_INT_RES1 1:0 +`define APP_INT_UART 2 +`define APP_INT_RES2 3 +`define APP_INT_ETH 4 +`define APP_INT_PS2 5 +`define APP_INT_RES3 19:6 + +// +// Address map +// +`define APP_ADDR_DEC_W 8 +`define APP_ADDR_SRAM `APP_ADDR_DEC_W'h00 +`define APP_ADDR_FLASH `APP_ADDR_DEC_W'h04 +`define APP_ADDR_DECP_W 4 +`define APP_ADDR_PERIP `APP_ADDR_DECP_W'h9 +`define APP_ADDR_SPI `APP_ADDR_DEC_W'h97 +`define APP_ADDR_ETH `APP_ADDR_DEC_W'h92 +`define APP_ADDR_AUDIO `APP_ADDR_DEC_W'h9d +`define APP_ADDR_UART `APP_ADDR_DEC_W'h90 +`define APP_ADDR_PS2 `APP_ADDR_DEC_W'h94 +`define APP_ADDR_RES1 `APP_ADDR_DEC_W'h9e +`define APP_ADDR_RES2 `APP_ADDR_DEC_W'h9f + +// +// Set-up GENERIC_TAP, GENERIC_MEMORY if GENERIC_FPGA was chosen +// and GENERIC_CLOCK_DIVISION if NO_CLOCK_DIVISION was not set +// +`ifdef GENERIC_FPGA + `undef FPGA_TAP + `undef FPGA_CLOCK_DIVISION + `undef XILINX_FPGA + `undef SPARTAN3A + + `define GENERIC_TAP + `define GENERIC_MEMORY + `ifndef NO_CLOCK_DIVISION + `define GENERIC_CLOCK_DIVISION + `endif +`endif Index: release-1.0/backend/spartan3a_dsp_kit/gcc-opt.mk =================================================================== --- release-1.0/backend/spartan3a_dsp_kit/gcc-opt.mk (nonexistent) +++ release-1.0/backend/spartan3a_dsp_kit/gcc-opt.mk (revision 151) @@ -0,0 +1 @@ +GCC_OPT=-mhard-mul -mhard-div -nostdlib Index: release-1.0/backend/spartan3a_dsp_kit/spartan3a_dsp_kit.ucf =================================================================== --- release-1.0/backend/spartan3a_dsp_kit/spartan3a_dsp_kit.ucf (nonexistent) +++ release-1.0/backend/spartan3a_dsp_kit/spartan3a_dsp_kit.ucf (revision 151) @@ -0,0 +1,72 @@ +########################### +## +## Global signals +## +net "clk" loc = "f13"; #125MHz clock +net "reset" loc = "j17"; #SW5 +########################### + +########################### +## +## JTAG +## +#net "jtag_tms" loc = "aa23"; #SAM D0 +#net "jtag_tdi" loc = "u20"; #SAM D2 +#net "jtag_tdo" loc = "aa25"; #SAM D4 +#net "jtag_tck" loc = "u18" | CLOCK_DEDICATED_ROUTE = FALSE; #SAM D6 +#net "jtag_gnd" loc = "y23"; #SAM D8 +#net "jtag_vref" loc = "t20"; #SAM D10 +########################### + +############################# +## +## SPI Flash External Memory +## +#NET "spi_flash_mosi" LOC = "ab15"; +#NET "spi_flash_miso" LOC = "af24"; +#NET "spi_flash_sclk" LOC = "ae24"; +#NET "spi_flash_ss(1)" LOC = "ac25"; +#NET "spi_flash_ss(0)" LOC = "aa7"; +########################### + +########################### +## +## UART +## +net "uart_stx" loc = "p22"; +net "uart_srx" loc = "n21"; +########################### + +########################### +## +## ETH +## +NET "eth_txd(3)" LOC = "b1"; +NET "eth_txd(2)" LOC = "b2"; +NET "eth_txd(1)" LOC = "j9"; +NET "eth_txd(0)" LOC = "j8"; + +NET "eth_tx_en" LOC = "d3"; +NET "eth_tx_clk" LOC = "p2"; +NET "eth_tx_er" LOC = "e4"; + +NET "eth_rxd(3)" LOC = "d2"; +NET "eth_rxd(2)" LOC = "g5"; +NET "eth_rxd(1)" LOC = "g2"; +NET "eth_rxd(0)" LOC = "c2"; + +NET "eth_rx_er" LOC = "j3"; +NET "eth_rx_dv" LOC = "d1"; + +NET "eth_rx_clk" LOC = "p1"; + +NET "eth_mdio" LOC = "f5" | PULLUP; +NET "eth_crs" LOC = "g1"; +NET "eth_col" LOC = "y3"; +NET "eth_mdc" LOC = "f4"; + +NET "eth_trste" LOC = "g4"; + +NET "eth_fds_mdint" LOC = "j1"; +########################### +
release-1.0/backend/spartan3a_dsp_kit/spartan3a_dsp_kit.ucf Property changes : Added: svn:executable ## -0,0 +1 ## +* \ No newline at end of property Index: release-1.0/backend/spartan3a_dsp_kit/board.h =================================================================== --- release-1.0/backend/spartan3a_dsp_kit/board.h (nonexistent) +++ release-1.0/backend/spartan3a_dsp_kit/board.h (revision 151) @@ -0,0 +1,40 @@ +#ifndef _BOARD_H_ +#define _BOARD_H_ + +#define MC_ENABLED 0 + +#define IC_ENABLE 0 +#define IC_SIZE 8192 +#define DC_ENABLE 0 +#define DC_SIZE 8192 + + +#define IN_CLK 25000000 + + +#define STACK_SIZE 0x01000 + +#define UART_BAUD_RATE 115200 + +#define UART_BASE 0x90000000 +#define UART_IRQ 2 +#define ETH_BASE 0x92000000 +#define ETH_IRQ 4 +#define I2C_BASE 0x9D000000 +#define I2C_IRQ 3 +#define CAN_BASE 0x94000000 +#define CAN_IRQ 5 + +#define MC_BASE_ADDR 0x60000000 +#define SPI_BASE 0xa0000000 + +#define ETH_DATA_BASE 0xa8000000 /* Address for ETH_DATA */ + +#define ETH_MACADDR0 0x00 +#define ETH_MACADDR1 0x12 +#define ETH_MACADDR2 0x34 +#define ETH_MACADDR3 0x56 +#define ETH_MACADDR4 0x78 +#define ETH_MACADDR5 0x9a + +#endif
release-1.0/backend/spartan3a_dsp_kit/board.h Property changes : Added: svn:executable ## -0,0 +1 ## +* \ No newline at end of property Index: release-1.0/backend/spartan3a_dsp_kit/orp.ld =================================================================== --- release-1.0/backend/spartan3a_dsp_kit/orp.ld (nonexistent) +++ release-1.0/backend/spartan3a_dsp_kit/orp.ld (revision 151) @@ -0,0 +1,60 @@ +MEMORY + { + reset : ORIGIN = 0x00000000, LENGTH = 0x00000200 + vectors : ORIGIN = 0x00000200, LENGTH = 0x00001000 + ram : ORIGIN = 0x00001200, LENGTH = 0x0001EE00 /*0x20000 total*/ + } + +SECTIONS +{ + .reset : + { + *(.reset) + } > reset + + + + .vectors : + { + _vec_start = .; + *(.vectors) + _vec_end = .; + } > vectors + + .text : + { + *(.text) + } > ram + + .rodata : + { + *(.rodata) + *(.rodata.*) + } > ram + + .icm : + { + _icm_start = .; + *(.icm) + _icm_end = .; + } > ram + + .data : + { + _dst_beg = .; + *(.data) + _dst_end = .; + } > ram + + .bss : + { + *(.bss) + } > ram + + .stack (NOLOAD) : + { + *(.stack) + _src_addr = .; + } > ram + +}
release-1.0/backend/spartan3a_dsp_kit/orp.ld Property changes : Added: svn:executable ## -0,0 +1 ## +* \ No newline at end of property Index: release-1.0/backend/ug257/minsoc_bench_defines.v =================================================================== --- release-1.0/backend/ug257/minsoc_bench_defines.v (nonexistent) +++ release-1.0/backend/ug257/minsoc_bench_defines.v (revision 151) @@ -0,0 +1,29 @@ +//set RTL for simulation, override FPGA specific definitions (JTAG TAP, MEMORY and CLOCK DIVIDER) +`define GENERIC_FPGA +`define MEMORY_MODEL //simulation uses a memory model enabling INITIALIZE_MEMORY_MODEL. If you comment this, START_UP might be interesting. +`define NO_CLOCK_DIVISION //if commented out, generic clock division is implemented (odd divisors are rounded down) +//~set RTL for simulation, override FPGA specific definitions (JTAG TAP, MEMORY and CLOCK DIVIDER) + +`define FREQ_NUM_FOR_NS 100000000 + +`define FREQ 10000000 +`define CLK_PERIOD (`FREQ_NUM_FOR_NS/`FREQ) + +`define ETH_PHY_FREQ 25000000 +`define ETH_PHY_PERIOD (`FREQ_NUM_FOR_NS/`ETH_PHY_FREQ) //40ns + +`define UART_BAUDRATE 9600 + +`define VPI_DEBUG + +//`define WAVEFORM_OUTPUT + +//`define START_UP //pass firmware over spi to or1k_startup + +`define INITIALIZE_MEMORY_MODEL //instantaneously initialize memory model with firmware + //only use with the memory model. + //If you use the original memory (`define MEMORY_MODEL + //commented out), comment this too. + +`define TEST_UART +//`define TEST_ETHERNET
release-1.0/backend/ug257/minsoc_bench_defines.v Property changes : Added: svn:executable ## -0,0 +1 ## +* \ No newline at end of property Index: release-1.0/backend/ug257/configure =================================================================== --- release-1.0/backend/ug257/configure (nonexistent) +++ release-1.0/backend/ug257/configure (revision 151) @@ -0,0 +1,132 @@ +#!/bin/bash + +#NON STANDARD SCRIPT, USE ANOTHER AS TEMPLATE, NON STANDARD PART IS MARKED AS COMMENT + +#new boards have to udpate this +BOARD=ug257 #this has to have the name of the directory this file is in +DEVICE_PART='xc3s1600e-4-fg320' +CONSTRAINT_FILE='ug257.ucf' +#~new boards update + +#system workings +MINSOC_DIR=`pwd`/../.. +BACKEND_DIR=$MINSOC_DIR/backend +SYN_DIR=$MINSOC_DIR/syn +SYNSRC_DIR=$MINSOC_DIR/prj/xilinx +SYNSUPPORT_DIR=$SYN_DIR/buildSupport +MAKEFILE_DIR=$SYN_DIR/xilinx + +SYN_FILES=(ethmac.xst uart_top.xst adbg_top.xst or1200_top.xst minsoc_top.xst) +MAKEFILE=Makefile + +FIND_PART='DEVICE_PART' +FIND_CONSTRAINT='CONSTRAINT_FILE' + +BOARD_DIR=$BACKEND_DIR/$BOARD +BOARD_FILES=(board.h orp.ld minsoc_defines.v minsoc_bench_defines.v gcc-opt.mk $CONSTRAINT_FILE) + +in_minsoc=`pwd | grep minsoc/backend/${BOARD}$` +if [ -z $in_minsoc ] +then + echo "" + echo " !!!WARNING!!!" + echo "This script cannot be run if not in a board directory inside minsoc/backend," + echo "because it relies on the directory structure of the minsoc system." + echo "" + echo "Possibly your minsoc directory is named differently, minsoc_trunk for example." + echo "Its name must be minsoc only." + echo "" + exit 1 +fi + +#NON STANDARD SCRIPT PART +echo "THIS SCRIPT HAS A NON-STANDARD BEGINNING." +echo "__________________________________________________________________________" +echo "${BOARD} requires another configuration for or1200_rel1." + +echo "" +echo "Copying or1200_defines.v, to or1200 implementation directory..." +echo "(minsoc/rtl/verilog/or1200/rtl/verilog)" +echo "__________________________________________________________________________" +cp $BOARD_DIR/or1200_defines.v $MINSOC_DIR/rtl/verilog/or1200/rtl/verilog +echo "" +echo "REGULAR SCRIPT STARTS NOW" +echo "__________________________________________________________________________" +#~NON STANDARD SCRIPT PART + +echo "" +echo "This script sets up the SoC for simulations and synthesis." +echo "" +echo "In order to do so, SoC board's specific files for firmware compilation, " +echo "testbench generation and synthesis are configured." +echo "Firmware and testbench looks for board specific files under $BACKEND_DIR." +echo "Synthesis work under $SYN_DIR." +echo "" +echo "" + +echo "Copying board specific SoC files from $BOARD_DIR to $BACKEND_DIR directory." +echo "__________________________________________________________________________" +echo "" +for file in "${BOARD_FILES[@]}" +do + if [ $file != NONE ] + then + echo "Copying $file, to backend directory..." + cp $BOARD_DIR/$file $BACKEND_DIR + fi +done +echo "" +echo "" + +echo "Generating project files for simulation and synthesis..." +echo "__________________________________________________________________________" +echo "" +make -C $MINSOC_DIR/prj +echo "Generation complete." +echo "" +echo "" + +if [ $CONSTRAINT_FILE == 'NONE' ] +then + echo "Skipping synthesis preparation. Standard implementation can only be simulated." + echo "" + echo "" +else + echo "Device part for files under $SYNSRC_DIR will be patched and stored " + echo "temporarily." + echo "Afterwards, they are copied to $SYNSUPPORT_DIR." + echo "__________________________________________________________________________" + echo "" + for file in "${SYN_FILES[@]}" + do + echo "Updating synthesis file, $file..." + echo "Copying $file to synthesis directory..." + echo "" + sed "s/$FIND_PART/$DEVICE_PART/g" $SYNSRC_DIR/$file > TMPFILE + sed "s/$FIND_CONSTRAINT/$CONSTRAINT_FILE/g" TMPFILE > TMPFILE2 && mv TMPFILE2 $SYNSUPPORT_DIR/$file + rm TMPFILE + done + + echo "Updating Makefile file under $MAKEFILE_DIR..." + echo "Copying Makefile to synthesis directory, $SYN_DIR..." + echo "" + sed "s/$FIND_PART/$DEVICE_PART/g" $MAKEFILE_DIR/$MAKEFILE > TMPFILE + sed "s/$FIND_CONSTRAINT/$CONSTRAINT_FILE/g" TMPFILE > TMPFILE2 && mv TMPFILE2 $SYN_DIR/$MAKEFILE + rm TMPFILE + cp $MAKEFILE_DIR/setup.bat $SYN_DIR/setup.bat + echo "" + echo "" +fi + +#Precompiling firmwares +echo "Precompiling delivered libraries and firmwares..." +make -C ../../sw/utils +make -C ../../sw/support +make -C ../../sw/drivers +make -C ../../sw/uart +make -C ../../sw/eth +echo "done." +echo "" +echo "" + +echo "Configuration done."
release-1.0/backend/ug257/configure Property changes : Added: svn:executable ## -0,0 +1 ## +* \ No newline at end of property Index: release-1.0/backend/ug257/gcc-opt.mk =================================================================== --- release-1.0/backend/ug257/gcc-opt.mk (nonexistent) +++ release-1.0/backend/ug257/gcc-opt.mk (revision 151) @@ -0,0 +1 @@ +GCC_OPT=-mhard-mul -mhard-div -nostdlib Index: release-1.0/backend/ug257/or1200_defines.v =================================================================== --- release-1.0/backend/ug257/or1200_defines.v (nonexistent) +++ release-1.0/backend/ug257/or1200_defines.v (revision 151) @@ -0,0 +1,1754 @@ +////////////////////////////////////////////////////////////////////// +//// //// +//// OR1200's definitions //// +//// //// +//// This file is part of the OpenRISC 1200 project //// +//// http://www.opencores.org/cores/or1k/ //// +//// //// +//// Description //// +//// Parameters of the OR1200 core //// +//// //// +//// To Do: //// +//// - add parameters that are missing //// +//// //// +//// Author(s): //// +//// - Damjan Lampret, lampret@opencores.org //// +//// //// +////////////////////////////////////////////////////////////////////// +//// //// +//// Copyright (C) 2000 Authors and OPENCORES.ORG //// +//// //// +//// This source file may be used and distributed without //// +//// restriction provided that this copyright statement is not //// +//// removed from the file and that any derivative work contains //// +//// the original copyright notice and the associated disclaimer. //// +//// //// +//// This source file is free software; you can redistribute it //// +//// and/or modify it under the terms of the GNU Lesser General //// +//// Public License as published by the Free Software Foundation; //// +//// either version 2.1 of the License, or (at your option) any //// +//// later version. //// +//// //// +//// This source is distributed in the hope that it will be //// +//// useful, but WITHOUT ANY WARRANTY; without even the implied //// +//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR //// +//// PURPOSE. See the GNU Lesser General Public License for more //// +//// details. //// +//// //// +//// You should have received a copy of the GNU Lesser General //// +//// Public License along with this source; if not, download it //// +//// from http://www.opencores.org/lgpl.shtml //// +//// //// +////////////////////////////////////////////////////////////////////// +// +// CVS Revision History +// +// $Log: not supported by cvs2svn $ +// Revision 1.44 2005/10/19 11:37:56 jcastillo +// Added support for RAMB16 Xilinx4/Spartan3 primitives +// +// Revision 1.43 2005/01/07 09:23:39 andreje +// l.ff1 and l.cmov instructions added +// +// Revision 1.42 2004/06/08 18:17:36 lampret +// Non-functional changes. Coding style fixes. +// +// Revision 1.41 2004/05/09 20:03:20 lampret +// By default l.cust5 insns are disabled +// +// Revision 1.40 2004/05/09 19:49:04 lampret +// Added some l.cust5 custom instructions as example +// +// Revision 1.39 2004/04/08 11:00:46 simont +// Add support for 512B instruction cache. +// +// Revision 1.38 2004/04/05 08:29:57 lampret +// Merged branch_qmem into main tree. +// +// Revision 1.35.4.6 2004/02/11 01:40:11 lampret +// preliminary HW breakpoints support in debug unit (by default disabled). To enable define OR1200_DU_HWBKPTS. +// +// Revision 1.35.4.5 2004/01/15 06:46:38 markom +// interface to debug changed; no more opselect; stb-ack protocol +// +// Revision 1.35.4.4 2004/01/11 22:45:46 andreje +// Separate instruction and data QMEM decoders, QMEM acknowledge and byte-select added +// +// Revision 1.35.4.3 2003/12/17 13:43:38 simons +// Exception prefix configuration changed. +// +// Revision 1.35.4.2 2003/12/05 00:05:03 lampret +// Static exception prefix. +// +// Revision 1.35.4.1 2003/07/08 15:36:37 lampret +// Added embedded memory QMEM. +// +// Revision 1.35 2003/04/24 00:16:07 lampret +// No functional changes. Added defines to disable implementation of multiplier/MAC +// +// Revision 1.34 2003/04/20 22:23:57 lampret +// No functional change. Only added customization for exception vectors. +// +// Revision 1.33 2003/04/07 20:56:07 lampret +// Fixed OR1200_CLKDIV_x_SUPPORTED defines. Better description. +// +// Revision 1.32 2003/04/07 01:26:57 lampret +// RFRAM defines comments updated. Altera LPM option added. +// +// Revision 1.31 2002/12/08 08:57:56 lampret +// Added optional support for WB B3 specification (xwb_cti_o, xwb_bte_o). Made xwb_cab_o optional. +// +// Revision 1.30 2002/10/28 15:09:22 mohor +// Previous check-in was done by mistake. +// +// Revision 1.29 2002/10/28 15:03:50 mohor +// Signal scanb_sen renamed to scanb_en. +// +// Revision 1.28 2002/10/17 20:04:40 lampret +// Added BIST scan. Special VS RAMs need to be used to implement BIST. +// +// Revision 1.27 2002/09/16 03:13:23 lampret +// Removed obsolete comment. +// +// Revision 1.26 2002/09/08 05:52:16 lampret +// Added optional l.div/l.divu insns. By default they are disabled. +// +// Revision 1.25 2002/09/07 19:16:10 lampret +// If SR[CY] implemented with OR1200_IMPL_ADDC enabled, l.add/l.addi also set SR[CY]. +// +// Revision 1.24 2002/09/07 05:42:02 lampret +// Added optional SR[CY]. Added define to enable additional (compare) flag modifiers. Defines are OR1200_IMPL_ADDC and OR1200_ADDITIONAL_FLAG_MODIFIERS. +// +// Revision 1.23 2002/09/04 00:50:34 lampret +// Now most of the configuration registers are updatded automatically based on defines in or1200_defines.v. +// +// Revision 1.22 2002/09/03 22:28:21 lampret +// As per Taylor Su suggestion all case blocks are full case by default and optionally (OR1200_CASE_DEFAULT) can be disabled to increase clock frequncy. +// +// Revision 1.21 2002/08/22 02:18:55 lampret +// Store buffer has been tested and it works. BY default it is still disabled until uClinux confirms correct operation on FPGA board. +// +// Revision 1.20 2002/08/18 21:59:45 lampret +// Disable SB until it is tested +// +// Revision 1.19 2002/08/18 19:53:08 lampret +// Added store buffer. +// +// Revision 1.18 2002/08/15 06:04:11 lampret +// Fixed Xilinx trace buffer address. REported by Taylor Su. +// +// Revision 1.17 2002/08/12 05:31:44 lampret +// Added OR1200_WB_RETRY. Moved WB registered outsputs / samples inputs into lower section. +// +// Revision 1.16 2002/07/14 22:17:17 lampret +// Added simple trace buffer [only for Xilinx Virtex target]. Fixed instruction fetch abort when new exception is recognized. +// +// Revision 1.15 2002/06/08 16:20:21 lampret +// Added defines for enabling generic FF based memory macro for register file. +// +// Revision 1.14 2002/03/29 16:24:06 lampret +// Changed comment about synopsys to _synopsys_ because synthesis was complaining about unknown directives +// +// Revision 1.13 2002/03/29 15:16:55 lampret +// Some of the warnings fixed. +// +// Revision 1.12 2002/03/28 19:25:42 lampret +// Added second type of Virtual Silicon two-port SRAM (for register file). Changed defines for VS STP RAMs. +// +// Revision 1.11 2002/03/28 19:13:17 lampret +// Updated defines. +// +// Revision 1.10 2002/03/14 00:30:24 lampret +// Added alternative for critical path in DU. +// +// Revision 1.9 2002/03/11 01:26:26 lampret +// Fixed async loop. Changed multiplier type for ASIC. +// +// Revision 1.8 2002/02/11 04:33:17 lampret +// Speed optimizations (removed duplicate _cyc_ and _stb_). Fixed D/IMMU cache-inhibit attr. +// +// Revision 1.7 2002/02/01 19:56:54 lampret +// Fixed combinational loops. +// +// Revision 1.6 2002/01/19 14:10:22 lampret +// Fixed OR1200_XILINX_RAM32X1D. +// +// Revision 1.5 2002/01/18 07:56:00 lampret +// No more low/high priority interrupts (PICPR removed). Added tick timer exception. Added exception prefix (SR[EPH]). Fixed single-step bug whenreading NPC. +// +// Revision 1.4 2002/01/14 09:44:12 lampret +// Default ASIC configuration does not sample WB inputs. +// +// Revision 1.3 2002/01/08 00:51:08 lampret +// Fixed typo. OR1200_REGISTERED_OUTPUTS was not defined. Should be. +// +// Revision 1.2 2002/01/03 21:23:03 lampret +// Uncommented OR1200_REGISTERED_OUTPUTS for FPGA target. +// +// Revision 1.1 2002/01/03 08:16:15 lampret +// New prefixes for RTL files, prefixed module names. Updated cache controllers and MMUs. +// +// Revision 1.20 2001/12/04 05:02:36 lampret +// Added OR1200_GENERIC_MULTP2_32X32 and OR1200_ASIC_MULTP2_32X32 +// +// Revision 1.19 2001/11/27 19:46:57 lampret +// Now FPGA and ASIC target are separate. +// +// Revision 1.18 2001/11/23 21:42:31 simons +// Program counter divided to PPC and NPC. +// +// Revision 1.17 2001/11/23 08:38:51 lampret +// Changed DSR/DRR behavior and exception detection. +// +// Revision 1.16 2001/11/20 21:30:38 lampret +// Added OR1200_REGISTERED_INPUTS. +// +// Revision 1.15 2001/11/19 14:29:48 simons +// Cashes disabled. +// +// Revision 1.14 2001/11/13 10:02:21 lampret +// Added 'setpc'. Renamed some signals (except_flushpipe into flushpipe etc) +// +// Revision 1.13 2001/11/12 01:45:40 lampret +// Moved flag bit into SR. Changed RF enable from constant enable to dynamic enable for read ports. +// +// Revision 1.12 2001/11/10 03:43:57 lampret +// Fixed exceptions. +// +// Revision 1.11 2001/11/02 18:57:14 lampret +// Modified virtual silicon instantiations. +// +// Revision 1.10 2001/10/21 17:57:16 lampret +// Removed params from generic_XX.v. Added translate_off/on in sprs.v and id.v. Removed spr_addr from dc.v and ic.v. Fixed CR+LF. +// +// Revision 1.9 2001/10/19 23:28:46 lampret +// Fixed some synthesis warnings. Configured with caches and MMUs. +// +// Revision 1.8 2001/10/14 13:12:09 lampret +// MP3 version. +// +// Revision 1.1.1.1 2001/10/06 10:18:36 igorm +// no message +// +// Revision 1.3 2001/08/17 08:01:19 lampret +// IC enable/disable. +// +// Revision 1.2 2001/08/13 03:36:20 lampret +// Added cfg regs. Moved all defines into one defines.v file. More cleanup. +// +// Revision 1.1 2001/08/09 13:39:33 lampret +// Major clean-up. +// +// Revision 1.2 2001/07/22 03:31:54 lampret +// Fixed RAM's oen bug. Cache bypass under development. +// +// Revision 1.1 2001/07/20 00:46:03 lampret +// Development version of RTL. Libraries are missing. +// +// + +// +// Dump VCD +// +//`define OR1200_VCD_DUMP + +// +// Generate debug messages during simulation +// +//`define OR1200_VERBOSE + +// `define OR1200_ASIC +//////////////////////////////////////////////////////// +// +// Typical configuration for an ASIC +// +`ifdef OR1200_ASIC + +// +// Target ASIC memories +// +//`define OR1200_ARTISAN_SSP +//`define OR1200_ARTISAN_SDP +//`define OR1200_ARTISAN_STP +`define OR1200_VIRTUALSILICON_SSP +//`define OR1200_VIRTUALSILICON_STP_T1 +//`define OR1200_VIRTUALSILICON_STP_T2 + +// +// Do not implement Data cache +// +//`define OR1200_NO_DC + +// +// Do not implement Insn cache +// +//`define OR1200_NO_IC + +// +// Do not implement Data MMU +// +//`define OR1200_NO_DMMU + +// +// Do not implement Insn MMU +// +//`define OR1200_NO_IMMU + +// +// Select between ASIC optimized and generic multiplier +// +//`define OR1200_ASIC_MULTP2_32X32 +`define OR1200_GENERIC_MULTP2_32X32 + +// +// Size/type of insn/data cache if implemented +// +// `define OR1200_IC_1W_512B +// `define OR1200_IC_1W_4KB +`define OR1200_IC_1W_8KB +// `define OR1200_DC_1W_4KB +`define OR1200_DC_1W_8KB + +`else + + +///////////////////////////////////////////////////////// +// +// Typical configuration for an FPGA +// + +// +// Target FPGA memories +// +//`define OR1200_ALTERA_LPM +`define OR1200_XILINX_RAMB16 +//`define OR1200_XILINX_RAMB4 +//`define OR1200_XILINX_RAM32X1D +//`define OR1200_USE_RAM16X1D_FOR_RAM32X1D + +// +// Do not implement Data cache +// +`define OR1200_NO_DC + +// +// Do not implement Insn cache +// +`define OR1200_NO_IC + +// +// Do not implement Data MMU +// +`define OR1200_NO_DMMU + +// +// Do not implement Insn MMU +// +`define OR1200_NO_IMMU + +// +// Select between ASIC and generic multiplier +// +// (Generic seems to trigger a bug in the Cadence Ncsim simulator) +// +//`define OR1200_ASIC_MULTP2_32X32 +`define OR1200_GENERIC_MULTP2_32X32 + +// +// Size/type of insn/data cache if implemented +// (consider available FPGA memory resources) +// +//`define OR1200_IC_1W_512B +`define OR1200_IC_1W_4KB +//`define OR1200_IC_1W_8KB +`define OR1200_DC_1W_4KB +//`define OR1200_DC_1W_8KB + +`endif + + +////////////////////////////////////////////////////////// +// +// Do not change below unless you know what you are doing +// + +// +// Enable RAM BIST +// +// At the moment this only works for Virtual Silicon +// single port RAMs. For other RAMs it has not effect. +// Special wrapper for VS RAMs needs to be provided +// with scan flops to facilitate bist scan. +// +//`define OR1200_BIST + +// +// Register OR1200 WISHBONE outputs +// (must be defined/enabled) +// +`define OR1200_REGISTERED_OUTPUTS + +// +// Register OR1200 WISHBONE inputs +// +// (must be undefined/disabled) +// +//`define OR1200_REGISTERED_INPUTS + +// +// Disable bursts if they are not supported by the +// memory subsystem (only affect cache line fill) +// +//`define OR1200_NO_BURSTS +// + +// +// WISHBONE retry counter range +// +// 2^value range for retry counter. Retry counter +// is activated whenever *wb_rty_i is asserted and +// until retry counter expires, corresponding +// WISHBONE interface is deactivated. +// +// To disable retry counters and *wb_rty_i all together, +// undefine this macro. +// +//`define OR1200_WB_RETRY 7 + +// +// WISHBONE Consecutive Address Burst +// +// This was used prior to WISHBONE B3 specification +// to identify bursts. It is no longer needed but +// remains enabled for compatibility with old designs. +// +// To remove *wb_cab_o ports undefine this macro. +// +`define OR1200_WB_CAB + +// +// WISHBONE B3 compatible interface +// +// This follows the WISHBONE B3 specification. +// It is not enabled by default because most +// designs still don't use WB b3. +// +// To enable *wb_cti_o/*wb_bte_o ports, +// define this macro. +// +//`define OR1200_WB_B3 + +// +// Enable additional synthesis directives if using +// _Synopsys_ synthesis tool +// +//`define OR1200_ADDITIONAL_SYNOPSYS_DIRECTIVES + +// +// Enables default statement in some case blocks +// and disables Synopsys synthesis directive full_case +// +// By default it is enabled. When disabled it +// can increase clock frequency. +// +`define OR1200_CASE_DEFAULT + +// +// Operand width / register file address width +// +// (DO NOT CHANGE) +// +`define OR1200_OPERAND_WIDTH 32 +`define OR1200_REGFILE_ADDR_WIDTH 5 + +// +// l.add/l.addi/l.and and optional l.addc/l.addic +// also set (compare) flag when result of their +// operation equals zero +// +// At the time of writing this, default or32 +// C/C++ compiler doesn't generate code that +// would benefit from this optimization. +// +// By default this optimization is disabled to +// save area. +// +//`define OR1200_ADDITIONAL_FLAG_MODIFIERS + +// +// Implement l.addc/l.addic instructions +// +// By default implementation of l.addc/l.addic +// instructions is enabled in case you need them. +// If you don't use them, then disable implementation +// to save area. +// +`define OR1200_IMPL_ADDC + +// +// Implement carry bit SR[CY] +// +// By default implementation of SR[CY] is enabled +// to be compliant with the simulator. However +// SR[CY] is explicitly only used by l.addc/l.addic +// instructions and if these two insns are not +// implemented there is not much point having SR[CY]. +// +`define OR1200_IMPL_CY + +// +// Implement optional l.div/l.divu instructions +// +// By default divide instructions are not implemented +// to save area and increase clock frequency. or32 C/C++ +// compiler can use soft library for division. +// +// To implement divide, multiplier needs to be implemented. +// +//`define OR1200_IMPL_DIV + +// +// Implement rotate in the ALU +// +// At the time of writing this, or32 +// C/C++ compiler doesn't generate rotate +// instructions. However or32 assembler +// can assemble code that uses rotate insn. +// This means that rotate instructions +// must be used manually inserted. +// +// By default implementation of rotate +// is disabled to save area and increase +// clock frequency. +// +//`define OR1200_IMPL_ALU_ROTATE + +// +// Type of ALU compare to implement +// +// Try either one to find what yields +// higher clock frequencyin your case. +// +//`define OR1200_IMPL_ALU_COMP1 +`define OR1200_IMPL_ALU_COMP2 + +// +// Implement multiplier +// +// By default multiplier is implemented +// +`define OR1200_MULT_IMPLEMENTED + +// +// Implement multiply-and-accumulate +// +// By default MAC is implemented. To +// implement MAC, multiplier needs to be +// implemented. +// +`define OR1200_MAC_IMPLEMENTED + +// +// Low power, slower multiplier +// +// Select between low-power (larger) multiplier +// and faster multiplier. The actual difference +// is only AND logic that prevents distribution +// of operands into the multiplier when instruction +// in execution is not multiply instruction +// +//`define OR1200_LOWPWR_MULT + +// +// Clock ratio RISC clock versus WB clock +// +// If you plan to run WB:RISC clock fixed to 1:1, disable +// both defines +// +// For WB:RISC 1:2 or 1:1, enable OR1200_CLKDIV_2_SUPPORTED +// and use clmode to set ratio +// +// For WB:RISC 1:4, 1:2 or 1:1, enable both defines and use +// clmode to set ratio +// +`define OR1200_CLKDIV_2_SUPPORTED +//`define OR1200_CLKDIV_4_SUPPORTED + +// +// Type of register file RAM +// +// Memory macro w/ two ports (see or1200_tpram_32x32.v) +//`define OR1200_RFRAM_TWOPORT +// +// Memory macro dual port (see or1200_dpram_32x32.v) +`define OR1200_RFRAM_DUALPORT +// +// Generic (flip-flop based) register file (see or1200_rfram_generic.v) +//`define OR1200_RFRAM_GENERIC + +// +// Type of mem2reg aligner to implement. +// +// Once OR1200_IMPL_MEM2REG2 yielded faster +// circuit, however with today tools it will +// most probably give you slower circuit. +// +`define OR1200_IMPL_MEM2REG1 +//`define OR1200_IMPL_MEM2REG2 + +// +// ALUOPs +// +`define OR1200_ALUOP_WIDTH 4 +`define OR1200_ALUOP_NOP 4'd4 +/* Order defined by arith insns that have two source operands both in regs + (see binutils/include/opcode/or32.h) */ +`define OR1200_ALUOP_ADD 4'd0 +`define OR1200_ALUOP_ADDC 4'd1 +`define OR1200_ALUOP_SUB 4'd2 +`define OR1200_ALUOP_AND 4'd3 +`define OR1200_ALUOP_OR 4'd4 +`define OR1200_ALUOP_XOR 4'd5 +`define OR1200_ALUOP_MUL 4'd6 +`define OR1200_ALUOP_CUST5 4'd7 +`define OR1200_ALUOP_SHROT 4'd8 +`define OR1200_ALUOP_DIV 4'd9 +`define OR1200_ALUOP_DIVU 4'd10 +/* Order not specifically defined. */ +`define OR1200_ALUOP_IMM 4'd11 +`define OR1200_ALUOP_MOVHI 4'd12 +`define OR1200_ALUOP_COMP 4'd13 +`define OR1200_ALUOP_MTSR 4'd14 +`define OR1200_ALUOP_MFSR 4'd15 +`define OR1200_ALUOP_CMOV 4'd14 +`define OR1200_ALUOP_FF1 4'd15 +// +// MACOPs +// +`define OR1200_MACOP_WIDTH 2 +`define OR1200_MACOP_NOP 2'b00 +`define OR1200_MACOP_MAC 2'b01 +`define OR1200_MACOP_MSB 2'b10 + +// +// Shift/rotate ops +// +`define OR1200_SHROTOP_WIDTH 2 +`define OR1200_SHROTOP_NOP 2'd0 +`define OR1200_SHROTOP_SLL 2'd0 +`define OR1200_SHROTOP_SRL 2'd1 +`define OR1200_SHROTOP_SRA 2'd2 +`define OR1200_SHROTOP_ROR 2'd3 + +// Execution cycles per instruction +`define OR1200_MULTICYCLE_WIDTH 2 +`define OR1200_ONE_CYCLE 2'd0 +`define OR1200_TWO_CYCLES 2'd1 + +// Operand MUX selects +`define OR1200_SEL_WIDTH 2 +`define OR1200_SEL_RF 2'd0 +`define OR1200_SEL_IMM 2'd1 +`define OR1200_SEL_EX_FORW 2'd2 +`define OR1200_SEL_WB_FORW 2'd3 + +// +// BRANCHOPs +// +`define OR1200_BRANCHOP_WIDTH 3 +`define OR1200_BRANCHOP_NOP 3'd0 +`define OR1200_BRANCHOP_J 3'd1 +`define OR1200_BRANCHOP_JR 3'd2 +`define OR1200_BRANCHOP_BAL 3'd3 +`define OR1200_BRANCHOP_BF 3'd4 +`define OR1200_BRANCHOP_BNF 3'd5 +`define OR1200_BRANCHOP_RFE 3'd6 + +// +// LSUOPs +// +// Bit 0: sign extend +// Bits 1-2: 00 doubleword, 01 byte, 10 halfword, 11 singleword +// Bit 3: 0 load, 1 store +`define OR1200_LSUOP_WIDTH 4 +`define OR1200_LSUOP_NOP 4'b0000 +`define OR1200_LSUOP_LBZ 4'b0010 +`define OR1200_LSUOP_LBS 4'b0011 +`define OR1200_LSUOP_LHZ 4'b0100 +`define OR1200_LSUOP_LHS 4'b0101 +`define OR1200_LSUOP_LWZ 4'b0110 +`define OR1200_LSUOP_LWS 4'b0111 +`define OR1200_LSUOP_LD 4'b0001 +`define OR1200_LSUOP_SD 4'b1000 +`define OR1200_LSUOP_SB 4'b1010 +`define OR1200_LSUOP_SH 4'b1100 +`define OR1200_LSUOP_SW 4'b1110 + +// FETCHOPs +`define OR1200_FETCHOP_WIDTH 1 +`define OR1200_FETCHOP_NOP 1'b0 +`define OR1200_FETCHOP_LW 1'b1 + +// +// Register File Write-Back OPs +// +// Bit 0: register file write enable +// Bits 2-1: write-back mux selects +`define OR1200_RFWBOP_WIDTH 3 +`define OR1200_RFWBOP_NOP 3'b000 +`define OR1200_RFWBOP_ALU 3'b001 +`define OR1200_RFWBOP_LSU 3'b011 +`define OR1200_RFWBOP_SPRS 3'b101 +`define OR1200_RFWBOP_LR 3'b111 + +// Compare instructions +`define OR1200_COP_SFEQ 3'b000 +`define OR1200_COP_SFNE 3'b001 +`define OR1200_COP_SFGT 3'b010 +`define OR1200_COP_SFGE 3'b011 +`define OR1200_COP_SFLT 3'b100 +`define OR1200_COP_SFLE 3'b101 +`define OR1200_COP_X 3'b111 +`define OR1200_SIGNED_COMPARE 'd3 +`define OR1200_COMPOP_WIDTH 4 + +// +// TAGs for instruction bus +// +`define OR1200_ITAG_IDLE 4'h0 // idle bus +`define OR1200_ITAG_NI 4'h1 // normal insn +`define OR1200_ITAG_BE 4'hb // Bus error exception +`define OR1200_ITAG_PE 4'hc // Page fault exception +`define OR1200_ITAG_TE 4'hd // TLB miss exception + +// +// TAGs for data bus +// +`define OR1200_DTAG_IDLE 4'h0 // idle bus +`define OR1200_DTAG_ND 4'h1 // normal data +`define OR1200_DTAG_AE 4'ha // Alignment exception +`define OR1200_DTAG_BE 4'hb // Bus error exception +`define OR1200_DTAG_PE 4'hc // Page fault exception +`define OR1200_DTAG_TE 4'hd // TLB miss exception + + +////////////////////////////////////////////// +// +// ORBIS32 ISA specifics +// + +// SHROT_OP position in machine word +`define OR1200_SHROTOP_POS 7:6 + +// ALU instructions multicycle field in machine word +`define OR1200_ALUMCYC_POS 9:8 + +// +// Instruction opcode groups (basic) +// +`define OR1200_OR32_J 6'b000000 +`define OR1200_OR32_JAL 6'b000001 +`define OR1200_OR32_BNF 6'b000011 +`define OR1200_OR32_BF 6'b000100 +`define OR1200_OR32_NOP 6'b000101 +`define OR1200_OR32_MOVHI 6'b000110 +`define OR1200_OR32_XSYNC 6'b001000 +`define OR1200_OR32_RFE 6'b001001 +/* */ +`define OR1200_OR32_JR 6'b010001 +`define OR1200_OR32_JALR 6'b010010 +`define OR1200_OR32_MACI 6'b010011 +/* */ +`define OR1200_OR32_LWZ 6'b100001 +`define OR1200_OR32_LBZ 6'b100011 +`define OR1200_OR32_LBS 6'b100100 +`define OR1200_OR32_LHZ 6'b100101 +`define OR1200_OR32_LHS 6'b100110 +`define OR1200_OR32_ADDI 6'b100111 +`define OR1200_OR32_ADDIC 6'b101000 +`define OR1200_OR32_ANDI 6'b101001 +`define OR1200_OR32_ORI 6'b101010 +`define OR1200_OR32_XORI 6'b101011 +`define OR1200_OR32_MULI 6'b101100 +`define OR1200_OR32_MFSPR 6'b101101 +`define OR1200_OR32_SH_ROTI 6'b101110 +`define OR1200_OR32_SFXXI 6'b101111 +/* */ +`define OR1200_OR32_MTSPR 6'b110000 +`define OR1200_OR32_MACMSB 6'b110001 +/* */ +`define OR1200_OR32_SW 6'b110101 +`define OR1200_OR32_SB 6'b110110 +`define OR1200_OR32_SH 6'b110111 +`define OR1200_OR32_ALU 6'b111000 +`define OR1200_OR32_SFXX 6'b111001 +//`define OR1200_OR32_CUST5 6'b111100 + + +///////////////////////////////////////////////////// +// +// Exceptions +// + +// +// Exception vectors per OR1K architecture: +// 0xPPPPP100 - reset +// 0xPPPPP200 - bus error +// ... etc +// where P represents exception prefix. +// +// Exception vectors can be customized as per +// the following formula: +// 0xPPPPPNVV - exception N +// +// P represents exception prefix +// N represents exception N +// VV represents length of the individual vector space, +// usually it is 8 bits wide and starts with all bits zero +// + +// +// PPPPP and VV parts +// +// Sum of these two defines needs to be 28 +// +`define OR1200_EXCEPT_EPH0_P 20'h00000 +`define OR1200_EXCEPT_EPH1_P 20'hF0000 +`define OR1200_EXCEPT_V 8'h00 + +// +// N part width +// +`define OR1200_EXCEPT_WIDTH 4 + +// +// Definition of exception vectors +// +// To avoid implementation of a certain exception, +// simply comment out corresponding line +// +`define OR1200_EXCEPT_UNUSED `OR1200_EXCEPT_WIDTH'hf +`define OR1200_EXCEPT_TRAP `OR1200_EXCEPT_WIDTH'he +`define OR1200_EXCEPT_BREAK `OR1200_EXCEPT_WIDTH'hd +`define OR1200_EXCEPT_SYSCALL `OR1200_EXCEPT_WIDTH'hc +`define OR1200_EXCEPT_RANGE `OR1200_EXCEPT_WIDTH'hb +`define OR1200_EXCEPT_ITLBMISS `OR1200_EXCEPT_WIDTH'ha +`define OR1200_EXCEPT_DTLBMISS `OR1200_EXCEPT_WIDTH'h9 +`define OR1200_EXCEPT_INT `OR1200_EXCEPT_WIDTH'h8 +`define OR1200_EXCEPT_ILLEGAL `OR1200_EXCEPT_WIDTH'h7 +`define OR1200_EXCEPT_ALIGN `OR1200_EXCEPT_WIDTH'h6 +`define OR1200_EXCEPT_TICK `OR1200_EXCEPT_WIDTH'h5 +`define OR1200_EXCEPT_IPF `OR1200_EXCEPT_WIDTH'h4 +`define OR1200_EXCEPT_DPF `OR1200_EXCEPT_WIDTH'h3 +`define OR1200_EXCEPT_BUSERR `OR1200_EXCEPT_WIDTH'h2 +`define OR1200_EXCEPT_RESET `OR1200_EXCEPT_WIDTH'h1 +`define OR1200_EXCEPT_NONE `OR1200_EXCEPT_WIDTH'h0 + + +///////////////////////////////////////////////////// +// +// SPR groups +// + +// Bits that define the group +`define OR1200_SPR_GROUP_BITS 15:11 + +// Width of the group bits +`define OR1200_SPR_GROUP_WIDTH 5 + +// Bits that define offset inside the group +`define OR1200_SPR_OFS_BITS 10:0 + +// List of groups +`define OR1200_SPR_GROUP_SYS 5'd00 +`define OR1200_SPR_GROUP_DMMU 5'd01 +`define OR1200_SPR_GROUP_IMMU 5'd02 +`define OR1200_SPR_GROUP_DC 5'd03 +`define OR1200_SPR_GROUP_IC 5'd04 +`define OR1200_SPR_GROUP_MAC 5'd05 +`define OR1200_SPR_GROUP_DU 5'd06 +`define OR1200_SPR_GROUP_PM 5'd08 +`define OR1200_SPR_GROUP_PIC 5'd09 +`define OR1200_SPR_GROUP_TT 5'd10 + + +///////////////////////////////////////////////////// +// +// System group +// + +// +// System registers +// +`define OR1200_SPR_CFGR 7'd0 +`define OR1200_SPR_RF 6'd32 // 1024 >> 5 +`define OR1200_SPR_NPC 11'd16 +`define OR1200_SPR_SR 11'd17 +`define OR1200_SPR_PPC 11'd18 +`define OR1200_SPR_EPCR 11'd32 +`define OR1200_SPR_EEAR 11'd48 +`define OR1200_SPR_ESR 11'd64 + +// +// SR bits +// +`define OR1200_SR_WIDTH 16 +`define OR1200_SR_SM 0 +`define OR1200_SR_TEE 1 +`define OR1200_SR_IEE 2 +`define OR1200_SR_DCE 3 +`define OR1200_SR_ICE 4 +`define OR1200_SR_DME 5 +`define OR1200_SR_IME 6 +`define OR1200_SR_LEE 7 +`define OR1200_SR_CE 8 +`define OR1200_SR_F 9 +`define OR1200_SR_CY 10 // Unused +`define OR1200_SR_OV 11 // Unused +`define OR1200_SR_OVE 12 // Unused +`define OR1200_SR_DSX 13 // Unused +`define OR1200_SR_EPH 14 +`define OR1200_SR_FO 15 +`define OR1200_SR_CID 31:28 // Unimplemented + +// +// Bits that define offset inside the group +// +`define OR1200_SPROFS_BITS 10:0 + +// +// Default Exception Prefix +// +// 1'b0 - OR1200_EXCEPT_EPH0_P (0x0000_0000) +// 1'b1 - OR1200_EXCEPT_EPH1_P (0xF000_0000) +// +`define OR1200_SR_EPH_DEF 1'b0 + +///////////////////////////////////////////////////// +// +// Power Management (PM) +// + +// Define it if you want PM implemented +//`define OR1200_PM_IMPLEMENTED + +// Bit positions inside PMR (don't change) +`define OR1200_PM_PMR_SDF 3:0 +`define OR1200_PM_PMR_DME 4 +`define OR1200_PM_PMR_SME 5 +`define OR1200_PM_PMR_DCGE 6 +`define OR1200_PM_PMR_UNUSED 31:7 + +// PMR offset inside PM group of registers +`define OR1200_PM_OFS_PMR 11'b0 + +// PM group +`define OR1200_SPRGRP_PM 5'd8 + +// Define if PMR can be read/written at any address inside PM group +`define OR1200_PM_PARTIAL_DECODING + +// Define if reading PMR is allowed +`define OR1200_PM_READREGS + +// Define if unused PMR bits should be zero +`define OR1200_PM_UNUSED_ZERO + + +///////////////////////////////////////////////////// +// +// Debug Unit (DU) +// + +// Define it if you want DU implemented +`define OR1200_DU_IMPLEMENTED + +// +// Define if you want HW Breakpoints +// (if HW breakpoints are not implemented +// only default software trapping is +// possible with l.trap insn - this is +// however already enough for use +// with or32 gdb) +// +`define OR1200_DU_HWBKPTS + +// Number of DVR/DCR pairs if HW breakpoints enabled +`define OR1200_DU_DVRDCR_PAIRS 8 + +// Define if you want trace buffer +//`define OR1200_DU_TB_IMPLEMENTED + +// +// Address offsets of DU registers inside DU group +// +// To not implement a register, doq not define its address +// +`ifdef OR1200_DU_HWBKPTS +`define OR1200_DU_DVR0 11'd0 +`define OR1200_DU_DVR1 11'd1 +`define OR1200_DU_DVR2 11'd2 +`define OR1200_DU_DVR3 11'd3 +`define OR1200_DU_DVR4 11'd4 +`define OR1200_DU_DVR5 11'd5 +`define OR1200_DU_DVR6 11'd6 +`define OR1200_DU_DVR7 11'd7 +`define OR1200_DU_DCR0 11'd8 +`define OR1200_DU_DCR1 11'd9 +`define OR1200_DU_DCR2 11'd10 +`define OR1200_DU_DCR3 11'd11 +`define OR1200_DU_DCR4 11'd12 +`define OR1200_DU_DCR5 11'd13 +`define OR1200_DU_DCR6 11'd14 +`define OR1200_DU_DCR7 11'd15 +`endif +`define OR1200_DU_DMR1 11'd16 +`ifdef OR1200_DU_HWBKPTS +`define OR1200_DU_DMR2 11'd17 +`define OR1200_DU_DWCR0 11'd18 +`define OR1200_DU_DWCR1 11'd19 +`endif +`define OR1200_DU_DSR 11'd20 +`define OR1200_DU_DRR 11'd21 +`ifdef OR1200_DU_TB_IMPLEMENTED +`define OR1200_DU_TBADR 11'h0ff +`define OR1200_DU_TBIA 11'h1xx +`define OR1200_DU_TBIM 11'h2xx +`define OR1200_DU_TBAR 11'h3xx +`define OR1200_DU_TBTS 11'h4xx +`endif + +// Position of offset bits inside SPR address +`define OR1200_DUOFS_BITS 10:0 + +// DCR bits +`define OR1200_DU_DCR_DP 0 +`define OR1200_DU_DCR_CC 3:1 +`define OR1200_DU_DCR_SC 4 +`define OR1200_DU_DCR_CT 7:5 + +// DMR1 bits +`define OR1200_DU_DMR1_CW0 1:0 +`define OR1200_DU_DMR1_CW1 3:2 +`define OR1200_DU_DMR1_CW2 5:4 +`define OR1200_DU_DMR1_CW3 7:6 +`define OR1200_DU_DMR1_CW4 9:8 +`define OR1200_DU_DMR1_CW5 11:10 +`define OR1200_DU_DMR1_CW6 13:12 +`define OR1200_DU_DMR1_CW7 15:14 +`define OR1200_DU_DMR1_CW8 17:16 +`define OR1200_DU_DMR1_CW9 19:18 +`define OR1200_DU_DMR1_RES 21:20 +`define OR1200_DU_DMR1_ST 22 +`define OR1200_DU_DMR1_BT 23 + +// DMR2 bits +`define OR1200_DU_DMR2_WCE0 0 +`define OR1200_DU_DMR2_WCE1 1 +`define OR1200_DU_DMR2_AWTC 11:2 +`define OR1200_DU_DMR2_WGB 21:12 + +// DWCR bits +`define OR1200_DU_DWCR_COUNT 15:0 +`define OR1200_DU_DWCR_MATCH 31:16 + +// DSR bits +`define OR1200_DU_DSR_WIDTH 14 +`define OR1200_DU_DSR_RSTE 0 +`define OR1200_DU_DSR_BUSEE 1 +`define OR1200_DU_DSR_DPFE 2 +`define OR1200_DU_DSR_IPFE 3 +`define OR1200_DU_DSR_TTE 4 +`define OR1200_DU_DSR_AE 5 +`define OR1200_DU_DSR_IIE 6 +`define OR1200_DU_DSR_IE 7 +`define OR1200_DU_DSR_DME 8 +`define OR1200_DU_DSR_IME 9 +`define OR1200_DU_DSR_RE 10 +`define OR1200_DU_DSR_SCE 11 +`define OR1200_DU_DSR_BE 12 +`define OR1200_DU_DSR_TE 13 + +// DRR bits +`define OR1200_DU_DRR_RSTE 0 +`define OR1200_DU_DRR_BUSEE 1 +`define OR1200_DU_DRR_DPFE 2 +`define OR1200_DU_DRR_IPFE 3 +`define OR1200_DU_DRR_TTE 4 +`define OR1200_DU_DRR_AE 5 +`define OR1200_DU_DRR_IIE 6 +`define OR1200_DU_DRR_IE 7 +`define OR1200_DU_DRR_DME 8 +`define OR1200_DU_DRR_IME 9 +`define OR1200_DU_DRR_RE 10 +`define OR1200_DU_DRR_SCE 11 +`define OR1200_DU_DRR_BE 12 +`define OR1200_DU_DRR_TE 13 + +// Define if reading DU regs is allowed +`define OR1200_DU_READREGS + +// Define if unused DU registers bits should be zero +`define OR1200_DU_UNUSED_ZERO + +// Define if IF/LSU status is not needed by devel i/f +`define OR1200_DU_STATUS_UNIMPLEMENTED + +///////////////////////////////////////////////////// +// +// Programmable Interrupt Controller (PIC) +// + +// Define it if you want PIC implemented +`define OR1200_PIC_IMPLEMENTED + +// Define number of interrupt inputs (2-31) +`define OR1200_PIC_INTS 20 + +// Address offsets of PIC registers inside PIC group +`define OR1200_PIC_OFS_PICMR 2'd0 +`define OR1200_PIC_OFS_PICSR 2'd2 + +// Position of offset bits inside SPR address +`define OR1200_PICOFS_BITS 1:0 + +// Define if you want these PIC registers to be implemented +`define OR1200_PIC_PICMR +`define OR1200_PIC_PICSR + +// Define if reading PIC registers is allowed +`define OR1200_PIC_READREGS + +// Define if unused PIC register bits should be zero +`define OR1200_PIC_UNUSED_ZERO + + +///////////////////////////////////////////////////// +// +// Tick Timer (TT) +// + +// Define it if you want TT implemented +`define OR1200_TT_IMPLEMENTED + +// Address offsets of TT registers inside TT group +`define OR1200_TT_OFS_TTMR 1'd0 +`define OR1200_TT_OFS_TTCR 1'd1 + +// Position of offset bits inside SPR group +`define OR1200_TTOFS_BITS 0 + +// Define if you want these TT registers to be implemented +`define OR1200_TT_TTMR +`define OR1200_TT_TTCR + +// TTMR bits +`define OR1200_TT_TTMR_TP 27:0 +`define OR1200_TT_TTMR_IP 28 +`define OR1200_TT_TTMR_IE 29 +`define OR1200_TT_TTMR_M 31:30 + +// Define if reading TT registers is allowed +`define OR1200_TT_READREGS + + +////////////////////////////////////////////// +// +// MAC +// +`define OR1200_MAC_ADDR 0 // MACLO 0xxxxxxxx1, MACHI 0xxxxxxxx0 +`define OR1200_MAC_SPR_WE // Define if MACLO/MACHI are SPR writable + +// +// Shift {MACHI,MACLO} into destination register when executing l.macrc +// +// According to architecture manual there is no shift, so default value is 0. +// +// However the implementation has deviated in this from the arch manual and had hard coded shift by 28 bits which +// is a useful optimization for MP3 decoding (if using libmad fixed point library). Shifts are no longer +// default setup, but if you need to remain backward compatible, define your shift bits, which were normally +// dest_GPR = {MACHI,MACLO}[59:28] +`define OR1200_MAC_SHIFTBY 0 // 0 = According to arch manual, 28 = obsolete backward compatibility + + +////////////////////////////////////////////// +// +// Data MMU (DMMU) +// + +// +// Address that selects between TLB TR and MR +// +`define OR1200_DTLB_TM_ADDR 7 + +// +// DTLBMR fields +// +`define OR1200_DTLBMR_V_BITS 0 +`define OR1200_DTLBMR_CID_BITS 4:1 +`define OR1200_DTLBMR_RES_BITS 11:5 +`define OR1200_DTLBMR_VPN_BITS 31:13 + +// +// DTLBTR fields +// +`define OR1200_DTLBTR_CC_BITS 0 +`define OR1200_DTLBTR_CI_BITS 1 +`define OR1200_DTLBTR_WBC_BITS 2 +`define OR1200_DTLBTR_WOM_BITS 3 +`define OR1200_DTLBTR_A_BITS 4 +`define OR1200_DTLBTR_D_BITS 5 +`define OR1200_DTLBTR_URE_BITS 6 +`define OR1200_DTLBTR_UWE_BITS 7 +`define OR1200_DTLBTR_SRE_BITS 8 +`define OR1200_DTLBTR_SWE_BITS 9 +`define OR1200_DTLBTR_RES_BITS 11:10 +`define OR1200_DTLBTR_PPN_BITS 31:13 + +// +// DTLB configuration +// +`define OR1200_DMMU_PS 13 // 13 for 8KB page size +`define OR1200_DTLB_INDXW 6 // 6 for 64 entry DTLB 7 for 128 entries +`define OR1200_DTLB_INDXL `OR1200_DMMU_PS // 13 13 +`define OR1200_DTLB_INDXH `OR1200_DMMU_PS+`OR1200_DTLB_INDXW-1 // 18 19 +`define OR1200_DTLB_INDX `OR1200_DTLB_INDXH:`OR1200_DTLB_INDXL // 18:13 19:13 +`define OR1200_DTLB_TAGW 32-`OR1200_DTLB_INDXW-`OR1200_DMMU_PS // 13 12 +`define OR1200_DTLB_TAGL `OR1200_DTLB_INDXH+1 // 19 20 +`define OR1200_DTLB_TAG 31:`OR1200_DTLB_TAGL // 31:19 31:20 +`define OR1200_DTLBMRW `OR1200_DTLB_TAGW+1 // +1 because of V bit +`define OR1200_DTLBTRW 32-`OR1200_DMMU_PS+5 // +5 because of protection bits and CI + +// +// Cache inhibit while DMMU is not enabled/implemented +// +// cache inhibited 0GB-4GB 1'b1 +// cache inhibited 0GB-2GB !dcpu_adr_i[31] +// cache inhibited 0GB-1GB 2GB-3GB !dcpu_adr_i[30] +// cache inhibited 1GB-2GB 3GB-4GB dcpu_adr_i[30] +// cache inhibited 2GB-4GB (default) dcpu_adr_i[31] +// cached 0GB-4GB 1'b0 +// +`define OR1200_DMMU_CI dcpu_adr_i[31] + + +////////////////////////////////////////////// +// +// Insn MMU (IMMU) +// + +// +// Address that selects between TLB TR and MR +// +`define OR1200_ITLB_TM_ADDR 7 + +// +// ITLBMR fields +// +`define OR1200_ITLBMR_V_BITS 0 +`define OR1200_ITLBMR_CID_BITS 4:1 +`define OR1200_ITLBMR_RES_BITS 11:5 +`define OR1200_ITLBMR_VPN_BITS 31:13 + +// +// ITLBTR fields +// +`define OR1200_ITLBTR_CC_BITS 0 +`define OR1200_ITLBTR_CI_BITS 1 +`define OR1200_ITLBTR_WBC_BITS 2 +`define OR1200_ITLBTR_WOM_BITS 3 +`define OR1200_ITLBTR_A_BITS 4 +`define OR1200_ITLBTR_D_BITS 5 +`define OR1200_ITLBTR_SXE_BITS 6 +`define OR1200_ITLBTR_UXE_BITS 7 +`define OR1200_ITLBTR_RES_BITS 11:8 +`define OR1200_ITLBTR_PPN_BITS 31:13 + +// +// ITLB configuration +// +`define OR1200_IMMU_PS 13 // 13 for 8KB page size +`define OR1200_ITLB_INDXW 6 // 6 for 64 entry ITLB 7 for 128 entries +`define OR1200_ITLB_INDXL `OR1200_IMMU_PS // 13 13 +`define OR1200_ITLB_INDXH `OR1200_IMMU_PS+`OR1200_ITLB_INDXW-1 // 18 19 +`define OR1200_ITLB_INDX `OR1200_ITLB_INDXH:`OR1200_ITLB_INDXL // 18:13 19:13 +`define OR1200_ITLB_TAGW 32-`OR1200_ITLB_INDXW-`OR1200_IMMU_PS // 13 12 +`define OR1200_ITLB_TAGL `OR1200_ITLB_INDXH+1 // 19 20 +`define OR1200_ITLB_TAG 31:`OR1200_ITLB_TAGL // 31:19 31:20 +`define OR1200_ITLBMRW `OR1200_ITLB_TAGW+1 // +1 because of V bit +`define OR1200_ITLBTRW 32-`OR1200_IMMU_PS+3 // +3 because of protection bits and CI + +// +// Cache inhibit while IMMU is not enabled/implemented +// Note: all combinations that use icpu_adr_i cause async loop +// +// cache inhibited 0GB-4GB 1'b1 +// cache inhibited 0GB-2GB !icpu_adr_i[31] +// cache inhibited 0GB-1GB 2GB-3GB !icpu_adr_i[30] +// cache inhibited 1GB-2GB 3GB-4GB icpu_adr_i[30] +// cache inhibited 2GB-4GB (default) icpu_adr_i[31] +// cached 0GB-4GB 1'b0 +// +`define OR1200_IMMU_CI 1'b0 + + +///////////////////////////////////////////////// +// +// Insn cache (IC) +// + +// 3 for 8 bytes, 4 for 16 bytes etc +`define OR1200_ICLS 4 + +// +// IC configurations +// +`ifdef OR1200_IC_1W_512B +`define OR1200_ICSIZE 9 // 512 +`define OR1200_ICINDX `OR1200_ICSIZE-2 // 7 +`define OR1200_ICINDXH `OR1200_ICSIZE-1 // 8 +`define OR1200_ICTAGL `OR1200_ICINDXH+1 // 9 +`define OR1200_ICTAG `OR1200_ICSIZE-`OR1200_ICLS // 5 +`define OR1200_ICTAG_W 24 +`endif +`ifdef OR1200_IC_1W_4KB +`define OR1200_ICSIZE 12 // 4096 +`define OR1200_ICINDX `OR1200_ICSIZE-2 // 10 +`define OR1200_ICINDXH `OR1200_ICSIZE-1 // 11 +`define OR1200_ICTAGL `OR1200_ICINDXH+1 // 12 +`define OR1200_ICTAG `OR1200_ICSIZE-`OR1200_ICLS // 8 +`define OR1200_ICTAG_W 21 +`endif +`ifdef OR1200_IC_1W_8KB +`define OR1200_ICSIZE 13 // 8192 +`define OR1200_ICINDX `OR1200_ICSIZE-2 // 11 +`define OR1200_ICINDXH `OR1200_ICSIZE-1 // 12 +`define OR1200_ICTAGL `OR1200_ICINDXH+1 // 13 +`define OR1200_ICTAG `OR1200_ICSIZE-`OR1200_ICLS // 9 +`define OR1200_ICTAG_W 20 +`endif + + +///////////////////////////////////////////////// +// +// Data cache (DC) +// + +// 3 for 8 bytes, 4 for 16 bytes etc +`define OR1200_DCLS 4 + +// Define to perform store refill (potential performance penalty) +// `define OR1200_DC_STORE_REFILL + +// +// DC configurations +// +`ifdef OR1200_DC_1W_4KB +`define OR1200_DCSIZE 12 // 4096 +`define OR1200_DCINDX `OR1200_DCSIZE-2 // 10 +`define OR1200_DCINDXH `OR1200_DCSIZE-1 // 11 +`define OR1200_DCTAGL `OR1200_DCINDXH+1 // 12 +`define OR1200_DCTAG `OR1200_DCSIZE-`OR1200_DCLS // 8 +`define OR1200_DCTAG_W 21 +`endif +`ifdef OR1200_DC_1W_8KB +`define OR1200_DCSIZE 13 // 8192 +`define OR1200_DCINDX `OR1200_DCSIZE-2 // 11 +`define OR1200_DCINDXH `OR1200_DCSIZE-1 // 12 +`define OR1200_DCTAGL `OR1200_DCINDXH+1 // 13 +`define OR1200_DCTAG `OR1200_DCSIZE-`OR1200_DCLS // 9 +`define OR1200_DCTAG_W 20 +`endif + +///////////////////////////////////////////////// +// +// Store buffer (SB) +// + +// +// Store buffer +// +// It will improve performance by "caching" CPU stores +// using store buffer. This is most important for function +// prologues because DC can only work in write though mode +// and all stores would have to complete external WB writes +// to memory. +// Store buffer is between DC and data BIU. +// All stores will be stored into store buffer and immediately +// completed by the CPU, even though actual external writes +// will be performed later. As a consequence store buffer masks +// all data bus errors related to stores (data bus errors +// related to loads are delivered normally). +// All pending CPU loads will wait until store buffer is empty to +// ensure strict memory model. Right now this is necessary because +// we don't make destinction between cached and cache inhibited +// address space, so we simply empty store buffer until loads +// can begin. +// +// It makes design a bit bigger, depending what is the number of +// entries in SB FIFO. Number of entries can be changed further +// down. +// +//`define OR1200_SB_IMPLEMENTED + +// +// Number of store buffer entries +// +// Verified number of entries are 4 and 8 entries +// (2 and 3 for OR1200_SB_LOG). OR1200_SB_ENTRIES must +// always match 2**OR1200_SB_LOG. +// To disable store buffer, undefine +// OR1200_SB_IMPLEMENTED. +// +`define OR1200_SB_LOG 2 // 2 or 3 +`define OR1200_SB_ENTRIES 4 // 4 or 8 + + +///////////////////////////////////////////////// +// +// Quick Embedded Memory (QMEM) +// + +// +// Quick Embedded Memory +// +// Instantiation of dedicated insn/data memory (RAM or ROM). +// Insn fetch has effective throughput 1insn / clock cycle. +// Data load takes two clock cycles / access, data store +// takes 1 clock cycle / access (if there is no insn fetch)). +// Memory instantiation is shared between insn and data, +// meaning if insn fetch are performed, data load/store +// performance will be lower. +// +// Main reason for QMEM is to put some time critical functions +// into this memory and to have predictable and fast access +// to these functions. (soft fpu, context switch, exception +// handlers, stack, etc) +// +// It makes design a bit bigger and slower. QMEM sits behind +// IMMU/DMMU so all addresses are physical (so the MMUs can be +// used with QMEM and QMEM is seen by the CPU just like any other +// memory in the system). IC/DC are sitting behind QMEM so the +// whole design timing might be worse with QMEM implemented. +// +//`define OR1200_QMEM_IMPLEMENTED + +// +// Base address and mask of QMEM +// +// Base address defines first address of QMEM. Mask defines +// QMEM range in address space. Actual size of QMEM is however +// determined with instantiated RAM/ROM. However bigger +// mask will reserve more address space for QMEM, but also +// make design faster, while more tight mask will take +// less address space but also make design slower. If +// instantiated RAM/ROM is smaller than space reserved with +// the mask, instatiated RAM/ROM will also be shadowed +// at higher addresses in reserved space. +// +`define OR1200_QMEM_IADDR 32'h0080_0000 +`define OR1200_QMEM_IMASK 32'hfff0_0000 // Max QMEM size 1MB +`define OR1200_QMEM_DADDR 32'h0080_0000 +`define OR1200_QMEM_DMASK 32'hfff0_0000 // Max QMEM size 1MB + +// +// QMEM interface byte-select capability +// +// To enable qmem_sel* ports, define this macro. +// +//`define OR1200_QMEM_BSEL + +// +// QMEM interface acknowledge +// +// To enable qmem_ack port, define this macro. +// +//`define OR1200_QMEM_ACK + +///////////////////////////////////////////////////// +// +// VR, UPR and Configuration Registers +// +// +// VR, UPR and configuration registers are optional. If +// implemented, operating system can automatically figure +// out how to use the processor because it knows +// what units are available in the processor and how they +// are configured. +// +// This section must be last in or1200_defines.v file so +// that all units are already configured and thus +// configuration registers are properly set. +// + +// Define if you want configuration registers implemented +//`define OR1200_CFGR_IMPLEMENTED + +// Define if you want full address decode inside SYS group +`define OR1200_SYS_FULL_DECODE + +// Offsets of VR, UPR and CFGR registers +`define OR1200_SPRGRP_SYS_VR 4'h0 +`define OR1200_SPRGRP_SYS_UPR 4'h1 +`define OR1200_SPRGRP_SYS_CPUCFGR 4'h2 +`define OR1200_SPRGRP_SYS_DMMUCFGR 4'h3 +`define OR1200_SPRGRP_SYS_IMMUCFGR 4'h4 +`define OR1200_SPRGRP_SYS_DCCFGR 4'h5 +`define OR1200_SPRGRP_SYS_ICCFGR 4'h6 +`define OR1200_SPRGRP_SYS_DCFGR 4'h7 + +// VR fields +`define OR1200_VR_REV_BITS 5:0 +`define OR1200_VR_RES1_BITS 15:6 +`define OR1200_VR_CFG_BITS 23:16 +`define OR1200_VR_VER_BITS 31:24 + +// VR values +`define OR1200_VR_REV 6'h01 +`define OR1200_VR_RES1 10'h000 +`define OR1200_VR_CFG 8'h00 +`define OR1200_VR_VER 8'h12 + +// UPR fields +`define OR1200_UPR_UP_BITS 0 +`define OR1200_UPR_DCP_BITS 1 +`define OR1200_UPR_ICP_BITS 2 +`define OR1200_UPR_DMP_BITS 3 +`define OR1200_UPR_IMP_BITS 4 +`define OR1200_UPR_MP_BITS 5 +`define OR1200_UPR_DUP_BITS 6 +`define OR1200_UPR_PCUP_BITS 7 +`define OR1200_UPR_PMP_BITS 8 +`define OR1200_UPR_PICP_BITS 9 +`define OR1200_UPR_TTP_BITS 10 +`define OR1200_UPR_RES1_BITS 23:11 +`define OR1200_UPR_CUP_BITS 31:24 + +// UPR values +`define OR1200_UPR_UP 1'b1 +`ifdef OR1200_NO_DC +`define OR1200_UPR_DCP 1'b0 +`else +`define OR1200_UPR_DCP 1'b1 +`endif +`ifdef OR1200_NO_IC +`define OR1200_UPR_ICP 1'b0 +`else +`define OR1200_UPR_ICP 1'b1 +`endif +`ifdef OR1200_NO_DMMU +`define OR1200_UPR_DMP 1'b0 +`else +`define OR1200_UPR_DMP 1'b1 +`endif +`ifdef OR1200_NO_IMMU +`define OR1200_UPR_IMP 1'b0 +`else +`define OR1200_UPR_IMP 1'b1 +`endif +`define OR1200_UPR_MP 1'b1 // MAC always present +`ifdef OR1200_DU_IMPLEMENTED +`define OR1200_UPR_DUP 1'b1 +`else +`define OR1200_UPR_DUP 1'b0 +`endif +`define OR1200_UPR_PCUP 1'b0 // Performance counters not present +`ifdef OR1200_DU_IMPLEMENTED +`define OR1200_UPR_PMP 1'b1 +`else +`define OR1200_UPR_PMP 1'b0 +`endif +`ifdef OR1200_DU_IMPLEMENTED +`define OR1200_UPR_PICP 1'b1 +`else +`define OR1200_UPR_PICP 1'b0 +`endif +`ifdef OR1200_DU_IMPLEMENTED +`define OR1200_UPR_TTP 1'b1 +`else +`define OR1200_UPR_TTP 1'b0 +`endif +`define OR1200_UPR_RES1 13'h0000 +`define OR1200_UPR_CUP 8'h00 + +// CPUCFGR fields +`define OR1200_CPUCFGR_NSGF_BITS 3:0 +`define OR1200_CPUCFGR_HGF_BITS 4 +`define OR1200_CPUCFGR_OB32S_BITS 5 +`define OR1200_CPUCFGR_OB64S_BITS 6 +`define OR1200_CPUCFGR_OF32S_BITS 7 +`define OR1200_CPUCFGR_OF64S_BITS 8 +`define OR1200_CPUCFGR_OV64S_BITS 9 +`define OR1200_CPUCFGR_RES1_BITS 31:10 + +// CPUCFGR values +`define OR1200_CPUCFGR_NSGF 4'h0 +`define OR1200_CPUCFGR_HGF 1'b0 +`define OR1200_CPUCFGR_OB32S 1'b1 +`define OR1200_CPUCFGR_OB64S 1'b0 +`define OR1200_CPUCFGR_OF32S 1'b0 +`define OR1200_CPUCFGR_OF64S 1'b0 +`define OR1200_CPUCFGR_OV64S 1'b0 +`define OR1200_CPUCFGR_RES1 22'h000000 + +// DMMUCFGR fields +`define OR1200_DMMUCFGR_NTW_BITS 1:0 +`define OR1200_DMMUCFGR_NTS_BITS 4:2 +`define OR1200_DMMUCFGR_NAE_BITS 7:5 +`define OR1200_DMMUCFGR_CRI_BITS 8 +`define OR1200_DMMUCFGR_PRI_BITS 9 +`define OR1200_DMMUCFGR_TEIRI_BITS 10 +`define OR1200_DMMUCFGR_HTR_BITS 11 +`define OR1200_DMMUCFGR_RES1_BITS 31:12 + +// DMMUCFGR values +`ifdef OR1200_NO_DMMU +`define OR1200_DMMUCFGR_NTW 2'h0 // Irrelevant +`define OR1200_DMMUCFGR_NTS 3'h0 // Irrelevant +`define OR1200_DMMUCFGR_NAE 3'h0 // Irrelevant +`define OR1200_DMMUCFGR_CRI 1'b0 // Irrelevant +`define OR1200_DMMUCFGR_PRI 1'b0 // Irrelevant +`define OR1200_DMMUCFGR_TEIRI 1'b0 // Irrelevant +`define OR1200_DMMUCFGR_HTR 1'b0 // Irrelevant +`define OR1200_DMMUCFGR_RES1 20'h00000 +`else +`define OR1200_DMMUCFGR_NTW 2'h0 // 1 TLB way +`define OR1200_DMMUCFGR_NTS 3'h`OR1200_DTLB_INDXW // Num TLB sets +`define OR1200_DMMUCFGR_NAE 3'h0 // No ATB entries +`define OR1200_DMMUCFGR_CRI 1'b0 // No control register +`define OR1200_DMMUCFGR_PRI 1'b0 // No protection reg +`define OR1200_DMMUCFGR_TEIRI 1'b1 // TLB entry inv reg impl. +`define OR1200_DMMUCFGR_HTR 1'b0 // No HW TLB reload +`define OR1200_DMMUCFGR_RES1 20'h00000 +`endif + +// IMMUCFGR fields +`define OR1200_IMMUCFGR_NTW_BITS 1:0 +`define OR1200_IMMUCFGR_NTS_BITS 4:2 +`define OR1200_IMMUCFGR_NAE_BITS 7:5 +`define OR1200_IMMUCFGR_CRI_BITS 8 +`define OR1200_IMMUCFGR_PRI_BITS 9 +`define OR1200_IMMUCFGR_TEIRI_BITS 10 +`define OR1200_IMMUCFGR_HTR_BITS 11 +`define OR1200_IMMUCFGR_RES1_BITS 31:12 + +// IMMUCFGR values +`ifdef OR1200_NO_IMMU +`define OR1200_IMMUCFGR_NTW 2'h0 // Irrelevant +`define OR1200_IMMUCFGR_NTS 3'h0 // Irrelevant +`define OR1200_IMMUCFGR_NAE 3'h0 // Irrelevant +`define OR1200_IMMUCFGR_CRI 1'b0 // Irrelevant +`define OR1200_IMMUCFGR_PRI 1'b0 // Irrelevant +`define OR1200_IMMUCFGR_TEIRI 1'b0 // Irrelevant +`define OR1200_IMMUCFGR_HTR 1'b0 // Irrelevant +`define OR1200_IMMUCFGR_RES1 20'h00000 +`else +`define OR1200_IMMUCFGR_NTW 2'h0 // 1 TLB way +`define OR1200_IMMUCFGR_NTS 3'h`OR1200_ITLB_INDXW // Num TLB sets +`define OR1200_IMMUCFGR_NAE 3'h0 // No ATB entry +`define OR1200_IMMUCFGR_CRI 1'b0 // No control reg +`define OR1200_IMMUCFGR_PRI 1'b0 // No protection reg +`define OR1200_IMMUCFGR_TEIRI 1'b1 // TLB entry inv reg impl +`define OR1200_IMMUCFGR_HTR 1'b0 // No HW TLB reload +`define OR1200_IMMUCFGR_RES1 20'h00000 +`endif + +// DCCFGR fields +`define OR1200_DCCFGR_NCW_BITS 2:0 +`define OR1200_DCCFGR_NCS_BITS 6:3 +`define OR1200_DCCFGR_CBS_BITS 7 +`define OR1200_DCCFGR_CWS_BITS 8 +`define OR1200_DCCFGR_CCRI_BITS 9 +`define OR1200_DCCFGR_CBIRI_BITS 10 +`define OR1200_DCCFGR_CBPRI_BITS 11 +`define OR1200_DCCFGR_CBLRI_BITS 12 +`define OR1200_DCCFGR_CBFRI_BITS 13 +`define OR1200_DCCFGR_CBWBRI_BITS 14 +`define OR1200_DCCFGR_RES1_BITS 31:15 + +// DCCFGR values +`ifdef OR1200_NO_DC +`define OR1200_DCCFGR_NCW 3'h0 // Irrelevant +`define OR1200_DCCFGR_NCS 4'h0 // Irrelevant +`define OR1200_DCCFGR_CBS 1'b0 // Irrelevant +`define OR1200_DCCFGR_CWS 1'b0 // Irrelevant +`define OR1200_DCCFGR_CCRI 1'b1 // Irrelevant +`define OR1200_DCCFGR_CBIRI 1'b1 // Irrelevant +`define OR1200_DCCFGR_CBPRI 1'b0 // Irrelevant +`define OR1200_DCCFGR_CBLRI 1'b0 // Irrelevant +`define OR1200_DCCFGR_CBFRI 1'b1 // Irrelevant +`define OR1200_DCCFGR_CBWBRI 1'b0 // Irrelevant +`define OR1200_DCCFGR_RES1 17'h00000 +`else +`define OR1200_DCCFGR_NCW 3'h0 // 1 cache way +`define OR1200_DCCFGR_NCS (`OR1200_DCTAG) // Num cache sets +`define OR1200_DCCFGR_CBS (`OR1200_DCLS-4) // 16 byte cache block +`define OR1200_DCCFGR_CWS 1'b0 // Write-through strategy +`define OR1200_DCCFGR_CCRI 1'b1 // Cache control reg impl. +`define OR1200_DCCFGR_CBIRI 1'b1 // Cache block inv reg impl. +`define OR1200_DCCFGR_CBPRI 1'b0 // Cache block prefetch reg not impl. +`define OR1200_DCCFGR_CBLRI 1'b0 // Cache block lock reg not impl. +`define OR1200_DCCFGR_CBFRI 1'b1 // Cache block flush reg impl. +`define OR1200_DCCFGR_CBWBRI 1'b0 // Cache block WB reg not impl. +`define OR1200_DCCFGR_RES1 17'h00000 +`endif + +// ICCFGR fields +`define OR1200_ICCFGR_NCW_BITS 2:0 +`define OR1200_ICCFGR_NCS_BITS 6:3 +`define OR1200_ICCFGR_CBS_BITS 7 +`define OR1200_ICCFGR_CWS_BITS 8 +`define OR1200_ICCFGR_CCRI_BITS 9 +`define OR1200_ICCFGR_CBIRI_BITS 10 +`define OR1200_ICCFGR_CBPRI_BITS 11 +`define OR1200_ICCFGR_CBLRI_BITS 12 +`define OR1200_ICCFGR_CBFRI_BITS 13 +`define OR1200_ICCFGR_CBWBRI_BITS 14 +`define OR1200_ICCFGR_RES1_BITS 31:15 + +// ICCFGR values +`ifdef OR1200_NO_IC +`define OR1200_ICCFGR_NCW 3'h0 // Irrelevant +`define OR1200_ICCFGR_NCS 4'h0 // Irrelevant +`define OR1200_ICCFGR_CBS 1'b0 // Irrelevant +`define OR1200_ICCFGR_CWS 1'b0 // Irrelevant +`define OR1200_ICCFGR_CCRI 1'b0 // Irrelevant +`define OR1200_ICCFGR_CBIRI 1'b0 // Irrelevant +`define OR1200_ICCFGR_CBPRI 1'b0 // Irrelevant +`define OR1200_ICCFGR_CBLRI 1'b0 // Irrelevant +`define OR1200_ICCFGR_CBFRI 1'b0 // Irrelevant +`define OR1200_ICCFGR_CBWBRI 1'b0 // Irrelevant +`define OR1200_ICCFGR_RES1 17'h00000 +`else +`define OR1200_ICCFGR_NCW 3'h0 // 1 cache way +`define OR1200_ICCFGR_NCS (`OR1200_ICTAG) // Num cache sets +`define OR1200_ICCFGR_CBS (`OR1200_ICLS-4) // 16 byte cache block +`define OR1200_ICCFGR_CWS 1'b0 // Irrelevant +`define OR1200_ICCFGR_CCRI 1'b1 // Cache control reg impl. +`define OR1200_ICCFGR_CBIRI 1'b1 // Cache block inv reg impl. +`define OR1200_ICCFGR_CBPRI 1'b0 // Cache block prefetch reg not impl. +`define OR1200_ICCFGR_CBLRI 1'b0 // Cache block lock reg not impl. +`define OR1200_ICCFGR_CBFRI 1'b1 // Cache block flush reg impl. +`define OR1200_ICCFGR_CBWBRI 1'b0 // Irrelevant +`define OR1200_ICCFGR_RES1 17'h00000 +`endif + +// DCFGR fields +`define OR1200_DCFGR_NDP_BITS 2:0 +`define OR1200_DCFGR_WPCI_BITS 3 +`define OR1200_DCFGR_RES1_BITS 31:4 + +// DCFGR values +`ifdef OR1200_DU_HWBKPTS +`define OR1200_DCFGR_NDP 3'h`OR1200_DU_DVRDCR_PAIRS // # of DVR/DCR pairs +`ifdef OR1200_DU_DWCR0 +`define OR1200_DCFGR_WPCI 1'b1 +`else +`define OR1200_DCFGR_WPCI 1'b0 // WP counters not impl. +`endif +`else +`define OR1200_DCFGR_NDP 3'h0 // Zero DVR/DCR pairs +`define OR1200_DCFGR_WPCI 1'b0 // WP counters not impl. +`endif +`define OR1200_DCFGR_RES1 28'h0000000 + Index: release-1.0/backend/ug257/ug257.ucf =================================================================== --- release-1.0/backend/ug257/ug257.ucf (nonexistent) +++ release-1.0/backend/ug257/ug257.ucf (revision 151) @@ -0,0 +1,64 @@ +# +# Soldered 50MHz clock. +# +NET "clk" LOC = "C9"; + +# +# Use button "south" as reset. +# +NET "reset" LOC = "K17" | PULLDOWN ; + +# +# UART serial port (RS232 DCE) - connector DB9 female. +# +NET "uart_srx" LOC = "R7"; +NET "uart_stx" LOC = "M14" | DRIVE = 8 | SLEW = SLOW ; + +########################### +## +## ETH +## +#NET "eth_txd(3)" LOC = "t5"; +#NET "eth_txd(2)" LOC = "r5"; +#NET "eth_txd(1)" LOC = "t15"; +#NET "eth_txd(0)" LOC = "r11"; +# +#NET "eth_tx_en" LOC = "p15"; +#NET "eth_tx_clk" LOC = "t7" | CLOCK_DEDICATED_ROUTE = FALSE; +#NET "eth_tx_er" LOC = "r6"; +# +#NET "eth_rxd(3)" LOC = "v14"; +#NET "eth_rxd(2)" LOC = "u11"; +#NET "eth_rxd(1)" LOC = "t11"; +#NET "eth_rxd(0)" LOC = "v8"; +# +#NET "eth_rx_er" LOC = "u14"; +#NET "eth_rx_dv" LOC = "v2"; +# +#NET "eth_rx_clk" LOC = "v3" | CLOCK_DEDICATED_ROUTE = FALSE; +# +#NET "eth_mdio" LOC = "u5" | PULLUP; +#NET "eth_crs" LOC = "u13"; +#NET "eth_col" LOC = "u6"; +#NET "eth_mdc" LOC = "p9"; +# +#NET "eth_trste" LOC = "p13"; #put it to a non connected FPGA pin (starter kit schematic BANK3) +# +#NET "eth_fds_mdint" LOC = "r13" | PULLUP; #put it to a non connected FPGA pin (starter kit schematic BANK3)(pullup not to generate interrupts) +########################### + +# +# JTAG signals - on J4 6-pin accessory header. +# + +#NET "jtag_tms" LOC = "D7" | PULLDOWN ; +#NET "jtag_tdi" LOC = "C7" | PULLDOWN ; +#NET "jtag_tdo" LOC = "F8" | SLEW = FAST | DRIVE = 8 ; +#NET "jtag_tck" LOC = "E8" | PULLDOWN ; + +#net "jtag_gnd" loc = "k2"; #put it to a non connected FPGA pin (starter kit schematic BANK3) +#net "jtag_vref" loc = "k7"; #put it to a non connected FPGA pin (starter kit schematic BANK3) + +# +# End of file. +#
release-1.0/backend/ug257/ug257.ucf Property changes : Added: svn:executable ## -0,0 +1 ## +* \ No newline at end of property Index: release-1.0/backend/ug257/minsoc_defines.v =================================================================== --- release-1.0/backend/ug257/minsoc_defines.v (nonexistent) +++ release-1.0/backend/ug257/minsoc_defines.v (revision 151) @@ -0,0 +1,150 @@ +// +// Define FPGA manufacturer +// +//`define GENERIC_FPGA +//`define ALTERA_FPGA +`define XILINX_FPGA + +// +// Define Xilinx FPGA family +// +`ifdef XILINX_FPGA +//`define SPARTAN2 +//`define SPARTAN3 +`define SPARTAN3E +//`define SPARTAN3A +//`define VIRTEX +//`define VIRTEX2 +//`define VIRTEX4 +//`define VIRTEX5 + +// +// Define Altera FPGA family +// +`elsif ALTERA_FPGA +//`define ARRIA_GX +//`define ARRIA_II_GX +//`define CYCLONE_I +//`define CYCLONE_II +`define CYCLONE_III +//`define CYCLONE_III_LS +//`define CYCLONE_IV_E +//`define CYCLONE_IV_GS +//`define MAX_II +//`define MAX_V +//`define MAX3000A +//`define MAX7000AE +//`define MAX7000B +//`define MAX7000S +//`define STRATIX +//`define STRATIX_II +//`define STRATIX_II_GX +//`define STRATIX_III +`endif + +// +// Memory +// +`define MEMORY_ADR_WIDTH 13 //MEMORY_ADR_WIDTH IS NOT ALLOWED TO BE LESS THAN 12, + //memory is composed by blocks of address width 11 + //Address width of memory -> select memory depth, + //2 powers MEMORY_ADR_WIDTH defines the memory depth + //the memory data width is 32 bit, + //memory amount in Bytes = 4*memory depth + +// +// Memory type (uncomment something if ASIC or generic memory) +// +//`define GENERIC_MEMORY +//`define AVANT_ATP +//`define VIRAGE_SSP +//`define VIRTUALSILICON_SSP + + +// +// TAP selection +// +//`define GENERIC_TAP +`define FPGA_TAP + +// +// Clock Division selection +// +//`define NO_CLOCK_DIVISION +//`define GENERIC_CLOCK_DIVISION +`define FPGA_CLOCK_DIVISION // For Altera ALTPLL, only CYCLONE_III family has been tested. + +// +// Define division +// +`define CLOCK_DIVISOR 5 //in case of GENERIC_CLOCK_DIVISION the real value will be rounded + //down to an even value in FPGA case, check minsoc_clock_manager + //for allowed divisors. + //DO NOT USE CLOCK_DIVISOR = 1 COMMENT THE CLOCK DIVISION SELECTION + //INSTEAD. + +// +// Reset polarity +// +//`define NEGATIVE_RESET //rstn +`define POSITIVE_RESET //rst + +// +// Start-up circuit (only necessary later to load firmware automatically from SPI memory) +// +//`define START_UP + +// +// Connected modules +// +`define UART +//`define ETHERNET + +// +// Ethernet reset +// +`define ETH_RESET 1'b0 +//`define ETH_RESET 1'b1 + +// +// Interrupts +// +`define APP_INT_RES1 1:0 +`define APP_INT_UART 2 +`define APP_INT_RES2 3 +`define APP_INT_ETH 4 +`define APP_INT_PS2 5 +`define APP_INT_RES3 19:6 + +// +// Address map +// +`define APP_ADDR_DEC_W 8 +`define APP_ADDR_SRAM `APP_ADDR_DEC_W'h00 +`define APP_ADDR_FLASH `APP_ADDR_DEC_W'h04 +`define APP_ADDR_DECP_W 4 +`define APP_ADDR_PERIP `APP_ADDR_DECP_W'h9 +`define APP_ADDR_SPI `APP_ADDR_DEC_W'h97 +`define APP_ADDR_ETH `APP_ADDR_DEC_W'h92 +`define APP_ADDR_AUDIO `APP_ADDR_DEC_W'h9d +`define APP_ADDR_UART `APP_ADDR_DEC_W'h90 +`define APP_ADDR_PS2 `APP_ADDR_DEC_W'h94 +`define APP_ADDR_RES1 `APP_ADDR_DEC_W'h9e +`define APP_ADDR_RES2 `APP_ADDR_DEC_W'h9f + +// +// Set-up GENERIC_TAP, GENERIC_MEMORY if GENERIC_FPGA was chosen +// and GENERIC_CLOCK_DIVISION if NO_CLOCK_DIVISION was not set +// +`ifdef GENERIC_FPGA + `undef FPGA_TAP + `undef FPGA_CLOCK_DIVISION + `undef XILINX_FPGA + `undef SPARTAN3E + + `define GENERIC_TAP + `define GENERIC_MEMORY + `ifndef NO_CLOCK_DIVISION + `define GENERIC_CLOCK_DIVISION + `endif +`endif
release-1.0/backend/ug257/minsoc_defines.v Property changes : Added: svn:executable ## -0,0 +1 ## +* \ No newline at end of property Index: release-1.0/backend/ug257/board.h =================================================================== --- release-1.0/backend/ug257/board.h (nonexistent) +++ release-1.0/backend/ug257/board.h (revision 151) @@ -0,0 +1,40 @@ +#ifndef _BOARD_H_ +#define _BOARD_H_ + +#define MC_ENABLED 0 + +#define IC_ENABLE 0 +#define IC_SIZE 8192 +#define DC_ENABLE 0 +#define DC_SIZE 8192 + + +#define IN_CLK 10000000 + + +#define STACK_SIZE 0x01000 + +#define UART_BAUD_RATE 9600 + +#define UART_BASE 0x90000000 +#define UART_IRQ 2 +#define ETH_BASE 0x92000000 +#define ETH_IRQ 4 +#define I2C_BASE 0x9D000000 +#define I2C_IRQ 3 +#define CAN_BASE 0x94000000 +#define CAN_IRQ 5 + +#define MC_BASE_ADDR 0x60000000 +#define SPI_BASE 0xa0000000 + +#define ETH_DATA_BASE 0xa8000000 /* Address for ETH_DATA */ + +#define ETH_MACADDR0 0x00 +#define ETH_MACADDR1 0x12 +#define ETH_MACADDR2 0x34 +#define ETH_MACADDR3 0x56 +#define ETH_MACADDR4 0x78 +#define ETH_MACADDR5 0x9a + +#endif
release-1.0/backend/ug257/board.h Property changes : Added: svn:executable ## -0,0 +1 ## +* \ No newline at end of property Index: release-1.0/backend/ug257/orp.ld =================================================================== --- release-1.0/backend/ug257/orp.ld (nonexistent) +++ release-1.0/backend/ug257/orp.ld (revision 151) @@ -0,0 +1,60 @@ +MEMORY + { + reset : ORIGIN = 0x00000000, LENGTH = 0x00000200 + vectors : ORIGIN = 0x00000200, LENGTH = 0x00001000 + ram : ORIGIN = 0x00001200, LENGTH = 0x00002E00 + } + +SECTIONS +{ + .reset : + { + *(.reset) + } > reset + + + + .vectors : + { + _vec_start = .; + *(.vectors) + _vec_end = .; + } > vectors + + .text : + { + *(.text) + } > ram + + .rodata : + { + *(.rodata) + *(.rodata.*) + } > ram + + .icm : + { + _icm_start = .; + *(.icm) + _icm_end = .; + } > ram + + .data : + { + _dst_beg = .; + *(.data) + _dst_end = .; + } > ram + + .bss : + { + *(.bss) + } > ram + + .stack (NOLOAD) : + { + *(.stack) + _src_addr = .; + } > ram + +}
release-1.0/backend/ug257/orp.ld Property changes : Added: svn:executable ## -0,0 +1 ## +* \ No newline at end of property Index: release-1.0/backend/std/minsoc_bench_defines.v =================================================================== --- release-1.0/backend/std/minsoc_bench_defines.v (nonexistent) +++ release-1.0/backend/std/minsoc_bench_defines.v (revision 151) @@ -0,0 +1,29 @@ +//set RTL for simulation, override FPGA specific definitions (JTAG TAP, MEMORY and CLOCK DIVIDER) +`define GENERIC_FPGA +`define MEMORY_MODEL //simulation uses a memory model enabling INITIALIZE_MEMORY_MODEL. If you comment this, START_UP might be interesting. +`define NO_CLOCK_DIVISION //if commented out, generic clock division is implemented (odd divisors are rounded down) +//~set RTL for simulation, override FPGA specific definitions (JTAG TAP, MEMORY and CLOCK DIVIDER) + +`define FREQ_NUM_FOR_NS 100000000 + +`define FREQ 25000000 +`define CLK_PERIOD (`FREQ_NUM_FOR_NS/`FREQ) + +`define ETH_PHY_FREQ 25000000 +`define ETH_PHY_PERIOD (`FREQ_NUM_FOR_NS/`ETH_PHY_FREQ) //40ns + +`define UART_BAUDRATE 115200 + +`define VPI_DEBUG + +//`define WAVEFORM_OUTPUT + +//`define START_UP //pass firmware over spi to or1k_startup + +`define INITIALIZE_MEMORY_MODEL //instantaneously initialize memory model with firmware + //only use with the memory model. + //If you use the original memory (`define MEMORY_MODEL + //commented out), comment this too. + +`define TEST_UART +//`define TEST_ETHERNET
release-1.0/backend/std/minsoc_bench_defines.v Property changes : Added: svn:executable ## -0,0 +1 ## +* \ No newline at end of property Index: release-1.0/backend/std/configure =================================================================== --- release-1.0/backend/std/configure (nonexistent) +++ release-1.0/backend/std/configure (revision 151) @@ -0,0 +1,115 @@ +#!/bin/bash + +#new boards have to udpate this +BOARD=std #this has to have the name of the directory this file is in +DEVICE_PART='NONE' +CONSTRAINT_FILE='NONE' +#~new boards update + +#system workings +MINSOC_DIR=`pwd`/../.. +BACKEND_DIR=$MINSOC_DIR/backend +SYN_DIR=$MINSOC_DIR/syn +SYNSRC_DIR=$MINSOC_DIR/prj/xilinx +SYNSUPPORT_DIR=$SYN_DIR/buildSupport +MAKEFILE_DIR=$SYN_DIR/xilinx + +SYN_FILES=(ethmac.xst uart_top.xst adbg_top.xst or1200_top.xst minsoc_top.xst) +MAKEFILE=Makefile + +FIND_PART='DEVICE_PART' +FIND_CONSTRAINT='CONSTRAINT_FILE' + +BOARD_DIR=$BACKEND_DIR/$BOARD +BOARD_FILES=(board.h orp.ld minsoc_defines.v minsoc_bench_defines.v gcc-opt.mk $CONSTRAINT_FILE) + +in_minsoc=`pwd | grep minsoc/backend/${BOARD}$` +if [ -z $in_minsoc ] +then + echo "" + echo " !!!WARNING!!!" + echo "This script cannot be run if not in a board directory inside minsoc/backend," + echo "because it relies on the directory structure of the minsoc system." + echo "" + echo "Possibly your minsoc directory is named differently, minsoc_trunk for example." + echo "Its name must be minsoc only." + echo "" + exit 1 +fi + +echo "" +echo "This script sets up the SoC for simulations and synthesis." +echo "" +echo "In order to do so, SoC board's specific files for firmware compilation, " +echo "testbench generation and synthesis are configured." +echo "Firmware and testbench looks for board specific files under $BACKEND_DIR." +echo "Synthesis work under $SYN_DIR." +echo "" +echo "" + +echo "Copying board specific SoC files from $BOARD_DIR to $BACKEND_DIR directory." +echo "__________________________________________________________________________" +echo "" +for file in "${BOARD_FILES[@]}" +do + if [ $file != NONE ] + then + echo "Copying $file, to backend directory..." + cp $BOARD_DIR/$file $BACKEND_DIR + fi +done +echo "" +echo "" + +echo "Generating project files for simulation and synthesis..." +echo "__________________________________________________________________________" +echo "" +make -C $MINSOC_DIR/prj +echo "Generation complete." +echo "" +echo "" + +if [ $CONSTRAINT_FILE == 'NONE' ] +then + echo "Skipping synthesis preparation. Standard implementation can only be simulated." + echo "" + echo "" +else + echo "Device part for files under $SYNSRC_DIR will be patched and stored " + echo "temporarily." + echo "Afterwards, they are copied to $SYNSUPPORT_DIR." + echo "__________________________________________________________________________" + echo "" + for file in "${SYN_FILES[@]}" + do + echo "Updating synthesis file, $file..." + echo "Copying $file to synthesis directory..." + echo "" + sed "s/$FIND_PART/$DEVICE_PART/g" $SYNSRC_DIR/$file > TMPFILE + sed "s/$FIND_CONSTRAINT/$CONSTRAINT_FILE/g" TMPFILE > TMPFILE2 && mv TMPFILE2 $SYNSUPPORT_DIR/$file + rm TMPFILE + done + + echo "Updating Makefile file under $MAKEFILE_DIR..." + echo "Copying Makefile to synthesis directory, $SYN_DIR..." + echo "" + sed "s/$FIND_PART/$DEVICE_PART/g" $MAKEFILE_DIR/$MAKEFILE > TMPFILE + sed "s/$FIND_CONSTRAINT/$CONSTRAINT_FILE/g" TMPFILE > TMPFILE2 && mv TMPFILE2 $SYN_DIR/$MAKEFILE + rm TMPFILE + cp $MAKEFILE_DIR/setup.bat $SYN_DIR/setup.bat + echo "" + echo "" +fi + +#Precompiling firmwares +echo "Precompiling delivered libraries and firmwares..." +make -C ../../sw/utils +make -C ../../sw/support +make -C ../../sw/drivers +make -C ../../sw/uart +make -C ../../sw/eth +echo "done." +echo "" +echo "" + +echo "Configuration done."
release-1.0/backend/std/configure Property changes : Added: svn:executable ## -0,0 +1 ## +* \ No newline at end of property Index: release-1.0/backend/std/gcc-opt.mk =================================================================== --- release-1.0/backend/std/gcc-opt.mk (nonexistent) +++ release-1.0/backend/std/gcc-opt.mk (revision 151) @@ -0,0 +1 @@ +GCC_OPT=-mhard-mul -mhard-div -nostdlib Index: release-1.0/backend/std/minsoc_defines.v =================================================================== --- release-1.0/backend/std/minsoc_defines.v (nonexistent) +++ release-1.0/backend/std/minsoc_defines.v (revision 151) @@ -0,0 +1,148 @@ +// +// Define FPGA manufacturer +// +`define GENERIC_FPGA +//`define ALTERA_FPGA +//`define XILINX_FPGA + +// +// Define Xilinx FPGA family +// +`ifdef XILINX_FPGA +//`define SPARTAN2 +//`define SPARTAN3 +//`define SPARTAN3E +`define SPARTAN3A +//`define VIRTEX +//`define VIRTEX2 +//`define VIRTEX4 +//`define VIRTEX5 + +// +// Define Altera FPGA family +// +`elsif ALTERA_FPGA +//`define ARRIA_GX +//`define ARRIA_II_GX +//`define CYCLONE_I +//`define CYCLONE_II +`define CYCLONE_III +//`define CYCLONE_III_LS +//`define CYCLONE_IV_E +//`define CYCLONE_IV_GS +//`define MAX_II +//`define MAX_V +//`define MAX3000A +//`define MAX7000AE +//`define MAX7000B +//`define MAX7000S +//`define STRATIX +//`define STRATIX_II +//`define STRATIX_II_GX +//`define STRATIX_III +`endif + +// +// Memory +// +`define MEMORY_ADR_WIDTH 13 //MEMORY_ADR_WIDTH IS NOT ALLOWED TO BE LESS THAN 12, + //memory is composed by blocks of address width 11 + //Address width of memory -> select memory depth, + //2 powers MEMORY_ADR_WIDTH defines the memory depth + //the memory data width is 32 bit, + //memory amount in Bytes = 4*memory depth + +// +// Memory type (uncomment something if ASIC or generic memory) +// +//`define GENERIC_MEMORY +//`define AVANT_ATP +//`define VIRAGE_SSP +//`define VIRTUALSILICON_SSP + + +// +// TAP selection +// +//`define GENERIC_TAP +`define FPGA_TAP + +// +// Clock Division selection +// +//`define NO_CLOCK_DIVISION +//`define GENERIC_CLOCK_DIVISION +`define FPGA_CLOCK_DIVISION // For Altera ALTPLL, only CYCLONE_III family has been tested. + +// +// Define division +// +`define CLOCK_DIVISOR 5 //in case of GENERIC_CLOCK_DIVISION the real value will be rounded + //down to an even value in FPGA case, check minsoc_clock_manager + //for allowed divisors. + //DO NOT USE CLOCK_DIVISOR = 1 COMMENT THE CLOCK DIVISION SELECTION + //INSTEAD. + +// +// Reset polarity +// +`define NEGATIVE_RESET //rstn +//`define POSITIVE_RESET //rst + +// +// Start-up circuit (only necessary later to load firmware automatically from SPI memory) +// +//`define START_UP + +// +// Connected modules +// +`define UART +`define ETHERNET + +// +// Ethernet reset +// +`define ETH_RESET 1'b0 +//`define ETH_RESET 1'b1 + +// +// Interrupts +// +`define APP_INT_RES1 1:0 +`define APP_INT_UART 2 +`define APP_INT_RES2 3 +`define APP_INT_ETH 4 +`define APP_INT_PS2 5 +`define APP_INT_RES3 19:6 + +// +// Address map +// +`define APP_ADDR_DEC_W 8 +`define APP_ADDR_SRAM `APP_ADDR_DEC_W'h00 +`define APP_ADDR_FLASH `APP_ADDR_DEC_W'h04 +`define APP_ADDR_DECP_W 4 +`define APP_ADDR_PERIP `APP_ADDR_DECP_W'h9 +`define APP_ADDR_SPI `APP_ADDR_DEC_W'h97 +`define APP_ADDR_ETH `APP_ADDR_DEC_W'h92 +`define APP_ADDR_AUDIO `APP_ADDR_DEC_W'h9d +`define APP_ADDR_UART `APP_ADDR_DEC_W'h90 +`define APP_ADDR_PS2 `APP_ADDR_DEC_W'h94 +`define APP_ADDR_RES1 `APP_ADDR_DEC_W'h9e +`define APP_ADDR_RES2 `APP_ADDR_DEC_W'h9f + +// +// Set-up GENERIC_TAP, GENERIC_MEMORY if GENERIC_FPGA was chosen +// and GENERIC_CLOCK_DIVISION if NO_CLOCK_DIVISION was not set +// +`ifdef GENERIC_FPGA + `undef FPGA_TAP + `undef FPGA_CLOCK_DIVISION + + `define GENERIC_TAP + `define GENERIC_MEMORY + `ifndef NO_CLOCK_DIVISION + `define GENERIC_CLOCK_DIVISION + `endif +`endif
release-1.0/backend/std/minsoc_defines.v Property changes : Added: svn:executable ## -0,0 +1 ## +* \ No newline at end of property Index: release-1.0/backend/std/board.h =================================================================== --- release-1.0/backend/std/board.h (nonexistent) +++ release-1.0/backend/std/board.h (revision 151) @@ -0,0 +1,40 @@ +#ifndef _BOARD_H_ +#define _BOARD_H_ + +#define MC_ENABLED 0 + +#define IC_ENABLE 0 +#define IC_SIZE 8192 +#define DC_ENABLE 0 +#define DC_SIZE 8192 + + +#define IN_CLK 25000000 + + +#define STACK_SIZE 0x01000 + +#define UART_BAUD_RATE 115200 + +#define UART_BASE 0x90000000 +#define UART_IRQ 2 +#define ETH_BASE 0x92000000 +#define ETH_IRQ 4 +#define I2C_BASE 0x9D000000 +#define I2C_IRQ 3 +#define CAN_BASE 0x94000000 +#define CAN_IRQ 5 + +#define MC_BASE_ADDR 0x60000000 +#define SPI_BASE 0xa0000000 + +#define ETH_DATA_BASE 0xa8000000 /* Address for ETH_DATA */ + +#define ETH_MACADDR0 0x00 +#define ETH_MACADDR1 0x12 +#define ETH_MACADDR2 0x34 +#define ETH_MACADDR3 0x56 +#define ETH_MACADDR4 0x78 +#define ETH_MACADDR5 0x9a + +#endif
release-1.0/backend/std/board.h Property changes : Added: svn:executable ## -0,0 +1 ## +* \ No newline at end of property Index: release-1.0/backend/std/orp.ld =================================================================== --- release-1.0/backend/std/orp.ld (nonexistent) +++ release-1.0/backend/std/orp.ld (revision 151) @@ -0,0 +1,60 @@ +MEMORY + { + reset : ORIGIN = 0x00000000, LENGTH = 0x00000200 + vectors : ORIGIN = 0x00000200, LENGTH = 0x00001000 + ram : ORIGIN = 0x00001200, LENGTH = 0x00006E00 /*0x8000 total*/ + } + +SECTIONS +{ + .reset : + { + *(.reset) + } > reset + + + + .vectors : + { + _vec_start = .; + *(.vectors) + _vec_end = .; + } > vectors + + .text : + { + *(.text) + } > ram + + .rodata : + { + *(.rodata) + *(.rodata.*) + } > ram + + .icm : + { + _icm_start = .; + *(.icm) + _icm_end = .; + } > ram + + .data : + { + _dst_beg = .; + *(.data) + _dst_end = .; + } > ram + + .bss : + { + *(.bss) + } > ram + + .stack (NOLOAD) : + { + *(.stack) + _src_addr = .; + } > ram + +}
release-1.0/backend/std/orp.ld Property changes : Added: svn:executable ## -0,0 +1 ## +* \ No newline at end of property Index: release-1.0/backend/altera_3c25_board/minsoc_bench_defines.v =================================================================== --- release-1.0/backend/altera_3c25_board/minsoc_bench_defines.v (nonexistent) +++ release-1.0/backend/altera_3c25_board/minsoc_bench_defines.v (revision 151) @@ -0,0 +1,29 @@ +//set RTL for simulation, override FPGA specific definitions (JTAG TAP, MEMORY and CLOCK DIVIDER) +`define GENERIC_FPGA +`define MEMORY_MODEL //simulation uses a memory model enabling INITIALIZE_MEMORY_MODEL. If you comment this, START_UP might be interesting. +`define NO_CLOCK_DIVISION //if commented out, generic clock division is implemented (odd divisors are rounded down) +//~set RTL for simulation, override FPGA specific definitions (JTAG TAP, MEMORY and CLOCK DIVIDER) + +`define FREQ_NUM_FOR_NS 100000000 + +`define FREQ 25000000 +`define CLK_PERIOD (`FREQ_NUM_FOR_NS/`FREQ) + +`define ETH_PHY_FREQ 25000000 +`define ETH_PHY_PERIOD (`FREQ_NUM_FOR_NS/`ETH_PHY_FREQ) //40ns + +`define UART_BAUDRATE 115200 + +`define VPI_DEBUG + +//`define WAVEFORM_OUTPUT + +//`define START_UP //pass firmware over spi to or1k_startup + +`define INITIALIZE_MEMORY_MODEL //instantaneously initialize memory model with firmware + //only use with the memory model. + //If you use the original memory (`define MEMORY_MODEL + //commented out), comment this too. + +`define TEST_UART +//`define TEST_ETHERNET
release-1.0/backend/altera_3c25_board/minsoc_bench_defines.v Property changes : Added: svn:executable ## -0,0 +1 ## +* \ No newline at end of property Index: release-1.0/backend/altera_3c25_board/configure =================================================================== --- release-1.0/backend/altera_3c25_board/configure (nonexistent) +++ release-1.0/backend/altera_3c25_board/configure (revision 151) @@ -0,0 +1,123 @@ +#!/bin/bash + +#new boards have to udpate this +BOARD=altera_3c25_board #this has to have the name of the directory this file is in +DEVICE_PART=EP3C25Q240C8 +CONSTRAINT_FILE='altera_3c25_board.ucf' +FAMILY_PART="Cyclone III" +#~new boards update + +#system workings +MINSOC_DIR=`pwd`/../.. +BACKEND_DIR=$MINSOC_DIR/backend +SYN_DIR=$MINSOC_DIR/syn +SYNSRC_DIR=$MINSOC_DIR/prj/altera +SYNSUPPORT_DIR=$SYN_DIR/buildSupport +MAKEFILE_DIR=$SYN_DIR/altera + +PROJECT_FILE=minsoc_top.qsf + +SYN_FILES=(adbg_top.vprj jtag_top.vprj or1200_top.vprj uart_top.vprj minsoc_top.vprj altera_virtual_jtag.vhdprj) +MAKEFILE=Makefile + +FIND_PART='DEVICE_PART' +FIND_FAMILY='FAMILY_PART' +FIND_VERSION='SW_VERSION' +FIND_CONSTRAINT='CONSTRAINT_FILE' + +BOARD_DIR=$BACKEND_DIR/$BOARD +BOARD_FILES=(board.h orp.ld minsoc_defines.v minsoc_bench_defines.v gcc-opt.mk $CONSTRAINT_FILE) + +in_minsoc=`pwd | grep minsoc/backend/${BOARD}$` +if [ -z $in_minsoc ] +then + echo "" + echo " !!!WARNING!!!" + echo "This script cannot be run if not in a board directory inside minsoc/backend," + echo "because it relies on the directory structure of the minsoc system." + echo "" + echo "Possibly your minsoc directory is named differently, minsoc_trunk for example." + echo "Its name must be minsoc only." + echo "" + exit 1 +fi + +echo "" +echo "This script sets up the SoC for simulations and synthesis." +echo "" +echo "In order to do so, SoC board's specific files for firmware compilation, " +echo "testbench generation and synthesis are configured." +echo "Firmware and testbench looks for board specific files under $BACKEND_DIR." +echo "Synthesis work under $SYN_DIR." +echo "" +echo "" + +echo "Copying board specific SoC files from $BOARD_DIR to $BACKEND_DIR directory." +echo "__________________________________________________________________________" +echo "" +for file in "${BOARD_FILES[@]}" +do + if [ $file != NONE ] + then + echo "Copying $file, to backend directory..." + cp $BOARD_DIR/$file $BACKEND_DIR + fi +done + +echo "Generating project files for simulation and synthesis..." +echo "__________________________________________________________________________" +echo "" +make -C $MINSOC_DIR/prj +echo "Generation complete." +echo "" +echo "" + +if [ $CONSTRAINT_FILE == 'NONE' ] +then + echo "Skipping synthesis preparation. Standard implementation can only be simulated." + echo "" + echo "" +else + echo "Device part and family for files under $SYNSRC_DIR will patched and stored " + echo "temporarily." + echo "Afterwards, they are copied to $SYNSUPPORT_DIR." + echo "__________________________________________________________________________" + echo "" + sed "s/$FIND_PART/$DEVICE_PART/g" $MAKEFILE_DIR/$PROJECT_FILE > TMPFILE + sed "s/$FIND_FAMILY/$FAMILY_PART/g" TMPFILE > TMPFILE2 + #sed "s/$FIND_VERSION/$SW_VERSION/g" TMPFILE> TMPFILE + echo "Adding settings from constraint file..." + cat $CONSTRAINT_FILE >> TMPFILE2 + + echo "Generating quartus settings from prj files in $SYNSRC_DIR" + for file in "${SYN_FILES[@]}" + do + echo "Adding settings from file $file..." + cat $SYNSRC_DIR/$file >> TMPFILE2 + done + mv TMPFILE2 $SYNSUPPORT_DIR/$PROJECT_FILE + rm TMPFILE + echo "" + echo "Generated quartus settings file in $SYNSUPPORT_DIR/$PROJECT_FILE" + echo "" + + echo "Copying Makefile from $MAKEFILE_DIR to synthesis directory, $SYN_DIR..." + cp $MAKEFILE_DIR/$MAKEFILE $SYN_DIR/$MAKEFILE + cp $MAKEFILE_DIR/setup.bat $SYN_DIR/setup.bat + echo "For synthesis help go to $SYN_DIR and type \"make\"." + echo "" + echo "" +fi + +#Precompiling firmwares +echo "Precompiling delivered libraries and firmwares..." +make -C ../../sw/utils +make -C ../../sw/support +make -C ../../sw/drivers +make -C ../../sw/uart +make -C ../../sw/eth +echo "done." +echo "" +echo "" + +echo "Configuration done."
release-1.0/backend/altera_3c25_board/configure Property changes : Added: svn:executable ## -0,0 +1 ## +* \ No newline at end of property Index: release-1.0/backend/altera_3c25_board/minsoc_defines.v =================================================================== --- release-1.0/backend/altera_3c25_board/minsoc_defines.v (nonexistent) +++ release-1.0/backend/altera_3c25_board/minsoc_defines.v (revision 151) @@ -0,0 +1,150 @@ +// +// Define FPGA manufacturer +// +//`define GENERIC_FPGA +`define ALTERA_FPGA +//`define XILINX_FPGA + +// +// Define Xilinx FPGA family +// +`ifdef XILINX_FPGA +//`define SPARTAN2 +//`define SPARTAN3 +//`define SPARTAN3E +`define SPARTAN3A +//`define VIRTEX +//`define VIRTEX2 +//`define VIRTEX4 +//`define VIRTEX5 + +// +// Define Altera FPGA family +// +`elsif ALTERA_FPGA +//`define ARRIA_GX +//`define ARRIA_II_GX +//`define CYCLONE_I +//`define CYCLONE_II +`define CYCLONE_III +//`define CYCLONE_III_LS +//`define CYCLONE_IV_E +//`define CYCLONE_IV_GS +//`define MAX_II +//`define MAX_V +//`define MAX3000A +//`define MAX7000AE +//`define MAX7000B +//`define MAX7000S +//`define STRATIX +//`define STRATIX_II +//`define STRATIX_II_GX +//`define STRATIX_III +`endif + +// +// Memory +// +`define MEMORY_ADR_WIDTH 13 //MEMORY_ADR_WIDTH IS NOT ALLOWED TO BE LESS THAN 12, + //memory is composed by blocks of address width 11 + //Address width of memory -> select memory depth, + //2 powers MEMORY_ADR_WIDTH defines the memory depth + //the memory data width is 32 bit, + //memory amount in Bytes = 4*memory depth + +// +// Memory type (uncomment something if ASIC or generic memory) +// +//`define GENERIC_MEMORY +//`define AVANT_ATP +//`define VIRAGE_SSP +//`define VIRTUALSILICON_SSP + + +// +// TAP selection +// +//`define GENERIC_TAP +`define FPGA_TAP + +// +// Clock Division selection +// +//`define NO_CLOCK_DIVISION +//`define GENERIC_CLOCK_DIVISION +`define FPGA_CLOCK_DIVISION // For Altera ALTPLL, only CYCLONE_III family has been tested. + +// +// Define division +// +`define CLOCK_DIVISOR 2 //in case of GENERIC_CLOCK_DIVISION the real value will be rounded + //down to an even value in FPGA case, check minsoc_clock_manager + //for allowed divisors. + //DO NOT USE CLOCK_DIVISOR = 1 COMMENT THE CLOCK DIVISION SELECTION + //INSTEAD. + +// +// Reset polarity +// +`define NEGATIVE_RESET //rstn +//`define POSITIVE_RESET //rst + +// +// Start-up circuit (only necessary later to load firmware automatically from SPI memory) +// +//`define START_UP + +// +// Connected modules +// +`define UART +//`define ETHERNET + +// +// Ethernet reset +// +//`define ETH_RESET 1'b0 +`define ETH_RESET 1'b1 + +// +// Interrupts +// +`define APP_INT_RES1 1:0 +`define APP_INT_UART 2 +`define APP_INT_RES2 3 +`define APP_INT_ETH 4 +`define APP_INT_PS2 5 +`define APP_INT_RES3 19:6 + +// +// Address map +// +`define APP_ADDR_DEC_W 8 +`define APP_ADDR_SRAM `APP_ADDR_DEC_W'h00 +`define APP_ADDR_FLASH `APP_ADDR_DEC_W'h04 +`define APP_ADDR_DECP_W 4 +`define APP_ADDR_PERIP `APP_ADDR_DECP_W'h9 +`define APP_ADDR_SPI `APP_ADDR_DEC_W'h97 +`define APP_ADDR_ETH `APP_ADDR_DEC_W'h92 +`define APP_ADDR_AUDIO `APP_ADDR_DEC_W'h9d +`define APP_ADDR_UART `APP_ADDR_DEC_W'h90 +`define APP_ADDR_PS2 `APP_ADDR_DEC_W'h94 +`define APP_ADDR_RES1 `APP_ADDR_DEC_W'h9e +`define APP_ADDR_RES2 `APP_ADDR_DEC_W'h9f + +// +// Set-up GENERIC_TAP, GENERIC_MEMORY if GENERIC_FPGA was chosen +// and GENERIC_CLOCK_DIVISION if NO_CLOCK_DIVISION was not set +// +`ifdef GENERIC_FPGA + `undef FPGA_TAP + `undef FPGA_CLOCK_DIVISION + `undef ALTERA_FPGA + `undef CYCLONE_III + + `define GENERIC_TAP + `define GENERIC_MEMORY + `ifndef NO_CLOCK_DIVISION + `define GENERIC_CLOCK_DIVISION + `endif +`endif Index: release-1.0/backend/altera_3c25_board/gcc-opt.mk =================================================================== --- release-1.0/backend/altera_3c25_board/gcc-opt.mk (nonexistent) +++ release-1.0/backend/altera_3c25_board/gcc-opt.mk (revision 151) @@ -0,0 +1 @@ +GCC_OPT=-mhard-mul -mhard-div -nostdlib Index: release-1.0/backend/altera_3c25_board/altera_3c25_board.ucf =================================================================== --- release-1.0/backend/altera_3c25_board/altera_3c25_board.ucf (nonexistent) +++ release-1.0/backend/altera_3c25_board/altera_3c25_board.ucf (revision 151) @@ -0,0 +1,16 @@ +# Altera 3c25 board based pinout and definitions. +# This file uses quartus qsf file format for compose final config file. + +# RS232 Port +set_location_assignment PIN_12 -to uart_srx +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to uart_srx +set_location_assignment PIN_14 -to uart_stx +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to uart_stx + +# 50 Mhz Pin +set_location_assignment PIN_152 -to clk +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to clk + +# Reset pin. +set_location_assignment PIN_200 -to reset +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to reset Index: release-1.0/backend/altera_3c25_board/board.h =================================================================== --- release-1.0/backend/altera_3c25_board/board.h (nonexistent) +++ release-1.0/backend/altera_3c25_board/board.h (revision 151) @@ -0,0 +1,40 @@ +#ifndef _BOARD_H_ +#define _BOARD_H_ + +#define MC_ENABLED 0 + +#define IC_ENABLE 0 +#define IC_SIZE 8192 +#define DC_ENABLE 0 +#define DC_SIZE 8192 + + +#define IN_CLK 25000000 + + +#define STACK_SIZE 0x01000 + +#define UART_BAUD_RATE 115200 + +#define UART_BASE 0x90000000 +#define UART_IRQ 2 +#define ETH_BASE 0x92000000 +#define ETH_IRQ 4 +#define I2C_BASE 0x9D000000 +#define I2C_IRQ 3 +#define CAN_BASE 0x94000000 +#define CAN_IRQ 5 + +#define MC_BASE_ADDR 0x60000000 +#define SPI_BASE 0xa0000000 + +#define ETH_DATA_BASE 0xa8000000 /* Address for ETH_DATA */ + +#define ETH_MACADDR0 0x00 +#define ETH_MACADDR1 0x12 +#define ETH_MACADDR2 0x34 +#define ETH_MACADDR3 0x56 +#define ETH_MACADDR4 0x78 +#define ETH_MACADDR5 0x9a + +#endif
release-1.0/backend/altera_3c25_board/board.h Property changes : Added: svn:executable ## -0,0 +1 ## +* \ No newline at end of property Index: release-1.0/backend/altera_3c25_board/orp.ld =================================================================== --- release-1.0/backend/altera_3c25_board/orp.ld (nonexistent) +++ release-1.0/backend/altera_3c25_board/orp.ld (revision 151) @@ -0,0 +1,60 @@ +MEMORY + { + reset : ORIGIN = 0x00000000, LENGTH = 0x00000200 + vectors : ORIGIN = 0x00000200, LENGTH = 0x00001000 + ram : ORIGIN = 0x00001200, LENGTH = 0x0001EE00 /*0x20000 total*/ + } + +SECTIONS +{ + .reset : + { + *(.reset) + } > reset + + + + .vectors : + { + _vec_start = .; + *(.vectors) + _vec_end = .; + } > vectors + + .text : + { + *(.text) + } > ram + + .rodata : + { + *(.rodata) + *(.rodata.*) + } > ram + + .icm : + { + _icm_start = .; + *(.icm) + _icm_end = .; + } > ram + + .data : + { + _dst_beg = .; + *(.data) + _dst_end = .; + } > ram + + .bss : + { + *(.bss) + } > ram + + .stack (NOLOAD) : + { + *(.stack) + _src_addr = .; + } > ram + +}
release-1.0/backend/altera_3c25_board/orp.ld Property changes : Added: svn:executable ## -0,0 +1 ## +* \ No newline at end of property Index: release-1.0/backend/spartan3e_starter_kit/minsoc_bench_defines.v =================================================================== --- release-1.0/backend/spartan3e_starter_kit/minsoc_bench_defines.v (nonexistent) +++ release-1.0/backend/spartan3e_starter_kit/minsoc_bench_defines.v (revision 151) @@ -0,0 +1,29 @@ +//set RTL for simulation, override FPGA specific definitions (JTAG TAP, MEMORY and CLOCK DIVIDER) +`define GENERIC_FPGA +`define MEMORY_MODEL //simulation uses a memory model enabling INITIALIZE_MEMORY_MODEL. If you comment this, START_UP might be interesting. +`define NO_CLOCK_DIVISION //if commented out, generic clock division is implemented (odd divisors are rounded down) +//~set RTL for simulation, override FPGA specific definitions (JTAG TAP, MEMORY and CLOCK DIVIDER) + +`define FREQ_NUM_FOR_NS 100000000 + +`define FREQ 25000000 +`define CLK_PERIOD (`FREQ_NUM_FOR_NS/`FREQ) + +`define ETH_PHY_FREQ 25000000 +`define ETH_PHY_PERIOD (`FREQ_NUM_FOR_NS/`ETH_PHY_FREQ) //40ns + +`define UART_BAUDRATE 115200 + +`define VPI_DEBUG + +//`define WAVEFORM_OUTPUT + +//`define START_UP //pass firmware over spi to or1k_startup + +`define INITIALIZE_MEMORY_MODEL //instantaneously initialize memory model with firmware + //only use with the memory model. + //If you use the original memory (`define MEMORY_MODEL + //commented out), comment this too. + +`define TEST_UART +//`define TEST_ETHERNET
release-1.0/backend/spartan3e_starter_kit/minsoc_bench_defines.v Property changes : Added: svn:executable ## -0,0 +1 ## +* \ No newline at end of property Index: release-1.0/backend/spartan3e_starter_kit/configure =================================================================== --- release-1.0/backend/spartan3e_starter_kit/configure (nonexistent) +++ release-1.0/backend/spartan3e_starter_kit/configure (revision 151) @@ -0,0 +1,132 @@ +#!/bin/bash + +#NON STANDARD SCRIPT, USE ANOTHER AS TEMPLATE, NON STANDARD PART IS MARKED AS COMMENT + +#new boards have to udpate this +BOARD=spartan3e_starter_kit #this has to have the name of the directory this file is in +DEVICE_PART='xc3s500e-4-fg320' +CONSTRAINT_FILE='spartan3e_starter_kit.ucf' +#~new boards update + +#system workings +MINSOC_DIR=`pwd`/../.. +BACKEND_DIR=$MINSOC_DIR/backend +SYN_DIR=$MINSOC_DIR/syn +SYNSRC_DIR=$MINSOC_DIR/prj/xilinx +SYNSUPPORT_DIR=$SYN_DIR/buildSupport +MAKEFILE_DIR=$SYN_DIR/xilinx + +SYN_FILES=(ethmac.xst uart_top.xst adbg_top.xst or1200_top.xst minsoc_top.xst) +MAKEFILE=Makefile + +FIND_PART='DEVICE_PART' +FIND_CONSTRAINT='CONSTRAINT_FILE' + +BOARD_DIR=$BACKEND_DIR/$BOARD +BOARD_FILES=(board.h orp.ld minsoc_defines.v minsoc_bench_defines.v gcc-opt.mk $CONSTRAINT_FILE) + +in_minsoc=`pwd | grep minsoc/backend/${BOARD}$` +if [ -z $in_minsoc ] +then + echo "" + echo " !!!WARNING!!!" + echo "This script cannot be run if not in a board directory inside minsoc/backend," + echo "because it relies on the directory structure of the minsoc system." + echo "" + echo "Possibly your minsoc directory is named differently, minsoc_trunk for example." + echo "Its name must be minsoc only." + echo "" + exit 1 +fi + +#NON STANDARD SCRIPT PART +echo "THIS SCRIPT HAS A NON-STANDARD BEGINNING." +echo "__________________________________________________________________________" +echo "${BOARD} requires another configuration for or1200_rel1." + +echo "" +echo "Copying or1200_defines.v, to or1200 implementation directory..." +echo "(minsoc/rtl/verilog/or1200/rtl/verilog)" +echo "__________________________________________________________________________" +cp $BOARD_DIR/or1200_defines.v $MINSOC_DIR/rtl/verilog/or1200/rtl/verilog +echo "" +echo "REGULAR SCRIPT STARTS NOW" +echo "__________________________________________________________________________" +#~NON STANDARD SCRIPT PART + +echo "" +echo "This script sets up the SoC for simulations and synthesis." +echo "" +echo "In order to do so, SoC board's specific files for firmware compilation, " +echo "testbench generation and synthesis are configured." +echo "Firmware and testbench looks for board specific files under $BACKEND_DIR." +echo "Synthesis work under $SYN_DIR." +echo "" +echo "" + +echo "Copying board specific SoC files from $BOARD_DIR to $BACKEND_DIR directory." +echo "__________________________________________________________________________" +echo "" +for file in "${BOARD_FILES[@]}" +do + if [ $file != NONE ] + then + echo "Copying $file, to backend directory..." + cp $BOARD_DIR/$file $BACKEND_DIR + fi +done +echo "" +echo "" + +echo "Generating project files for simulation and synthesis..." +echo "__________________________________________________________________________" +echo "" +make -C $MINSOC_DIR/prj +echo "Generation complete." +echo "" +echo "" + +if [ $CONSTRAINT_FILE == 'NONE' ] +then + echo "Skipping synthesis preparation. Standard implementation can only be simulated." + echo "" + echo "" +else + echo "Device part for files under $SYNSRC_DIR will be patched and stored " + echo "temporarily." + echo "Afterwards, they are copied to $SYNSUPPORT_DIR." + echo "__________________________________________________________________________" + echo "" + for file in "${SYN_FILES[@]}" + do + echo "Updating synthesis file, $file..." + echo "Copying $file to synthesis directory..." + echo "" + sed "s/$FIND_PART/$DEVICE_PART/g" $SYNSRC_DIR/$file > TMPFILE + sed "s/$FIND_CONSTRAINT/$CONSTRAINT_FILE/g" TMPFILE > TMPFILE2 && mv TMPFILE2 $SYNSUPPORT_DIR/$file + rm TMPFILE + done + + echo "Updating Makefile file under $MAKEFILE_DIR..." + echo "Copying Makefile to synthesis directory, $SYN_DIR..." + echo "" + sed "s/$FIND_PART/$DEVICE_PART/g" $MAKEFILE_DIR/$MAKEFILE > TMPFILE + sed "s/$FIND_CONSTRAINT/$CONSTRAINT_FILE/g" TMPFILE > TMPFILE2 && mv TMPFILE2 $SYN_DIR/$MAKEFILE + rm TMPFILE + cp $MAKEFILE_DIR/setup.bat $SYN_DIR/setup.bat + echo "" + echo "" +fi + +#Precompiling firmwares +echo "Precompiling delivered libraries and firmwares..." +make -C ../../sw/utils +make -C ../../sw/support +make -C ../../sw/drivers +make -C ../../sw/uart +make -C ../../sw/eth +echo "done." +echo "" +echo "" + +echo "Configuration done."
release-1.0/backend/spartan3e_starter_kit/configure Property changes : Added: svn:executable ## -0,0 +1 ## +* \ No newline at end of property Index: release-1.0/backend/spartan3e_starter_kit/or1200_defines.v =================================================================== --- release-1.0/backend/spartan3e_starter_kit/or1200_defines.v (nonexistent) +++ release-1.0/backend/spartan3e_starter_kit/or1200_defines.v (revision 151) @@ -0,0 +1,1754 @@ +////////////////////////////////////////////////////////////////////// +//// //// +//// OR1200's definitions //// +//// //// +//// This file is part of the OpenRISC 1200 project //// +//// http://www.opencores.org/cores/or1k/ //// +//// //// +//// Description //// +//// Parameters of the OR1200 core //// +//// //// +//// To Do: //// +//// - add parameters that are missing //// +//// //// +//// Author(s): //// +//// - Damjan Lampret, lampret@opencores.org //// +//// //// +////////////////////////////////////////////////////////////////////// +//// //// +//// Copyright (C) 2000 Authors and OPENCORES.ORG //// +//// //// +//// This source file may be used and distributed without //// +//// restriction provided that this copyright statement is not //// +//// removed from the file and that any derivative work contains //// +//// the original copyright notice and the associated disclaimer. //// +//// //// +//// This source file is free software; you can redistribute it //// +//// and/or modify it under the terms of the GNU Lesser General //// +//// Public License as published by the Free Software Foundation; //// +//// either version 2.1 of the License, or (at your option) any //// +//// later version. //// +//// //// +//// This source is distributed in the hope that it will be //// +//// useful, but WITHOUT ANY WARRANTY; without even the implied //// +//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR //// +//// PURPOSE. See the GNU Lesser General Public License for more //// +//// details. //// +//// //// +//// You should have received a copy of the GNU Lesser General //// +//// Public License along with this source; if not, download it //// +//// from http://www.opencores.org/lgpl.shtml //// +//// //// +////////////////////////////////////////////////////////////////////// +// +// CVS Revision History +// +// $Log: not supported by cvs2svn $ +// Revision 1.44 2005/10/19 11:37:56 jcastillo +// Added support for RAMB16 Xilinx4/Spartan3 primitives +// +// Revision 1.43 2005/01/07 09:23:39 andreje +// l.ff1 and l.cmov instructions added +// +// Revision 1.42 2004/06/08 18:17:36 lampret +// Non-functional changes. Coding style fixes. +// +// Revision 1.41 2004/05/09 20:03:20 lampret +// By default l.cust5 insns are disabled +// +// Revision 1.40 2004/05/09 19:49:04 lampret +// Added some l.cust5 custom instructions as example +// +// Revision 1.39 2004/04/08 11:00:46 simont +// Add support for 512B instruction cache. +// +// Revision 1.38 2004/04/05 08:29:57 lampret +// Merged branch_qmem into main tree. +// +// Revision 1.35.4.6 2004/02/11 01:40:11 lampret +// preliminary HW breakpoints support in debug unit (by default disabled). To enable define OR1200_DU_HWBKPTS. +// +// Revision 1.35.4.5 2004/01/15 06:46:38 markom +// interface to debug changed; no more opselect; stb-ack protocol +// +// Revision 1.35.4.4 2004/01/11 22:45:46 andreje +// Separate instruction and data QMEM decoders, QMEM acknowledge and byte-select added +// +// Revision 1.35.4.3 2003/12/17 13:43:38 simons +// Exception prefix configuration changed. +// +// Revision 1.35.4.2 2003/12/05 00:05:03 lampret +// Static exception prefix. +// +// Revision 1.35.4.1 2003/07/08 15:36:37 lampret +// Added embedded memory QMEM. +// +// Revision 1.35 2003/04/24 00:16:07 lampret +// No functional changes. Added defines to disable implementation of multiplier/MAC +// +// Revision 1.34 2003/04/20 22:23:57 lampret +// No functional change. Only added customization for exception vectors. +// +// Revision 1.33 2003/04/07 20:56:07 lampret +// Fixed OR1200_CLKDIV_x_SUPPORTED defines. Better description. +// +// Revision 1.32 2003/04/07 01:26:57 lampret +// RFRAM defines comments updated. Altera LPM option added. +// +// Revision 1.31 2002/12/08 08:57:56 lampret +// Added optional support for WB B3 specification (xwb_cti_o, xwb_bte_o). Made xwb_cab_o optional. +// +// Revision 1.30 2002/10/28 15:09:22 mohor +// Previous check-in was done by mistake. +// +// Revision 1.29 2002/10/28 15:03:50 mohor +// Signal scanb_sen renamed to scanb_en. +// +// Revision 1.28 2002/10/17 20:04:40 lampret +// Added BIST scan. Special VS RAMs need to be used to implement BIST. +// +// Revision 1.27 2002/09/16 03:13:23 lampret +// Removed obsolete comment. +// +// Revision 1.26 2002/09/08 05:52:16 lampret +// Added optional l.div/l.divu insns. By default they are disabled. +// +// Revision 1.25 2002/09/07 19:16:10 lampret +// If SR[CY] implemented with OR1200_IMPL_ADDC enabled, l.add/l.addi also set SR[CY]. +// +// Revision 1.24 2002/09/07 05:42:02 lampret +// Added optional SR[CY]. Added define to enable additional (compare) flag modifiers. Defines are OR1200_IMPL_ADDC and OR1200_ADDITIONAL_FLAG_MODIFIERS. +// +// Revision 1.23 2002/09/04 00:50:34 lampret +// Now most of the configuration registers are updatded automatically based on defines in or1200_defines.v. +// +// Revision 1.22 2002/09/03 22:28:21 lampret +// As per Taylor Su suggestion all case blocks are full case by default and optionally (OR1200_CASE_DEFAULT) can be disabled to increase clock frequncy. +// +// Revision 1.21 2002/08/22 02:18:55 lampret +// Store buffer has been tested and it works. BY default it is still disabled until uClinux confirms correct operation on FPGA board. +// +// Revision 1.20 2002/08/18 21:59:45 lampret +// Disable SB until it is tested +// +// Revision 1.19 2002/08/18 19:53:08 lampret +// Added store buffer. +// +// Revision 1.18 2002/08/15 06:04:11 lampret +// Fixed Xilinx trace buffer address. REported by Taylor Su. +// +// Revision 1.17 2002/08/12 05:31:44 lampret +// Added OR1200_WB_RETRY. Moved WB registered outsputs / samples inputs into lower section. +// +// Revision 1.16 2002/07/14 22:17:17 lampret +// Added simple trace buffer [only for Xilinx Virtex target]. Fixed instruction fetch abort when new exception is recognized. +// +// Revision 1.15 2002/06/08 16:20:21 lampret +// Added defines for enabling generic FF based memory macro for register file. +// +// Revision 1.14 2002/03/29 16:24:06 lampret +// Changed comment about synopsys to _synopsys_ because synthesis was complaining about unknown directives +// +// Revision 1.13 2002/03/29 15:16:55 lampret +// Some of the warnings fixed. +// +// Revision 1.12 2002/03/28 19:25:42 lampret +// Added second type of Virtual Silicon two-port SRAM (for register file). Changed defines for VS STP RAMs. +// +// Revision 1.11 2002/03/28 19:13:17 lampret +// Updated defines. +// +// Revision 1.10 2002/03/14 00:30:24 lampret +// Added alternative for critical path in DU. +// +// Revision 1.9 2002/03/11 01:26:26 lampret +// Fixed async loop. Changed multiplier type for ASIC. +// +// Revision 1.8 2002/02/11 04:33:17 lampret +// Speed optimizations (removed duplicate _cyc_ and _stb_). Fixed D/IMMU cache-inhibit attr. +// +// Revision 1.7 2002/02/01 19:56:54 lampret +// Fixed combinational loops. +// +// Revision 1.6 2002/01/19 14:10:22 lampret +// Fixed OR1200_XILINX_RAM32X1D. +// +// Revision 1.5 2002/01/18 07:56:00 lampret +// No more low/high priority interrupts (PICPR removed). Added tick timer exception. Added exception prefix (SR[EPH]). Fixed single-step bug whenreading NPC. +// +// Revision 1.4 2002/01/14 09:44:12 lampret +// Default ASIC configuration does not sample WB inputs. +// +// Revision 1.3 2002/01/08 00:51:08 lampret +// Fixed typo. OR1200_REGISTERED_OUTPUTS was not defined. Should be. +// +// Revision 1.2 2002/01/03 21:23:03 lampret +// Uncommented OR1200_REGISTERED_OUTPUTS for FPGA target. +// +// Revision 1.1 2002/01/03 08:16:15 lampret +// New prefixes for RTL files, prefixed module names. Updated cache controllers and MMUs. +// +// Revision 1.20 2001/12/04 05:02:36 lampret +// Added OR1200_GENERIC_MULTP2_32X32 and OR1200_ASIC_MULTP2_32X32 +// +// Revision 1.19 2001/11/27 19:46:57 lampret +// Now FPGA and ASIC target are separate. +// +// Revision 1.18 2001/11/23 21:42:31 simons +// Program counter divided to PPC and NPC. +// +// Revision 1.17 2001/11/23 08:38:51 lampret +// Changed DSR/DRR behavior and exception detection. +// +// Revision 1.16 2001/11/20 21:30:38 lampret +// Added OR1200_REGISTERED_INPUTS. +// +// Revision 1.15 2001/11/19 14:29:48 simons +// Cashes disabled. +// +// Revision 1.14 2001/11/13 10:02:21 lampret +// Added 'setpc'. Renamed some signals (except_flushpipe into flushpipe etc) +// +// Revision 1.13 2001/11/12 01:45:40 lampret +// Moved flag bit into SR. Changed RF enable from constant enable to dynamic enable for read ports. +// +// Revision 1.12 2001/11/10 03:43:57 lampret +// Fixed exceptions. +// +// Revision 1.11 2001/11/02 18:57:14 lampret +// Modified virtual silicon instantiations. +// +// Revision 1.10 2001/10/21 17:57:16 lampret +// Removed params from generic_XX.v. Added translate_off/on in sprs.v and id.v. Removed spr_addr from dc.v and ic.v. Fixed CR+LF. +// +// Revision 1.9 2001/10/19 23:28:46 lampret +// Fixed some synthesis warnings. Configured with caches and MMUs. +// +// Revision 1.8 2001/10/14 13:12:09 lampret +// MP3 version. +// +// Revision 1.1.1.1 2001/10/06 10:18:36 igorm +// no message +// +// Revision 1.3 2001/08/17 08:01:19 lampret +// IC enable/disable. +// +// Revision 1.2 2001/08/13 03:36:20 lampret +// Added cfg regs. Moved all defines into one defines.v file. More cleanup. +// +// Revision 1.1 2001/08/09 13:39:33 lampret +// Major clean-up. +// +// Revision 1.2 2001/07/22 03:31:54 lampret +// Fixed RAM's oen bug. Cache bypass under development. +// +// Revision 1.1 2001/07/20 00:46:03 lampret +// Development version of RTL. Libraries are missing. +// +// + +// +// Dump VCD +// +//`define OR1200_VCD_DUMP + +// +// Generate debug messages during simulation +// +//`define OR1200_VERBOSE + +// `define OR1200_ASIC +//////////////////////////////////////////////////////// +// +// Typical configuration for an ASIC +// +`ifdef OR1200_ASIC + +// +// Target ASIC memories +// +//`define OR1200_ARTISAN_SSP +//`define OR1200_ARTISAN_SDP +//`define OR1200_ARTISAN_STP +`define OR1200_VIRTUALSILICON_SSP +//`define OR1200_VIRTUALSILICON_STP_T1 +//`define OR1200_VIRTUALSILICON_STP_T2 + +// +// Do not implement Data cache +// +//`define OR1200_NO_DC + +// +// Do not implement Insn cache +// +//`define OR1200_NO_IC + +// +// Do not implement Data MMU +// +//`define OR1200_NO_DMMU + +// +// Do not implement Insn MMU +// +//`define OR1200_NO_IMMU + +// +// Select between ASIC optimized and generic multiplier +// +//`define OR1200_ASIC_MULTP2_32X32 +`define OR1200_GENERIC_MULTP2_32X32 + +// +// Size/type of insn/data cache if implemented +// +// `define OR1200_IC_1W_512B +// `define OR1200_IC_1W_4KB +`define OR1200_IC_1W_8KB +// `define OR1200_DC_1W_4KB +`define OR1200_DC_1W_8KB + +`else + + +///////////////////////////////////////////////////////// +// +// Typical configuration for an FPGA +// + +// +// Target FPGA memories +// +//`define OR1200_ALTERA_LPM +`define OR1200_XILINX_RAMB16 +//`define OR1200_XILINX_RAMB4 +//`define OR1200_XILINX_RAM32X1D +//`define OR1200_USE_RAM16X1D_FOR_RAM32X1D + +// +// Do not implement Data cache +// +`define OR1200_NO_DC + +// +// Do not implement Insn cache +// +`define OR1200_NO_IC + +// +// Do not implement Data MMU +// +`define OR1200_NO_DMMU + +// +// Do not implement Insn MMU +// +`define OR1200_NO_IMMU + +// +// Select between ASIC and generic multiplier +// +// (Generic seems to trigger a bug in the Cadence Ncsim simulator) +// +//`define OR1200_ASIC_MULTP2_32X32 +`define OR1200_GENERIC_MULTP2_32X32 + +// +// Size/type of insn/data cache if implemented +// (consider available FPGA memory resources) +// +//`define OR1200_IC_1W_512B +`define OR1200_IC_1W_4KB +//`define OR1200_IC_1W_8KB +`define OR1200_DC_1W_4KB +//`define OR1200_DC_1W_8KB + +`endif + + +////////////////////////////////////////////////////////// +// +// Do not change below unless you know what you are doing +// + +// +// Enable RAM BIST +// +// At the moment this only works for Virtual Silicon +// single port RAMs. For other RAMs it has not effect. +// Special wrapper for VS RAMs needs to be provided +// with scan flops to facilitate bist scan. +// +//`define OR1200_BIST + +// +// Register OR1200 WISHBONE outputs +// (must be defined/enabled) +// +`define OR1200_REGISTERED_OUTPUTS + +// +// Register OR1200 WISHBONE inputs +// +// (must be undefined/disabled) +// +//`define OR1200_REGISTERED_INPUTS + +// +// Disable bursts if they are not supported by the +// memory subsystem (only affect cache line fill) +// +//`define OR1200_NO_BURSTS +// + +// +// WISHBONE retry counter range +// +// 2^value range for retry counter. Retry counter +// is activated whenever *wb_rty_i is asserted and +// until retry counter expires, corresponding +// WISHBONE interface is deactivated. +// +// To disable retry counters and *wb_rty_i all together, +// undefine this macro. +// +//`define OR1200_WB_RETRY 7 + +// +// WISHBONE Consecutive Address Burst +// +// This was used prior to WISHBONE B3 specification +// to identify bursts. It is no longer needed but +// remains enabled for compatibility with old designs. +// +// To remove *wb_cab_o ports undefine this macro. +// +`define OR1200_WB_CAB + +// +// WISHBONE B3 compatible interface +// +// This follows the WISHBONE B3 specification. +// It is not enabled by default because most +// designs still don't use WB b3. +// +// To enable *wb_cti_o/*wb_bte_o ports, +// define this macro. +// +//`define OR1200_WB_B3 + +// +// Enable additional synthesis directives if using +// _Synopsys_ synthesis tool +// +//`define OR1200_ADDITIONAL_SYNOPSYS_DIRECTIVES + +// +// Enables default statement in some case blocks +// and disables Synopsys synthesis directive full_case +// +// By default it is enabled. When disabled it +// can increase clock frequency. +// +`define OR1200_CASE_DEFAULT + +// +// Operand width / register file address width +// +// (DO NOT CHANGE) +// +`define OR1200_OPERAND_WIDTH 32 +`define OR1200_REGFILE_ADDR_WIDTH 5 + +// +// l.add/l.addi/l.and and optional l.addc/l.addic +// also set (compare) flag when result of their +// operation equals zero +// +// At the time of writing this, default or32 +// C/C++ compiler doesn't generate code that +// would benefit from this optimization. +// +// By default this optimization is disabled to +// save area. +// +//`define OR1200_ADDITIONAL_FLAG_MODIFIERS + +// +// Implement l.addc/l.addic instructions +// +// By default implementation of l.addc/l.addic +// instructions is enabled in case you need them. +// If you don't use them, then disable implementation +// to save area. +// +`define OR1200_IMPL_ADDC + +// +// Implement carry bit SR[CY] +// +// By default implementation of SR[CY] is enabled +// to be compliant with the simulator. However +// SR[CY] is explicitly only used by l.addc/l.addic +// instructions and if these two insns are not +// implemented there is not much point having SR[CY]. +// +`define OR1200_IMPL_CY + +// +// Implement optional l.div/l.divu instructions +// +// By default divide instructions are not implemented +// to save area and increase clock frequency. or32 C/C++ +// compiler can use soft library for division. +// +// To implement divide, multiplier needs to be implemented. +// +//`define OR1200_IMPL_DIV + +// +// Implement rotate in the ALU +// +// At the time of writing this, or32 +// C/C++ compiler doesn't generate rotate +// instructions. However or32 assembler +// can assemble code that uses rotate insn. +// This means that rotate instructions +// must be used manually inserted. +// +// By default implementation of rotate +// is disabled to save area and increase +// clock frequency. +// +//`define OR1200_IMPL_ALU_ROTATE + +// +// Type of ALU compare to implement +// +// Try either one to find what yields +// higher clock frequencyin your case. +// +//`define OR1200_IMPL_ALU_COMP1 +`define OR1200_IMPL_ALU_COMP2 + +// +// Implement multiplier +// +// By default multiplier is implemented +// +`define OR1200_MULT_IMPLEMENTED + +// +// Implement multiply-and-accumulate +// +// By default MAC is implemented. To +// implement MAC, multiplier needs to be +// implemented. +// +`define OR1200_MAC_IMPLEMENTED + +// +// Low power, slower multiplier +// +// Select between low-power (larger) multiplier +// and faster multiplier. The actual difference +// is only AND logic that prevents distribution +// of operands into the multiplier when instruction +// in execution is not multiply instruction +// +//`define OR1200_LOWPWR_MULT + +// +// Clock ratio RISC clock versus WB clock +// +// If you plan to run WB:RISC clock fixed to 1:1, disable +// both defines +// +// For WB:RISC 1:2 or 1:1, enable OR1200_CLKDIV_2_SUPPORTED +// and use clmode to set ratio +// +// For WB:RISC 1:4, 1:2 or 1:1, enable both defines and use +// clmode to set ratio +// +`define OR1200_CLKDIV_2_SUPPORTED +//`define OR1200_CLKDIV_4_SUPPORTED + +// +// Type of register file RAM +// +// Memory macro w/ two ports (see or1200_tpram_32x32.v) +//`define OR1200_RFRAM_TWOPORT +// +// Memory macro dual port (see or1200_dpram_32x32.v) +`define OR1200_RFRAM_DUALPORT +// +// Generic (flip-flop based) register file (see or1200_rfram_generic.v) +//`define OR1200_RFRAM_GENERIC + +// +// Type of mem2reg aligner to implement. +// +// Once OR1200_IMPL_MEM2REG2 yielded faster +// circuit, however with today tools it will +// most probably give you slower circuit. +// +`define OR1200_IMPL_MEM2REG1 +//`define OR1200_IMPL_MEM2REG2 + +// +// ALUOPs +// +`define OR1200_ALUOP_WIDTH 4 +`define OR1200_ALUOP_NOP 4'd4 +/* Order defined by arith insns that have two source operands both in regs + (see binutils/include/opcode/or32.h) */ +`define OR1200_ALUOP_ADD 4'd0 +`define OR1200_ALUOP_ADDC 4'd1 +`define OR1200_ALUOP_SUB 4'd2 +`define OR1200_ALUOP_AND 4'd3 +`define OR1200_ALUOP_OR 4'd4 +`define OR1200_ALUOP_XOR 4'd5 +`define OR1200_ALUOP_MUL 4'd6 +`define OR1200_ALUOP_CUST5 4'd7 +`define OR1200_ALUOP_SHROT 4'd8 +`define OR1200_ALUOP_DIV 4'd9 +`define OR1200_ALUOP_DIVU 4'd10 +/* Order not specifically defined. */ +`define OR1200_ALUOP_IMM 4'd11 +`define OR1200_ALUOP_MOVHI 4'd12 +`define OR1200_ALUOP_COMP 4'd13 +`define OR1200_ALUOP_MTSR 4'd14 +`define OR1200_ALUOP_MFSR 4'd15 +`define OR1200_ALUOP_CMOV 4'd14 +`define OR1200_ALUOP_FF1 4'd15 +// +// MACOPs +// +`define OR1200_MACOP_WIDTH 2 +`define OR1200_MACOP_NOP 2'b00 +`define OR1200_MACOP_MAC 2'b01 +`define OR1200_MACOP_MSB 2'b10 + +// +// Shift/rotate ops +// +`define OR1200_SHROTOP_WIDTH 2 +`define OR1200_SHROTOP_NOP 2'd0 +`define OR1200_SHROTOP_SLL 2'd0 +`define OR1200_SHROTOP_SRL 2'd1 +`define OR1200_SHROTOP_SRA 2'd2 +`define OR1200_SHROTOP_ROR 2'd3 + +// Execution cycles per instruction +`define OR1200_MULTICYCLE_WIDTH 2 +`define OR1200_ONE_CYCLE 2'd0 +`define OR1200_TWO_CYCLES 2'd1 + +// Operand MUX selects +`define OR1200_SEL_WIDTH 2 +`define OR1200_SEL_RF 2'd0 +`define OR1200_SEL_IMM 2'd1 +`define OR1200_SEL_EX_FORW 2'd2 +`define OR1200_SEL_WB_FORW 2'd3 + +// +// BRANCHOPs +// +`define OR1200_BRANCHOP_WIDTH 3 +`define OR1200_BRANCHOP_NOP 3'd0 +`define OR1200_BRANCHOP_J 3'd1 +`define OR1200_BRANCHOP_JR 3'd2 +`define OR1200_BRANCHOP_BAL 3'd3 +`define OR1200_BRANCHOP_BF 3'd4 +`define OR1200_BRANCHOP_BNF 3'd5 +`define OR1200_BRANCHOP_RFE 3'd6 + +// +// LSUOPs +// +// Bit 0: sign extend +// Bits 1-2: 00 doubleword, 01 byte, 10 halfword, 11 singleword +// Bit 3: 0 load, 1 store +`define OR1200_LSUOP_WIDTH 4 +`define OR1200_LSUOP_NOP 4'b0000 +`define OR1200_LSUOP_LBZ 4'b0010 +`define OR1200_LSUOP_LBS 4'b0011 +`define OR1200_LSUOP_LHZ 4'b0100 +`define OR1200_LSUOP_LHS 4'b0101 +`define OR1200_LSUOP_LWZ 4'b0110 +`define OR1200_LSUOP_LWS 4'b0111 +`define OR1200_LSUOP_LD 4'b0001 +`define OR1200_LSUOP_SD 4'b1000 +`define OR1200_LSUOP_SB 4'b1010 +`define OR1200_LSUOP_SH 4'b1100 +`define OR1200_LSUOP_SW 4'b1110 + +// FETCHOPs +`define OR1200_FETCHOP_WIDTH 1 +`define OR1200_FETCHOP_NOP 1'b0 +`define OR1200_FETCHOP_LW 1'b1 + +// +// Register File Write-Back OPs +// +// Bit 0: register file write enable +// Bits 2-1: write-back mux selects +`define OR1200_RFWBOP_WIDTH 3 +`define OR1200_RFWBOP_NOP 3'b000 +`define OR1200_RFWBOP_ALU 3'b001 +`define OR1200_RFWBOP_LSU 3'b011 +`define OR1200_RFWBOP_SPRS 3'b101 +`define OR1200_RFWBOP_LR 3'b111 + +// Compare instructions +`define OR1200_COP_SFEQ 3'b000 +`define OR1200_COP_SFNE 3'b001 +`define OR1200_COP_SFGT 3'b010 +`define OR1200_COP_SFGE 3'b011 +`define OR1200_COP_SFLT 3'b100 +`define OR1200_COP_SFLE 3'b101 +`define OR1200_COP_X 3'b111 +`define OR1200_SIGNED_COMPARE 'd3 +`define OR1200_COMPOP_WIDTH 4 + +// +// TAGs for instruction bus +// +`define OR1200_ITAG_IDLE 4'h0 // idle bus +`define OR1200_ITAG_NI 4'h1 // normal insn +`define OR1200_ITAG_BE 4'hb // Bus error exception +`define OR1200_ITAG_PE 4'hc // Page fault exception +`define OR1200_ITAG_TE 4'hd // TLB miss exception + +// +// TAGs for data bus +// +`define OR1200_DTAG_IDLE 4'h0 // idle bus +`define OR1200_DTAG_ND 4'h1 // normal data +`define OR1200_DTAG_AE 4'ha // Alignment exception +`define OR1200_DTAG_BE 4'hb // Bus error exception +`define OR1200_DTAG_PE 4'hc // Page fault exception +`define OR1200_DTAG_TE 4'hd // TLB miss exception + + +////////////////////////////////////////////// +// +// ORBIS32 ISA specifics +// + +// SHROT_OP position in machine word +`define OR1200_SHROTOP_POS 7:6 + +// ALU instructions multicycle field in machine word +`define OR1200_ALUMCYC_POS 9:8 + +// +// Instruction opcode groups (basic) +// +`define OR1200_OR32_J 6'b000000 +`define OR1200_OR32_JAL 6'b000001 +`define OR1200_OR32_BNF 6'b000011 +`define OR1200_OR32_BF 6'b000100 +`define OR1200_OR32_NOP 6'b000101 +`define OR1200_OR32_MOVHI 6'b000110 +`define OR1200_OR32_XSYNC 6'b001000 +`define OR1200_OR32_RFE 6'b001001 +/* */ +`define OR1200_OR32_JR 6'b010001 +`define OR1200_OR32_JALR 6'b010010 +`define OR1200_OR32_MACI 6'b010011 +/* */ +`define OR1200_OR32_LWZ 6'b100001 +`define OR1200_OR32_LBZ 6'b100011 +`define OR1200_OR32_LBS 6'b100100 +`define OR1200_OR32_LHZ 6'b100101 +`define OR1200_OR32_LHS 6'b100110 +`define OR1200_OR32_ADDI 6'b100111 +`define OR1200_OR32_ADDIC 6'b101000 +`define OR1200_OR32_ANDI 6'b101001 +`define OR1200_OR32_ORI 6'b101010 +`define OR1200_OR32_XORI 6'b101011 +`define OR1200_OR32_MULI 6'b101100 +`define OR1200_OR32_MFSPR 6'b101101 +`define OR1200_OR32_SH_ROTI 6'b101110 +`define OR1200_OR32_SFXXI 6'b101111 +/* */ +`define OR1200_OR32_MTSPR 6'b110000 +`define OR1200_OR32_MACMSB 6'b110001 +/* */ +`define OR1200_OR32_SW 6'b110101 +`define OR1200_OR32_SB 6'b110110 +`define OR1200_OR32_SH 6'b110111 +`define OR1200_OR32_ALU 6'b111000 +`define OR1200_OR32_SFXX 6'b111001 +//`define OR1200_OR32_CUST5 6'b111100 + + +///////////////////////////////////////////////////// +// +// Exceptions +// + +// +// Exception vectors per OR1K architecture: +// 0xPPPPP100 - reset +// 0xPPPPP200 - bus error +// ... etc +// where P represents exception prefix. +// +// Exception vectors can be customized as per +// the following formula: +// 0xPPPPPNVV - exception N +// +// P represents exception prefix +// N represents exception N +// VV represents length of the individual vector space, +// usually it is 8 bits wide and starts with all bits zero +// + +// +// PPPPP and VV parts +// +// Sum of these two defines needs to be 28 +// +`define OR1200_EXCEPT_EPH0_P 20'h00000 +`define OR1200_EXCEPT_EPH1_P 20'hF0000 +`define OR1200_EXCEPT_V 8'h00 + +// +// N part width +// +`define OR1200_EXCEPT_WIDTH 4 + +// +// Definition of exception vectors +// +// To avoid implementation of a certain exception, +// simply comment out corresponding line +// +`define OR1200_EXCEPT_UNUSED `OR1200_EXCEPT_WIDTH'hf +`define OR1200_EXCEPT_TRAP `OR1200_EXCEPT_WIDTH'he +`define OR1200_EXCEPT_BREAK `OR1200_EXCEPT_WIDTH'hd +`define OR1200_EXCEPT_SYSCALL `OR1200_EXCEPT_WIDTH'hc +`define OR1200_EXCEPT_RANGE `OR1200_EXCEPT_WIDTH'hb +`define OR1200_EXCEPT_ITLBMISS `OR1200_EXCEPT_WIDTH'ha +`define OR1200_EXCEPT_DTLBMISS `OR1200_EXCEPT_WIDTH'h9 +`define OR1200_EXCEPT_INT `OR1200_EXCEPT_WIDTH'h8 +`define OR1200_EXCEPT_ILLEGAL `OR1200_EXCEPT_WIDTH'h7 +`define OR1200_EXCEPT_ALIGN `OR1200_EXCEPT_WIDTH'h6 +`define OR1200_EXCEPT_TICK `OR1200_EXCEPT_WIDTH'h5 +`define OR1200_EXCEPT_IPF `OR1200_EXCEPT_WIDTH'h4 +`define OR1200_EXCEPT_DPF `OR1200_EXCEPT_WIDTH'h3 +`define OR1200_EXCEPT_BUSERR `OR1200_EXCEPT_WIDTH'h2 +`define OR1200_EXCEPT_RESET `OR1200_EXCEPT_WIDTH'h1 +`define OR1200_EXCEPT_NONE `OR1200_EXCEPT_WIDTH'h0 + + +///////////////////////////////////////////////////// +// +// SPR groups +// + +// Bits that define the group +`define OR1200_SPR_GROUP_BITS 15:11 + +// Width of the group bits +`define OR1200_SPR_GROUP_WIDTH 5 + +// Bits that define offset inside the group +`define OR1200_SPR_OFS_BITS 10:0 + +// List of groups +`define OR1200_SPR_GROUP_SYS 5'd00 +`define OR1200_SPR_GROUP_DMMU 5'd01 +`define OR1200_SPR_GROUP_IMMU 5'd02 +`define OR1200_SPR_GROUP_DC 5'd03 +`define OR1200_SPR_GROUP_IC 5'd04 +`define OR1200_SPR_GROUP_MAC 5'd05 +`define OR1200_SPR_GROUP_DU 5'd06 +`define OR1200_SPR_GROUP_PM 5'd08 +`define OR1200_SPR_GROUP_PIC 5'd09 +`define OR1200_SPR_GROUP_TT 5'd10 + + +///////////////////////////////////////////////////// +// +// System group +// + +// +// System registers +// +`define OR1200_SPR_CFGR 7'd0 +`define OR1200_SPR_RF 6'd32 // 1024 >> 5 +`define OR1200_SPR_NPC 11'd16 +`define OR1200_SPR_SR 11'd17 +`define OR1200_SPR_PPC 11'd18 +`define OR1200_SPR_EPCR 11'd32 +`define OR1200_SPR_EEAR 11'd48 +`define OR1200_SPR_ESR 11'd64 + +// +// SR bits +// +`define OR1200_SR_WIDTH 16 +`define OR1200_SR_SM 0 +`define OR1200_SR_TEE 1 +`define OR1200_SR_IEE 2 +`define OR1200_SR_DCE 3 +`define OR1200_SR_ICE 4 +`define OR1200_SR_DME 5 +`define OR1200_SR_IME 6 +`define OR1200_SR_LEE 7 +`define OR1200_SR_CE 8 +`define OR1200_SR_F 9 +`define OR1200_SR_CY 10 // Unused +`define OR1200_SR_OV 11 // Unused +`define OR1200_SR_OVE 12 // Unused +`define OR1200_SR_DSX 13 // Unused +`define OR1200_SR_EPH 14 +`define OR1200_SR_FO 15 +`define OR1200_SR_CID 31:28 // Unimplemented + +// +// Bits that define offset inside the group +// +`define OR1200_SPROFS_BITS 10:0 + +// +// Default Exception Prefix +// +// 1'b0 - OR1200_EXCEPT_EPH0_P (0x0000_0000) +// 1'b1 - OR1200_EXCEPT_EPH1_P (0xF000_0000) +// +`define OR1200_SR_EPH_DEF 1'b0 + +///////////////////////////////////////////////////// +// +// Power Management (PM) +// + +// Define it if you want PM implemented +//`define OR1200_PM_IMPLEMENTED + +// Bit positions inside PMR (don't change) +`define OR1200_PM_PMR_SDF 3:0 +`define OR1200_PM_PMR_DME 4 +`define OR1200_PM_PMR_SME 5 +`define OR1200_PM_PMR_DCGE 6 +`define OR1200_PM_PMR_UNUSED 31:7 + +// PMR offset inside PM group of registers +`define OR1200_PM_OFS_PMR 11'b0 + +// PM group +`define OR1200_SPRGRP_PM 5'd8 + +// Define if PMR can be read/written at any address inside PM group +`define OR1200_PM_PARTIAL_DECODING + +// Define if reading PMR is allowed +`define OR1200_PM_READREGS + +// Define if unused PMR bits should be zero +`define OR1200_PM_UNUSED_ZERO + + +///////////////////////////////////////////////////// +// +// Debug Unit (DU) +// + +// Define it if you want DU implemented +`define OR1200_DU_IMPLEMENTED + +// +// Define if you want HW Breakpoints +// (if HW breakpoints are not implemented +// only default software trapping is +// possible with l.trap insn - this is +// however already enough for use +// with or32 gdb) +// +`define OR1200_DU_HWBKPTS + +// Number of DVR/DCR pairs if HW breakpoints enabled +`define OR1200_DU_DVRDCR_PAIRS 8 + +// Define if you want trace buffer +//`define OR1200_DU_TB_IMPLEMENTED + +// +// Address offsets of DU registers inside DU group +// +// To not implement a register, doq not define its address +// +`ifdef OR1200_DU_HWBKPTS +`define OR1200_DU_DVR0 11'd0 +`define OR1200_DU_DVR1 11'd1 +`define OR1200_DU_DVR2 11'd2 +`define OR1200_DU_DVR3 11'd3 +`define OR1200_DU_DVR4 11'd4 +`define OR1200_DU_DVR5 11'd5 +`define OR1200_DU_DVR6 11'd6 +`define OR1200_DU_DVR7 11'd7 +`define OR1200_DU_DCR0 11'd8 +`define OR1200_DU_DCR1 11'd9 +`define OR1200_DU_DCR2 11'd10 +`define OR1200_DU_DCR3 11'd11 +`define OR1200_DU_DCR4 11'd12 +`define OR1200_DU_DCR5 11'd13 +`define OR1200_DU_DCR6 11'd14 +`define OR1200_DU_DCR7 11'd15 +`endif +`define OR1200_DU_DMR1 11'd16 +`ifdef OR1200_DU_HWBKPTS +`define OR1200_DU_DMR2 11'd17 +`define OR1200_DU_DWCR0 11'd18 +`define OR1200_DU_DWCR1 11'd19 +`endif +`define OR1200_DU_DSR 11'd20 +`define OR1200_DU_DRR 11'd21 +`ifdef OR1200_DU_TB_IMPLEMENTED +`define OR1200_DU_TBADR 11'h0ff +`define OR1200_DU_TBIA 11'h1xx +`define OR1200_DU_TBIM 11'h2xx +`define OR1200_DU_TBAR 11'h3xx +`define OR1200_DU_TBTS 11'h4xx +`endif + +// Position of offset bits inside SPR address +`define OR1200_DUOFS_BITS 10:0 + +// DCR bits +`define OR1200_DU_DCR_DP 0 +`define OR1200_DU_DCR_CC 3:1 +`define OR1200_DU_DCR_SC 4 +`define OR1200_DU_DCR_CT 7:5 + +// DMR1 bits +`define OR1200_DU_DMR1_CW0 1:0 +`define OR1200_DU_DMR1_CW1 3:2 +`define OR1200_DU_DMR1_CW2 5:4 +`define OR1200_DU_DMR1_CW3 7:6 +`define OR1200_DU_DMR1_CW4 9:8 +`define OR1200_DU_DMR1_CW5 11:10 +`define OR1200_DU_DMR1_CW6 13:12 +`define OR1200_DU_DMR1_CW7 15:14 +`define OR1200_DU_DMR1_CW8 17:16 +`define OR1200_DU_DMR1_CW9 19:18 +`define OR1200_DU_DMR1_RES 21:20 +`define OR1200_DU_DMR1_ST 22 +`define OR1200_DU_DMR1_BT 23 + +// DMR2 bits +`define OR1200_DU_DMR2_WCE0 0 +`define OR1200_DU_DMR2_WCE1 1 +`define OR1200_DU_DMR2_AWTC 11:2 +`define OR1200_DU_DMR2_WGB 21:12 + +// DWCR bits +`define OR1200_DU_DWCR_COUNT 15:0 +`define OR1200_DU_DWCR_MATCH 31:16 + +// DSR bits +`define OR1200_DU_DSR_WIDTH 14 +`define OR1200_DU_DSR_RSTE 0 +`define OR1200_DU_DSR_BUSEE 1 +`define OR1200_DU_DSR_DPFE 2 +`define OR1200_DU_DSR_IPFE 3 +`define OR1200_DU_DSR_TTE 4 +`define OR1200_DU_DSR_AE 5 +`define OR1200_DU_DSR_IIE 6 +`define OR1200_DU_DSR_IE 7 +`define OR1200_DU_DSR_DME 8 +`define OR1200_DU_DSR_IME 9 +`define OR1200_DU_DSR_RE 10 +`define OR1200_DU_DSR_SCE 11 +`define OR1200_DU_DSR_BE 12 +`define OR1200_DU_DSR_TE 13 + +// DRR bits +`define OR1200_DU_DRR_RSTE 0 +`define OR1200_DU_DRR_BUSEE 1 +`define OR1200_DU_DRR_DPFE 2 +`define OR1200_DU_DRR_IPFE 3 +`define OR1200_DU_DRR_TTE 4 +`define OR1200_DU_DRR_AE 5 +`define OR1200_DU_DRR_IIE 6 +`define OR1200_DU_DRR_IE 7 +`define OR1200_DU_DRR_DME 8 +`define OR1200_DU_DRR_IME 9 +`define OR1200_DU_DRR_RE 10 +`define OR1200_DU_DRR_SCE 11 +`define OR1200_DU_DRR_BE 12 +`define OR1200_DU_DRR_TE 13 + +// Define if reading DU regs is allowed +`define OR1200_DU_READREGS + +// Define if unused DU registers bits should be zero +`define OR1200_DU_UNUSED_ZERO + +// Define if IF/LSU status is not needed by devel i/f +`define OR1200_DU_STATUS_UNIMPLEMENTED + +///////////////////////////////////////////////////// +// +// Programmable Interrupt Controller (PIC) +// + +// Define it if you want PIC implemented +`define OR1200_PIC_IMPLEMENTED + +// Define number of interrupt inputs (2-31) +`define OR1200_PIC_INTS 20 + +// Address offsets of PIC registers inside PIC group +`define OR1200_PIC_OFS_PICMR 2'd0 +`define OR1200_PIC_OFS_PICSR 2'd2 + +// Position of offset bits inside SPR address +`define OR1200_PICOFS_BITS 1:0 + +// Define if you want these PIC registers to be implemented +`define OR1200_PIC_PICMR +`define OR1200_PIC_PICSR + +// Define if reading PIC registers is allowed +`define OR1200_PIC_READREGS + +// Define if unused PIC register bits should be zero +`define OR1200_PIC_UNUSED_ZERO + + +///////////////////////////////////////////////////// +// +// Tick Timer (TT) +// + +// Define it if you want TT implemented +`define OR1200_TT_IMPLEMENTED + +// Address offsets of TT registers inside TT group +`define OR1200_TT_OFS_TTMR 1'd0 +`define OR1200_TT_OFS_TTCR 1'd1 + +// Position of offset bits inside SPR group +`define OR1200_TTOFS_BITS 0 + +// Define if you want these TT registers to be implemented +`define OR1200_TT_TTMR +`define OR1200_TT_TTCR + +// TTMR bits +`define OR1200_TT_TTMR_TP 27:0 +`define OR1200_TT_TTMR_IP 28 +`define OR1200_TT_TTMR_IE 29 +`define OR1200_TT_TTMR_M 31:30 + +// Define if reading TT registers is allowed +`define OR1200_TT_READREGS + + +////////////////////////////////////////////// +// +// MAC +// +`define OR1200_MAC_ADDR 0 // MACLO 0xxxxxxxx1, MACHI 0xxxxxxxx0 +`define OR1200_MAC_SPR_WE // Define if MACLO/MACHI are SPR writable + +// +// Shift {MACHI,MACLO} into destination register when executing l.macrc +// +// According to architecture manual there is no shift, so default value is 0. +// +// However the implementation has deviated in this from the arch manual and had hard coded shift by 28 bits which +// is a useful optimization for MP3 decoding (if using libmad fixed point library). Shifts are no longer +// default setup, but if you need to remain backward compatible, define your shift bits, which were normally +// dest_GPR = {MACHI,MACLO}[59:28] +`define OR1200_MAC_SHIFTBY 0 // 0 = According to arch manual, 28 = obsolete backward compatibility + + +////////////////////////////////////////////// +// +// Data MMU (DMMU) +// + +// +// Address that selects between TLB TR and MR +// +`define OR1200_DTLB_TM_ADDR 7 + +// +// DTLBMR fields +// +`define OR1200_DTLBMR_V_BITS 0 +`define OR1200_DTLBMR_CID_BITS 4:1 +`define OR1200_DTLBMR_RES_BITS 11:5 +`define OR1200_DTLBMR_VPN_BITS 31:13 + +// +// DTLBTR fields +// +`define OR1200_DTLBTR_CC_BITS 0 +`define OR1200_DTLBTR_CI_BITS 1 +`define OR1200_DTLBTR_WBC_BITS 2 +`define OR1200_DTLBTR_WOM_BITS 3 +`define OR1200_DTLBTR_A_BITS 4 +`define OR1200_DTLBTR_D_BITS 5 +`define OR1200_DTLBTR_URE_BITS 6 +`define OR1200_DTLBTR_UWE_BITS 7 +`define OR1200_DTLBTR_SRE_BITS 8 +`define OR1200_DTLBTR_SWE_BITS 9 +`define OR1200_DTLBTR_RES_BITS 11:10 +`define OR1200_DTLBTR_PPN_BITS 31:13 + +// +// DTLB configuration +// +`define OR1200_DMMU_PS 13 // 13 for 8KB page size +`define OR1200_DTLB_INDXW 6 // 6 for 64 entry DTLB 7 for 128 entries +`define OR1200_DTLB_INDXL `OR1200_DMMU_PS // 13 13 +`define OR1200_DTLB_INDXH `OR1200_DMMU_PS+`OR1200_DTLB_INDXW-1 // 18 19 +`define OR1200_DTLB_INDX `OR1200_DTLB_INDXH:`OR1200_DTLB_INDXL // 18:13 19:13 +`define OR1200_DTLB_TAGW 32-`OR1200_DTLB_INDXW-`OR1200_DMMU_PS // 13 12 +`define OR1200_DTLB_TAGL `OR1200_DTLB_INDXH+1 // 19 20 +`define OR1200_DTLB_TAG 31:`OR1200_DTLB_TAGL // 31:19 31:20 +`define OR1200_DTLBMRW `OR1200_DTLB_TAGW+1 // +1 because of V bit +`define OR1200_DTLBTRW 32-`OR1200_DMMU_PS+5 // +5 because of protection bits and CI + +// +// Cache inhibit while DMMU is not enabled/implemented +// +// cache inhibited 0GB-4GB 1'b1 +// cache inhibited 0GB-2GB !dcpu_adr_i[31] +// cache inhibited 0GB-1GB 2GB-3GB !dcpu_adr_i[30] +// cache inhibited 1GB-2GB 3GB-4GB dcpu_adr_i[30] +// cache inhibited 2GB-4GB (default) dcpu_adr_i[31] +// cached 0GB-4GB 1'b0 +// +`define OR1200_DMMU_CI dcpu_adr_i[31] + + +////////////////////////////////////////////// +// +// Insn MMU (IMMU) +// + +// +// Address that selects between TLB TR and MR +// +`define OR1200_ITLB_TM_ADDR 7 + +// +// ITLBMR fields +// +`define OR1200_ITLBMR_V_BITS 0 +`define OR1200_ITLBMR_CID_BITS 4:1 +`define OR1200_ITLBMR_RES_BITS 11:5 +`define OR1200_ITLBMR_VPN_BITS 31:13 + +// +// ITLBTR fields +// +`define OR1200_ITLBTR_CC_BITS 0 +`define OR1200_ITLBTR_CI_BITS 1 +`define OR1200_ITLBTR_WBC_BITS 2 +`define OR1200_ITLBTR_WOM_BITS 3 +`define OR1200_ITLBTR_A_BITS 4 +`define OR1200_ITLBTR_D_BITS 5 +`define OR1200_ITLBTR_SXE_BITS 6 +`define OR1200_ITLBTR_UXE_BITS 7 +`define OR1200_ITLBTR_RES_BITS 11:8 +`define OR1200_ITLBTR_PPN_BITS 31:13 + +// +// ITLB configuration +// +`define OR1200_IMMU_PS 13 // 13 for 8KB page size +`define OR1200_ITLB_INDXW 6 // 6 for 64 entry ITLB 7 for 128 entries +`define OR1200_ITLB_INDXL `OR1200_IMMU_PS // 13 13 +`define OR1200_ITLB_INDXH `OR1200_IMMU_PS+`OR1200_ITLB_INDXW-1 // 18 19 +`define OR1200_ITLB_INDX `OR1200_ITLB_INDXH:`OR1200_ITLB_INDXL // 18:13 19:13 +`define OR1200_ITLB_TAGW 32-`OR1200_ITLB_INDXW-`OR1200_IMMU_PS // 13 12 +`define OR1200_ITLB_TAGL `OR1200_ITLB_INDXH+1 // 19 20 +`define OR1200_ITLB_TAG 31:`OR1200_ITLB_TAGL // 31:19 31:20 +`define OR1200_ITLBMRW `OR1200_ITLB_TAGW+1 // +1 because of V bit +`define OR1200_ITLBTRW 32-`OR1200_IMMU_PS+3 // +3 because of protection bits and CI + +// +// Cache inhibit while IMMU is not enabled/implemented +// Note: all combinations that use icpu_adr_i cause async loop +// +// cache inhibited 0GB-4GB 1'b1 +// cache inhibited 0GB-2GB !icpu_adr_i[31] +// cache inhibited 0GB-1GB 2GB-3GB !icpu_adr_i[30] +// cache inhibited 1GB-2GB 3GB-4GB icpu_adr_i[30] +// cache inhibited 2GB-4GB (default) icpu_adr_i[31] +// cached 0GB-4GB 1'b0 +// +`define OR1200_IMMU_CI 1'b0 + + +///////////////////////////////////////////////// +// +// Insn cache (IC) +// + +// 3 for 8 bytes, 4 for 16 bytes etc +`define OR1200_ICLS 4 + +// +// IC configurations +// +`ifdef OR1200_IC_1W_512B +`define OR1200_ICSIZE 9 // 512 +`define OR1200_ICINDX `OR1200_ICSIZE-2 // 7 +`define OR1200_ICINDXH `OR1200_ICSIZE-1 // 8 +`define OR1200_ICTAGL `OR1200_ICINDXH+1 // 9 +`define OR1200_ICTAG `OR1200_ICSIZE-`OR1200_ICLS // 5 +`define OR1200_ICTAG_W 24 +`endif +`ifdef OR1200_IC_1W_4KB +`define OR1200_ICSIZE 12 // 4096 +`define OR1200_ICINDX `OR1200_ICSIZE-2 // 10 +`define OR1200_ICINDXH `OR1200_ICSIZE-1 // 11 +`define OR1200_ICTAGL `OR1200_ICINDXH+1 // 12 +`define OR1200_ICTAG `OR1200_ICSIZE-`OR1200_ICLS // 8 +`define OR1200_ICTAG_W 21 +`endif +`ifdef OR1200_IC_1W_8KB +`define OR1200_ICSIZE 13 // 8192 +`define OR1200_ICINDX `OR1200_ICSIZE-2 // 11 +`define OR1200_ICINDXH `OR1200_ICSIZE-1 // 12 +`define OR1200_ICTAGL `OR1200_ICINDXH+1 // 13 +`define OR1200_ICTAG `OR1200_ICSIZE-`OR1200_ICLS // 9 +`define OR1200_ICTAG_W 20 +`endif + + +///////////////////////////////////////////////// +// +// Data cache (DC) +// + +// 3 for 8 bytes, 4 for 16 bytes etc +`define OR1200_DCLS 4 + +// Define to perform store refill (potential performance penalty) +// `define OR1200_DC_STORE_REFILL + +// +// DC configurations +// +`ifdef OR1200_DC_1W_4KB +`define OR1200_DCSIZE 12 // 4096 +`define OR1200_DCINDX `OR1200_DCSIZE-2 // 10 +`define OR1200_DCINDXH `OR1200_DCSIZE-1 // 11 +`define OR1200_DCTAGL `OR1200_DCINDXH+1 // 12 +`define OR1200_DCTAG `OR1200_DCSIZE-`OR1200_DCLS // 8 +`define OR1200_DCTAG_W 21 +`endif +`ifdef OR1200_DC_1W_8KB +`define OR1200_DCSIZE 13 // 8192 +`define OR1200_DCINDX `OR1200_DCSIZE-2 // 11 +`define OR1200_DCINDXH `OR1200_DCSIZE-1 // 12 +`define OR1200_DCTAGL `OR1200_DCINDXH+1 // 13 +`define OR1200_DCTAG `OR1200_DCSIZE-`OR1200_DCLS // 9 +`define OR1200_DCTAG_W 20 +`endif + +///////////////////////////////////////////////// +// +// Store buffer (SB) +// + +// +// Store buffer +// +// It will improve performance by "caching" CPU stores +// using store buffer. This is most important for function +// prologues because DC can only work in write though mode +// and all stores would have to complete external WB writes +// to memory. +// Store buffer is between DC and data BIU. +// All stores will be stored into store buffer and immediately +// completed by the CPU, even though actual external writes +// will be performed later. As a consequence store buffer masks +// all data bus errors related to stores (data bus errors +// related to loads are delivered normally). +// All pending CPU loads will wait until store buffer is empty to +// ensure strict memory model. Right now this is necessary because +// we don't make destinction between cached and cache inhibited +// address space, so we simply empty store buffer until loads +// can begin. +// +// It makes design a bit bigger, depending what is the number of +// entries in SB FIFO. Number of entries can be changed further +// down. +// +//`define OR1200_SB_IMPLEMENTED + +// +// Number of store buffer entries +// +// Verified number of entries are 4 and 8 entries +// (2 and 3 for OR1200_SB_LOG). OR1200_SB_ENTRIES must +// always match 2**OR1200_SB_LOG. +// To disable store buffer, undefine +// OR1200_SB_IMPLEMENTED. +// +`define OR1200_SB_LOG 2 // 2 or 3 +`define OR1200_SB_ENTRIES 4 // 4 or 8 + + +///////////////////////////////////////////////// +// +// Quick Embedded Memory (QMEM) +// + +// +// Quick Embedded Memory +// +// Instantiation of dedicated insn/data memory (RAM or ROM). +// Insn fetch has effective throughput 1insn / clock cycle. +// Data load takes two clock cycles / access, data store +// takes 1 clock cycle / access (if there is no insn fetch)). +// Memory instantiation is shared between insn and data, +// meaning if insn fetch are performed, data load/store +// performance will be lower. +// +// Main reason for QMEM is to put some time critical functions +// into this memory and to have predictable and fast access +// to these functions. (soft fpu, context switch, exception +// handlers, stack, etc) +// +// It makes design a bit bigger and slower. QMEM sits behind +// IMMU/DMMU so all addresses are physical (so the MMUs can be +// used with QMEM and QMEM is seen by the CPU just like any other +// memory in the system). IC/DC are sitting behind QMEM so the +// whole design timing might be worse with QMEM implemented. +// +//`define OR1200_QMEM_IMPLEMENTED + +// +// Base address and mask of QMEM +// +// Base address defines first address of QMEM. Mask defines +// QMEM range in address space. Actual size of QMEM is however +// determined with instantiated RAM/ROM. However bigger +// mask will reserve more address space for QMEM, but also +// make design faster, while more tight mask will take +// less address space but also make design slower. If +// instantiated RAM/ROM is smaller than space reserved with +// the mask, instatiated RAM/ROM will also be shadowed +// at higher addresses in reserved space. +// +`define OR1200_QMEM_IADDR 32'h0080_0000 +`define OR1200_QMEM_IMASK 32'hfff0_0000 // Max QMEM size 1MB +`define OR1200_QMEM_DADDR 32'h0080_0000 +`define OR1200_QMEM_DMASK 32'hfff0_0000 // Max QMEM size 1MB + +// +// QMEM interface byte-select capability +// +// To enable qmem_sel* ports, define this macro. +// +//`define OR1200_QMEM_BSEL + +// +// QMEM interface acknowledge +// +// To enable qmem_ack port, define this macro. +// +//`define OR1200_QMEM_ACK + +///////////////////////////////////////////////////// +// +// VR, UPR and Configuration Registers +// +// +// VR, UPR and configuration registers are optional. If +// implemented, operating system can automatically figure +// out how to use the processor because it knows +// what units are available in the processor and how they +// are configured. +// +// This section must be last in or1200_defines.v file so +// that all units are already configured and thus +// configuration registers are properly set. +// + +// Define if you want configuration registers implemented +//`define OR1200_CFGR_IMPLEMENTED + +// Define if you want full address decode inside SYS group +`define OR1200_SYS_FULL_DECODE + +// Offsets of VR, UPR and CFGR registers +`define OR1200_SPRGRP_SYS_VR 4'h0 +`define OR1200_SPRGRP_SYS_UPR 4'h1 +`define OR1200_SPRGRP_SYS_CPUCFGR 4'h2 +`define OR1200_SPRGRP_SYS_DMMUCFGR 4'h3 +`define OR1200_SPRGRP_SYS_IMMUCFGR 4'h4 +`define OR1200_SPRGRP_SYS_DCCFGR 4'h5 +`define OR1200_SPRGRP_SYS_ICCFGR 4'h6 +`define OR1200_SPRGRP_SYS_DCFGR 4'h7 + +// VR fields +`define OR1200_VR_REV_BITS 5:0 +`define OR1200_VR_RES1_BITS 15:6 +`define OR1200_VR_CFG_BITS 23:16 +`define OR1200_VR_VER_BITS 31:24 + +// VR values +`define OR1200_VR_REV 6'h01 +`define OR1200_VR_RES1 10'h000 +`define OR1200_VR_CFG 8'h00 +`define OR1200_VR_VER 8'h12 + +// UPR fields +`define OR1200_UPR_UP_BITS 0 +`define OR1200_UPR_DCP_BITS 1 +`define OR1200_UPR_ICP_BITS 2 +`define OR1200_UPR_DMP_BITS 3 +`define OR1200_UPR_IMP_BITS 4 +`define OR1200_UPR_MP_BITS 5 +`define OR1200_UPR_DUP_BITS 6 +`define OR1200_UPR_PCUP_BITS 7 +`define OR1200_UPR_PMP_BITS 8 +`define OR1200_UPR_PICP_BITS 9 +`define OR1200_UPR_TTP_BITS 10 +`define OR1200_UPR_RES1_BITS 23:11 +`define OR1200_UPR_CUP_BITS 31:24 + +// UPR values +`define OR1200_UPR_UP 1'b1 +`ifdef OR1200_NO_DC +`define OR1200_UPR_DCP 1'b0 +`else +`define OR1200_UPR_DCP 1'b1 +`endif +`ifdef OR1200_NO_IC +`define OR1200_UPR_ICP 1'b0 +`else +`define OR1200_UPR_ICP 1'b1 +`endif +`ifdef OR1200_NO_DMMU +`define OR1200_UPR_DMP 1'b0 +`else +`define OR1200_UPR_DMP 1'b1 +`endif +`ifdef OR1200_NO_IMMU +`define OR1200_UPR_IMP 1'b0 +`else +`define OR1200_UPR_IMP 1'b1 +`endif +`define OR1200_UPR_MP 1'b1 // MAC always present +`ifdef OR1200_DU_IMPLEMENTED +`define OR1200_UPR_DUP 1'b1 +`else +`define OR1200_UPR_DUP 1'b0 +`endif +`define OR1200_UPR_PCUP 1'b0 // Performance counters not present +`ifdef OR1200_DU_IMPLEMENTED +`define OR1200_UPR_PMP 1'b1 +`else +`define OR1200_UPR_PMP 1'b0 +`endif +`ifdef OR1200_DU_IMPLEMENTED +`define OR1200_UPR_PICP 1'b1 +`else +`define OR1200_UPR_PICP 1'b0 +`endif +`ifdef OR1200_DU_IMPLEMENTED +`define OR1200_UPR_TTP 1'b1 +`else +`define OR1200_UPR_TTP 1'b0 +`endif +`define OR1200_UPR_RES1 13'h0000 +`define OR1200_UPR_CUP 8'h00 + +// CPUCFGR fields +`define OR1200_CPUCFGR_NSGF_BITS 3:0 +`define OR1200_CPUCFGR_HGF_BITS 4 +`define OR1200_CPUCFGR_OB32S_BITS 5 +`define OR1200_CPUCFGR_OB64S_BITS 6 +`define OR1200_CPUCFGR_OF32S_BITS 7 +`define OR1200_CPUCFGR_OF64S_BITS 8 +`define OR1200_CPUCFGR_OV64S_BITS 9 +`define OR1200_CPUCFGR_RES1_BITS 31:10 + +// CPUCFGR values +`define OR1200_CPUCFGR_NSGF 4'h0 +`define OR1200_CPUCFGR_HGF 1'b0 +`define OR1200_CPUCFGR_OB32S 1'b1 +`define OR1200_CPUCFGR_OB64S 1'b0 +`define OR1200_CPUCFGR_OF32S 1'b0 +`define OR1200_CPUCFGR_OF64S 1'b0 +`define OR1200_CPUCFGR_OV64S 1'b0 +`define OR1200_CPUCFGR_RES1 22'h000000 + +// DMMUCFGR fields +`define OR1200_DMMUCFGR_NTW_BITS 1:0 +`define OR1200_DMMUCFGR_NTS_BITS 4:2 +`define OR1200_DMMUCFGR_NAE_BITS 7:5 +`define OR1200_DMMUCFGR_CRI_BITS 8 +`define OR1200_DMMUCFGR_PRI_BITS 9 +`define OR1200_DMMUCFGR_TEIRI_BITS 10 +`define OR1200_DMMUCFGR_HTR_BITS 11 +`define OR1200_DMMUCFGR_RES1_BITS 31:12 + +// DMMUCFGR values +`ifdef OR1200_NO_DMMU +`define OR1200_DMMUCFGR_NTW 2'h0 // Irrelevant +`define OR1200_DMMUCFGR_NTS 3'h0 // Irrelevant +`define OR1200_DMMUCFGR_NAE 3'h0 // Irrelevant +`define OR1200_DMMUCFGR_CRI 1'b0 // Irrelevant +`define OR1200_DMMUCFGR_PRI 1'b0 // Irrelevant +`define OR1200_DMMUCFGR_TEIRI 1'b0 // Irrelevant +`define OR1200_DMMUCFGR_HTR 1'b0 // Irrelevant +`define OR1200_DMMUCFGR_RES1 20'h00000 +`else +`define OR1200_DMMUCFGR_NTW 2'h0 // 1 TLB way +`define OR1200_DMMUCFGR_NTS 3'h`OR1200_DTLB_INDXW // Num TLB sets +`define OR1200_DMMUCFGR_NAE 3'h0 // No ATB entries +`define OR1200_DMMUCFGR_CRI 1'b0 // No control register +`define OR1200_DMMUCFGR_PRI 1'b0 // No protection reg +`define OR1200_DMMUCFGR_TEIRI 1'b1 // TLB entry inv reg impl. +`define OR1200_DMMUCFGR_HTR 1'b0 // No HW TLB reload +`define OR1200_DMMUCFGR_RES1 20'h00000 +`endif + +// IMMUCFGR fields +`define OR1200_IMMUCFGR_NTW_BITS 1:0 +`define OR1200_IMMUCFGR_NTS_BITS 4:2 +`define OR1200_IMMUCFGR_NAE_BITS 7:5 +`define OR1200_IMMUCFGR_CRI_BITS 8 +`define OR1200_IMMUCFGR_PRI_BITS 9 +`define OR1200_IMMUCFGR_TEIRI_BITS 10 +`define OR1200_IMMUCFGR_HTR_BITS 11 +`define OR1200_IMMUCFGR_RES1_BITS 31:12 + +// IMMUCFGR values +`ifdef OR1200_NO_IMMU +`define OR1200_IMMUCFGR_NTW 2'h0 // Irrelevant +`define OR1200_IMMUCFGR_NTS 3'h0 // Irrelevant +`define OR1200_IMMUCFGR_NAE 3'h0 // Irrelevant +`define OR1200_IMMUCFGR_CRI 1'b0 // Irrelevant +`define OR1200_IMMUCFGR_PRI 1'b0 // Irrelevant +`define OR1200_IMMUCFGR_TEIRI 1'b0 // Irrelevant +`define OR1200_IMMUCFGR_HTR 1'b0 // Irrelevant +`define OR1200_IMMUCFGR_RES1 20'h00000 +`else +`define OR1200_IMMUCFGR_NTW 2'h0 // 1 TLB way +`define OR1200_IMMUCFGR_NTS 3'h`OR1200_ITLB_INDXW // Num TLB sets +`define OR1200_IMMUCFGR_NAE 3'h0 // No ATB entry +`define OR1200_IMMUCFGR_CRI 1'b0 // No control reg +`define OR1200_IMMUCFGR_PRI 1'b0 // No protection reg +`define OR1200_IMMUCFGR_TEIRI 1'b1 // TLB entry inv reg impl +`define OR1200_IMMUCFGR_HTR 1'b0 // No HW TLB reload +`define OR1200_IMMUCFGR_RES1 20'h00000 +`endif + +// DCCFGR fields +`define OR1200_DCCFGR_NCW_BITS 2:0 +`define OR1200_DCCFGR_NCS_BITS 6:3 +`define OR1200_DCCFGR_CBS_BITS 7 +`define OR1200_DCCFGR_CWS_BITS 8 +`define OR1200_DCCFGR_CCRI_BITS 9 +`define OR1200_DCCFGR_CBIRI_BITS 10 +`define OR1200_DCCFGR_CBPRI_BITS 11 +`define OR1200_DCCFGR_CBLRI_BITS 12 +`define OR1200_DCCFGR_CBFRI_BITS 13 +`define OR1200_DCCFGR_CBWBRI_BITS 14 +`define OR1200_DCCFGR_RES1_BITS 31:15 + +// DCCFGR values +`ifdef OR1200_NO_DC +`define OR1200_DCCFGR_NCW 3'h0 // Irrelevant +`define OR1200_DCCFGR_NCS 4'h0 // Irrelevant +`define OR1200_DCCFGR_CBS 1'b0 // Irrelevant +`define OR1200_DCCFGR_CWS 1'b0 // Irrelevant +`define OR1200_DCCFGR_CCRI 1'b1 // Irrelevant +`define OR1200_DCCFGR_CBIRI 1'b1 // Irrelevant +`define OR1200_DCCFGR_CBPRI 1'b0 // Irrelevant +`define OR1200_DCCFGR_CBLRI 1'b0 // Irrelevant +`define OR1200_DCCFGR_CBFRI 1'b1 // Irrelevant +`define OR1200_DCCFGR_CBWBRI 1'b0 // Irrelevant +`define OR1200_DCCFGR_RES1 17'h00000 +`else +`define OR1200_DCCFGR_NCW 3'h0 // 1 cache way +`define OR1200_DCCFGR_NCS (`OR1200_DCTAG) // Num cache sets +`define OR1200_DCCFGR_CBS (`OR1200_DCLS-4) // 16 byte cache block +`define OR1200_DCCFGR_CWS 1'b0 // Write-through strategy +`define OR1200_DCCFGR_CCRI 1'b1 // Cache control reg impl. +`define OR1200_DCCFGR_CBIRI 1'b1 // Cache block inv reg impl. +`define OR1200_DCCFGR_CBPRI 1'b0 // Cache block prefetch reg not impl. +`define OR1200_DCCFGR_CBLRI 1'b0 // Cache block lock reg not impl. +`define OR1200_DCCFGR_CBFRI 1'b1 // Cache block flush reg impl. +`define OR1200_DCCFGR_CBWBRI 1'b0 // Cache block WB reg not impl. +`define OR1200_DCCFGR_RES1 17'h00000 +`endif + +// ICCFGR fields +`define OR1200_ICCFGR_NCW_BITS 2:0 +`define OR1200_ICCFGR_NCS_BITS 6:3 +`define OR1200_ICCFGR_CBS_BITS 7 +`define OR1200_ICCFGR_CWS_BITS 8 +`define OR1200_ICCFGR_CCRI_BITS 9 +`define OR1200_ICCFGR_CBIRI_BITS 10 +`define OR1200_ICCFGR_CBPRI_BITS 11 +`define OR1200_ICCFGR_CBLRI_BITS 12 +`define OR1200_ICCFGR_CBFRI_BITS 13 +`define OR1200_ICCFGR_CBWBRI_BITS 14 +`define OR1200_ICCFGR_RES1_BITS 31:15 + +// ICCFGR values +`ifdef OR1200_NO_IC +`define OR1200_ICCFGR_NCW 3'h0 // Irrelevant +`define OR1200_ICCFGR_NCS 4'h0 // Irrelevant +`define OR1200_ICCFGR_CBS 1'b0 // Irrelevant +`define OR1200_ICCFGR_CWS 1'b0 // Irrelevant +`define OR1200_ICCFGR_CCRI 1'b0 // Irrelevant +`define OR1200_ICCFGR_CBIRI 1'b0 // Irrelevant +`define OR1200_ICCFGR_CBPRI 1'b0 // Irrelevant +`define OR1200_ICCFGR_CBLRI 1'b0 // Irrelevant +`define OR1200_ICCFGR_CBFRI 1'b0 // Irrelevant +`define OR1200_ICCFGR_CBWBRI 1'b0 // Irrelevant +`define OR1200_ICCFGR_RES1 17'h00000 +`else +`define OR1200_ICCFGR_NCW 3'h0 // 1 cache way +`define OR1200_ICCFGR_NCS (`OR1200_ICTAG) // Num cache sets +`define OR1200_ICCFGR_CBS (`OR1200_ICLS-4) // 16 byte cache block +`define OR1200_ICCFGR_CWS 1'b0 // Irrelevant +`define OR1200_ICCFGR_CCRI 1'b1 // Cache control reg impl. +`define OR1200_ICCFGR_CBIRI 1'b1 // Cache block inv reg impl. +`define OR1200_ICCFGR_CBPRI 1'b0 // Cache block prefetch reg not impl. +`define OR1200_ICCFGR_CBLRI 1'b0 // Cache block lock reg not impl. +`define OR1200_ICCFGR_CBFRI 1'b1 // Cache block flush reg impl. +`define OR1200_ICCFGR_CBWBRI 1'b0 // Irrelevant +`define OR1200_ICCFGR_RES1 17'h00000 +`endif + +// DCFGR fields +`define OR1200_DCFGR_NDP_BITS 2:0 +`define OR1200_DCFGR_WPCI_BITS 3 +`define OR1200_DCFGR_RES1_BITS 31:4 + +// DCFGR values +`ifdef OR1200_DU_HWBKPTS +`define OR1200_DCFGR_NDP 3'h`OR1200_DU_DVRDCR_PAIRS // # of DVR/DCR pairs +`ifdef OR1200_DU_DWCR0 +`define OR1200_DCFGR_WPCI 1'b1 +`else +`define OR1200_DCFGR_WPCI 1'b0 // WP counters not impl. +`endif +`else +`define OR1200_DCFGR_NDP 3'h0 // Zero DVR/DCR pairs +`define OR1200_DCFGR_WPCI 1'b0 // WP counters not impl. +`endif +`define OR1200_DCFGR_RES1 28'h0000000 + Index: release-1.0/backend/spartan3e_starter_kit/minsoc_defines.v =================================================================== --- release-1.0/backend/spartan3e_starter_kit/minsoc_defines.v (nonexistent) +++ release-1.0/backend/spartan3e_starter_kit/minsoc_defines.v (revision 151) @@ -0,0 +1,150 @@ +// +// Define FPGA manufacturer +// +//`define GENERIC_FPGA +//`define ALTERA_FPGA +`define XILINX_FPGA + +// +// Define Xilinx FPGA family +// +`ifdef XILINX_FPGA +//`define SPARTAN2 +//`define SPARTAN3 +`define SPARTAN3E +//`define SPARTAN3A +//`define VIRTEX +//`define VIRTEX2 +//`define VIRTEX4 +//`define VIRTEX5 + +// +// Define Altera FPGA family +// +`elsif ALTERA_FPGA +//`define ARRIA_GX +//`define ARRIA_II_GX +//`define CYCLONE_I +//`define CYCLONE_II +`define CYCLONE_III +//`define CYCLONE_III_LS +//`define CYCLONE_IV_E +//`define CYCLONE_IV_GS +//`define MAX_II +//`define MAX_V +//`define MAX3000A +//`define MAX7000AE +//`define MAX7000B +//`define MAX7000S +//`define STRATIX +//`define STRATIX_II +//`define STRATIX_II_GX +//`define STRATIX_III +`endif + +// +// Memory +// +`define MEMORY_ADR_WIDTH 13 //MEMORY_ADR_WIDTH IS NOT ALLOWED TO BE LESS THAN 12, + //memory is composed by blocks of address width 11 + //Address width of memory -> select memory depth, + //2 powers MEMORY_ADR_WIDTH defines the memory depth + //the memory data width is 32 bit, + //memory amount in Bytes = 4*memory depth + +// +// Memory type (uncomment something if ASIC or generic memory) +// +//`define GENERIC_MEMORY +//`define AVANT_ATP +//`define VIRAGE_SSP +//`define VIRTUALSILICON_SSP + + +// +// TAP selection +// +//`define GENERIC_TAP +`define FPGA_TAP + +// +// Clock Division selection +// +//`define NO_CLOCK_DIVISION +//`define GENERIC_CLOCK_DIVISION +`define FPGA_CLOCK_DIVISION // For Altera ALTPLL, only CYCLONE_III family has been tested. + +// +// Define division +// +`define CLOCK_DIVISOR 2 //in case of GENERIC_CLOCK_DIVISION the real value will be rounded + //down to an even value in FPGA case, check minsoc_clock_manager + //for allowed divisors. + //DO NOT USE CLOCK_DIVISOR = 1 COMMENT THE CLOCK DIVISION SELECTION + //INSTEAD. + +// +// Reset polarity +// +//`define NEGATIVE_RESET //rstn +`define POSITIVE_RESET //rst + +// +// Start-up circuit (only necessary later to load firmware automatically from SPI memory) +// +//`define START_UP + +// +// Connected modules +// +`define UART +//`define ETHERNET + +// +// Ethernet reset +// +`define ETH_RESET 1'b0 +//`define ETH_RESET 1'b1 + +// +// Interrupts +// +`define APP_INT_RES1 1:0 +`define APP_INT_UART 2 +`define APP_INT_RES2 3 +`define APP_INT_ETH 4 +`define APP_INT_PS2 5 +`define APP_INT_RES3 19:6 + +// +// Address map +// +`define APP_ADDR_DEC_W 8 +`define APP_ADDR_SRAM `APP_ADDR_DEC_W'h00 +`define APP_ADDR_FLASH `APP_ADDR_DEC_W'h04 +`define APP_ADDR_DECP_W 4 +`define APP_ADDR_PERIP `APP_ADDR_DECP_W'h9 +`define APP_ADDR_SPI `APP_ADDR_DEC_W'h97 +`define APP_ADDR_ETH `APP_ADDR_DEC_W'h92 +`define APP_ADDR_AUDIO `APP_ADDR_DEC_W'h9d +`define APP_ADDR_UART `APP_ADDR_DEC_W'h90 +`define APP_ADDR_PS2 `APP_ADDR_DEC_W'h94 +`define APP_ADDR_RES1 `APP_ADDR_DEC_W'h9e +`define APP_ADDR_RES2 `APP_ADDR_DEC_W'h9f + +// +// Set-up GENERIC_TAP, GENERIC_MEMORY if GENERIC_FPGA was chosen +// and GENERIC_CLOCK_DIVISION if NO_CLOCK_DIVISION was not set +// +`ifdef GENERIC_FPGA + `undef FPGA_TAP + `undef FPGA_CLOCK_DIVISION + `undef XILINX_FPGA + `undef SPARTAN3E + + `define GENERIC_TAP + `define GENERIC_MEMORY + `ifndef NO_CLOCK_DIVISION + `define GENERIC_CLOCK_DIVISION + `endif +`endif
release-1.0/backend/spartan3e_starter_kit/minsoc_defines.v Property changes : Added: svn:executable ## -0,0 +1 ## +* \ No newline at end of property Index: release-1.0/backend/spartan3e_starter_kit/gcc-opt.mk =================================================================== --- release-1.0/backend/spartan3e_starter_kit/gcc-opt.mk (nonexistent) +++ release-1.0/backend/spartan3e_starter_kit/gcc-opt.mk (revision 151) @@ -0,0 +1 @@ +GCC_OPT=-mhard-mul -mhard-div -nostdlib Index: release-1.0/backend/spartan3e_starter_kit/spartan3e_starter_kit.ucf =================================================================== --- release-1.0/backend/spartan3e_starter_kit/spartan3e_starter_kit.ucf (nonexistent) +++ release-1.0/backend/spartan3e_starter_kit/spartan3e_starter_kit.ucf (revision 151) @@ -0,0 +1,64 @@ +# +# Soldered 50MHz clock. +# +NET "clk" LOC = "C9"; + +# +# Use button "south" as reset. +# +NET "reset" LOC = "K17" | PULLDOWN ; + +# +# UART serial port (RS232 DCE) - connector DB9 female. +# +NET "uart_srx" LOC = "R7"; +NET "uart_stx" LOC = "M14" | DRIVE = 8 | SLEW = SLOW ; + +########################### +## +## ETH +## +#NET "eth_txd(3)" LOC = "t5"; +#NET "eth_txd(2)" LOC = "r5"; +#NET "eth_txd(1)" LOC = "t15"; +#NET "eth_txd(0)" LOC = "r11"; +# +#NET "eth_tx_en" LOC = "p15"; +#NET "eth_tx_clk" LOC = "t7" | CLOCK_DEDICATED_ROUTE = FALSE; +#NET "eth_tx_er" LOC = "r6"; +# +#NET "eth_rxd(3)" LOC = "v14"; +#NET "eth_rxd(2)" LOC = "u11"; +#NET "eth_rxd(1)" LOC = "t11"; +#NET "eth_rxd(0)" LOC = "v8"; +# +#NET "eth_rx_er" LOC = "u14"; +#NET "eth_rx_dv" LOC = "v2"; +# +#NET "eth_rx_clk" LOC = "v3" | CLOCK_DEDICATED_ROUTE = FALSE; +# +#NET "eth_mdio" LOC = "u5" | PULLUP; +#NET "eth_crs" LOC = "u13"; +#NET "eth_col" LOC = "u6"; +#NET "eth_mdc" LOC = "p9"; +# +#NET "eth_trste" LOC = "p13"; #put it to a non connected FPGA pin (starter kit schematic BANK3) +# +#NET "eth_fds_mdint" LOC = "r13" | PULLUP; #put it to a non connected FPGA pin (starter kit schematic BANK3)(pullup not to generate interrupts) +########################### + +# +# JTAG signals - on J4 6-pin accessory header. +# + +#NET "jtag_tms" LOC = "D7" | PULLDOWN ; +#NET "jtag_tdi" LOC = "C7" | PULLDOWN ; +#NET "jtag_tdo" LOC = "F8" | SLEW = FAST | DRIVE = 8 ; +#NET "jtag_tck" LOC = "E8" | PULLDOWN ; + +#net "jtag_gnd" loc = "k2"; #put it to a non connected FPGA pin (starter kit schematic BANK3) +#net "jtag_vref" loc = "k7"; #put it to a non connected FPGA pin (starter kit schematic BANK3) + +# +# End of file. +#
release-1.0/backend/spartan3e_starter_kit/spartan3e_starter_kit.ucf Property changes : Added: svn:executable ## -0,0 +1 ## +* \ No newline at end of property Index: release-1.0/backend/spartan3e_starter_kit/board.h =================================================================== --- release-1.0/backend/spartan3e_starter_kit/board.h (nonexistent) +++ release-1.0/backend/spartan3e_starter_kit/board.h (revision 151) @@ -0,0 +1,40 @@ +#ifndef _BOARD_H_ +#define _BOARD_H_ + +#define MC_ENABLED 0 + +#define IC_ENABLE 0 +#define IC_SIZE 8192 +#define DC_ENABLE 0 +#define DC_SIZE 8192 + + +#define IN_CLK 25000000 + + +#define STACK_SIZE 0x01000 + +#define UART_BAUD_RATE 115200 + +#define UART_BASE 0x90000000 +#define UART_IRQ 2 +#define ETH_BASE 0x92000000 +#define ETH_IRQ 4 +#define I2C_BASE 0x9D000000 +#define I2C_IRQ 3 +#define CAN_BASE 0x94000000 +#define CAN_IRQ 5 + +#define MC_BASE_ADDR 0x60000000 +#define SPI_BASE 0xa0000000 + +#define ETH_DATA_BASE 0xa8000000 /* Address for ETH_DATA */ + +#define ETH_MACADDR0 0x00 +#define ETH_MACADDR1 0x12 +#define ETH_MACADDR2 0x34 +#define ETH_MACADDR3 0x56 +#define ETH_MACADDR4 0x78 +#define ETH_MACADDR5 0x9a + +#endif
release-1.0/backend/spartan3e_starter_kit/board.h Property changes : Added: svn:executable ## -0,0 +1 ## +* \ No newline at end of property Index: release-1.0/backend/spartan3e_starter_kit/orp.ld =================================================================== --- release-1.0/backend/spartan3e_starter_kit/orp.ld (nonexistent) +++ release-1.0/backend/spartan3e_starter_kit/orp.ld (revision 151) @@ -0,0 +1,60 @@ +MEMORY + { + reset : ORIGIN = 0x00000000, LENGTH = 0x00000200 + vectors : ORIGIN = 0x00000200, LENGTH = 0x00001000 + ram : ORIGIN = 0x00001200, LENGTH = 0x00006E00 /*0x8000 total*/ + } + +SECTIONS +{ + .reset : + { + *(.reset) + } > reset + + + + .vectors : + { + _vec_start = .; + *(.vectors) + _vec_end = .; + } > vectors + + .text : + { + *(.text) + } > ram + + .rodata : + { + *(.rodata) + *(.rodata.*) + } > ram + + .icm : + { + _icm_start = .; + *(.icm) + _icm_end = .; + } > ram + + .data : + { + _dst_beg = .; + *(.data) + _dst_end = .; + } > ram + + .bss : + { + *(.bss) + } > ram + + .stack (NOLOAD) : + { + *(.stack) + _src_addr = .; + } > ram + +}
release-1.0/backend/spartan3e_starter_kit/orp.ld Property changes : Added: svn:executable ## -0,0 +1 ## +* \ No newline at end of property Index: release-1.0/sim/run/run_bench =================================================================== --- release-1.0/sim/run/run_bench (nonexistent) +++ release-1.0/sim/run/run_bench (revision 151) @@ -0,0 +1,13 @@ +#!/bin/bash + +set -o errexit +set -o nounset +set -o pipefail +set -o posix # Make command substitution subshells inherit the errexit option. + # Otherwise, the 'command' in this example will not fail for non-zero exit codes: echo "$(command)" + +# A word count should always deliver the number of bytes in the hex file, +# regardless of the number of hex bytes per line. +FIRMWARE_SIZE_IN_BYTES="$(wc -w <"$1")" + +vvp -M ../../bench/verilog/vpi/ -mjp-io-vpi minsoc_bench +file_name="$1" +firmware_size="$FIRMWARE_SIZE_IN_BYTES" -lxt2
release-1.0/sim/run/run_bench Property changes : Added: svn:executable ## -0,0 +1 ## +* \ No newline at end of property Index: release-1.0/sim/run/generate_bench =================================================================== --- release-1.0/sim/run/generate_bench (nonexistent) +++ release-1.0/sim/run/generate_bench (revision 151) @@ -0,0 +1,2 @@ +#!/bin/sh +iverilog -c ../../prj/sim/minsoc_verilog.src -o minsoc_bench
release-1.0/sim/run/generate_bench Property changes : Added: svn:executable ## -0,0 +1 ## +* \ No newline at end of property Index: release-1.0/sim/run/start_server =================================================================== --- release-1.0/sim/run/start_server (nonexistent) +++ release-1.0/sim/run/start_server (revision 151) @@ -0,0 +1,2 @@ +#!/bin/sh +adv_jtag_bridge -x0 -l 0:4 -c 0x8 vpi
release-1.0/sim/run/start_server Property changes : Added: svn:executable ## -0,0 +1 ## +* \ No newline at end of property Index: release-1.0/sim/modelsim/run_sim.bat =================================================================== --- release-1.0/sim/modelsim/run_sim.bat (nonexistent) +++ release-1.0/sim/modelsim/run_sim.bat (revision 151) @@ -0,0 +1,13 @@ +@echo off +set /p target_firmware=Input the target firmware hex file along with its path. Ex: "..\..\sw\uart\uart.hex": + +for /f "tokens=*" %%i in ('find /c /v "NOTTHISSTRING" %target_firmware%') do set line_output=%%i +for /f "tokens=1,2 delims=:" %%a in ("%line_output%") do set firmware_size=%%b +set firmware_size=%firmware_size: =% + +if EXIST %target_firmware% ( +vsim -lib minsoc minsoc_bench -pli ../../bench/verilog/vpi/jp-io-vpi.dll +file_name=%target_firmware% +firmware_size=%firmware_size% +) else ( +echo %target_firmware% could not be found. +set /p exit=Press ENTER to close this window... +)
release-1.0/sim/modelsim/run_sim.bat Property changes : Added: svn:executable ## -0,0 +1 ## +* \ No newline at end of property Index: release-1.0/sim/modelsim/run_sim.sh =================================================================== --- release-1.0/sim/modelsim/run_sim.sh (nonexistent) +++ release-1.0/sim/modelsim/run_sim.sh (revision 151) @@ -0,0 +1,13 @@ +#!/bin/bash + +set -o errexit +set -o nounset +set -o pipefail +set -o posix # Make command substitution subshells inherit the errexit option. + # Otherwise, the 'command' in this example will not fail for non-zero exit codes: echo "$(command)" + +# A word count should always deliver the number of bytes in the hex file, +# regardless of the number of hex bytes per line. +FIRMWARE_SIZE_IN_BYTES="$(wc -w <"$1")" + +vsim -lib minsoc minsoc_bench -pli ../../bench/verilog/vpi/jp-io-vpi.so +file_name=$1 +firmware_size="$FIRMWARE_SIZE_IN_BYTES"
release-1.0/sim/modelsim/run_sim.sh Property changes : Added: svn:executable ## -0,0 +1 ## +* \ No newline at end of property Index: release-1.0/sim/modelsim/compile_design.bat =================================================================== --- release-1.0/sim/modelsim/compile_design.bat (nonexistent) +++ release-1.0/sim/modelsim/compile_design.bat (revision 151) @@ -0,0 +1,5 @@ +@echo off +vlog -incr -work minsoc -f ../../prj/sim/minsoc_verilog.src +::vcom -work minsoc -f ../../prj/sim/minsoc_vhdl.src +echo Finished... +set /p exit=Press ENTER to close this window...
release-1.0/sim/modelsim/compile_design.bat Property changes : Added: svn:executable ## -0,0 +1 ## +* \ No newline at end of property Index: release-1.0/sim/modelsim/prepare_modelsim.bat =================================================================== --- release-1.0/sim/modelsim/prepare_modelsim.bat (nonexistent) +++ release-1.0/sim/modelsim/prepare_modelsim.bat (revision 151) @@ -0,0 +1,5 @@ +@echo off +vlib minsoc +vmap minsoc ./minsoc +echo Finished... +set /p exit=Press ENTER to close this window...
release-1.0/sim/modelsim/prepare_modelsim.bat Property changes : Added: svn:executable ## -0,0 +1 ## +* \ No newline at end of property Index: release-1.0/sim/modelsim/compile_design.sh =================================================================== --- release-1.0/sim/modelsim/compile_design.sh (nonexistent) +++ release-1.0/sim/modelsim/compile_design.sh (revision 151) @@ -0,0 +1,4 @@ +#!/bin/bash + +vlog -incr -work minsoc -f ../../prj/sim/minsoc_verilog.src +#vcom -work minsoc -f ../../prj/sim/minsoc_vhdl.src
release-1.0/sim/modelsim/compile_design.sh Property changes : Added: svn:executable ## -0,0 +1 ## +* \ No newline at end of property Index: release-1.0/sim/modelsim/prepare_modelsim.sh =================================================================== --- release-1.0/sim/modelsim/prepare_modelsim.sh (nonexistent) +++ release-1.0/sim/modelsim/prepare_modelsim.sh (revision 151) @@ -0,0 +1,4 @@ +#!/bin/bash + +vlib minsoc +vmap minsoc ./minsoc
release-1.0/sim/modelsim/prepare_modelsim.sh Property changes : Added: svn:executable ## -0,0 +1 ## +* \ No newline at end of property Index: release-1.0/sim/results/wave.do.sav =================================================================== --- release-1.0/sim/results/wave.do.sav (nonexistent) +++ release-1.0/sim/results/wave.do.sav (revision 151) @@ -0,0 +1,49 @@ +[size] 1280 1001 +[pos] -1 -1 +*-29.000000 16828000000 285000000 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 +[treeopen] minsoc_bench. +[treeopen] minsoc_bench.minsoc_top_0. +@28 +minsoc_bench.reset +minsoc_bench.minsoc_top_0.or1200_top.iwb_cyc_o +minsoc_bench.minsoc_top_0.or1200_top.iwb_stb_o +minsoc_bench.minsoc_top_0.or1200_top.iwb_we_o +@22 +minsoc_bench.minsoc_top_0.or1200_top.iwb_adr_o[31:0] +minsoc_bench.minsoc_top_0.or1200_top.iwb_dat_i[31:0] +@28 +minsoc_bench.minsoc_top_0.or1200_top.iwb_ack_i +minsoc_bench.minsoc_top_0.or1200_top.dwb_cyc_o +minsoc_bench.minsoc_top_0.or1200_top.dwb_stb_o +minsoc_bench.minsoc_top_0.or1200_top.dwb_we_o +@22 +minsoc_bench.minsoc_top_0.or1200_top.dwb_adr_o[31:0] +minsoc_bench.minsoc_top_0.or1200_top.dwb_dat_o[31:0] +@28 +minsoc_bench.minsoc_top_0.or1200_top.dwb_ack_i +@22 +minsoc_bench.minsoc_top_0.or1200_top.or1200_cpu.or1200_sprs.sr[15:0] +minsoc_bench.minsoc_top_0.or1200_top.or1200_cpu.or1200_operandmuxes.rf_dataa[31:0] +minsoc_bench.minsoc_top_0.or1200_top.or1200_cpu.or1200_operandmuxes.rf_datab[31:0] +@28 +minsoc_bench.minsoc_top_0.or1200_top.or1200_cpu.or1200_alu.flag +minsoc_bench.minsoc_top_0.or1200_top.or1200_cpu.or1200_alu.flag_we +@22 +minsoc_bench.minsoc_top_0.or1200_top.or1200_cpu.or1200_alu.result[31:0] +minsoc_bench.minsoc_top_0.or1200_top.or1200_cpu.or1200_alu.alu_op[3:0] +minsoc_bench.minsoc_top_0.or1200_top.or1200_cpu.or1200_operandmuxes.operand_a[31:0] +minsoc_bench.minsoc_top_0.or1200_top.or1200_cpu.or1200_operandmuxes.operand_b[31:0] +@28 +minsoc_bench.uart_stx +minsoc_bench.minsoc_top_0.uart_top.wb_cyc_i +minsoc_bench.minsoc_top_0.uart_top.wb_stb_i +minsoc_bench.minsoc_top_0.uart_top.wb_we_i +@22 +minsoc_bench.minsoc_top_0.uart_top.wb_adr_i[4:0] +minsoc_bench.minsoc_top_0.uart_top.wb_dat8_i[7:0] +minsoc_bench.minsoc_top_0.uart_top.wb_dat8_o[7:0] +@28 +minsoc_bench.minsoc_top_0.uart_top.wb_ack_o +minsoc_bench.minsoc_top_0.spi_flash_ss[1:0] +minsoc_bench.minsoc_top_0.spi_flash_sclk +minsoc_bench.minsoc_top_0.spi_flash_miso
release-1.0/sim/results/wave.do.sav Property changes : Added: svn:executable ## -0,0 +1 ## +* \ No newline at end of property Index: release-1.0/sw/eth/eth.c =================================================================== --- release-1.0/sw/eth/eth.c (nonexistent) +++ release-1.0/sw/eth/eth.c (revision 151) @@ -0,0 +1,61 @@ +#include +#include +#include +#include + +#include +#include + + +extern int eth_rx_len; +extern int eth_rx_done, eth_tx_done; +extern unsigned char * eth_rx_data; +extern unsigned char * eth_tx_data; + +void eth_receive() +{ + int i; + uart_print_str("Length: \n"); + uart_print_long(eth_rx_len); + uart_print_str("\n"); + uart_print_str("Data: \n"); + for ( i = 0; i < eth_rx_len; i++ ) + { + uart_print_short(eth_rx_data[i]); + uart_print_str("\n"); + } + eth_recv_ack(); +} + +int main() +{ + uart_init(); + + int_init(); + eth_init(); + int_add(UART_IRQ, &uart_interrupt, NULL); + int_add(ETH_IRQ, ð_interrupt, NULL); + + /* We can't use printf because in this simple example + we don't link C library. */ + uart_print_str("Hello World.\n"); + + eth_tx_data[0] = 0xFF; + eth_tx_data[1] = 0x2B; + eth_tx_data[2] = 0x40; + eth_tx_data[3] = 0x50; + + eth_send(4); + + while(1) + { + if (eth_rx_done) + { + eth_receive(); + } + } + + report(0xdeaddead); + or32_exit(0); +} +
release-1.0/sw/eth/eth.c Property changes : Added: svn:executable ## -0,0 +1 ## +* \ No newline at end of property Index: release-1.0/sw/eth/Makefile =================================================================== --- release-1.0/sw/eth/Makefile (nonexistent) +++ release-1.0/sw/eth/Makefile (revision 151) @@ -0,0 +1,125 @@ +include ../support/Makefile.inc +include $(BACKEND_DIR)/gcc-opt.mk + +#USER INPUT +SRCS = eth.c +OR32_TARGET = eth.hex +TARGET = +TARGETLIB = +MODEL = static #dynamic|static +VERSION = 0.1 +MODE = debug #release|debug + +INCLUDEDIRS = $(BACKEND_DIR) $(SUPPORT_DIR) $(DRIVERS_DIR) +#libsystemc or systemc (system ignores lib at the beginning) +LIBNAMES = +LIBDIRS = +DEPENDDIR = ./depend + + +#CONFIGURATION +DEBUGPARAM = +RELEASEPARAM = + +DEBUGFLAGS = -g -O0 +RELEASEFLAGS = -O2 -fomit-frame-pointer + +CFLAGS = -Wall +CC = or32-elf-gcc +AR = or32-elf-ar +RANLIB = or32-elf-ranlib + +CFLAGS += $(GCC_OPT) + + +#MECHANICS +INCLUDESPATH = $(addprefix -I, $(INCLUDEDIRS)) +LIBSPATH = $(addprefix -L, $(LIBDIRS)) +LIBSLINKAGE = $(addprefix -l, $(subst lib, , $(LIBNAMES)) ) +COMMA = , +RPATH = $(addprefix -Wl$(COMMA)-R, $(LIBDIRS)) + +OBJS = $(addsuffix .o, $(basename $(SRCS))) +DEPS = $(addprefix $(DEPENDDIR)/, $(addsuffix .d, $(basename $(SRCS) ) ) ) + +STATICLIB = $(addprefix lib, $(addsuffix .a, $(TARGETLIB) ) ) +DYNAMICLIB = $(addprefix lib, $(addsuffix .so, $(TARGETLIB) ) ) +SONAME = $(addsuffix .$(VERSION), $(DYNAMICLIB)) + +ifeq (debug,$(findstring debug, $(MODE))) +CFLAGS += $(DEBUGFLAGS) $(addprefix -D, $(DEBUGPARAM)) +else +CFLAGS += $(RELEASEFLAGS) $(addprefix -D, $(RELEASEPARAM)) +endif + +ifdef TARGETLIB +ifeq (dynamic,$(findstring dynamic, $(MODEL))) +TARGET = $(DYNAMICLIB) +CFLAGS += -fPIC +else +TARGET = $(STATICLIB) +endif +endif + + +#MAKEFILE RULES +all: $(TARGET) $(OR32_TARGET) + +depend: $(DEPS) + +docs: Doxyfile + doxygen + +distclean: + make clean + rm -rf $(DEPENDDIR) Doxygen + + +-include $(DEPS) + + +ifndef TARGETLIB +$(TARGET): $(OBJS) + $(CC) $(LIBSPATH) $(RPATH) -o $@ $^ $(LIBSLINKAGE) +endif + + +$(STATICLIB): $(OBJS) + $(AR) cru $@ $^ + $(RANLIB) $@ + +$(DYNAMICLIB): $(OBJS) + $(CC) -shared -Wl,-soname,$(SONAME) -o $@ $^ + ln -fs $@ $(SONAME) + + +%.o: %.c + $(CC) $(CFLAGS) $(INCLUDESPATH) -c $< -o $@ + + +$(DEPENDDIR)/%.d: %.c + mkdir -p $(DEPENDDIR) + $(CC) $(INCLUDESPATH) -MM -MF $@ $< + + +# DO NOT DELETE + +STEM = $(subst .hex, , $(OR32_TARGET)) +BINARY = $(addsuffix .bin, $(STEM) ) +EXECUTABLE = $(addsuffix .or32, $(STEM) ) + +$(OR32_TARGET): $(BINARY) + $(BIN2HEX) $? 1 -size_word > $@ + +$(BINARY): $(EXECUTABLE) + $(OR32_TOOL_PREFIX)-objcopy -O binary $? $@ + +#except.o and reset.o should be already inside of $(SUPPORT) (libsupport.a) but for some reason the compiler ignores that fact +#(e.g. or32-elf-objdump -t libsupport.a shows it) +$(EXECUTABLE): $(OBJS) ../support/except.o ../support/reset.o $(SUPPORT) $(DRIVERS) + $(CC) $(CFLAGS) $(GCC_LIB_OPTS) -T $(LINKER_SCRIPT) $^ -o $@ + +clean: + rm -f *.o *~ $(TARGET) $(STATICLIB) $(DYNAMICLIB) $(SONAME) $(OR32_TARGET) $(BINARY) $(EXECUTABLE) + +#EOF Index: release-1.0/sw/uart/uart.c =================================================================== --- release-1.0/sw/uart/uart.c (nonexistent) +++ release-1.0/sw/uart/uart.c (revision 151) @@ -0,0 +1,21 @@ +#include +#include +#include +#include + +#include + +int main() +{ + uart_init(); + + int_init(); + int_add(UART_IRQ, &uart_interrupt, NULL); + + /* We can't use printf because in this simple example + we don't link C library. */ + uart_print_str("Hello World.\n"); + + report(0xdeaddead); + or32_exit(0); +}
release-1.0/sw/uart/uart.c Property changes : Added: svn:executable ## -0,0 +1 ## +* \ No newline at end of property Index: release-1.0/sw/uart/Makefile =================================================================== --- release-1.0/sw/uart/Makefile (nonexistent) +++ release-1.0/sw/uart/Makefile (revision 151) @@ -0,0 +1,125 @@ +include ../support/Makefile.inc +include $(BACKEND_DIR)/gcc-opt.mk + +#USER INPUT +SRCS = uart.c +OR32_TARGET = uart.hex +TARGET = +TARGETLIB = +MODEL = static #dynamic|static +VERSION = 0.1 +MODE = debug #release|debug + +INCLUDEDIRS = $(BACKEND_DIR) $(SUPPORT_DIR) $(DRIVERS_DIR) +#libsystemc or systemc (system ignores lib at the beginning) +LIBNAMES = +LIBDIRS = +DEPENDDIR = ./depend + + +#CONFIGURATION +DEBUGPARAM = +RELEASEPARAM = + +DEBUGFLAGS = -g -O0 +RELEASEFLAGS = -O2 -fomit-frame-pointer + +CFLAGS = -Wall +CC = or32-elf-gcc +AR = or32-elf-ar +RANLIB = or32-elf-ranlib + +CFLAGS += $(GCC_OPT) + + +#MECHANICS +INCLUDESPATH = $(addprefix -I, $(INCLUDEDIRS)) +LIBSPATH = $(addprefix -L, $(LIBDIRS)) +LIBSLINKAGE = $(addprefix -l, $(subst lib, , $(LIBNAMES)) ) +COMMA = , +RPATH = $(addprefix -Wl$(COMMA)-R, $(LIBDIRS)) + +OBJS = $(addsuffix .o, $(basename $(SRCS))) +DEPS = $(addprefix $(DEPENDDIR)/, $(addsuffix .d, $(basename $(SRCS) ) ) ) + +STATICLIB = $(addprefix lib, $(addsuffix .a, $(TARGETLIB) ) ) +DYNAMICLIB = $(addprefix lib, $(addsuffix .so, $(TARGETLIB) ) ) +SONAME = $(addsuffix .$(VERSION), $(DYNAMICLIB)) + +ifeq (debug,$(findstring debug, $(MODE))) +CFLAGS += $(DEBUGFLAGS) $(addprefix -D, $(DEBUGPARAM)) +else +CFLAGS += $(RELEASEFLAGS) $(addprefix -D, $(RELEASEPARAM)) +endif + +ifdef TARGETLIB +ifeq (dynamic,$(findstring dynamic, $(MODEL))) +TARGET = $(DYNAMICLIB) +CFLAGS += -fPIC +else +TARGET = $(STATICLIB) +endif +endif + + +#MAKEFILE RULES +all: $(TARGET) $(OR32_TARGET) + +depend: $(DEPS) + +docs: Doxyfile + doxygen + +distclean: + make clean + rm -rf $(DEPENDDIR) Doxygen + + +-include $(DEPS) + + +ifndef TARGETLIB +$(TARGET): $(OBJS) + $(CC) $(LIBSPATH) $(RPATH) -o $@ $^ $(LIBSLINKAGE) +endif + + +$(STATICLIB): $(OBJS) + $(AR) cru $@ $^ + $(RANLIB) $@ + +$(DYNAMICLIB): $(OBJS) + $(CC) -shared -Wl,-soname,$(SONAME) -o $@ $^ + ln -fs $@ $(SONAME) + + +%.o: %.c + $(CC) $(CFLAGS) $(INCLUDESPATH) -c $< -o $@ + + +$(DEPENDDIR)/%.d: %.c + mkdir -p $(DEPENDDIR) + $(CC) $(INCLUDESPATH) -MM -MF $@ $< + + +# DO NOT DELETE + +STEM = $(subst .hex, , $(OR32_TARGET)) +BINARY = $(addsuffix .bin, $(STEM) ) +EXECUTABLE = $(addsuffix .or32, $(STEM) ) + +$(OR32_TARGET): $(BINARY) + $(BIN2HEX) $? 1 -size_word > $@ + +$(BINARY): $(EXECUTABLE) + $(OR32_TOOL_PREFIX)-objcopy -O binary $? $@ + +#except.o and reset.o should be already inside of $(SUPPORT) (libsupport.a) but for some reason the compiler ignores that fact +#(e.g. or32-elf-objdump -t libsupport.a shows it) +$(EXECUTABLE): $(OBJS) ../support/except.o ../support/reset.o $(SUPPORT) $(DRIVERS) + $(CC) $(CFLAGS) $(GCC_LIB_OPTS) -T $(LINKER_SCRIPT) $^ -o $@ + +clean: + rm -f *.o *~ $(TARGET) $(STATICLIB) $(DYNAMICLIB) $(SONAME) $(OR32_TARGET) $(BINARY) $(EXECUTABLE) + +#EOF Index: release-1.0/sw/drivers/uart.c =================================================================== --- release-1.0/sw/drivers/uart.c (nonexistent) +++ release-1.0/sw/drivers/uart.c (revision 151) @@ -0,0 +1,134 @@ +#include +#include +#include "uart.h" + +#define BOTH_EMPTY (UART_LSR_TEMT | UART_LSR_THRE) + +#define WAIT_FOR_XMITR \ + do { \ + lsr = REG8(UART_BASE + UART_LSR); \ + } while ((lsr & BOTH_EMPTY) != BOTH_EMPTY) + +#define WAIT_FOR_THRE \ + do { \ + lsr = REG8(UART_BASE + UART_LSR); \ + } while ((lsr & UART_LSR_THRE) != UART_LSR_THRE) + +#define CHECK_FOR_CHAR (REG8(UART_BASE + UART_LSR) & UART_LSR_DR) + +#define WAIT_FOR_CHAR \ + do { \ + lsr = REG8(UART_BASE + UART_LSR); \ + } while ((lsr & UART_LSR_DR) != UART_LSR_DR) + +#define UART_TX_BUFF_LEN 32 +#define UART_TX_BUFF_MASK (UART_TX_BUFF_LEN -1) + +char tx_buff[UART_TX_BUFF_LEN]; +volatile int tx_level, rx_level; + +void uart_init(void) +{ + int divisor; + + /* Reset receiver and transmiter */ + /* Set RX interrupt for each byte */ + REG8(UART_BASE + UART_FCR) = UART_FCR_ENABLE_FIFO | UART_FCR_CLEAR_RCVR | UART_FCR_CLEAR_XMIT | UART_FCR_TRIGGER_1; + + /* Enable RX interrupt */ + REG8(UART_BASE + UART_IER) = UART_IER_RDI | UART_IER_THRI; + + /* Set 8 bit char, 1 stop bit, no parity */ + REG8(UART_BASE + UART_LCR) = UART_LCR_WLEN8 & ~(UART_LCR_STOP | UART_LCR_PARITY); + + /* Set baud rate */ + divisor = IN_CLK/(16 * UART_BAUD_RATE); + REG8(UART_BASE + UART_LCR) |= UART_LCR_DLAB; + REG8(UART_BASE + UART_DLM) = (divisor >> 8) & 0x000000ff; + REG8(UART_BASE + UART_DLL) = divisor & 0x000000ff; + REG8(UART_BASE + UART_LCR) &= ~(UART_LCR_DLAB); + + return; +} + +void uart_putc(char c) +{ + unsigned char lsr; + + WAIT_FOR_THRE; + REG8(UART_BASE + UART_TX) = c; + WAIT_FOR_XMITR; +} + + + +char uart_getc() +{ + char c; + c = REG8(UART_BASE + UART_RX); + return c; +} + + +void uart_interrupt() +{ + char lala; + unsigned char interrupt_id; + interrupt_id = REG8(UART_BASE + UART_IIR); + if ( interrupt_id & UART_IIR_RDI ) + { + lala = uart_getc(); + uart_putc(lala+1); + } + +} + +void uart_print_str(char *p) +{ + while(*p != 0) { + uart_putc(*p); + p++; + } +} + +void uart_print_long(unsigned long ul) +{ + int i; + char c; + + + uart_print_str("0x"); + for(i=0; i<8; i++) { + + c = (char) (ul>>((7-i)*4)) & 0xf; + if(c >= 0x0 && c<=0x9) + c += '0'; + else + c += 'a' - 10; + uart_putc(c); + } + +} + +void uart_print_short(unsigned long ul) +{ + int i; + char c; + char flag=0; + + + uart_print_str("0x"); + for(i=0; i<8; i++) { + + c = (char) (ul>>((7-i)*4)) & 0xf; + if(c >= 0x0 && c<=0x9) + c += '0'; + else + c += 'a' - 10; + if ((c != '0') || (i==7)) + flag=1; + if(flag) + uart_putc(c); + } + +} Index: release-1.0/sw/drivers/eth.c =================================================================== --- release-1.0/sw/drivers/eth.c (nonexistent) +++ release-1.0/sw/drivers/eth.c (revision 151) @@ -0,0 +1,99 @@ +#include +#include +#include "eth.h" + +int eth_tx_done; +int eth_rx_done; +int eth_rx_len; +unsigned char eth_tx_packet[1536]; //max length +unsigned char eth_rx_packet[1536]; +unsigned char * eth_tx_data; +unsigned char * eth_rx_data; + +void eth_recv_ack(void) +{ + eth_rx_done = 0; + eth_rx_len = 0; + //accept further data (reset RXBD to empty) + REG32(ETH_BASE + ETH_RXBD0L) = RX_READY; //len = 0 | IRQ & WR = 1 | EMPTY = 1 +} + +void eth_init() +{ + //TXEN & RXEN = 1; PAD & CRC = 1; FULLD = 1 + REG32(ETH_BASE + ETH_MODER) = ETH_TXEN | ETH_RXEN | ETH_PAD | ETH_CRCEN | ETH_FULLD; + //PHY Address = 0x001 + REG32(ETH_BASE + ETH_MIIADDRESS) = 0x00000001; + + //enable all interrupts + REG32(ETH_BASE + ETH_INT_MASK) = ETH_RXB | ETH_TXB; + + //set MAC ADDRESS + REG32(ETH_BASE + ETH_MAC_ADDR1) = (OWN_MAC_ADDRESS_5 << 8) | OWN_MAC_ADDRESS_4; //low word = mac address high word + REG32(ETH_BASE + ETH_MAC_ADDR0) = (OWN_MAC_ADDRESS_3 << 24) | (OWN_MAC_ADDRESS_2 << 16) + | (OWN_MAC_ADDRESS_1 << 8) | OWN_MAC_ADDRESS_0; //mac address rest + + //configure TXBD0 + REG32(ETH_BASE + ETH_TXBD0H) = (unsigned long)eth_tx_packet; //address used for tx_data + REG32(ETH_BASE + ETH_TXBD0L) = TX_READY; //length = 0 | PAD & CRC = 1 | IRQ & WR = 1 + + //configure RXBD0 + REG32(ETH_BASE + ETH_RXBD0H) = (unsigned long)eth_rx_packet; //address used for tx_data + REG32(ETH_BASE + ETH_RXBD0L) = RX_READY; //len = 0 | IRQ & WR = 1 | EMPTY = 1 + + //set txdata + eth_tx_packet[0] = BROADCAST_ADDRESS_5; + eth_tx_packet[1] = BROADCAST_ADDRESS_4; + eth_tx_packet[2] = BROADCAST_ADDRESS_3; + eth_tx_packet[3] = BROADCAST_ADDRESS_2; + eth_tx_packet[4] = BROADCAST_ADDRESS_1; + eth_tx_packet[5] = BROADCAST_ADDRESS_0; + + eth_tx_packet[6] = OWN_MAC_ADDRESS_5; + eth_tx_packet[7] = OWN_MAC_ADDRESS_4; + eth_tx_packet[8] = OWN_MAC_ADDRESS_3; + eth_tx_packet[9] = OWN_MAC_ADDRESS_2; + eth_tx_packet[10] = OWN_MAC_ADDRESS_1; + eth_tx_packet[11] = OWN_MAC_ADDRESS_0; + + //erase interrupts + REG32(ETH_BASE + ETH_INT_SOURCE) = ETH_RXC | ETH_TXC | ETH_BUSY | ETH_RXE | ETH_RXB | ETH_TXE | ETH_TXB; + + eth_tx_done = 1; + eth_rx_done = 0; + eth_rx_len = 0; + eth_tx_data = ð_tx_packet[HDR_LEN]; + eth_rx_data = ð_rx_packet[HDR_LEN]; +} + +int eth_send(int length) +{ + if (!eth_tx_done) //if previous command not fully processed, bail out + return -1; + + eth_tx_done = 0; + eth_tx_packet[12] = length >> 8; + eth_tx_packet[13] = length; + + REG32(ETH_BASE + ETH_TXBD0L) = (( 0x0000FFFF & ( length + HDR_LEN ) ) << 16) | BD_SND; + + return length; +} + +void eth_interrupt() +{ + unsigned long source = REG32(ETH_BASE + ETH_INT_SOURCE); + if ( source & ETH_TXB ) + { + eth_tx_done = 1; + //erase interrupt + REG32(ETH_BASE + ETH_INT_SOURCE) |= ETH_TXB; + } + if ( source & ETH_RXB ) + { + eth_rx_done = 1; + eth_rx_len = (REG32(ETH_BASE + ETH_RXBD0L) >> 16) - HDR_LEN - CRC_LEN; + //erase interrupt + REG32(ETH_BASE + ETH_INT_SOURCE) |= ETH_RXB; + } +} Index: release-1.0/sw/drivers/can.c =================================================================== --- release-1.0/sw/drivers/can.c (nonexistent) +++ release-1.0/sw/drivers/can.c (revision 151) @@ -0,0 +1,149 @@ +#include +#include +#include "can.h" + +int can_rx_done, can_tx_done; +int can_rx_rd_ptr; +int can_rx_wr_ptr; +int can_rx_buf_overflow; + +can_type can_rx_data[CAN_BUF_LEN], can_tx_data; + +can_type * can_get(void) +{ + if ( !can_rx_done ) + return NULL; + + can_rx_done--; + + int tmp; + tmp = can_rx_rd_ptr; + + if (can_rx_rd_ptr < CAN_BUF_LEN-1) + can_rx_rd_ptr++; + else + can_rx_rd_ptr = 0; + + return &can_rx_data[tmp]; +} + +void can_init(void) +{ + unsigned char sync_jmp, baudrate_presc, timing_seg1, timing_seg2, tripple_samp = 0; + unsigned char acpt_code, acpt_mask = 0; + unsigned char clk_div = 0 & CAN_BUS_CLKDIV_MASK; + + sync_jmp = 1; + baudrate_presc = 1; + timing_seg1 = 11; + timing_seg2 = 2; + tripple_samp = 1; + + acpt_code = 0x81; + acpt_mask = 0xFF; + + char timing0, timing1 = 0; + + timing0 = (sync_jmp << CAN_BUS_TIMING_0_SYNC_JMP_SHIFT) & CAN_BUS_TIMING_0_SYNC_JMP; + timing0 |= baudrate_presc & CAN_BUS_TIMING_0_BAUD_PRESC; + + timing1 = (tripple_samp << CAN_BUS_TIMING_1_TRIPLE_SAMP_SHIFT) & CAN_BUS_TIMING_1_TRIPLE_SAMP; + timing1 |= (timing_seg2 << CAN_BUS_TIMING_1_TIME_SEG2_SHIFT) & CAN_BUS_TIMING_1_TIME_SEG2; + timing1 |= timing_seg1 & CAN_BUS_TIMING_1_TIME_SEG1; + + REG8(CAN_BASE+CAN_MODE) = CAN_MODE_RESET; + + REG8(CAN_BASE+CAN_BUS_TIMING_0) = timing0; + REG8(CAN_BASE+CAN_BUS_TIMING_1) = timing1; + + REG8(CAN_BASE+CAN_ACPT_CODE0) = acpt_code; + REG8(CAN_BASE+CAN_ACPT_MASK0) = acpt_mask; + + REG8(CAN_BASE+CAN_BUS_MODE) &= ~CAN_BUS_MODE_CLOCK_OFF & ~CAN_BUS_MODE_EXTENDED_MODE; + + REG8(CAN_BASE+CAN_MODE) &= ~CAN_MODE_RESET; + REG8(CAN_BASE+CAN_BUS_CLKDIV) = clk_div; + + REG8(CAN_BASE+CAN_MODE) |= CAN_MODE_TX_IRQ_EN | CAN_MODE_RECV_IRQ_EN; + + can_tx_done = 1; + can_rx_done = 0; + can_rx_rd_ptr = 0; + can_rx_wr_ptr = 0; + can_rx_buf_overflow = 0; +} + +void can_recv_basic() +{ + unsigned char byte0, byte1; + + byte0 = REG8(CAN_BASE+CAN_RX_BUF); + byte1 = REG8(CAN_BASE+CAN_RX_BUF+1); + + can_rx_data[can_rx_wr_ptr].data[0] = REG8(CAN_BASE+CAN_RX_BUF+2); + can_rx_data[can_rx_wr_ptr].data[1] = REG8(CAN_BASE+CAN_RX_BUF+3); + can_rx_data[can_rx_wr_ptr].data[2] = REG8(CAN_BASE+CAN_RX_BUF+4); + can_rx_data[can_rx_wr_ptr].data[3] = REG8(CAN_BASE+CAN_RX_BUF+5); + can_rx_data[can_rx_wr_ptr].data[4] = REG8(CAN_BASE+CAN_RX_BUF+6); + can_rx_data[can_rx_wr_ptr].data[5] = REG8(CAN_BASE+CAN_RX_BUF+7); + can_rx_data[can_rx_wr_ptr].data[6] = REG8(CAN_BASE+CAN_RX_BUF+8); + can_rx_data[can_rx_wr_ptr].data[7] = REG8(CAN_BASE+CAN_RX_BUF+9); + + REG8(CAN_BASE+CAN_CMD) = CAN_CMD_RELEASE_BUFFER; + + can_rx_data[can_rx_wr_ptr].identifier = (byte0 << 3) | (byte1 >> 5); + can_rx_data[can_rx_wr_ptr].rtr = byte1 & 0x10; + can_rx_data[can_rx_wr_ptr].len = byte1 & 0x0F; + + if (can_rx_wr_ptr < CAN_BUF_LEN-1) + can_rx_wr_ptr++; + else + can_rx_wr_ptr = 0; + + if (can_rx_wr_ptr == can_rx_rd_ptr+1) //buffer overflow + { + can_rx_done = 1; + can_rx_buf_overflow++; + } + else + can_rx_done++; +} + +int can_send_basic() +{ + if (!can_tx_done) //if previous command not fully processed, bail out + return -1; + + can_tx_done = 0; + REG8(CAN_BASE+CAN_TX_BUF) = can_tx_data.identifier >> 3; + REG8(CAN_BASE+CAN_TX_BUF+1) = (can_tx_data.identifier << 5) | ((can_tx_data.rtr << 4) & 0x10) | (can_tx_data.len & 0x0F); + + REG8(CAN_BASE+CAN_TX_BUF+2) = can_tx_data.data[0]; + REG8(CAN_BASE+CAN_TX_BUF+3) = can_tx_data.data[1]; + REG8(CAN_BASE+CAN_TX_BUF+4) = can_tx_data.data[2]; + REG8(CAN_BASE+CAN_TX_BUF+5) = can_tx_data.data[3]; + REG8(CAN_BASE+CAN_TX_BUF+6) = can_tx_data.data[4]; + REG8(CAN_BASE+CAN_TX_BUF+7) = can_tx_data.data[5]; + REG8(CAN_BASE+CAN_TX_BUF+8) = can_tx_data.data[6]; + REG8(CAN_BASE+CAN_TX_BUF+9) = can_tx_data.data[7]; + + REG8(CAN_BASE+CAN_CMD) = CAN_CMD_TX_REQ; + + return can_tx_data.len; +} + +void can_irq(void) +{ + unsigned char irq_req, rx_done; + irq_req = REG8(CAN_BASE+IRQ_READ); + rx_done = irq_req & CAN_IRQ_READ_RX; + can_tx_done = irq_req & CAN_IRQ_READ_TX; + if (rx_done) + can_recv_basic(); +} + +void can_abort(void) +{ + REG8(CAN_BASE+CAN_CMD) = CAN_CMD_ABORT_TX; +} + Index: release-1.0/sw/drivers/Makefile =================================================================== --- release-1.0/sw/drivers/Makefile (nonexistent) +++ release-1.0/sw/drivers/Makefile (revision 151) @@ -0,0 +1,125 @@ +include ../support/Makefile.inc +include $(BACKEND_DIR)/gcc-opt.mk + +#USER INPUT +SRCS = can.c eth.c i2c.c interrupts.c uart.c +OR32_TARGET = +TARGET = +TARGETLIB = drivers +MODEL = static #dynamic|static +VERSION = 0.1 +MODE = debug #release|debug + +INCLUDEDIRS = $(BACKEND_DIR) $(SUPPORT_DIR) +#libsystemc or systemc (system ignores lib at the beginning) +LIBNAMES = +LIBDIRS = +DEPENDDIR = ./depend + + +#CONFIGURATION +DEBUGPARAM = +RELEASEPARAM = + +DEBUGFLAGS = -g -O0 +RELEASEFLAGS = -O2 -fomit-frame-pointer + +CFLAGS = -Wall +CC = or32-elf-gcc +AR = or32-elf-ar +RANLIB = or32-elf-ranlib + +CFLAGS += $(GCC_OPT) + + +#MECHANICS +INCLUDESPATH = $(addprefix -I, $(INCLUDEDIRS)) +LIBSPATH = $(addprefix -L, $(LIBDIRS)) +LIBSLINKAGE = $(addprefix -l, $(subst lib, , $(LIBNAMES)) ) +COMMA = , +RPATH = $(addprefix -Wl$(COMMA)-R, $(LIBDIRS)) + +OBJS = $(addsuffix .o, $(basename $(SRCS))) +DEPS = $(addprefix $(DEPENDDIR)/, $(addsuffix .d, $(basename $(SRCS) ) ) ) + +STATICLIB = $(addprefix lib, $(addsuffix .a, $(TARGETLIB) ) ) +DYNAMICLIB = $(addprefix lib, $(addsuffix .so, $(TARGETLIB) ) ) +SONAME = $(addsuffix .$(VERSION), $(DYNAMICLIB)) + +ifeq (debug,$(findstring debug, $(MODE))) +CFLAGS += $(DEBUGFLAGS) $(addprefix -D, $(DEBUGPARAM)) +else +CFLAGS += $(RELEASEFLAGS) $(addprefix -D, $(RELEASEPARAM)) +endif + +ifdef TARGETLIB +ifeq (dynamic,$(findstring dynamic, $(MODEL))) +TARGET = $(DYNAMICLIB) +CFLAGS += -fPIC +else +TARGET = $(STATICLIB) +endif +endif + + +#MAKEFILE RULES +all: $(TARGET) $(OR32_TARGET) + +depend: $(DEPS) + +docs: Doxyfile + doxygen + +distclean: + make clean + rm -rf $(DEPENDDIR) Doxygen + + +-include $(DEPS) + + +ifndef TARGETLIB +$(TARGET): $(OBJS) + $(CC) $(LIBSPATH) $(RPATH) -o $@ $^ $(LIBSLINKAGE) +endif + + +$(STATICLIB): $(OBJS) + $(AR) cru $@ $^ + $(RANLIB) $@ + +$(DYNAMICLIB): $(OBJS) + $(CC) -shared -Wl,-soname,$(SONAME) -o $@ $^ + ln -fs $@ $(SONAME) + + +%.o: %.c + $(CC) $(CFLAGS) $(INCLUDESPATH) -c $< -o $@ + + +$(DEPENDDIR)/%.d: %.c + mkdir -p $(DEPENDDIR) + $(CC) $(INCLUDESPATH) -MM -MF $@ $< + + +# DO NOT DELETE + +STEM = $(subst .hex, , $(OR32_TARGET)) +BINARY = $(addsuffix .bin, $(STEM) ) +EXECUTABLE = $(addsuffix .or32, $(STEM) ) + +$(OR32_TARGET): $(BINARY) + $(BIN2HEX) $? 1 -size_word > $@ + +$(BINARY): $(EXECUTABLE) + $(OR32_TOOL_PREFIX)-objcopy -O binary $? $@ + +#except.o and reset.o should be already inside of $(SUPPORT) (libsupport.a) but for some reason the compiler ignores that fact +#(e.g. or32-elf-objdump -t libsupport.a shows it) +$(EXECUTABLE): $(OBJS) ../support/except.o ../support/reset.o $(SUPPORT) $(DRIVERS) + $(CC) $(CFLAGS) $(GCC_LIB_OPTS) -T $(LINKER_SCRIPT) $^ -o $@ + +clean: + rm -f *.o *~ $(TARGET) $(STATICLIB) $(DYNAMICLIB) $(SONAME) $(OR32_TARGET) $(BINARY) $(EXECUTABLE) + +#EOF Index: release-1.0/sw/drivers/i2c.c =================================================================== --- release-1.0/sw/drivers/i2c.c (nonexistent) +++ release-1.0/sw/drivers/i2c.c (revision 151) @@ -0,0 +1,165 @@ +#include +#include +#include "i2c.h" + +int i2c_rd_done, i2c_wr_done; + +int i2c_pending_write; + +int i2c_rd_ptr, i2c_wr_ptr; + +int i2c_buf_overflow; +i2c_type i2c_data[I2C_BUF_LEN]; + +unsigned char start, pointer_write, write_hbyte, write_lbyte, read_hbyte, read_lbyte; +unsigned char cmd_list[5]; +unsigned char dat_list[5]; +int i2c_index; +int i2c_end; + +i2c_type * i2c_get(void) +{ + if ( !i2c_rd_done ) + return NULL; + + i2c_rd_done--; + + int tmp; + tmp = i2c_rd_ptr; + + if (i2c_rd_ptr < I2C_BUF_LEN-1) + i2c_rd_ptr++; + else + i2c_rd_ptr = 0; + + return &i2c_data[tmp]; +} + +void i2c_init(void) +{ + REG8(I2C_BASE+I2C_PRESC_HI) = 0x00; + REG8(I2C_BASE+I2C_PRESC_LO) = 49; //100kHz + REG8(I2C_BASE+I2C_CTR) = I2C_CTR_EN | I2C_CTR_IRQ_EN; + i2c_rd_done = 0; + i2c_wr_done = 0; + i2c_index = 0; + i2c_wr_ptr = 0; + i2c_rd_ptr = 0; + i2c_buf_overflow = 0; +} + +void i2c_set_ack_lvl(int ack_lvl, int final_ack_lvl) +{ + int ack, final_ack; + + ack = ( ack_lvl ) ? I2C_CR_NACK : I2C_CR_ACK; + final_ack = ( final_ack_lvl ) ? I2C_CR_NACK : I2C_CR_ACK; + + start = I2C_CR_STA | I2C_CR_WR | ack; + pointer_write = I2C_CR_WR | ack; + write_hbyte = I2C_CR_WR | ack; + write_lbyte = I2C_CR_WR | I2C_CR_STO | final_ack; + read_hbyte = I2C_CR_RD | ack; + read_lbyte = I2C_CR_RD | I2C_CR_STO | final_ack; +} + +void i2c_byte_transfer(void) +{ + if ( i2c_index > 0 ) + if ( cmd_list[i2c_index-1] == read_hbyte ) + i2c_data[i2c_wr_ptr].data = (REG8(I2C_BASE+I2C_RXR) << 8) & 0xFF00; + + REG8(I2C_BASE+I2C_TXR) = dat_list[i2c_index]; + REG8(I2C_BASE+I2C_CR) = cmd_list[i2c_index]; + + i2c_index++; +} + +void i2c_irq(void) +{ + REG8(I2C_BASE+I2C_CR) = I2C_CR_CLR_IRQ; + if (i2c_index <= i2c_end ) + i2c_byte_transfer(); + else + { + if ( cmd_list[i2c_index-1] == read_lbyte ) + i2c_data[i2c_wr_ptr].data |= REG8(I2C_BASE+I2C_RXR); + + i2c_index = 0; + + if ( i2c_pending_write ) + i2c_wr_done = 1; + else + { + if (i2c_wr_ptr < I2C_BUF_LEN-1) + i2c_wr_ptr++; + else + i2c_wr_ptr = 0; + + if (i2c_wr_ptr == i2c_rd_ptr+1) + { + i2c_rd_done = 1; + i2c_buf_overflow++; + } + else + i2c_rd_done++; + } + } +} + +int i2c_trans(i2c_mode * mode, i2c_type * data) +{ + if ( i2c_index != 0 ) //if previous command not fully processed, bail out + return -1; + + i2c_wr_done = 0; + + int i = 0; + + if ( mode->ptr_set || mode->read_write ) //start conditions with pointer set: (write always set ptr) + { + dat_list[i] = (data->address << 1) & I2C_TXR_ADR; + dat_list[i] |= I2C_TXR_W; + cmd_list[i++] = start; + + dat_list[i] = data->pointer; + cmd_list[i++] = pointer_write; + + if ( !mode->read_write ) //REstart for read, NO-REstart for write + { + dat_list[i] = (data->address << 1) & I2C_TXR_ADR; + dat_list[i] |= I2C_TXR_R; + cmd_list[i++] = start; + } + } + else //start conditions with NO pointer set (read only): ONE start + { + dat_list[i] = (data->address << 1) & I2C_TXR_ADR; + dat_list[i] |= I2C_TXR_R; + cmd_list[i++] = start; + } + + if ( mode->byte_word ) //read/write high byte + { + dat_list[i] = data->data >> 8; + cmd_list[i++] = (mode->read_write) ? write_hbyte : read_hbyte; + } + + dat_list[i] = data->data; //read/write low byte + cmd_list[i] = (mode->read_write) ? write_lbyte : read_lbyte; + + i2c_end = i; + + if ( !mode->read_write ) //set data to 0 for read, avoid or implications ((short)data |= byte) + { + i2c_data[i2c_wr_ptr] = *data; + i2c_data[i2c_wr_ptr].data = 0x0000; + } + + i2c_pending_write = mode->read_write; + + i2c_index = 0; + i2c_byte_transfer(); + + return mode->read_write+1; +} Index: release-1.0/sw/drivers/interrupts.c =================================================================== --- release-1.0/sw/drivers/interrupts.c (nonexistent) +++ release-1.0/sw/drivers/interrupts.c (revision 151) @@ -0,0 +1,14 @@ +// Dummy or32 except vectors +void buserr_except(){} +void dpf_except(){} +void ipf_except(){} +void align_except(){} +void illegal_except(){} +void dtlbmiss_except(){} +void itlbmiss_except(){} +void range_except(){} +void syscall_except(){} +void res1_except(){} +void trap_except(){} +void res2_except(){} + Index: release-1.0/sw/drivers/uart.h =================================================================== --- release-1.0/sw/drivers/uart.h (nonexistent) +++ release-1.0/sw/drivers/uart.h (revision 151) @@ -0,0 +1,126 @@ +#define UART_RX 0 /* In: Receive buffer (DLAB=0) */ +#define UART_TX 0 /* Out: Transmit buffer (DLAB=0) */ +#define UART_DLL 0 /* Out: Divisor Latch Low (DLAB=1) */ +#define UART_DLM 1 /* Out: Divisor Latch High (DLAB=1) */ +#define UART_IER 1 /* Out: Interrupt Enable Register */ +#define UART_IIR 2 /* In: Interrupt ID Register */ +#define UART_FCR 2 /* Out: FIFO Control Register */ +#define UART_EFR 2 /* I/O: Extended Features Register */ + /* (DLAB=1, 16C660 only) */ +#define UART_LCR 3 /* Out: Line Control Register */ +#define UART_MCR 4 /* Out: Modem Control Register */ +#define UART_LSR 5 /* In: Line Status Register */ +#define UART_MSR 6 /* In: Modem Status Register */ +#define UART_SCR 7 /* I/O: Scratch Register */ + +/* + * These are the definitions for the FIFO Control Register + * (16650 only) + */ +#define UART_FCR_ENABLE_FIFO 0x01 /* Enable the FIFO */ +#define UART_FCR_CLEAR_RCVR 0x02 /* Clear the RCVR FIFO */ +#define UART_FCR_CLEAR_XMIT 0x04 /* Clear the XMIT FIFO */ +#define UART_FCR_DMA_SELECT 0x08 /* For DMA applications */ +#define UART_FCR_TRIGGER_MASK 0xC0 /* Mask for the FIFO trigger range */ +#define UART_FCR_TRIGGER_1 0x00 /* Mask for trigger set at 1 */ +#define UART_FCR_TRIGGER_4 0x40 /* Mask for trigger set at 4 */ +#define UART_FCR_TRIGGER_8 0x80 /* Mask for trigger set at 8 */ +#define UART_FCR_TRIGGER_14 0xC0 /* Mask for trigger set at 14 */ + +/* 16650 redefinitions */ +#define UART_FCR6_R_TRIGGER_8 0x00 /* Mask for receive trigger set at 1 */ +#define UART_FCR6_R_TRIGGER_16 0x40 /* Mask for receive trigger set at 4 */ +#define UART_FCR6_R_TRIGGER_24 0x80 /* Mask for receive trigger set at 8 */ +#define UART_FCR6_R_TRIGGER_28 0xC0 /* Mask for receive trigger set at 14 */ +#define UART_FCR6_T_TRIGGER_16 0x00 /* Mask for transmit trigger set at 16 */ +#define UART_FCR6_T_TRIGGER_8 0x10 /* Mask for transmit trigger set at 8 */ +#define UART_FCR6_T_TRIGGER_24 0x20 /* Mask for transmit trigger set at 24 */ +#define UART_FCR6_T_TRIGGER_30 0x30 /* Mask for transmit trigger set at 30 */ + +/* + * These are the definitions for the Line Control Register + * + * Note: if the word length is 5 bits (UART_LCR_WLEN5), then setting + * UART_LCR_STOP will select 1.5 stop bits, not 2 stop bits. + */ +#define UART_LCR_DLAB 0x80 /* Divisor latch access bit */ +#define UART_LCR_SBC 0x40 /* Set break control */ +#define UART_LCR_SPAR 0x20 /* Stick parity (?) */ +#define UART_LCR_EPAR 0x10 /* Even parity select */ +#define UART_LCR_PARITY 0x08 /* Parity Enable */ +#define UART_LCR_STOP 0x04 /* Stop bits: 0=1 stop bit, 1= 2 stop bits */ +#define UART_LCR_WLEN5 0x00 /* Wordlength: 5 bits */ +#define UART_LCR_WLEN6 0x01 /* Wordlength: 6 bits */ +#define UART_LCR_WLEN7 0x02 /* Wordlength: 7 bits */ +#define UART_LCR_WLEN8 0x03 /* Wordlength: 8 bits */ + +/* + * These are the definitions for the Line Status Register + */ +#define UART_LSR_TEMT 0x40 /* Transmitter empty */ +#define UART_LSR_THRE 0x20 /* Transmit-hold-register empty */ +#define UART_LSR_BI 0x10 /* Break interrupt indicator */ +#define UART_LSR_FE 0x08 /* Frame error indicator */ +#define UART_LSR_PE 0x04 /* Parity error indicator */ +#define UART_LSR_OE 0x02 /* Overrun error indicator */ +#define UART_LSR_DR 0x01 /* Receiver data ready */ + +/* + * These are the definitions for the Interrupt Identification Register + */ +#define UART_IIR_NO_INT 0x01 /* No interrupts pending */ +#define UART_IIR_ID 0x06 /* Mask for the interrupt ID */ + +#define UART_IIR_MSI 0x00 /* Modem status interrupt */ +#define UART_IIR_THRI 0x02 /* Transmitter holding register empty */ +#define UART_IIR_TOI 0x0c /* Receive time out interrupt */ +#define UART_IIR_RDI 0x04 /* Receiver data interrupt */ +#define UART_IIR_RLSI 0x06 /* Receiver line status interrupt */ + +/* + * These are the definitions for the Interrupt Enable Register + */ +#define UART_IER_MSI 0x08 /* Enable Modem status interrupt */ +#define UART_IER_RLSI 0x04 /* Enable receiver line status interrupt */ +#define UART_IER_THRI 0x02 /* Enable Transmitter holding register int. */ +#define UART_IER_RDI 0x01 /* Enable receiver data interrupt */ + +/* + * These are the definitions for the Modem Control Register + */ +#define UART_MCR_LOOP 0x10 /* Enable loopback test mode */ +#define UART_MCR_OUT2 0x08 /* Out2 complement */ +#define UART_MCR_OUT1 0x04 /* Out1 complement */ +#define UART_MCR_RTS 0x02 /* RTS complement */ +#define UART_MCR_DTR 0x01 /* DTR complement */ + +/* + * These are the definitions for the Modem Status Register + */ +#define UART_MSR_DCD 0x80 /* Data Carrier Detect */ +#define UART_MSR_RI 0x40 /* Ring Indicator */ +#define UART_MSR_DSR 0x20 /* Data Set Ready */ +#define UART_MSR_CTS 0x10 /* Clear to Send */ +#define UART_MSR_DDCD 0x08 /* Delta DCD */ +#define UART_MSR_TERI 0x04 /* Trailing edge ring indicator */ +#define UART_MSR_DDSR 0x02 /* Delta DSR */ +#define UART_MSR_DCTS 0x01 /* Delta CTS */ +#define UART_MSR_ANY_DELTA 0x0F /* Any of the delta bits! */ + +/* + * These are the definitions for the Extended Features Register + * (StarTech 16C660 only, when DLAB=1) + */ +#define UART_EFR_CTS 0x80 /* CTS flow control */ +#define UART_EFR_RTS 0x40 /* RTS flow control */ +#define UART_EFR_SCD 0x20 /* Special character detect */ +#define UART_EFR_ENI 0x10 /* Enhanced Interrupt */ + + +void uart_init(void); +void uart_putc(char); +char uart_getc(void); +void uart_print_str(char *); +void uart_print_long(unsigned long); +void uart_interrupt(); +void uart_print_short(unsigned long ul); Index: release-1.0/sw/drivers/i2c.h =================================================================== --- release-1.0/sw/drivers/i2c.h (nonexistent) +++ release-1.0/sw/drivers/i2c.h (revision 151) @@ -0,0 +1,60 @@ +struct i2c_type +{ + unsigned char address; + unsigned char pointer; + unsigned short data; +}; + +struct i2c_mode +{ + unsigned char read_write; + unsigned char byte_word; + unsigned char ptr_set; +}; + +typedef struct i2c_type i2c_type; +typedef struct i2c_mode i2c_mode; + + + +void i2c_init(void); +void i2c_irq(void); + +i2c_type * i2c_get(void); //return pointer to first non read received data + +void i2c_set_ack_lvl(int ack_lvl, int final_ack_lvl); +int i2c_trans(i2c_mode * mode, i2c_type * data); //return (-1) or length (still processing previous) or asserted + +#define I2C_BUF_LEN 10 +#define I2C_PRESC_LO 0x00 +#define I2C_PRESC_HI 0x01 + +#define I2C_CTR 0x02 + +#define I2C_TXR 0x03 +#define I2C_RXR 0x03 + +#define I2C_CR 0x04 +#define I2C_SR 0x04 + +//BITS +#define I2C_CTR_EN 0x80 +#define I2C_CTR_IRQ_EN 0x40 + +#define I2C_TXR_ADR 0xFE +#define I2C_TXR_W 0x00 +#define I2C_TXR_R 0x01 + +#define I2C_CR_STA 0x80 +#define I2C_CR_STO 0x40 +#define I2C_CR_RD 0x20 +#define I2C_CR_WR 0x10 +#define I2C_CR_ACK 0x00 +#define I2C_CR_NACK 0x08 +#define I2C_CR_CLR_IRQ 0x01 + +#define I2C_SR_R_ACK 0x80 +#define I2C_SR_BUSY 0x40 +#define I2C_SR_ARB_LOST 0x20 +#define I2C_SR_TX_BUSY 0x02 +#define I2C_SR_IRQ_FLAG 0x01 Index: release-1.0/sw/drivers/eth.h =================================================================== --- release-1.0/sw/drivers/eth.h (nonexistent) +++ release-1.0/sw/drivers/eth.h (revision 151) @@ -0,0 +1,108 @@ +void eth_init(); +void eth_interrupt(); +void eth_recv_ack(void); + +int eth_send(int length); //return (-1) or length (still processing previous) or asserted + +#define ETH_MODER 0x00 +#define ETH_INT_SOURCE 0x04 +#define ETH_INT_MASK 0x08 +#define ETH_IPGT 0x0C +#define ETH_IPGR1 0x10 +#define ETH_IPGR2 0x14 +#define ETH_PACKETLEN 0x18 +#define ETH_COLLCONF 0x1C +#define ETH_TX_BD_NUM 0x20 +#define ETH_CTRLMODER 0x24 +#define ETH_MIIMODER 0x28 +#define ETH_MIICOMMAND 0x2C +#define ETH_MIIADDRESS 0x30 +#define ETH_MIITX_DATA 0x34 +#define ETH_MIIRX_DATA 0x38 +#define ETH_MIISTATUS 0x3C +#define ETH_MAC_ADDR0 0x40 +#define ETH_MAC_ADDR1 0x44 +#define ETH_HASH0_ADR 0x48 +#define ETH_HASH1_ADR 0x4C +#define ETH_TXCTRL 0x50 + +#define ETH_TXBD0H 0x404 +#define ETH_TXBD0L 0x400 + +#define ETH_RXBD0H 0x604 //this depends on TX_BD_NUM but this is the standard value +#define ETH_RXBD0L 0x600 //this depends on TX_BD_NUM but this is the standard value + +//MODER BITS +#define ETH_RECSMAL 0x00010000 +#define ETH_PAD 0x00008000 +#define ETH_HUGEN 0x00004000 +#define ETH_CRCEN 0x00002000 +#define ETH_DLYCRCEN 0x00001000 +#define ETH_FULLD 0x00000400 +#define ETH_EXDFREN 0x00000200 +#define ETH_NOBCKOF 0x00000100 +#define ETH_LOOPBCK 0x00000080 +#define ETH_IFG 0x00000040 +#define ETH_PRO 0x00000020 +#define ETH_IAM 0x00000010 +#define ETH_BRO 0x00000008 +#define ETH_NOPRE 0x00000004 +#define ETH_TXEN 0x00000002 +#define ETH_RXEN 0x00000001 + +//INTERRUPTS BITS +#define ETH_RXC 0x00000040 +#define ETH_TXC 0x00000020 +#define ETH_BUSY 0x00000010 +#define ETH_RXE 0x00000008 +#define ETH_RXB 0x00000004 +#define ETH_TXE 0x00000002 +#define ETH_TXB 0x00000001 + +//BUFFER DESCRIPTOR BITS +#define ETH_RXBD_EMPTY 0x00008000 +#define ETH_RXBD_IRQ 0x00004000 +#define ETH_RXBD_WRAP 0x00002000 +#define ETH_RXBD_CF 0x00000100 +#define ETH_RXBD_MISS 0x00000080 +#define ETH_RXBD_OR 0x00000040 +#define ETH_RXBD_IS 0x00000020 +#define ETH_RXBD_DN 0x00000010 +#define ETH_RXBD_TL 0x00000008 +#define ETH_RXBD_SF 0x00000004 +#define ETH_RXBD_CRC 0x00000002 +#define ETH_RXBD_LC 0x00000001 + +#define ETH_TXBD_READY 0x00008000 +#define ETH_TXBD_IRQ 0x00004000 +#define ETH_TXBD_WRAP 0x00002000 +#define ETH_TXBD_PAD 0x00001000 +#define ETH_TXBD_CRC 0x00000800 +#define ETH_TXBD_UR 0x00000100 +#define ETH_TXBD_RL 0x00000008 +#define ETH_TXBD_LC 0x00000004 +#define ETH_TXBD_DF 0x00000002 +#define ETH_TXBD_CS 0x00000001 + +//user defines +#define OWN_MAC_ADDRESS_5 0x55 +#define OWN_MAC_ADDRESS_4 0x47 +#define OWN_MAC_ADDRESS_3 0x34 +#define OWN_MAC_ADDRESS_2 0x22 +#define OWN_MAC_ADDRESS_1 0x88 +#define OWN_MAC_ADDRESS_0 0x92 + +#define BROADCAST_ADDRESS_5 0xFF +#define BROADCAST_ADDRESS_4 0xFF +#define BROADCAST_ADDRESS_3 0xFF +#define BROADCAST_ADDRESS_2 0xFF +#define BROADCAST_ADDRESS_1 0xFF +#define BROADCAST_ADDRESS_0 0xFF + +#define HDR_LEN 14 +#define CRC_LEN 4 +#define BD_SND ( ETH_TXBD_READY | ETH_TXBD_IRQ | ETH_TXBD_WRAP | ETH_TXBD_PAD | ETH_TXBD_CRC ) +#define RX_READY ( ETH_RXBD_EMPTY | ETH_RXBD_IRQ | ETH_RXBD_WRAP ) +#define TX_READY ( ETH_TXBD_IRQ | ETH_TXBD_WRAP | ETH_TXBD_PAD | ETH_TXBD_CRC ) + +//~user defines Index: release-1.0/sw/drivers/can.h =================================================================== --- release-1.0/sw/drivers/can.h (nonexistent) +++ release-1.0/sw/drivers/can.h (revision 151) @@ -0,0 +1,156 @@ +struct can_type +{ + unsigned char rtr; + unsigned char len; + unsigned short identifier; + unsigned char data[8]; +}; + +typedef struct can_type can_type; + +#define CAN_BUF_LEN 10 + +void can_init(void); +void can_irq(void); + +can_type * can_get(void); //return pointer to first non read received data + +int can_send_basic(); //return (-1) or length (still processing previous) or asserted +void can_abort(void); + +//BOTH MODES +#define CAN_MODE 0x00 +#define CAN_CMD 0x01 +#define CAN_STATUS 0x02 +#define IRQ_READ 0x03 + +#define CAN_ACPT_CODE0 0x04 //only writable while in reset mode +#define CAN_ACPT_MASK0 0x05 //only writable while in reset mode + +#define CAN_BUS_TIMING_0 0x06 //only writable while in reset mode +#define CAN_BUS_TIMING_1 0x07 //only writable while in reset mode + +#define CAN_BUS_CLKDIV 0x1F //only writable while NOT in reset mode + +#define CAN_TX_BUF 0x0A //only accessable while NOT in reset mode +#define CAN_TX_LEN 10 + +#define CAN_RX_BUF 0x14 //free read access for basic mode +#define CAN_RX_LEN 10 + +//only accessable while in reset mode +#define CAN_BUS_MODE 0x1F + + +//EXTENDED MODE ONLY +//only for extended mode & only accessable while in reset mode +#define CAN_IRQ_EN_EXT 0x04 //also writable if NOT in reset mode + +//read only regs +#define CAN_ARBIT_LOSS_CNT 0x0B //cnt of arbitration loss +#define CAN_ERROR_CAPTURE_CODE 0x0C +#define CAN_RX_MSG_CNT 0x1D +//~read only regs + +#define CAN_ERROR_WARN_LIMIT 0x0D + +#define CAN_RX_ERR_CNT 0x0E +#define CAN_TX_ERR_CNT 0x0F + +#define CAN_ACPT_CODE0_EXT 0x10 //also writable if NOT in reset mode +#define CAN_ACPT_CODE1 0x11 +#define CAN_ACPT_CODE2 0x12 +#define CAN_ACPT_CODE3 0x13 + +#define CAN_ACPT_MASK0_EXT 0x14 //also writable if NOT in reset mode +#define CAN_ACPT_MASK1 0x15 +#define CAN_ACPT_MASK2 0x16 +#define CAN_ACPT_MASK3 0x17 + +#define CAN_TX_BUF_EXT 0x10 //accessable if transmit_buffer_status=1 +#define CAN_TX_LEN_EXT 13 //ignores reset mode + +#define CAN_RX_BUF_EXT 0x10 //read access only in NOT reset mode +#define CAN_RX_LEN_EXT 13 + + +//BITS DEFINITIONS + +//BASIC MODE +#define CAN_MODE_RESET 0x01 +#define CAN_MODE_LISTEN_ONLY_BASIC 0x20 +#define CAN_MODE_RECV_IRQ_EN 0x02 +#define CAN_MODE_TX_IRQ_EN 0x04 +#define CAN_MODE_ERROR_IRQ_EN 0x08 +#define CAN_MODE_OVERRUN_IRQ_EN 0x10 +//EXTENDED MODE +#define CAN_MODE_LISTEN_ONLY_EXT 0x02 +#define CAN_MODE_SELF_TEST_MODE 0x04 +#define CAN_MODE_ACPT_FILTER_MODE 0x08 + +//CMD +#define CAN_CMD_CLR_DATA_OVERRUN 0x08 +#define CAN_CMD_RELEASE_BUFFER 0x04 +#define CAN_CMD_TX_REQ 0x11 +#define CAN_CMD_ABORT_TX 0x02 + +//STATUS +#define CAN_STATUS_NODE_BUS_OFF 0x80 +#define CAN_STATUS_ERROR 0x40 +#define CAN_STATUS_TX 0x20 +#define CAN_STATUS_RX 0x10 +#define CAN_STATUS_TX_COMPLETE 0x08 +#define CAN_STATUS_TX_BUF 0x04 +#define CAN_STATUS_OVERRUN 0x02 +#define CAN_STATUS_RX_BUF 0x01 + +//IRQ READ +#define CAN_IRQ_READ_BUS_ERROR 0x80 +#define CAN_IRQ_READ_ARBIT_LOST 0x40 +#define CAN_IRQ_READ_ERROR_PASSIV 0x20 +#define CAN_IRQ_READ_OVERRUN 0x08 +#define CAN_IRQ_READ_ERROR 0x04 +#define CAN_IRQ_READ_TX 0x02 +#define CAN_IRQ_READ_RX 0x01 + +//BUS_TIMING_0 +#define CAN_BUS_TIMING_0_SYNC_JMP_SHIFT 6 +#define CAN_BUS_TIMING_0_SYNC_JMP 0xC0 +#define CAN_BUS_TIMING_0_BAUD_PRESC 0x3F + +//BUS_TIMING_1 +#define CAN_BUS_TIMING_1_TRIPLE_SAMP_SHIFT 7 +#define CAN_BUS_TIMING_1_TRIPLE_SAMP 0x80 +#define CAN_BUS_TIMING_1_TIME_SEG2_SHIFT 4 +#define CAN_BUS_TIMING_1_TIME_SEG2 0x70 +#define CAN_BUS_TIMING_1_TIME_SEG1 0x0F + +//CLKDIV +//only writable while NOT in reset mode +#define CAN_BUS_CLKDIV_MASK 0x07 + + +//EXTENDED MODE ONLY +//CLKMODE +//only writable while in reset mode +#define CAN_BUS_MODE_CLOCK_OFF 0x08 +#define CAN_BUS_MODE_EXTENDED_MODE 0x80 + +//EXTENDED MODE IRQ +#define CAN_IRQ_EN_EXT_BUS_ERROR 0x80 +#define CAN_IRQ_EN_EXT_ARBIT_LOST 0x40 +#define CAN_IRQ_EN_EXT_ERROR_PASSIV 0x20 +#define CAN_IRQ_EN_EXT_OVERRUN 0x08 +#define CAN_IRQ_EN_EXT_ERROR 0x04 +#define CAN_IRQ_EN_EXT_TX 0x02 +#define CAN_IRQ_EN_EXT_RX 0x01 + +//EXTENDED ERROR CODES +#define CAN_ERROR_CAPTURE_CODE_TYPE_SHIFT 6 +#define CAN_ERROR_CAPTURE_CODE_TYPE 0xC0 +#define CAN_ERROR_CAPTURE_CODE_TYPE_BIT 0x0 +#define CAN_ERROR_CAPTURE_CODE_TYPE_FORM 0x1 +#define CAN_ERROR_CAPTURE_CODE_TYPE_STUFF 0x2 +#define CAN_ERROR_CAPTURE_CODE_TYPE_OTHER 0x3 +#define CAN_ERROR_CAPTURE_CODE_DIR 0x40 //1 = TX | 0 = RX +#define CAN_ERROR_CAPTURE_CODE_SEG 0x1F Index: release-1.0/sw/utils/bin2hex.c =================================================================== --- release-1.0/sw/utils/bin2hex.c (nonexistent) +++ release-1.0/sw/utils/bin2hex.c (revision 151) @@ -0,0 +1,169 @@ +/*$$HEADER*/ +/******************************************************************************/ +/* */ +/* H E A D E R I N F O R M A T I O N */ +/* */ +/******************************************************************************/ + +// Project Name : ORPSoC v2 +// File Name : bin2hex.c +// Prepared By : +// Project Start : + +/*$$COPYRIGHT NOTICE*/ +/******************************************************************************/ +/* */ +/* C O P Y R I G H T N O T I C E */ +/* */ +/******************************************************************************/ +/* + This library is free software; you can redistribute it and/or + modify it under the terms of the GNU Lesser General Public + License as published by the Free Software Foundation; + version 2.1 of the License, a copy of which is available from + http://www.gnu.org/licenses/old-licenses/lgpl-2.1.txt. + + This library is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + Lesser General Public License for more details. + + You should have received a copy of the GNU Lesser General Public + License along with this library; if not, write to the Free Software + Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA +*/ + +/*$$DESCRIPTION*/ +/******************************************************************************/ +/* */ +/* D E S C R I P T I O N */ +/* */ +/******************************************************************************/ +// +// Generates basic ASCII hex output to stdout from binary file input +// Compile and run the program with no options for usage. +// +// Modified by R. Diez in 2011 so that, when using option -size_word, +// padding zeroes are eventually appended, so that the length of +// the resulting file matches the length written in the header. + +#include +#include +#include +/* Number of bytes before line is broken + For example if target flash is 8 bits wide, + define BREAK as 1. If it is 16 bits wide, + define it as 2 etc. +*/ +#define BREAK 1 + +int main(int argc, char **argv) +{ + + FILE *fd; + int c; + int i = 0; + int write_size_word=0; // Disabled by default + int filename_index=1; + int bytes_per_line=1; + int bytes_per_line_index=2; + unsigned int padding_size = 0; + + if(argc < 3) { + fprintf(stderr,"\n\tInsufficient options.\n"); + fprintf(stderr,"\tPlease specify, in this order: a binary file to\n"); + fprintf(stderr,"\tconvert and the number of bytes of data to output\n"); + fprintf(stderr,"\tper line.\n"); + fprintf(stderr,"\tOptionally specify the option -size_word to output\n"); + fprintf(stderr,"\tthe size of the image in the first 4 bytes. This is\n"); + fprintf(stderr,"\tused by some of the new OR1k bootloaders. Note that\n"); + fprintf(stderr,"\tpadding zeroes will be appended so that the image size\n"); + fprintf(stderr,"\tis a multiple of 4.\n\n"); + exit(1); + } + + if(argc == 4) + { + if (strcmp("-size_word", argv[3]) == 0) + // We will calculate the number of bytes first + write_size_word=1; + } + + fd = fopen( argv[filename_index], "r" ); + + bytes_per_line = atoi(argv[bytes_per_line_index]); + + if ((bytes_per_line == 0) || (bytes_per_line > 8)) + { + fprintf(stderr,"bytes per line incorrect or missing: %s\n",argv[bytes_per_line_index]); + exit(1); + } + + // Now subtract 1 from bytes_per_line + //if (bytes_per_line == 2) + // bytes_per_line--; + + if (fd == NULL) { + fprintf(stderr,"failed to open input file: %s\n",argv[1]); + exit(1); + } + + if (write_size_word) + { + unsigned int image_size; + + // or1200 startup method of determining size of boot image we're copying by reading out + // the very first word in flash is used. Determine the length of this file + fseek(fd, 0, SEEK_END); + image_size = ftell(fd); + fseek(fd,0,SEEK_SET); + + // Now we should have the size of the file in bytes. Let's ensure it's a word multiple + padding_size = ( 4 - (image_size % 4) ) % 4; + image_size += padding_size; + + // Sanity check on image size + if (image_size < 8){ + fprintf(stderr, "Bad binary image. Size too small\n"); + return 1; + } + + // Now write out the image size + i=0; + printf("%.2x",(image_size >> 24) & 0xff); + if(++i==bytes_per_line){ printf("\n"); i=0; } + printf("%.2x",(image_size >> 16) & 0xff); + if(++i==bytes_per_line){ printf("\n"); i=0; } + printf("%.2x",(image_size >> 8) & 0xff); + if(++i==bytes_per_line){ printf("\n"); i=0; } + printf("%.2x",(image_size) & 0xff); + if(++i==bytes_per_line){ printf("\n"); i=0; } + } + + // Fix for the current bootloader software! Skip the first 4 bytes of application data. Hopefully it's not important. 030509 -- jb + for(i=0;i<4;i++) + c=fgetc(fd); + + i=0; + + // Now write out the binary data to hex format + while ((c = fgetc(fd)) != EOF) { + printf("%.2x", (unsigned int) c); + if (++i == bytes_per_line) { + printf("\n"); + i = 0; + } + } + + unsigned j; + for ( j = 0; j < padding_size; ++j ) { + // printf("Adding one padding byte.\n"); + printf("%.2x", 0); + if (++i == bytes_per_line) { + printf("\n"); + i = 0; + } + } + + return 0; +}
release-1.0/sw/utils/bin2hex.c Property changes : Added: svn:executable ## -0,0 +1 ## +* \ No newline at end of property Index: release-1.0/sw/utils/Makefile =================================================================== --- release-1.0/sw/utils/Makefile (nonexistent) +++ release-1.0/sw/utils/Makefile (revision 151) @@ -0,0 +1,58 @@ +#*$$HEADER*# +#******************************************************************************# +#* *# +#* H E A D E R I N F O R M A T I O N *# +#* *# +#******************************************************************************# + +## Project Name : ORPSoC v2 +## File Name : Makefile +## Prepared By : +## Project Start : + +#*$$COPYRIGHT NOTICE*# +#******************************************************************************# +#* *# +#* C O P Y R I G H T N O T I C E *# +#* *# +#******************************************************************************# +#* +# This library is free software; you can redistribute it and/or +# modify it under the terms of the GNU Lesser General Public +# License as published by the Free Software Foundation; +# version 2.1 of the License, a copy of which is available from +# http://www.gnu.org/licenses/old-licenses/lgpl-2.1.txt. +# +# This library is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU +# Lesser General Public License for more details. +# +# You should have received a copy of the GNU Lesser General Public +# License along with this library; if not, write to the Free Software +# Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA +# +#*$$DESCRIPTION*# +#******************************************************************************# +#* *# +#* D E S C R I P T I O N *# +#* *# +#******************************************************************************# +## +## Makefile for the ORPSoC software utilities +## + +PROGRAMS = bin2c bin2srec bin2flimg bin2hex bin2vmem +# NB: 'loader' not in that list + +CC = gcc +CFLAGS = -O2 -Wall + +% : %.c + @/bin/rm -f $@ + $(CC) -o $@ $(CFLAGS) $< + +all: $(PROGRAMS) + +clean: + /bin/rm -f $(PROGRAMS) *~ *.bak
release-1.0/sw/utils/Makefile Property changes : Added: svn:executable ## -0,0 +1 ## +* \ No newline at end of property Index: release-1.0/sw/utils/bin2vmem.c =================================================================== --- release-1.0/sw/utils/bin2vmem.c (nonexistent) +++ release-1.0/sw/utils/bin2vmem.c (revision 151) @@ -0,0 +1,159 @@ +/*$$HEADER*/ +/******************************************************************************/ +/* */ +/* H E A D E R I N F O R M A T I O N */ +/* */ +/******************************************************************************/ + +// Project Name : ORPSoC v2 +// File Name : bin2vmem.c +// Prepared By : jb, jb@orsoc.se +// Project Start : 2009-05-13 + +/*$$COPYRIGHT NOTICE*/ +/******************************************************************************/ +/* */ +/* C O P Y R I G H T N O T I C E */ +/* */ +/******************************************************************************/ +/* + This library is free software; you can redistribute it and/or + modify it under the terms of the GNU Lesser General Public + License as published by the Free Software Foundation; + version 2.1 of the License, a copy of which is available from + http://www.gnu.org/licenses/old-licenses/lgpl-2.1.txt. + + This library is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + Lesser General Public License for more details. + + You should have received a copy of the GNU Lesser General Public + License along with this library; if not, write to the Free Software + Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA +*/ + +/*$$DESCRIPTION*/ +/******************************************************************************/ +/* */ +/* D E S C R I P T I O N */ +/* */ +/******************************************************************************/ +// +// Generates VMEM output to stdout from binary images. +// Use with redirection like: ./bin2vmem app.bin > app.vmem +// To change either the number of bytes per word or word per line, change +// the following defines. +// Currently output is WORD addressed, NOT byte addressed +// eg: @00000000 00000000 00000000 00000000 00000000 +// @00000004 00000000 00000000 00000000 00000000 +// @00000008 00000000 00000000 00000000 00000000 +// @0000000c 00000000 00000000 00000000 00000000 +// etc.. +// + +#define WORDS_PER_LINE 4 +#define BYTES_PER_WORD 4 + +#include +#include +#include + +int main(int argc, char **argv) +{ + + FILE *fd; + int c; + int i = 0; + int write_size_word=0; // Disabled by default + int filename_index=1; + unsigned int image_size; + + // Counters keeping track of what we've printed + int current_addr = 0; + int word_counter = 0; + int byte_counter = 0; + + if(argc < 2) { + fprintf(stderr,"\n\tInsufficient options.\n"); + fprintf(stderr,"\tPlease specify a binary file to convert to VMEM\n"); + fprintf(stderr,"\n\tbin2vmem - creates vmem output to stdout from bin\n"); + exit(1); + } + + fd = fopen( argv[filename_index], "r" ); + + if (fd == NULL) { + fprintf(stderr,"failed to open input file: %s\n",argv[1]); + exit(1); + } + + fseek(fd, 0, SEEK_END); + image_size = ftell(fd); + fseek(fd,0,SEEK_SET); + + if (write_size_word) + { + // or1200 startup method of determining size of boot image we're copying by reading out + // the very first word in flash is used. Determine the length of this file + fseek(fd, 0, SEEK_END); + image_size = ftell(fd); + fseek(fd,0,SEEK_SET); + + // Now we should have the size of the file in bytes. Let's ensure it's a word multiple + image_size+=3; + image_size &= 0xfffffffc; + + // Sanity check on image size + if (image_size < 8){ + fprintf(stderr, "Bad binary image. Size too small\n"); + return 1; + } + + // Now write out the image size + printf("@%8x", current_addr); + printf("%8x", image_size); + current_addr += WORDS_PER_LINE * BYTES_PER_WORD; + } + else + { + } + + + // Fix for the current bootloader software! Skip the first 4 bytes of application data. Hopefully it's not important. 030509 -- jb + //for(i=0;i<4;i++) + // c=fgetc(fd); + i=0; + int starting_new_line = 1; + // Now write out the binary data to VMEM format: @ADDRESSS XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX + while ((c = fgetc(fd)) != EOF) { + if (starting_new_line) + { + // New line - print the current addr and then increment it + printf("@%.8x", current_addr); + //current_addr += WORDS_PER_LINE * BYTES_PER_WORD; + current_addr += WORDS_PER_LINE; + starting_new_line = 0; + } + if (byte_counter == 0) + printf(" "); + + printf("%.2x", (unsigned int) c); // now print the actual char + + byte_counter++; + + if (byte_counter == BYTES_PER_WORD) + { + word_counter++; + byte_counter=0; + } + if (word_counter == WORDS_PER_LINE) + { + printf("\n"); + word_counter = 0; + starting_new_line = 1; + } + } + + return 0; +}
release-1.0/sw/utils/bin2vmem.c Property changes : Added: svn:executable ## -0,0 +1 ## +* \ No newline at end of property Index: release-1.0/sw/utils/bin2srec.c =================================================================== --- release-1.0/sw/utils/bin2srec.c (nonexistent) +++ release-1.0/sw/utils/bin2srec.c (revision 151) @@ -0,0 +1,99 @@ +/*$$HEADER*/ +/******************************************************************************/ +/* */ +/* H E A D E R I N F O R M A T I O N */ +/* */ +/******************************************************************************/ + +// Project Name : ORPSoC v2 +// File Name : bin2srec.c +// Prepared By : +// Project Start : + +/*$$COPYRIGHT NOTICE*/ +/******************************************************************************/ +/* */ +/* C O P Y R I G H T N O T I C E */ +/* */ +/******************************************************************************/ +/* + This library is free software; you can redistribute it and/or + modify it under the terms of the GNU Lesser General Public + License as published by the Free Software Foundation; + version 2.1 of the License, a copy of which is available from + http://www.gnu.org/licenses/old-licenses/lgpl-2.1.txt. + + This library is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + Lesser General Public License for more details. + + You should have received a copy of the GNU Lesser General Public + License along with this library; if not, write to the Free Software + Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA +*/ + +/*$$DESCRIPTION*/ +/******************************************************************************/ +/* */ +/* D E S C R I P T I O N */ +/* */ +/******************************************************************************/ +// +// Generates SREC file output to stdout from binary file +// + +#include +#include + +#define SMARK "S214" +#define SADDR 0x000000 +#define INIT_ADDR 0x100100 +#define SCHKSUM 0xff + +int main(int argc, char **argv) +{ + + FILE *fd; + int c, j; + unsigned long addr = INIT_ADDR; + unsigned char chksum; + + if(argc < 2) { + fprintf(stderr,"no input file specified\n"); + exit(1); + } + if(argc > 2) { + fprintf(stderr,"too many input files (more than one) specified\n"); + exit(1); + } + + fd = fopen( argv[1], "r" ); + if (fd == NULL) { + fprintf(stderr,"failed to open input file: %s\n",argv[1]); + exit(1); + } + + while (!feof(fd)) { + j = 0; + chksum = SCHKSUM; + printf("%s%.6lx", SMARK, addr); + while (j < 16) { + c = fgetc(fd); + if (c == EOF) { + c = 0; + } + printf("%.2x", c); + chksum -= c; + j++; + } + + chksum -= addr & 0xff; + chksum -= (addr >> 8) & 0xff; + chksum -= (addr >> 16) & 0xff; + chksum -= 0x14; + printf("%.2x\r\n", chksum); + addr += 16; + } + return 0; +}
release-1.0/sw/utils/bin2srec.c Property changes : Added: svn:executable ## -0,0 +1 ## +* \ No newline at end of property Index: release-1.0/sw/utils/bin2flimg.c =================================================================== --- release-1.0/sw/utils/bin2flimg.c (nonexistent) +++ release-1.0/sw/utils/bin2flimg.c (revision 151) @@ -0,0 +1,92 @@ +/*$$HEADER*/ +/******************************************************************************/ +/* */ +/* H E A D E R I N F O R M A T I O N */ +/* */ +/******************************************************************************/ + +// Project Name : ORPSoC v2 +// File Name : bin2flimg.c +// Prepared By : +// Project Start : + +/*$$COPYRIGHT NOTICE*/ +/******************************************************************************/ +/* */ +/* C O P Y R I G H T N O T I C E */ +/* */ +/******************************************************************************/ +/* + This library is free software; you can redistribute it and/or + modify it under the terms of the GNU Lesser General Public + License as published by the Free Software Foundation; + version 2.1 of the License, a copy of which is available from + http://www.gnu.org/licenses/old-licenses/lgpl-2.1.txt. + + This library is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + Lesser General Public License for more details. + + You should have received a copy of the GNU Lesser General Public + License along with this library; if not, write to the Free Software + Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA +*/ + +/*$$DESCRIPTION*/ +/******************************************************************************/ +/* */ +/* D E S C R I P T I O N */ +/* */ +/******************************************************************************/ +// +// Generate flimg output to stdout from binary file input +// + +#include +#include + +int main(int argc, char **argv) +{ + + FILE *fd; + int c, j, width; + unsigned long word; + + if(argc < 3) { + fprintf(stderr,"no input file specified\n"); + exit(1); + } + if(argc > 3) { + fprintf(stderr,"too many input files (more than one) specified\n"); + exit(1); + } + + width = atoi(argv[1]); + + fd = fopen( argv[2], "r" ); + if (fd == NULL) { + fprintf(stderr,"failed to open input file: %s\n",argv[1]); + exit(1); + } + + while (!feof(fd)) { + j = 0; + word = 0; + while (j < width) { + c = fgetc(fd); + if (c == EOF) { + c = 0; + } + word = (word << 8) + c; + j++; + } + if(width == 1) + printf("%.2lx\n", word); + else if(width == 2) + printf("%.4lx\n", word); + else + printf("%.8lx\n", word); + } + return 0; +}
release-1.0/sw/utils/bin2flimg.c Property changes : Added: svn:executable ## -0,0 +1 ## +* \ No newline at end of property Index: release-1.0/sw/utils/bin2c.c =================================================================== --- release-1.0/sw/utils/bin2c.c (nonexistent) +++ release-1.0/sw/utils/bin2c.c (revision 151) @@ -0,0 +1,70 @@ +/*$$HEADER*/ +/******************************************************************************/ +/* */ +/* H E A D E R I N F O R M A T I O N */ +/* */ +/******************************************************************************/ + +// Project Name : ORPSoC v2 +// File Name : bin2c.c +// Prepared By : +// Project Start : + +/*$$COPYRIGHT NOTICE*/ +/******************************************************************************/ +/* */ +/* C O P Y R I G H T N O T I C E */ +/* */ +/******************************************************************************/ +/* + This library is free software; you can redistribute it and/or + modify it under the terms of the GNU Lesser General Public + License as published by the Free Software Foundation; + version 2.1 of the License, a copy of which is available from + http://www.gnu.org/licenses/old-licenses/lgpl-2.1.txt. + + This library is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + Lesser General Public License for more details. + + You should have received a copy of the GNU Lesser General Public + License along with this library; if not, write to the Free Software + Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA +*/ + +/*$$DESCRIPTION*/ +/******************************************************************************/ +/* */ +/* D E S C R I P T I O N */ +/* */ +/******************************************************************************/ +// +// Generate C file containing binary data in hex format in an array +// + +#include + +int main(void) +{ + + int c, i = 0; + + printf("#ifdef HAVE_CONFIG_H\n"); + printf("# include \"config.h\"\n"); + printf("#endif\n\n"); + printf("#ifdef EMBED\n"); + + printf("unsigned char flash_data[] = {\n"); + + while((c = getchar()) != EOF) { + printf("0x%.2x, ", c); + if(!(i % 32)) + printf("\n"); + i++; + } + + printf(" };\n"); + printf("#endif\n"); + return(0); +}
release-1.0/sw/utils/bin2c.c Property changes : Added: svn:executable ## -0,0 +1 ## +* \ No newline at end of property Index: release-1.0/sw/support/reset.S =================================================================== --- release-1.0/sw/support/reset.S (nonexistent) +++ release-1.0/sw/support/reset.S (revision 151) @@ -0,0 +1,112 @@ +/* Support file for c based tests */ +#include "or1200.h" +#include + + .section .stack + .space STACK_SIZE +_stack: + + .section .reset, "ax" + + .org 0x100 +_reset_vector: + l.nop + l.nop + l.addi r2,r0,0x0 + l.addi r3,r0,0x0 + l.addi r4,r0,0x0 + l.addi r5,r0,0x0 + l.addi r6,r0,0x0 + l.addi r7,r0,0x0 + l.addi r8,r0,0x0 + l.addi r9,r0,0x0 + l.addi r10,r0,0x0 + l.addi r11,r0,0x0 + l.addi r12,r0,0x0 + l.addi r13,r0,0x0 + l.addi r14,r0,0x0 + l.addi r15,r0,0x0 + l.addi r16,r0,0x0 + l.addi r17,r0,0x0 + l.addi r18,r0,0x0 + l.addi r19,r0,0x0 + l.addi r20,r0,0x0 + l.addi r21,r0,0x0 + l.addi r22,r0,0x0 + l.addi r23,r0,0x0 + l.addi r24,r0,0x0 + l.addi r25,r0,0x0 + l.addi r26,r0,0x0 + l.addi r27,r0,0x0 + l.addi r28,r0,0x0 + l.addi r29,r0,0x0 + l.addi r30,r0,0x0 + l.addi r31,r0,0x0 + +/* + l.movhi r3,hi(MC_BASE_ADDR) + l.ori r3,r3,MC_BA_MASK + l.addi r5,r0,0x00 + l.sw 0(r3),r5 +*/ + l.movhi r3,hi(_start) + l.ori r3,r3,lo(_start) + l.jr r3 + l.nop + + .section .text + +_start: + +.if IC | DC + /* Flush IC and/or DC */ + l.addi r10,r0,0 + l.addi r11,r0,0 + l.addi r12,r0,0 +.if IC + l.addi r11,r0,IC_SIZE +.endif +.if DC + l.addi r12,r0,DC_SIZE +.endif + l.sfleu r12,r11 + l.bf loop + l.nop + l.add r11,r0,r12 +loop: +.if IC + l.mtspr r0,r10,SPR_ICBIR +.endif +.if DC + l.mtspr r0,r10,SPR_DCBIR +.endif + l.sfne r10,r11 + l.bf loop + l.addi r10,r10,16 + + /* Enable IC and/or DC */ + l.addi r10,r0,(SPR_SR_SM) +.if IC + l.ori r10,r10,(SPR_SR_ICE) +.endif +.if DC + l.ori r10,r10,(SPR_SR_DCE) +.endif + l.mtspr r0,r10,SPR_SR + l.nop + l.nop + l.nop + l.nop + l.nop +.endif + +/* Set stack pointer */ + l.movhi r1,hi(_stack) + l.ori r1,r1,lo(_stack) + +/* Jump to main */ + l.movhi r2,hi(CLABEL(reset)) + l.ori r2,r2,lo(CLABEL(reset)) + l.jr r2 + l.nop +
release-1.0/sw/support/reset.S Property changes : Added: svn:executable ## -0,0 +1 ## +* \ No newline at end of property Index: release-1.0/sw/support/Makefile.inc =================================================================== --- release-1.0/sw/support/Makefile.inc (nonexistent) +++ release-1.0/sw/support/Makefile.inc (revision 151) @@ -0,0 +1,21 @@ +# File to be included in all makefiles + +ROOTDIR = .. + +BACKEND_DIR := $(ROOTDIR)/../backend +SUPPORT_DIR := $(ROOTDIR)/support +DRIVERS_DIR := $(ROOTDIR)/drivers +UTILS_DIR := $(ROOTDIR)/utils + +SUPPORT := $(SUPPORT_DIR)/libsupport.a +DRIVERS := $(DRIVERS_DIR)/libdrivers.a + +LINKER_SCRIPT := $(BACKEND_DIR)/orp.ld + +OR32_TOOL_PREFIX=or32-elf + +BIN2HEX = $(UTILS_DIR)/bin2hex + +ifdef UART_PRINTF +GCC_OPT += -DUART_PRINTF +endif
release-1.0/sw/support/Makefile.inc Property changes : Added: svn:executable ## -0,0 +1 ## +* \ No newline at end of property Index: release-1.0/sw/support/Makefile =================================================================== --- release-1.0/sw/support/Makefile (nonexistent) +++ release-1.0/sw/support/Makefile (revision 151) @@ -0,0 +1,135 @@ +include ../support/Makefile.inc +include $(BACKEND_DIR)/gcc-opt.mk + +#USER INPUT +SRCS = reset.S except.S tick.c support.c int.c +OR32_TARGET = +TARGET = +TARGETLIB = support +MODEL = static #dynamic|static +VERSION = 0.1 +MODE = debug #release|debug + +INCLUDEDIRS = $(BACKEND_DIR) $(DRIVERS_DIR) +#libsystemc or systemc (system ignores lib at the beginning) +LIBNAMES = +LIBDIRS = +DEPENDDIR = ./depend + + +#CONFIGURATION +DEBUGPARAM = +RELEASEPARAM = + +DEBUGFLAGS = -g -O0 +RELEASEFLAGS = -O2 -fomit-frame-pointer + +CFLAGS = -Wall +CC = or32-elf-gcc +AR = or32-elf-ar +RANLIB = or32-elf-ranlib + +CFLAGS += $(GCC_OPT) + + +#MECHANICS +INCLUDESPATH = $(addprefix -I, $(INCLUDEDIRS)) +LIBSPATH = $(addprefix -L, $(LIBDIRS)) +LIBSLINKAGE = $(addprefix -l, $(subst lib, , $(LIBNAMES)) ) +COMMA = , +RPATH = $(addprefix -Wl$(COMMA)-R, $(LIBDIRS)) + +OBJS = $(addsuffix .o, $(basename $(SRCS))) +DEPS = $(addprefix $(DEPENDDIR)/, $(addsuffix .d, $(basename $(SRCS) ) ) ) + +STATICLIB = $(addprefix lib, $(addsuffix .a, $(TARGETLIB) ) ) +DYNAMICLIB = $(addprefix lib, $(addsuffix .so, $(TARGETLIB) ) ) +SONAME = $(addsuffix .$(VERSION), $(DYNAMICLIB)) + +ifeq (debug,$(findstring debug, $(MODE))) +CFLAGS += $(DEBUGFLAGS) $(addprefix -D, $(DEBUGPARAM)) +else +CFLAGS += $(RELEASEFLAGS) $(addprefix -D, $(RELEASEPARAM)) +endif + +ifdef TARGETLIB +ifeq (dynamic,$(findstring dynamic, $(MODEL))) +TARGET = $(DYNAMICLIB) +CFLAGS += -fPIC +else +TARGET = $(STATICLIB) +endif +endif + + +#MAKEFILE RULES +all: $(TARGET) $(OR32_TARGET) + +depend: $(DEPS) + +docs: Doxyfile + doxygen + +distclean: + make clean + rm -rf $(DEPENDDIR) Doxygen + + +-include $(DEPS) + + +ifndef TARGETLIB +$(TARGET): $(OBJS) + $(CC) $(LIBSPATH) $(RPATH) -o $@ $^ $(LIBSLINKAGE) +endif + + +$(STATICLIB): $(OBJS) + $(AR) cru $@ $^ + $(RANLIB) $@ + +$(DYNAMICLIB): $(OBJS) + $(CC) -shared -Wl,-soname,$(SONAME) -o $@ $^ + ln -fs $@ $(SONAME) + + +%.o: %.c + $(CC) $(CFLAGS) $(INCLUDESPATH) -c $< -o $@ + + +$(DEPENDDIR)/%.d: %.c + mkdir -p $(DEPENDDIR) + $(CC) $(INCLUDESPATH) -MM -MF $@ $< + + +# DO NOT DELETE + +STEM = $(subst .hex, , $(OR32_TARGET)) +BINARY = $(addsuffix .bin, $(STEM) ) +EXECUTABLE = $(addsuffix .or32, $(STEM) ) + +$(OR32_TARGET): $(BINARY) + $(BIN2HEX) $? 1 -size_word > $@ + +$(BINARY): $(EXECUTABLE) + $(OR32_TOOL_PREFIX)-objcopy -O binary $? $@ + +#except.o and reset.o should be already inside of $(SUPPORT) (libsupport.a) but for some reason the compiler ignores that fact +#(e.g. or32-elf-objdump -t libsupport.a shows it) +$(EXECUTABLE): $(OBJS) ../support/except.o ../support/reset.o $(SUPPORT) $(DRIVERS) + $(CC) $(CFLAGS) $(GCC_LIB_OPTS) -T $(LINKER_SCRIPT) $^ -o $@ + +clean: + rm -f *.o *~ $(TARGET) $(STATICLIB) $(DYNAMICLIB) $(SONAME) $(OR32_TARGET) $(BINARY) $(EXECUTABLE) + +#EOF + +#SUPPORT SPECIFIC + +%.o: %.S + $(CC) $(CFLAGS) $(INCLUDESPATH) -c -o $@ $< + +reset.o: reset.S + $(CC) $(CFLAGS) $(INCLUDESPATH) -c -DIC=0 -DDC=0 -o $@ $< + +#~SUPPORT SPECIFIC Index: release-1.0/sw/support/support.c =================================================================== --- release-1.0/sw/support/support.c (nonexistent) +++ release-1.0/sw/support/support.c (revision 151) @@ -0,0 +1,124 @@ +/* Support */ + +#ifndef OR32 +#include +#endif + +#include "or1200.h" +#include "support.h" +#include "int.h" + +#ifdef UART_PRINTF +#include +#endif + +#if OR32 +void int_main(); + +void ext_except() +{ + int_main(); +} + +/* Start function, called by reset exception handler. */ +void reset () +{ + int i = main(); + or32_exit (i); +} + +/* return value by making a syscall */ +void or32_exit (int i) +{ + asm("l.add r3,r0,%0": : "r" (i)); + asm("l.nop %0": :"K" (NOP_EXIT)); + while (1); +} + +#ifdef UART_PRINTF + +static int uart_init_done = 0; + +#define PRINTFBUFFER_SIZE 512 +char PRINTFBUFFER[PRINTFBUFFER_SIZE]; // Declare a global printf buffer + +void minsoc_printf(const char *fmt, ...) +{ + // init uart if not done already + if (!uart_init_done) + { + uart_init(); + uart_init_done = 1; + } + + va_list args; + va_start(args, fmt); + + //int str_l = vsnprintf(PRINTFBUFFER, PRINTFBUFFER_SIZE, fmt, args); + int str_l = vfnprintf(PRINTFBUFFER, PRINTFBUFFER_SIZE, fmt, args); + + if (!str_l) return; // no length string - just return + + int c=0; + // now print each char via the UART + while (c < str_l) + uart_putc(PRINTFBUFFER[c++]); + + va_end(args); +} + +#else +/* activate printf support in simulator */ +void minsoc_printf(const char *fmt, ...) +{ + va_list args; + va_start(args, fmt); + __asm__ __volatile__ (" l.addi\tr3,%1,0\n \ + l.addi\tr4,%2,0\n \ + l.nop %0": :"K" (NOP_PRINTF), "r" (fmt), "r" (args)); +} + +#endif + + + + + +/* print long */ +void report(unsigned long value) +{ + asm("l.addi\tr3,%0,0": :"r" (value)); + asm("l.nop %0": :"K" (NOP_REPORT)); +} + +/* just to satisfy linker */ +void __main() +{ +} + +/* start_TIMER */ +void start_timer(int x) +{ +} + +/* For writing into SPR. */ +void mtspr(unsigned long spr, unsigned long value) +{ + asm("l.mtspr\t\t%0,%1,0": : "r" (spr), "r" (value)); +} + +/* For reading SPR. */ +unsigned long mfspr(unsigned long spr) +{ + unsigned long value; + asm("l.mfspr\t\t%0,%1,0" : "=r" (value) : "r" (spr)); + return value; +} + +#else +void report(unsigned long value) +{ + printf("report(0x%x);\n", (unsigned) value); +} + +#endif
release-1.0/sw/support/support.c Property changes : Added: svn:executable ## -0,0 +1 ## +* \ No newline at end of property Index: release-1.0/sw/support/except.S =================================================================== --- release-1.0/sw/support/except.S (nonexistent) +++ release-1.0/sw/support/except.S (revision 151) @@ -0,0 +1,152 @@ +#include "or1200.h" + +// Linked from 0x200, so subtract 0x200 from each .org +.section .vectors, "ax" + +/* + .org 0x100 + + _reset: + l.nop + l.j _reset_except + l.nop + */ + +/* This cannot be a regular function because it would waste the return register r9 of the interrupted procedure. */ +/* Furthermore, if this would be a function and l.j handler would be outside of this, the return register set here would be use upon return of this function. */ +/* However, the desired behavior is to finish the handler and let the return of the service routine simply restore the registers and return to the interrupted procedure. */ +#define intr_handler(handler) \ + l.nop ;\ +l.addi r1,r1,-244 /*free 29 words (29 x 4 = 112) + 4 because stack points to contained data (stack is r1)*/;\ +/*plus 128 bytes not to mess with the previous frame pointer (32 register x 4 bytes = 128 bytes ) (required by C++ multiple threading) */;\ +l.sw 0x18(r1),r9 /*save register r9(return addr) to stack*/;\ +l.jal store_regs /*save registers r3-r31 (except r9) to stack (r9 is changed here)*/;\ +l.nop ;\ +;\ +l.movhi r9,hi(end_except) /*set return addr to end_except instruction*/;\ +l.ori r9,r9,lo(end_except)/*set return addr to end_except instruction*/;\ +l.j CLABEL(handler) ;\ +l.nop + +.org 0x000 +_except_200: +intr_handler(buserr_except) + + .org 0x100 + _except_300: +intr_handler(dpf_except) + + .org 0x200 + _except_400: +intr_handler(ipf_except) + + .org 0x300 + _except_500: +intr_handler(tick_except) + + .org 0x400 + _except_600: +intr_handler(align_except) + + .org 0x500 + _except_700: +intr_handler(illegal_except) + + .org 0x600 + _except_800: +intr_handler(ext_except) + + .org 0x700 + _except_900: +intr_handler(dtlbmiss_except) + + .org 0x800 + _except_a00: +intr_handler(itlbmiss_except) + + .org 0x900 + _except_b00: +intr_handler(range_except) + + .org 0xa00 + _except_c00: +intr_handler(syscall_except) + + .org 0xb00 + _except_d00: +intr_handler(res1_except) + + .org 0xc00 + _except_e00: +intr_handler(trap_except) + + .org 0xd00 + _except_f00: +intr_handler(res2_except) + + store_regs: //save registers r3-r31 (except r9) to stack + l.sw 0x00(r1),r3 + l.sw 0x04(r1),r4 + l.sw 0x08(r1),r5 + l.sw 0x0c(r1),r6 + l.sw 0x10(r1),r7 + l.sw 0x14(r1),r8 + l.sw 0x1c(r1),r10 + l.sw 0x20(r1),r11 + l.sw 0x24(r1),r12 + l.sw 0x28(r1),r13 + l.sw 0x2c(r1),r14 + l.sw 0x30(r1),r15 + l.sw 0x34(r1),r16 + l.sw 0x38(r1),r17 + l.sw 0x3c(r1),r18 + l.sw 0x40(r1),r19 + l.sw 0x44(r1),r20 + l.sw 0x48(r1),r21 + l.sw 0x4c(r1),r22 + l.sw 0x50(r1),r23 + l.sw 0x54(r1),r24 + l.sw 0x58(r1),r25 + l.sw 0x5c(r1),r26 + l.sw 0x60(r1),r27 + l.sw 0x64(r1),r28 + l.sw 0x68(r1),r29 + l.sw 0x6c(r1),r30 + l.sw 0x70(r1),r31 + l.jr r9 + l.nop + + end_except: //load back registers from stack r3-r31 + l.lwz r3,0x00(r1) + l.lwz r4,0x04(r1) + l.lwz r5,0x08(r1) + l.lwz r6,0x0c(r1) + l.lwz r7,0x10(r1) + l.lwz r8,0x14(r1) + l.lwz r9,0x18(r1) + l.lwz r10,0x1c(r1) + l.lwz r11,0x20(r1) + l.lwz r12,0x24(r1) + l.lwz r13,0x28(r1) + l.lwz r14,0x2c(r1) + l.lwz r15,0x30(r1) + l.lwz r16,0x34(r1) + l.lwz r17,0x38(r1) + l.lwz r18,0x3c(r1) + l.lwz r19,0x40(r1) + l.lwz r20,0x44(r1) + l.lwz r21,0x48(r1) + l.lwz r22,0x4c(r1) + l.lwz r23,0x50(r1) + l.lwz r24,0x54(r1) + l.lwz r25,0x58(r1) + l.lwz r26,0x5c(r1) + l.lwz r27,0x60(r1) + l.lwz r28,0x64(r1) + l.lwz r29,0x68(r1) + l.lwz r30,0x6c(r1) +l.lwz r31,0x70(r1) + l.addi r1,r1,244 //free stack places + l.rfe //recover SR register and prior PC (jumps back to program) + l.nop +
release-1.0/sw/support/except.S Property changes : Added: svn:executable ## -0,0 +1 ## +* \ No newline at end of property Index: release-1.0/sw/support/or1200.h =================================================================== --- release-1.0/sw/support/or1200.h (nonexistent) +++ release-1.0/sw/support/or1200.h (revision 151) @@ -0,0 +1,454 @@ +/* or1200.h -- Defines OR1K architecture specific special-purpose registers + Copyright (C) 1999 Damjan Lampret, lampret@opencores.org + + This file is part of OpenRISC 1000 Architectural Simulator. + + This program is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 2 of the License, or + (at your option) any later version. + + This program is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program; if not, write to the Free Software + Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. */ + +/* This file is also used by microkernel test bench. Among + others it is also used in assembly file(s). */ + +#define __CLABEL(prefix, label) prefix ## label +#define _CLABEL(prefix, label) __CLABEL(prefix, label) +#define CLABEL(label) _CLABEL(__USER_LABEL_PREFIX__, label) + +/* Definition of special-purpose registers (SPRs) */ + +#define MAX_GRPS (32) +#define MAX_SPRS_PER_GRP_BITS (11) +#define MAX_SPRS_PER_GRP (1 << MAX_SPRS_PER_GRP_BITS) +#define MAX_SPRS (0x10000) + +/* Base addresses for the groups */ +#define SPRGROUP_SYS (0<< MAX_SPRS_PER_GRP_BITS) +#define SPRGROUP_DMMU (1<< MAX_SPRS_PER_GRP_BITS) +#define SPRGROUP_IMMU (2<< MAX_SPRS_PER_GRP_BITS) +#define SPRGROUP_DC (3<< MAX_SPRS_PER_GRP_BITS) +#define SPRGROUP_IC (4<< MAX_SPRS_PER_GRP_BITS) +#define SPRGROUP_MAC (5<< MAX_SPRS_PER_GRP_BITS) +#define SPRGROUP_D (6<< MAX_SPRS_PER_GRP_BITS) +#define SPRGROUP_PC (7<< MAX_SPRS_PER_GRP_BITS) +#define SPRGROUP_PM (8<< MAX_SPRS_PER_GRP_BITS) +#define SPRGROUP_PIC (9<< MAX_SPRS_PER_GRP_BITS) +#define SPRGROUP_TT (10<< MAX_SPRS_PER_GRP_BITS) + +/* System control and status group */ +#define SPR_VR (SPRGROUP_SYS + 0) +#define SPR_UPR (SPRGROUP_SYS + 1) +#define SPR_CPUCFGR (SPRGROUP_SYS + 2) +#define SPR_DMMUCFGR (SPRGROUP_SYS + 3) +#define SPR_IMMUCFGR (SPRGROUP_SYS + 4) +#define SPR_DCCFGR (SPRGROUP_SYS + 5) +#define SPR_ICCFGR (SPRGROUP_SYS + 6) +#define SPR_DCFGR (SPRGROUP_SYS + 7) +#define SPR_PCCFGR (SPRGROUP_SYS + 8) +#define SPR_NPC (SPRGROUP_SYS + 16) /* CZ 21/06/01 */ +#define SPR_SR (SPRGROUP_SYS + 17) /* CZ 21/06/01 */ +#define SPR_PPC (SPRGROUP_SYS + 18) /* CZ 21/06/01 */ +#define SPR_EPCR_BASE (SPRGROUP_SYS + 32) /* CZ 21/06/01 */ +#define SPR_EPCR_LAST (SPRGROUP_SYS + 47) /* CZ 21/06/01 */ +#define SPR_EEAR_BASE (SPRGROUP_SYS + 48) +#define SPR_EEAR_LAST (SPRGROUP_SYS + 63) +#define SPR_ESR_BASE (SPRGROUP_SYS + 64) +#define SPR_ESR_LAST (SPRGROUP_SYS + 79) + +#if 0 +/* Data MMU group */ +#define SPR_DMMUCR (SPRGROUP_DMMU + 0) +#define SPR_DTLBMR_BASE(WAY) (SPRGROUP_DMMU + 0x200 + (WAY) * 0x200) +#define SPR_DTLBMR_LAST(WAY) (SPRGROUP_DMMU + 0x2ff + (WAY) * 0x200) +#define SPR_DTLBTR_BASE(WAY) (SPRGROUP_DMMU + 0x300 + (WAY) * 0x200) +#define SPR_DTLBTR_LAST(WAY) (SPRGROUP_DMMU + 0x3ff + (WAY) * 0x200) + +/* Instruction MMU group */ +#define SPR_IMMUCR (SPRGROUP_IMMU + 0) +#define SPR_ITLBMR_BASE(WAY) (SPRGROUP_IMMU + 0x200 + (WAY) * 0x200) +#define SPR_ITLBMR_LAST(WAY) (SPRGROUP_IMMU + 0x2ff + (WAY) * 0x200) +#define SPR_ITLBTR_BASE(WAY) (SPRGROUP_IMMU + 0x300 + (WAY) * 0x200) +#define SPR_ITLBTR_LAST(WAY) (SPRGROUP_IMMU + 0x3ff + (WAY) * 0x200) +#else + +/* Data MMU group */ +#define SPR_DMMUCR (SPRGROUP_DMMU + 0) +#define SPR_DTLBMR_BASE(WAY) (SPRGROUP_DMMU + 0x200 + (WAY) * 0x100) +#define SPR_DTLBMR_LAST(WAY) (SPRGROUP_DMMU + 0x27f + (WAY) * 0x100) +#define SPR_DTLBTR_BASE(WAY) (SPRGROUP_DMMU + 0x280 + (WAY) * 0x100) +#define SPR_DTLBTR_LAST(WAY) (SPRGROUP_DMMU + 0x2ff + (WAY) * 0x100) + +/* Instruction MMU group */ +#define SPR_IMMUCR (SPRGROUP_IMMU + 0) +#define SPR_ITLBMR_BASE(WAY) (SPRGROUP_IMMU + 0x200 + (WAY) * 0x100) +#define SPR_ITLBMR_LAST(WAY) (SPRGROUP_IMMU + 0x27f + (WAY) * 0x100) +#define SPR_ITLBTR_BASE(WAY) (SPRGROUP_IMMU + 0x280 + (WAY) * 0x100) +#define SPR_ITLBTR_LAST(WAY) (SPRGROUP_IMMU + 0x2ff + (WAY) * 0x100) +#endif +/* Data cache group */ +#define SPR_DCCR (SPRGROUP_DC + 0) +#define SPR_DCBPR (SPRGROUP_DC + 1) +#define SPR_DCBFR (SPRGROUP_DC + 2) +#define SPR_DCBIR (SPRGROUP_DC + 3) +#define SPR_DCBWR (SPRGROUP_DC + 4) +#define SPR_DCBLR (SPRGROUP_DC + 5) +#define SPR_DCR_BASE(WAY) (SPRGROUP_DC + 0x200 + (WAY) * 0x200) +#define SPR_DCR_LAST(WAY) (SPRGROUP_DC + 0x3ff + (WAY) * 0x200) + +/* Instruction cache group */ +#define SPR_ICCR (SPRGROUP_IC + 0) +#define SPR_ICBPR (SPRGROUP_IC + 1) +#define SPR_ICBIR (SPRGROUP_IC + 2) +#define SPR_ICBLR (SPRGROUP_IC + 3) +#define SPR_ICR_BASE(WAY) (SPRGROUP_IC + 0x200 + (WAY) * 0x200) +#define SPR_ICR_LAST(WAY) (SPRGROUP_IC + 0x3ff + (WAY) * 0x200) + +/* MAC group */ +#define SPR_MACLO (SPRGROUP_MAC + 1) +#define SPR_MACHI (SPRGROUP_MAC + 2) + +/* Debug group */ +#define SPR_DVR(N) (SPRGROUP_D + (N)) +#define SPR_DCR(N) (SPRGROUP_D + 8 + (N)) +#define SPR_DMR1 (SPRGROUP_D + 16) +#define SPR_DMR2 (SPRGROUP_D + 17) +#define SPR_DWCR0 (SPRGROUP_D + 18) +#define SPR_DWCR1 (SPRGROUP_D + 19) +#define SPR_DSR (SPRGROUP_D + 20) +#define SPR_DRR (SPRGROUP_D + 21) + +/* Performance counters group */ +#define SPR_PCCR(N) (SPRGROUP_PC + (N)) +#define SPR_PCMR(N) (SPRGROUP_PC + 8 + (N)) + +/* Power management group */ +#define SPR_PMR (SPRGROUP_PM + 0) + +/* PIC group */ +#define SPR_PICMR (SPRGROUP_PIC + 0) +#define SPR_PICPR (SPRGROUP_PIC + 1) +#define SPR_PICSR (SPRGROUP_PIC + 2) + +/* Tick Timer group */ +#define SPR_TTMR (SPRGROUP_TT + 0) +#define SPR_TTCR (SPRGROUP_TT + 1) + +/* + * Bit definitions for the Version Register + * + */ +#define SPR_VR_VER 0xffff0000 /* Processor version */ +#define SPR_VR_REV 0x0000003f /* Processor revision */ + +/* + * Bit definitions for the Unit Present Register + * + */ +#define SPR_UPR_UP 0x00000001 /* UPR present */ +#define SPR_UPR_DCP 0x00000002 /* Data cache present */ +#define SPR_UPR_ICP 0x00000004 /* Instruction cache present */ +#define SPR_UPR_DMP 0x00000008 /* Data MMU present */ +#define SPR_UPR_IMP 0x00000010 /* Instruction MMU present */ +#define SPR_UPR_OB32P 0x00000020 /* ORBIS32 present */ +#define SPR_UPR_OB64P 0x00000040 /* ORBIS64 present */ +#define SPR_UPR_OF32P 0x00000080 /* ORFPX32 present */ +#define SPR_UPR_OF64P 0x00000100 /* ORFPX64 present */ +#define SPR_UPR_OV32P 0x00000200 /* ORVDX32 present */ +#define SPR_UPR_OV64P 0x00000400 /* ORVDX64 present */ +#define SPR_UPR_DUP 0x00000800 /* Debug unit present */ +#define SPR_UPR_PCUP 0x00001000 /* Performance counters unit present */ +#define SPR_UPR_PMP 0x00002000 /* Power management present */ +#define SPR_UPR_PICP 0x00004000 /* PIC present */ +#define SPR_UPR_TTP 0x00008000 /* Tick timer present */ +#define SPR_UPR_SRP 0x00010000 /* Shadow registers present */ +#define SPR_UPR_RES 0x00fe0000 /* ORVDX32 present */ +#define SPR_UPR_CUST 0xff000000 /* Custom units */ + +/* + * Bit definitions for the Supervision Register + * + */ +#define SPR_SR_CID 0xf0000000 /* Context ID */ +#define SPR_SR_FO 0x00008000 /* Fixed one */ +#define SPR_SR_EPH 0x00004000 /* Exception Prefixi High */ +#define SPR_SR_DSX 0x00002000 /* Delay Slot Exception */ +#define SPR_SR_OVE 0x00001000 /* Overflow flag Exception */ +#define SPR_SR_OV 0x00000800 /* Overflow flag */ +#define SPR_SR_CY 0x00000400 /* Carry flag */ +#define SPR_SR_F 0x00000200 /* Condition Flag */ +#define SPR_SR_CE 0x00000100 /* CID Enable */ +#define SPR_SR_LEE 0x00000080 /* Little Endian Enable */ +#define SPR_SR_IME 0x00000040 /* Instruction MMU Enable */ +#define SPR_SR_DME 0x00000020 /* Data MMU Enable */ +#define SPR_SR_ICE 0x00000010 /* Instruction Cache Enable */ +#define SPR_SR_DCE 0x00000008 /* Data Cache Enable */ +#define SPR_SR_IEE 0x00000004 /* Interrupt Exception Enable */ +#define SPR_SR_TEE 0x00000002 /* Tick timer Exception Enable */ +#define SPR_SR_SM 0x00000001 /* Supervisor Mode */ + +/* + * Bit definitions for the Data MMU Control Register + * + */ +#define SPR_DMMUCR_P2S 0x0000003e /* Level 2 Page Size */ +#define SPR_DMMUCR_P1S 0x000007c0 /* Level 1 Page Size */ +#define SPR_DMMUCR_VADDR_WIDTH 0x0000f800 /* Virtual ADDR Width */ +#define SPR_DMMUCR_PADDR_WIDTH 0x000f0000 /* Physical ADDR Width */ + +/* + * Bit definitions for the Instruction MMU Control Register + * + */ +#define SPR_IMMUCR_P2S 0x0000003e /* Level 2 Page Size */ +#define SPR_IMMUCR_P1S 0x000007c0 /* Level 1 Page Size */ +#define SPR_IMMUCR_VADDR_WIDTH 0x0000f800 /* Virtual ADDR Width */ +#define SPR_IMMUCR_PADDR_WIDTH 0x000f0000 /* Physical ADDR Width */ + +/* + * Bit definitions for the Data TLB Match Register + * + */ +#define SPR_DTLBMR_V 0x00000001 /* Valid */ +#define SPR_DTLBMR_PL1 0x00000002 /* Page Level 1 (if 0 then PL2) */ +#define SPR_DTLBMR_CID 0x0000003c /* Context ID */ +#define SPR_DTLBMR_LRU 0x000000c0 /* Least Recently Used */ +#define SPR_DTLBMR_VPN 0xfffff000 /* Virtual Page Number */ + +/* + * Bit definitions for the Data TLB Translate Register + * + */ +#define SPR_DTLBTR_CC 0x00000001 /* Cache Coherency */ +#define SPR_DTLBTR_CI 0x00000002 /* Cache Inhibit */ +#define SPR_DTLBTR_WBC 0x00000004 /* Write-Back Cache */ +#define SPR_DTLBTR_WOM 0x00000008 /* Weakly-Ordered Memory */ +#define SPR_DTLBTR_A 0x00000010 /* Accessed */ +#define SPR_DTLBTR_D 0x00000020 /* Dirty */ +#define SPR_DTLBTR_URE 0x00000040 /* User Read Enable */ +#define SPR_DTLBTR_UWE 0x00000080 /* User Write Enable */ +#define SPR_DTLBTR_SRE 0x00000100 /* Supervisor Read Enable */ +#define SPR_DTLBTR_SWE 0x00000200 /* Supervisor Write Enable */ +#define SPR_DTLBTR_PPN 0xfffff000 /* Physical Page Number */ +#define DTLB_PR_NOLIMIT (SPR_DTLBTR_URE | \ + SPR_DTLBTR_UWE | \ + SPR_DTLBTR_SRE | \ + SPR_DTLBTR_SWE ) +/* + * Bit definitions for the Instruction TLB Match Register + * + */ +#define SPR_ITLBMR_V 0x00000001 /* Valid */ +#define SPR_ITLBMR_PL1 0x00000002 /* Page Level 1 (if 0 then PL2) */ +#define SPR_ITLBMR_CID 0x0000003c /* Context ID */ +#define SPR_ITLBMR_LRU 0x000000c0 /* Least Recently Used */ +#define SPR_ITLBMR_VPN 0xfffff000 /* Virtual Page Number */ + +/* + * Bit definitions for the Instruction TLB Translate Register + * + */ +#define SPR_ITLBTR_CC 0x00000001 /* Cache Coherency */ +#define SPR_ITLBTR_CI 0x00000002 /* Cache Inhibit */ +#define SPR_ITLBTR_WBC 0x00000004 /* Write-Back Cache */ +#define SPR_ITLBTR_WOM 0x00000008 /* Weakly-Ordered Memory */ +#define SPR_ITLBTR_A 0x00000010 /* Accessed */ +#define SPR_ITLBTR_D 0x00000020 /* Dirty */ +#define SPR_ITLBTR_SXE 0x00000040 /* User Read Enable */ +#define SPR_ITLBTR_UXE 0x00000080 /* User Write Enable */ +#define SPR_ITLBTR_PPN 0xfffff000 /* Physical Page Number */ +#define ITLB_PR_NOLIMIT (SPR_ITLBTR_SXE | \ + SPR_ITLBTR_UXE ) + + +/* + * Bit definitions for Data Cache Control register + * + */ +#define SPR_DCCR_EW 0x000000ff /* Enable ways */ + +/* + * Bit definitions for Insn Cache Control register + * + */ +#define SPR_ICCR_EW 0x000000ff /* Enable ways */ + +/* + * Bit definitions for Debug Control registers + * + */ +#define SPR_DCR_DP 0x00000001 /* DVR/DCR present */ +#define SPR_DCR_CC 0x0000000e /* Compare condition */ +#define SPR_DCR_SC 0x00000010 /* Signed compare */ +#define SPR_DCR_CT 0x000000e0 /* Compare to */ + +/* Bit results with SPR_DCR_CC mask */ +#define SPR_DCR_CC_MASKED 0x00000000 +#define SPR_DCR_CC_EQUAL 0x00000001 +#define SPR_DCR_CC_LESS 0x00000002 +#define SPR_DCR_CC_LESSE 0x00000003 +#define SPR_DCR_CC_GREAT 0x00000004 +#define SPR_DCR_CC_GREATE 0x00000005 +#define SPR_DCR_CC_NEQUAL 0x00000006 + +/* Bit results with SPR_DCR_CT mask */ +#define SPR_DCR_CT_DISABLED 0x00000000 +#define SPR_DCR_CT_IFEA 0x00000020 +#define SPR_DCR_CT_LEA 0x00000040 +#define SPR_DCR_CT_SEA 0x00000060 +#define SPR_DCR_CT_LD 0x00000080 +#define SPR_DCR_CT_SD 0x000000a0 +#define SPR_DCR_CT_LSEA 0x000000c0 + +/* + * Bit definitions for Debug Mode 1 register + * + */ +#define SPR_DMR1_CW0 0x00000003 /* Chain watchpoint 0 */ +#define SPR_DMR1_CW1 0x0000000c /* Chain watchpoint 1 */ +#define SPR_DMR1_CW2 0x00000030 /* Chain watchpoint 2 */ +#define SPR_DMR1_CW3 0x000000c0 /* Chain watchpoint 3 */ +#define SPR_DMR1_CW4 0x00000300 /* Chain watchpoint 4 */ +#define SPR_DMR1_CW5 0x00000c00 /* Chain watchpoint 5 */ +#define SPR_DMR1_CW6 0x00003000 /* Chain watchpoint 6 */ +#define SPR_DMR1_CW7 0x0000c000 /* Chain watchpoint 7 */ +#define SPR_DMR1_CW8 0x00030000 /* Chain watchpoint 8 */ +#define SPR_DMR1_CW9 0x000c0000 /* Chain watchpoint 9 */ +#define SPR_DMR1_CW10 0x00300000 /* Chain watchpoint 10 */ +#define SPR_DMR1_ST 0x00400000 /* Single-step trace*/ +#define SPR_DMR1_BT 0x00800000 /* Branch trace */ +#define SPR_DMR1_DXFW 0x01000000 /* Disable external force watchpoint */ + +/* + * Bit definitions for Debug Mode 2 register + * + */ +#define SPR_DMR2_WCE0 0x00000001 /* Watchpoint counter 0 enable */ +#define SPR_DMR2_WCE1 0x00000002 /* Watchpoint counter 0 enable */ +#define SPR_DMR2_AWTC 0x00001ffc /* Assign watchpoints to counters */ +#define SPR_DMR2_WGB 0x00ffe000 /* Watchpoints generating breakpoint */ + +/* + * Bit definitions for Debug watchpoint counter registers + * + */ +#define SPR_DWCR_COUNT 0x0000ffff /* Count */ +#define SPR_DWCR_MATCH 0xffff0000 /* Match */ + +/* + * Bit definitions for Debug stop register + * + */ +#define SPR_DSR_RSTE 0x00000001 /* Reset exception */ +#define SPR_DSR_BUSEE 0x00000002 /* Bus error exception */ +#define SPR_DSR_DPFE 0x00000004 /* Data Page Fault exception */ +#define SPR_DSR_IPFE 0x00000008 /* Insn Page Fault exception */ +#define SPR_DSR_TTE 0x00000010 /* iTick Timer exception */ +#define SPR_DSR_AE 0x00000020 /* Alignment exception */ +#define SPR_DSR_IIE 0x00000040 /* Illegal Instruction exception */ +#define SPR_DSR_IE 0x00000080 /* Interrupt exception */ +#define SPR_DSR_DME 0x00000100 /* DTLB miss exception */ +#define SPR_DSR_IME 0x00000200 /* ITLB miss exception */ +#define SPR_DSR_RE 0x00000400 /* Range exception */ +#define SPR_DSR_SCE 0x00000800 /* System call exception */ +#define SPR_DSR_SSE 0x00001000 /* Single Step Exception */ +#define SPR_DSR_TE 0x00002000 /* Trap exception */ + +/* + * Bit definitions for Debug reason register + * + */ +#define SPR_DRR_RSTE 0x00000001 /* Reset exception */ +#define SPR_DRR_BUSEE 0x00000002 /* Bus error exception */ +#define SPR_DRR_DPFE 0x00000004 /* Data Page Fault exception */ +#define SPR_DRR_IPFE 0x00000008 /* Insn Page Fault exception */ +#define SPR_DRR_TTE 0x00000010 /* Tick Timer exception */ +#define SPR_DRR_AE 0x00000020 /* Alignment exception */ +#define SPR_DRR_IIE 0x00000040 /* Illegal Instruction exception */ +#define SPR_DRR_IE 0x00000080 /* Interrupt exception */ +#define SPR_DRR_DME 0x00000100 /* DTLB miss exception */ +#define SPR_DRR_IME 0x00000200 /* ITLB miss exception */ +#define SPR_DRR_RE 0x00000400 /* Range exception */ +#define SPR_DRR_SCE 0x00000800 /* System call exception */ +#define SPR_DRR_TE 0x00001000 /* Trap exception */ + +/* + * Bit definitions for Performance counters mode registers + * + */ +#define SPR_PCMR_CP 0x00000001 /* Counter present */ +#define SPR_PCMR_UMRA 0x00000002 /* User mode read access */ +#define SPR_PCMR_CISM 0x00000004 /* Count in supervisor mode */ +#define SPR_PCMR_CIUM 0x00000008 /* Count in user mode */ +#define SPR_PCMR_LA 0x00000010 /* Load access event */ +#define SPR_PCMR_SA 0x00000020 /* Store access event */ +#define SPR_PCMR_IF 0x00000040 /* Instruction fetch event*/ +#define SPR_PCMR_DCM 0x00000080 /* Data cache miss event */ +#define SPR_PCMR_ICM 0x00000100 /* Insn cache miss event */ +#define SPR_PCMR_IFS 0x00000200 /* Insn fetch stall event */ +#define SPR_PCMR_LSUS 0x00000400 /* LSU stall event */ +#define SPR_PCMR_BS 0x00000800 /* Branch stall event */ +#define SPR_PCMR_DTLBM 0x00001000 /* DTLB miss event */ +#define SPR_PCMR_ITLBM 0x00002000 /* ITLB miss event */ +#define SPR_PCMR_DDS 0x00004000 /* Data dependency stall event */ +#define SPR_PCMR_WPE 0x03ff8000 /* Watchpoint events */ + +/* + * Bit definitions for the Power management register + * + */ +#define SPR_PMR_SDF 0x0000000f /* Slow down factor */ +#define SPR_PMR_DME 0x00000010 /* Doze mode enable */ +#define SPR_PMR_SME 0x00000020 /* Sleep mode enable */ +#define SPR_PMR_DCGE 0x00000040 /* Dynamic clock gating enable */ +#define SPR_PMR_SUME 0x00000080 /* Suspend mode enable */ + +/* + * Bit definitions for PICMR + * + */ +#define SPR_PICMR_IUM 0xfffffffc /* Interrupt unmask */ + +/* + * Bit definitions for PICPR + * + */ +#define SPR_PICPR_IPRIO 0xfffffffc /* Interrupt priority */ + +/* + * Bit definitions for PICSR + * + */ +#define SPR_PICSR_IS 0xffffffff /* Interrupt status */ + +/* + * Bit definitions for Tick Timer Control Register + * + */ +#define SPR_TTCR_PERIOD 0x0fffffff /* Time Period */ +#define SPR_TTMR_PERIOD SPR_TTCR_PERIOD +#define SPR_TTMR_IP 0x10000000 /* Interrupt Pending */ +#define SPR_TTMR_IE 0x20000000 /* Interrupt Enable */ +#define SPR_TTMR_RT 0x40000000 /* Restart tick */ +#define SPR_TTMR_SR 0x80000000 /* Single run */ +#define SPR_TTMR_CR 0xc0000000 /* Continuous run */ +#define SPR_TTMR_M 0xc0000000 /* Tick mode */ + +/* + * l.nop constants + * + */ +#define NOP_NOP 0x0000 /* Normal nop instruction */ +#define NOP_EXIT 0x0001 /* End of simulation */ +#define NOP_REPORT 0x0002 /* Simple report */ +#define NOP_PRINTF 0x0003 /* Simprintf instruction */ +#define NOP_REPORT_FIRST 0x0400 /* Report with number */ +#define NOP_REPORT_LAST 0x03ff /* Report with number */ Index: release-1.0/sw/support/tick.c =================================================================== --- release-1.0/sw/support/tick.c (nonexistent) +++ release-1.0/sw/support/tick.c (revision 151) @@ -0,0 +1,30 @@ +#include "or1200.h" +#include "support.h" +#include "tick.h" + +int tick_int; + +void tick_ack(void) +{ + tick_int--; +} + +void tick_init(void) +{ + mtspr(SPR_TTMR, 25000000 & SPR_TTMR_PERIOD); //1s + //mtspr(SPR_TTMR, 125000 & SPR_TTMR_PERIOD); //5ms + + mtspr(SPR_TTMR, mfspr(SPR_TTMR) | SPR_TTMR_RT | SPR_TTMR_IE); //restart after match, enable interrupt + mtspr(SPR_TTMR, mfspr(SPR_TTMR) & ~(SPR_TTMR_IP)); //clears interrupt + + //set OR1200 to accept exceptions + mtspr(SPR_SR, mfspr(SPR_SR) | SPR_SR_TEE); + + tick_int = 0; +} + +void tick_except(void) +{ + tick_int++; + mtspr(SPR_TTMR, mfspr(SPR_TTMR) & ~(SPR_TTMR_IP)); //clears interrupt +} Index: release-1.0/sw/support/support.h =================================================================== --- release-1.0/sw/support/support.h (nonexistent) +++ release-1.0/sw/support/support.h (revision 151) @@ -0,0 +1,33 @@ +/* Support file for or32 tests. This file should is included + in each test. It calls main() function and add support for + basic functions */ + +#ifndef SUPPORT_H +#define SUPPORT_H + +#include +#include +#include + +/* Register access macros */ +#define REG8(add) *((volatile unsigned char *)(add)) +#define REG16(add) *((volatile unsigned short *)(add)) +#define REG32(add) *((volatile unsigned long *)(add)) + +/* For writing into SPR. */ +void mtspr(unsigned long spr, unsigned long value); + +/* For reading SPR. */ +unsigned long mfspr(unsigned long spr); + +/* Function to be called at entry point - not defined here. */ +int main (); + +/* Prints out a value */ +void report(unsigned long value); + +/* return value by making a syscall */ +extern void or32_exit (int i) __attribute__ ((__noreturn__)); + + +#endif /* SUPPORT_H */
release-1.0/sw/support/support.h Property changes : Added: svn:executable ## -0,0 +1 ## +* \ No newline at end of property Index: release-1.0/sw/support/int.c =================================================================== --- release-1.0/sw/support/int.c (nonexistent) +++ release-1.0/sw/support/int.c (revision 151) @@ -0,0 +1,79 @@ +/* This file is part of test microkernel for OpenRISC 1000. */ +/* (C) 2001 Simon Srot, srot@opencores.org */ + +#include "support.h" +#include "or1200.h" +#include "int.h" + +/* Interrupt handlers table */ +struct ihnd int_handlers[MAX_INT_HANDLERS]; + +/* Initialize routine */ +int int_init() +{ + int i; + + for(i = 0; i < MAX_INT_HANDLERS; i++) { + int_handlers[i].handler = 0; + int_handlers[i].arg = 0; + } + mtspr(SPR_PICMR, 0x00000000); + + //set OR1200 to accept exceptions + mtspr(SPR_SR, mfspr(SPR_SR) | SPR_SR_IEE); + + return 0; +} + +/* Add interrupt handler */ +int int_add(unsigned long vect, void (* handler)(void *), void *arg) +{ + if(vect >= MAX_INT_HANDLERS) + return -1; + + int_handlers[vect].handler = handler; + int_handlers[vect].arg = arg; + + mtspr(SPR_PICMR, mfspr(SPR_PICMR) | (0x00000001L << vect)); + + return 0; +} + +/* Disable interrupt */ +int int_disable(unsigned long vect) +{ + if(vect >= MAX_INT_HANDLERS) + return -1; + + mtspr(SPR_PICMR, mfspr(SPR_PICMR) & ~(0x00000001L << vect)); + + return 0; +} + +/* Enable interrupt */ +int int_enable(unsigned long vect) +{ + if(vect >= MAX_INT_HANDLERS) + return -1; + + mtspr(SPR_PICMR, mfspr(SPR_PICMR) | (0x00000001L << vect)); + + return 0; +} + +/* Main interrupt handler */ +void int_main() +{ + unsigned long picsr = mfspr(SPR_PICSR); //process only the interrupts asserted at signal catch, ignore all during process + unsigned long i = 0; + + while(i < 32) { + if((picsr & (0x01L << i)) && (int_handlers[i].handler != 0)) { + (*int_handlers[i].handler)(int_handlers[i].arg); + } + i++; + } + + mtspr(SPR_PICSR, 0); //clear interrupt status: all modules have level interrupts, which have to be cleared by software, +} //thus this is safe, since non processed interrupts will get re-asserted soon enough +
release-1.0/sw/support/int.c Property changes : Added: svn:executable ## -0,0 +1 ## +* \ No newline at end of property Index: release-1.0/sw/support/int.h =================================================================== --- release-1.0/sw/support/int.h (nonexistent) +++ release-1.0/sw/support/int.h (revision 151) @@ -0,0 +1,14 @@ +/* Number of interrupt handlers */ +#define MAX_INT_HANDLERS 32 + +/* Handler entry */ +struct ihnd { + void (*handler)(void *); + void *arg; +}; + +/* Add interrupt handler */ +int int_add(unsigned long vect, void (* handler)(void *), void *arg); + +/* Initialize routine */ +int int_init();
release-1.0/sw/support/int.h Property changes : Added: svn:executable ## -0,0 +1 ## +* \ No newline at end of property Index: release-1.0/sw/support/tick.h =================================================================== --- release-1.0/sw/support/tick.h (nonexistent) +++ release-1.0/sw/support/tick.h (revision 151) @@ -0,0 +1,2 @@ +void tick_init(void); +void tick_ack(void); Index: release-1.0/prj/src/minsoc_bench.prj =================================================================== --- release-1.0/prj/src/minsoc_bench.prj (nonexistent) +++ release-1.0/prj/src/minsoc_bench.prj (revision 151) @@ -0,0 +1,8 @@ +PROJECT_DIR=(backend bench/verilog bench/verilog/vpi bench/verilog/sim_lib rtl/verilog) +PROJECT_SRC=(minsoc_bench_defines.v +minsoc_bench.v +minsoc_memory_model.v +dbg_comm_vpi.v +fpga_memory_primitives.v +timescale.v) + Index: release-1.0/prj/src/ethmac.prj =================================================================== --- release-1.0/prj/src/ethmac.prj (nonexistent) +++ release-1.0/prj/src/ethmac.prj (revision 151) @@ -0,0 +1,27 @@ +PROJECT_DIR=rtl/verilog/ethmac/rtl/verilog +PROJECT_SRC=(eth_cop.v +eth_registers.v +eth_rxethmac.v +eth_miim.v +ethmac.v +eth_rxaddrcheck.v +eth_outputcontrol.v +eth_rxstatem.v +eth_txethmac.v +eth_wishbone.v +eth_maccontrol.v +eth_txstatem.v +ethmac_defines.v +eth_spram_256x32.v +eth_shiftreg.v +eth_clockgen.v +eth_crc.v +eth_rxcounters.v +eth_macstatus.v +eth_random.v +eth_register.v +eth_fifo.v +eth_receivecontrol.v +eth_transmitcontrol.v +eth_txcounters.v +xilinx_dist_ram_16x32.v) Index: release-1.0/prj/src/blackboxes/or1200_top.v =================================================================== --- release-1.0/prj/src/blackboxes/or1200_top.v (nonexistent) +++ release-1.0/prj/src/blackboxes/or1200_top.v (revision 151) @@ -0,0 +1,145 @@ + + +`include "or1200_defines.v" + +module or1200_top( + // System + clk_i, rst_i, pic_ints_i, clmode_i, + + // Instruction WISHBONE INTERFACE + iwb_clk_i, iwb_rst_i, iwb_ack_i, iwb_err_i, iwb_rty_i, iwb_dat_i, + iwb_cyc_o, iwb_adr_o, iwb_stb_o, iwb_we_o, iwb_sel_o, iwb_dat_o, +`ifdef OR1200_WB_CAB + iwb_cab_o, +`endif +`ifdef OR1200_WB_B3 + iwb_cti_o, iwb_bte_o, +`endif + // Data WISHBONE INTERFACE + dwb_clk_i, dwb_rst_i, dwb_ack_i, dwb_err_i, dwb_rty_i, dwb_dat_i, + dwb_cyc_o, dwb_adr_o, dwb_stb_o, dwb_we_o, dwb_sel_o, dwb_dat_o, +`ifdef OR1200_WB_CAB + dwb_cab_o, +`endif +`ifdef OR1200_WB_B3 + dwb_cti_o, dwb_bte_o, +`endif + + // External Debug Interface + dbg_stall_i, dbg_ewt_i, dbg_lss_o, dbg_is_o, dbg_wp_o, dbg_bp_o, + dbg_stb_i, dbg_we_i, dbg_adr_i, dbg_dat_i, dbg_dat_o, dbg_ack_o, + +`ifdef OR1200_BIST + // RAM BIST + mbist_si_i, mbist_so_o, mbist_ctrl_i, +`endif + // Power Management + pm_cpustall_i, + pm_clksd_o, pm_dc_gate_o, pm_ic_gate_o, pm_dmmu_gate_o, + pm_immu_gate_o, pm_tt_gate_o, pm_cpu_gate_o, pm_wakeup_o, pm_lvolt_o + +); + +parameter dw = `OR1200_OPERAND_WIDTH; +parameter aw = `OR1200_OPERAND_WIDTH; +parameter ppic_ints = `OR1200_PIC_INTS; + +// +// I/O +// + +// +// System +// +input clk_i; +input rst_i; +input [1:0] clmode_i; // 00 WB=RISC, 01 WB=RISC/2, 10 N/A, 11 WB=RISC/4 +input [ppic_ints-1:0] pic_ints_i; + +// +// Instruction WISHBONE interface +// +input iwb_clk_i; // clock input +input iwb_rst_i; // reset input +input iwb_ack_i; // normal termination +input iwb_err_i; // termination w/ error +input iwb_rty_i; // termination w/ retry +input [dw-1:0] iwb_dat_i; // input data bus +output iwb_cyc_o; // cycle valid output +output [aw-1:0] iwb_adr_o; // address bus outputs +output iwb_stb_o; // strobe output +output iwb_we_o; // indicates write transfer +output [3:0] iwb_sel_o; // byte select outputs +output [dw-1:0] iwb_dat_o; // output data bus +`ifdef OR1200_WB_CAB +output iwb_cab_o; // indicates consecutive address burst +`endif +`ifdef OR1200_WB_B3 +output [2:0] iwb_cti_o; // cycle type identifier +output [1:0] iwb_bte_o; // burst type extension +`endif + +// +// Data WISHBONE interface +// +input dwb_clk_i; // clock input +input dwb_rst_i; // reset input +input dwb_ack_i; // normal termination +input dwb_err_i; // termination w/ error +input dwb_rty_i; // termination w/ retry +input [dw-1:0] dwb_dat_i; // input data bus +output dwb_cyc_o; // cycle valid output +output [aw-1:0] dwb_adr_o; // address bus outputs +output dwb_stb_o; // strobe output +output dwb_we_o; // indicates write transfer +output [3:0] dwb_sel_o; // byte select outputs +output [dw-1:0] dwb_dat_o; // output data bus +`ifdef OR1200_WB_CAB +output dwb_cab_o; // indicates consecutive address burst +`endif +`ifdef OR1200_WB_B3 +output [2:0] dwb_cti_o; // cycle type identifier +output [1:0] dwb_bte_o; // burst type extension +`endif + +// +// External Debug Interface +// +input dbg_stall_i; // External Stall Input +input dbg_ewt_i; // External Watchpoint Trigger Input +output [3:0] dbg_lss_o; // External Load/Store Unit Status +output [1:0] dbg_is_o; // External Insn Fetch Status +output [10:0] dbg_wp_o; // Watchpoints Outputs +output dbg_bp_o; // Breakpoint Output +input dbg_stb_i; // External Address/Data Strobe +input dbg_we_i; // External Write Enable +input [aw-1:0] dbg_adr_i; // External Address Input +input [dw-1:0] dbg_dat_i; // External Data Input +output [dw-1:0] dbg_dat_o; // External Data Output +output dbg_ack_o; // External Data Acknowledge (not WB compatible) + +`ifdef OR1200_BIST +// +// RAM BIST +// +input mbist_si_i; +input [`OR1200_MBIST_CTRL_WIDTH - 1:0] mbist_ctrl_i; +output mbist_so_o; +`endif + +// +// Power Management +// +input pm_cpustall_i; +output [3:0] pm_clksd_o; +output pm_dc_gate_o; +output pm_ic_gate_o; +output pm_dmmu_gate_o; +output pm_immu_gate_o; +output pm_tt_gate_o; +output pm_cpu_gate_o; +output pm_wakeup_o; +output pm_lvolt_o; + + +endmodule Index: release-1.0/prj/src/blackboxes/ethmac.v =================================================================== --- release-1.0/prj/src/blackboxes/ethmac.v (nonexistent) +++ release-1.0/prj/src/blackboxes/ethmac.v (revision 151) @@ -0,0 +1,113 @@ + + +`include "ethmac_defines.v" + +module ethmac +( + // WISHBONE common + wb_clk_i, wb_rst_i, wb_dat_i, wb_dat_o, + + // WISHBONE slave + wb_adr_i, wb_sel_i, wb_we_i, wb_cyc_i, wb_stb_i, wb_ack_o, wb_err_o, + + // WISHBONE master + m_wb_adr_o, m_wb_sel_o, m_wb_we_o, + m_wb_dat_o, m_wb_dat_i, m_wb_cyc_o, + m_wb_stb_o, m_wb_ack_i, m_wb_err_i, + +`ifdef ETH_WISHBONE_B3 + m_wb_cti_o, m_wb_bte_o, +`endif + + //TX + mtx_clk_pad_i, mtxd_pad_o, mtxen_pad_o, mtxerr_pad_o, + + //RX + mrx_clk_pad_i, mrxd_pad_i, mrxdv_pad_i, mrxerr_pad_i, mcoll_pad_i, mcrs_pad_i, + + // MIIM + mdc_pad_o, md_pad_i, md_pad_o, md_padoe_o, + + int_o + + // Bist +`ifdef ETH_BIST + , + // debug chain signals + mbist_si_i, // bist scan serial in + mbist_so_o, // bist scan serial out + mbist_ctrl_i // bist chain shift control +`endif + +); + + +parameter Tp = 1; + + +// WISHBONE common +input wb_clk_i; // WISHBONE clock +input wb_rst_i; // WISHBONE reset +input [31:0] wb_dat_i; // WISHBONE data input +output [31:0] wb_dat_o; // WISHBONE data output +output wb_err_o; // WISHBONE error output + +// WISHBONE slave +input [11:2] wb_adr_i; // WISHBONE address input +input [3:0] wb_sel_i; // WISHBONE byte select input +input wb_we_i; // WISHBONE write enable input +input wb_cyc_i; // WISHBONE cycle input +input wb_stb_i; // WISHBONE strobe input +output wb_ack_o; // WISHBONE acknowledge output + +// WISHBONE master +output [31:0] m_wb_adr_o; +output [3:0] m_wb_sel_o; +output m_wb_we_o; +input [31:0] m_wb_dat_i; +output [31:0] m_wb_dat_o; +output m_wb_cyc_o; +output m_wb_stb_o; +input m_wb_ack_i; +input m_wb_err_i; + +wire [29:0] m_wb_adr_tmp; + +`ifdef ETH_WISHBONE_B3 +output [2:0] m_wb_cti_o; // Cycle Type Identifier +output [1:0] m_wb_bte_o; // Burst Type Extension +`endif + +// Tx +input mtx_clk_pad_i; // Transmit clock (from PHY) +output [3:0] mtxd_pad_o; // Transmit nibble (to PHY) +output mtxen_pad_o; // Transmit enable (to PHY) +output mtxerr_pad_o; // Transmit error (to PHY) + +// Rx +input mrx_clk_pad_i; // Receive clock (from PHY) +input [3:0] mrxd_pad_i; // Receive nibble (from PHY) +input mrxdv_pad_i; // Receive data valid (from PHY) +input mrxerr_pad_i; // Receive data error (from PHY) + +// Common Tx and Rx +input mcoll_pad_i; // Collision (from PHY) +input mcrs_pad_i; // Carrier sense (from PHY) + +// MII Management interface +input md_pad_i; // MII data input (from I/O cell) +output mdc_pad_o; // MII Management data clock (to PHY) +output md_pad_o; // MII data output (to I/O cell) +output md_padoe_o; // MII data output enable (to I/O cell) + +output int_o; // Interrupt output + +// Bist +`ifdef ETH_BIST +input mbist_si_i; // bist scan serial in +output mbist_so_o; // bist scan serial out +input [`ETH_MBIST_CTRL_WIDTH - 1:0] mbist_ctrl_i; // bist chain shift control +`endif + + +endmodule Index: release-1.0/prj/src/blackboxes/uart_top.v =================================================================== --- release-1.0/prj/src/blackboxes/uart_top.v (nonexistent) +++ release-1.0/prj/src/blackboxes/uart_top.v (revision 151) @@ -0,0 +1,58 @@ + + +`include "uart_defines.v" + +module uart_top ( + wb_clk_i, + + // Wishbone signals + wb_rst_i, wb_adr_i, wb_dat_i, wb_dat_o, wb_we_i, wb_stb_i, wb_cyc_i, wb_ack_o, wb_sel_i, + int_o, // interrupt request + + // UART signals + // serial input/output + stx_pad_o, srx_pad_i, + + // modem signals + rts_pad_o, cts_pad_i, dtr_pad_o, dsr_pad_i, ri_pad_i, dcd_pad_i +`ifdef UART_HAS_BAUDRATE_OUTPUT + , baud_o +`endif + ); + +parameter uart_data_width = `UART_DATA_WIDTH; +parameter uart_addr_width = `UART_ADDR_WIDTH; + +input wb_clk_i; + +// WISHBONE interface +input wb_rst_i; +input [uart_addr_width-1:0] wb_adr_i; +input [uart_data_width-1:0] wb_dat_i; +output [uart_data_width-1:0] wb_dat_o; +input wb_we_i; +input wb_stb_i; +input wb_cyc_i; +input [3:0] wb_sel_i; +output wb_ack_o; +output int_o; + +// UART signals +input srx_pad_i; +output stx_pad_o; +output rts_pad_o; +input cts_pad_i; +output dtr_pad_o; +input dsr_pad_i; +input ri_pad_i; +input dcd_pad_i; + +// optional baudrate output +`ifdef UART_HAS_BAUDRATE_OUTPUT +output baud_o; +`endif + + +endmodule + + Index: release-1.0/prj/src/blackboxes/adbg_top.v =================================================================== --- release-1.0/prj/src/blackboxes/adbg_top.v (nonexistent) +++ release-1.0/prj/src/blackboxes/adbg_top.v (revision 151) @@ -0,0 +1,180 @@ + + +`include "adbg_defines.v" + +module adbg_top( + // JTAG signals + tck_i, + tdi_i, + tdo_o, + rst_i, + + + // TAP states + shift_dr_i, + pause_dr_i, + update_dr_i, + capture_dr_i, + + // Instructions + debug_select_i + + + `ifdef DBG_WISHBONE_SUPPORTED + // WISHBONE common signals + , + wb_clk_i, + wb_rst_i, + + // WISHBONE master interface + wb_adr_o, + wb_dat_o, + wb_dat_i, + wb_cyc_o, + wb_stb_o, + wb_sel_o, + wb_we_o, + wb_ack_i, + wb_cab_o, + wb_err_i, + wb_cti_o, + wb_bte_o + `endif + + `ifdef DBG_CPU0_SUPPORTED + // CPU signals + , + cpu0_clk_i, + cpu0_addr_o, + cpu0_data_i, + cpu0_data_o, + cpu0_bp_i, + cpu0_stall_o, + cpu0_stb_o, + cpu0_we_o, + cpu0_ack_i, + cpu0_rst_o + `endif + + `ifdef DBG_CPU1_SUPPORTED + // CPU signals + , + cpu1_clk_i, + cpu1_addr_o, + cpu1_data_i, + cpu1_data_o, + cpu1_bp_i, + cpu1_stall_o, + cpu1_stb_o, + cpu1_we_o, + cpu1_ack_i, + cpu1_rst_o + `endif + + `ifdef DBG_JSP_SUPPORTED + , + `ifndef DBG_WISHBONE_SUPPORTED + wb_clk_i, + wb_rst_i, + `endif + + // WISHBONE target interface + wb_jsp_adr_i, + wb_jsp_dat_o, + wb_jsp_dat_i, + wb_jsp_cyc_i, + wb_jsp_stb_i, + wb_jsp_sel_i, + wb_jsp_we_i, + wb_jsp_ack_o, + wb_jsp_cab_i, + wb_jsp_err_o, + wb_jsp_cti_i, + wb_jsp_bte_i, + int_o + `endif + + ); + + + // JTAG signals + input tck_i; + input tdi_i; + output tdo_o; + input rst_i; + + // TAP states + input shift_dr_i; + input pause_dr_i; + input update_dr_i; + input capture_dr_i; + + // Module select from TAP + input debug_select_i; + +`ifdef DBG_WISHBONE_SUPPORTED + input wb_clk_i; + input wb_rst_i; + output [31:0] wb_adr_o; + output [31:0] wb_dat_o; + input [31:0] wb_dat_i; + output wb_cyc_o; + output wb_stb_o; + output [3:0] wb_sel_o; + output wb_we_o; + input wb_ack_i; + output wb_cab_o; + input wb_err_i; + output [2:0] wb_cti_o; + output [1:0] wb_bte_o; +`endif + +`ifdef DBG_CPU0_SUPPORTED + // CPU signals + input cpu0_clk_i; + output [31:0] cpu0_addr_o; + input [31:0] cpu0_data_i; + output [31:0] cpu0_data_o; + input cpu0_bp_i; + output cpu0_stall_o; + output cpu0_stb_o; + output cpu0_we_o; + input cpu0_ack_i; + output cpu0_rst_o; +`endif + +`ifdef DBG_CPU1_SUPPORTED + input cpu1_clk_i; + output [31:0] cpu1_addr_o; + input [31:0] cpu1_data_i; + output [31:0] cpu1_data_o; + input cpu1_bp_i; + output cpu1_stall_o; + output cpu1_stb_o; + output cpu1_we_o; + input cpu1_ack_i; + output cpu1_rst_o; +`endif + +`ifdef DBG_JSP_SUPPORTED + `ifndef DBG_WISHBONE_SUPPORTED + input wb_clk_i; + input wb_rst_i; + `endif + input [31:0] wb_jsp_adr_i; + output [31:0] wb_jsp_dat_o; + input [31:0] wb_jsp_dat_i; + input wb_jsp_cyc_i; + input wb_jsp_stb_i; + input [3:0] wb_jsp_sel_i; + input wb_jsp_we_i; + output wb_jsp_ack_o; + input wb_jsp_cab_i; + output wb_jsp_err_o; + input [2:0] wb_jsp_cti_i; + input [1:0] wb_jsp_bte_i; + output int_o; +`endif + + +endmodule Index: release-1.0/prj/src/or1200_top.prj =================================================================== --- release-1.0/prj/src/or1200_top.prj (nonexistent) +++ release-1.0/prj/src/or1200_top.prj (revision 151) @@ -0,0 +1,60 @@ +PROJECT_DIR=rtl/verilog/or1200/rtl/verilog +PROJECT_SRC=(or1200_spram_512x20.v +or1200_spram_64x24.v +or1200_du.v +or1200_spram_2048x32_bw.v +or1200_rf.v +or1200_alu.v +or1200_dmmu_top.v +or1200_lsu.v +or1200_spram_1024x32.v +or1200_dc_top.v +or1200_cpu.v +or1200_gmultp2_32x32.v +or1200_immu_top.v +or1200_dpram_256x32.v +or1200_tt.v +or1200_iwb_biu.v +or1200_rfram_generic.v +or1200_dc_tag.v +or1200_spram_2048x8.v +or1200_immu_tlb.v +or1200_ic_tag.v +or1200_spram_64x14.v +or1200_spram_32x24.v +or1200_dpram_32x32.v +or1200_xcv_ram32x8d.v +or1200_spram_1024x8.v +or1200_mem2reg.v +or1200_pm.v +or1200_spram_256x21.v +or1200_operandmuxes.v +or1200_pic.v +or1200_cfgr.v +or1200_if.v +or1200_qmem_top.v +or1200_genpc.v +or1200_defines.v +or1200_wbmux.v +or1200_ic_ram.v +or1200_dmmu_tlb.v +or1200_sb_fifo.v +or1200_sprs.v +or1200_tpram_32x32.v +or1200_ctrl.v +or1200_sb.v +or1200_mult_mac.v +or1200_ic_fsm.v +or1200_amultp2_32x32.v +or1200_reg2mem.v +or1200_spram_2048x32.v +or1200_except.v +or1200_top.v +or1200_ic_top.v +or1200_dc_ram.v +or1200_spram_1024x32_bw.v +or1200_freeze.v +or1200_spram_128x32.v +or1200_dc_fsm.v +or1200_wb_biu.v +or1200_spram_64x22.v) Index: release-1.0/prj/src/altera_virtual_jtag.prj =================================================================== --- release-1.0/prj/src/altera_virtual_jtag.prj (nonexistent) +++ release-1.0/prj/src/altera_virtual_jtag.prj (revision 151) @@ -0,0 +1,2 @@ +PROJECT_DIR=rtl/verilog/adv_debug_sys/Hardware/altera_virtual_jtag/rtl/vhdl/ +PROJECT_SRC=altera_virtual_jtag.vhd Index: release-1.0/prj/src/minsoc_top.prj =================================================================== --- release-1.0/prj/src/minsoc_top.prj (nonexistent) +++ release-1.0/prj/src/minsoc_top.prj (revision 151) @@ -0,0 +1,17 @@ +PROJECT_DIR=(backend rtl/verilog rtl/verilog/minsoc_startup rtl/verilog/or1200/rtl/verilog rtl/verilog/adv_debug_sys/Hardware/adv_dbg_if/rtl/verilog rtl/verilog/ethmac/rtl/verilog rtl/verilog/uart16550/rtl/verilog) +PROJECT_SRC=(minsoc_defines.v +timescale.v +minsoc_top.v +minsoc_tc_top.v +minsoc_onchip_ram.v +minsoc_onchip_ram_top.v +minsoc_clock_manager.v +altera_pll.v +xilinx_dcm.v +minsoc_xilinx_internal_jtag.v +spi_top.v +spi_defines.v +spi_shift.v +spi_clgen.v +OR1K_startup_generic.v) + Index: release-1.0/prj/src/jtag_top.prj =================================================================== --- release-1.0/prj/src/jtag_top.prj (nonexistent) +++ release-1.0/prj/src/jtag_top.prj (revision 151) @@ -0,0 +1,3 @@ +PROJECT_DIR=rtl/verilog/adv_debug_sys/Hardware/jtag/tap/rtl/verilog +PROJECT_SRC=(tap_top.v +tap_defines.v) Index: release-1.0/prj/src/uart_top.prj =================================================================== --- release-1.0/prj/src/uart_top.prj (nonexistent) +++ release-1.0/prj/src/uart_top.prj (revision 151) @@ -0,0 +1,12 @@ +PROJECT_DIR=rtl/verilog/uart16550/rtl/verilog +PROJECT_SRC=(uart_top.v +uart_sync_flops.v +uart_transmitter.v +uart_debug_if.v +uart_wb.v +uart_receiver.v +uart_tfifo.v +uart_regs.v +uart_rfifo.v +uart_defines.v +raminfr.v) Index: release-1.0/prj/src/adbg_top.prj =================================================================== --- release-1.0/prj/src/adbg_top.prj (nonexistent) +++ release-1.0/prj/src/adbg_top.prj (revision 151) @@ -0,0 +1,11 @@ +PROJECT_DIR=rtl/verilog/adv_debug_sys/Hardware/adv_dbg_if/rtl/verilog +PROJECT_SRC=(adbg_wb_biu.v +adbg_wb_module.v +adbg_or1k_module.v +adbg_wb_defines.v +adbg_defines.v +adbg_crc32.v +adbg_or1k_biu.v +adbg_or1k_defines.v +adbg_or1k_status_reg.v +adbg_top.v) Index: release-1.0/prj/Makefile =================================================================== --- release-1.0/prj/Makefile (nonexistent) +++ release-1.0/prj/Makefile (revision 151) @@ -0,0 +1,58 @@ +VERILOG_PROJECTS = minsoc_bench.prj minsoc_top.prj or1200_top.prj adbg_top.prj jtag_top.prj uart_top.prj ethmac.prj +VHDL_PROJECTS = altera_virtual_jtag.prj + +PROJECTS = $(VERILOG_PROJECTS) $(VHDL_PROJECTS) +SRC_DIR = src +SCRIPTS_DIR = scripts + +SIMULATION_DIR = sim +XILINX_DIR = xilinx +ALTERA_DIR = altera + +SIM_VERILOG_FILES = $(addprefix $(SIMULATION_DIR)/, $(addsuffix .verilog, $(basename $(VERILOG_PROJECTS)))) +SIM_VHDL_FILES = $(addprefix $(SIMULATION_DIR)/, $(addsuffix .vhdl, $(basename $(VHDL_PROJECTS)))) + +XILINX_PRJ_FILES = $(addprefix $(XILINX_DIR)/, $(addsuffix .prj, $(basename $(PROJECTS)))) +XILINX_XST_FILES = $(addprefix $(XILINX_DIR)/, $(addsuffix .xst, $(basename $(PROJECTS)))) + +ALTERA_VERILOG_PRJ_FILES = $(addprefix $(ALTERA_DIR)/, $(addsuffix .vprj, $(basename $(VERILOG_PROJECTS)))) +ALTERA_VHDL_PRJ_FILES = $(addprefix $(ALTERA_DIR)/, $(addsuffix .vhdprj, $(basename $(VHDL_PROJECTS)))) + +all: $(SIMULATION_DIR)/minsoc_verilog.src $(SIMULATION_DIR)/minsoc_vhdl.src $(XILINX_PRJ_FILES) $(XILINX_XST_FILES) $(ALTERA_VERILOG_PRJ_FILES) $(ALTERA_VHDL_PRJ_FILES) + +clean: + rm -rf $(SIMULATION_DIR)/*.verilog $(SIMULATION_DIR)/*.vhdl $(SIMULATION_DIR)/*.src $(XILINX_DIR)/*.prj $(XILINX_DIR)/*.xst $(ALTERA_DIR)/*.vprj $(ALTERA_DIR)/*.vhdprj + + +$(XILINX_DIR)/minsoc_top.xst: $(SRC_DIR)/minsoc_top.prj + bash $(SCRIPTS_DIR)/xilinxxst.sh $^ $@ minsoc_top.prj minsoc_top topmodule + +$(XILINX_DIR)/minsoc_top.prj: $(SRC_DIR)/minsoc_top.prj + bash $(SCRIPTS_DIR)/xilinxprj.sh $^ $@ topmodule + +$(XILINX_DIR)/%.xst: $(SRC_DIR)/%.prj + bash $(SCRIPTS_DIR)/xilinxxst.sh $^ $@ $*.prj $* + +$(XILINX_DIR)/%.prj: $(SRC_DIR)/%.prj + bash $(SCRIPTS_DIR)/xilinxprj.sh $^ $@ + + +$(ALTERA_DIR)/%.vprj: $(SRC_DIR)/%.prj + bash $(SCRIPTS_DIR)/altvprj.sh $^ $@ + +$(ALTERA_DIR)/%.vhdprj: $(SRC_DIR)/%.prj + bash $(SCRIPTS_DIR)/altvhdprj.sh $^ $@ + + +$(SIMULATION_DIR)/minsoc_verilog.src: $(SIM_VERILOG_FILES) + cat $(SIM_VERILOG_FILES) > $(SIMULATION_DIR)/minsoc_verilog.src + +$(SIMULATION_DIR)/minsoc_vhdl.src: $(SIM_VHDL_FILES) + cat $(SIM_VHDL_FILES) > $(SIMULATION_DIR)/minsoc_vhdl.src + +$(SIMULATION_DIR)/%.verilog: $(SRC_DIR)/%.prj + bash $(SCRIPTS_DIR)/simverilog.sh $^ $@ + +$(SIMULATION_DIR)/%.vhdl: $(SRC_DIR)/%.prj + bash $(SCRIPTS_DIR)/simvhdl.sh $^ $@ + Index: release-1.0/prj/scripts/simvhdl.sh =================================================================== --- release-1.0/prj/scripts/simvhdl.sh (nonexistent) +++ release-1.0/prj/scripts/simvhdl.sh (revision 151) @@ -0,0 +1,58 @@ +#!/bin/bash + +#system workings +MINSOC_DIR=`pwd`/.. + +PROJECT=$1 +OUTPUT=$2 + +ENV=`uname -o` + +function adaptpath +{ + if [ "$ENV" == "Cygwin" ] + then + local cygpath=`cygpath -w $1` + local result=`echo $cygpath | sed 's/\\\\/\\//g'` + echo "$result" + else + echo "$1" + fi +} + +if [ ! -f $PROJECT ] +then + echo "Unexistent project file." + exit 1 +fi + +if [ -z "$OUTPUT" ] +then + echo "Second argument should be the destintion file for the file and directory inclusions." + exit 1 +fi +echo -n "" > $OUTPUT + +source $PROJECT + +for file in "${PROJECT_SRC[@]}" +do + FOUND=0 + + for dir in "${PROJECT_DIR[@]}" + do + if [ -f $MINSOC_DIR/$dir/$file ] + then + adapted_file=`adaptpath $MINSOC_DIR/$dir/$file` + echo "$adapted_file" >> $OUTPUT + FOUND=1 + break + fi + done + + if [ $FOUND != 1 ] + then + echo "FILE NOT FOUND: $file" + exit 1 + fi +done
release-1.0/prj/scripts/simvhdl.sh Property changes : Added: svn:executable ## -0,0 +1 ## +* \ No newline at end of property Index: release-1.0/prj/scripts/xilinxprj.sh =================================================================== --- release-1.0/prj/scripts/xilinxprj.sh (nonexistent) +++ release-1.0/prj/scripts/xilinxprj.sh (revision 151) @@ -0,0 +1,72 @@ +#!/bin/bash + +#system workings +MINSOC_DIR=`pwd`/.. + +PROJECT=$1 +SRC_OUTPUT=$2 +TOP_MODULE=$3 + +ENV=`uname -o` + +function adaptpath +{ + if [ "$ENV" == "Cygwin" ] + then + local cygpath=`cygpath -w $1` + echo "$cygpath" + else + echo "$1" + fi +} + +if [ ! -f $PROJECT ] +then + echo "Unexistent project file." + exit 1 +fi + +if [ -z "$SRC_OUTPUT" ] +then + echo "Third argument should be the destintion file for the source inclusions." + exit 1 +fi +echo -n "" > $SRC_OUTPUT + +source $PROJECT + +for file in "${PROJECT_SRC[@]}" +do + FOUND=0 + + for dir in "${PROJECT_DIR[@]}" + do + if [ -f $MINSOC_DIR/$dir/$file ] + then + adapted_file=`adaptpath $MINSOC_DIR/$dir/$file` + echo -n '`include "' >> $SRC_OUTPUT + echo -n "$adapted_file" >> $SRC_OUTPUT + echo '"' >> $SRC_OUTPUT + FOUND=1 + break + fi + done + + if [ $FOUND != 1 ] + then + echo "FILE NOT FOUND: $file" + exit 1 + fi +done + +if [ -n "$TOP_MODULE" ] +then + for file in src/blackboxes/*.v + do + dir=`pwd` + adapted_file=`adaptpath $dir/$file` + echo -n '`include "' >> $SRC_OUTPUT + echo -n "$adapted_file" >> $SRC_OUTPUT + echo '"' >> $SRC_OUTPUT + done +fi
release-1.0/prj/scripts/xilinxprj.sh Property changes : Added: svn:executable ## -0,0 +1 ## +* \ No newline at end of property Index: release-1.0/prj/scripts/altvhdprj.sh =================================================================== --- release-1.0/prj/scripts/altvhdprj.sh (nonexistent) +++ release-1.0/prj/scripts/altvhdprj.sh (revision 151) @@ -0,0 +1,64 @@ +#!/bin/bash + +#system workings +MINSOC_DIR=`pwd`/.. + +PROJECT=$1 +OUTPUT=$2 + +ENV=`uname -o` + +function adaptpath +{ + if [ "$ENV" == "Cygwin" ] + then + local cygpath=`cygpath -w $1` + local result=`echo $cygpath | sed 's/\\\\/\\//g'` + echo "$result" + else + echo "$1" + fi +} + +if [ ! -f $PROJECT ] +then + echo "Unexistent project file." + exit 1 +fi + +if [ -z "$OUTPUT" ] +then + echo "Second argument should be the destintion file for the file and directory inclusions." + exit 1 +fi +echo -n "" > $OUTPUT + +source $PROJECT + +for dir in "${PROJECT_DIR[@]}" +do + adapted_dir=`adaptpath $MINSOC_DIR/$dir` + echo "set_global_assignment -name SEARCH_PATH $adapted_dir" >> $OUTPUT +done + +for file in "${PROJECT_SRC[@]}" +do + FOUND=0 + + for dir in "${PROJECT_DIR[@]}" + do + if [ -f $MINSOC_DIR/$dir/$file ] + then + adapted_file=`adaptpath $MINSOC_DIR/$dir/$file` + echo "set_global_assignment -name VHDL_FILE $adapted_file" >> $OUTPUT + FOUND=1 + break + fi + done + + if [ $FOUND != 1 ] + then + echo "FILE NOT FOUND: $file" + exit 1 + fi +done
release-1.0/prj/scripts/altvhdprj.sh Property changes : Added: svn:executable ## -0,0 +1 ## +* \ No newline at end of property Index: release-1.0/prj/scripts/simverilog.sh =================================================================== --- release-1.0/prj/scripts/simverilog.sh (nonexistent) +++ release-1.0/prj/scripts/simverilog.sh (revision 151) @@ -0,0 +1,64 @@ +#!/bin/bash + +#system workings +MINSOC_DIR=`pwd`/.. + +PROJECT=$1 +OUTPUT=$2 + +ENV=`uname -o` + +function adaptpath +{ + if [ "$ENV" == "Cygwin" ] + then + local cygpath=`cygpath -w $1` + local result=`echo $cygpath | sed 's/\\\\/\\//g'` + echo "$result" + else + echo "$1" + fi +} + +if [ ! -f $PROJECT ] +then + echo "Unexistent project file." + exit 1 +fi + +if [ -z "$OUTPUT" ] +then + echo "Second argument should be the destintion file for the file and directory inclusions." + exit 1 +fi +echo -n "" > $OUTPUT + +source $PROJECT + +for dir in "${PROJECT_DIR[@]}" +do + adapted_dir=`adaptpath $MINSOC_DIR/$dir` + echo "+incdir+$adapted_dir" >> $OUTPUT +done + +for file in "${PROJECT_SRC[@]}" +do + FOUND=0 + + for dir in "${PROJECT_DIR[@]}" + do + if [ -f $MINSOC_DIR/$dir/$file ] + then + adapted_file=`adaptpath $MINSOC_DIR/$dir/$file` + echo "$adapted_file" >> $OUTPUT + FOUND=1 + break + fi + done + + if [ $FOUND != 1 ] + then + echo "FILE NOT FOUND: $file" + exit 1 + fi +done
release-1.0/prj/scripts/simverilog.sh Property changes : Added: svn:executable ## -0,0 +1 ## +* \ No newline at end of property Index: release-1.0/prj/scripts/altvprj.sh =================================================================== --- release-1.0/prj/scripts/altvprj.sh (nonexistent) +++ release-1.0/prj/scripts/altvprj.sh (revision 151) @@ -0,0 +1,64 @@ +#!/bin/bash + +#system workings +MINSOC_DIR=`pwd`/.. + +PROJECT=$1 +OUTPUT=$2 + +ENV=`uname -o` + +function adaptpath +{ + if [ "$ENV" == "Cygwin" ] + then + local cygpath=`cygpath -w $1` + local result=`echo $cygpath | sed 's/\\\\/\\//g'` + echo "$result" + else + echo "$1" + fi +} + +if [ ! -f $PROJECT ] +then + echo "Unexistent project file." + exit 1 +fi + +if [ -z "$OUTPUT" ] +then + echo "Second argument should be the destintion file for the file and directory inclusions." + exit 1 +fi +echo -n "" > $OUTPUT + +source $PROJECT + +for dir in "${PROJECT_DIR[@]}" +do + adapted_dir=`adaptpath $MINSOC_DIR/$dir` + echo "set_global_assignment -name SEARCH_PATH $adapted_dir" >> $OUTPUT +done + +for file in "${PROJECT_SRC[@]}" +do + FOUND=0 + + for dir in "${PROJECT_DIR[@]}" + do + if [ -f $MINSOC_DIR/$dir/$file ] + then + adapted_file=`adaptpath $MINSOC_DIR/$dir/$file` + echo "set_global_assignment -name VERILOG_FILE $adapted_file" >> $OUTPUT + FOUND=1 + break + fi + done + + if [ $FOUND != 1 ] + then + echo "FILE NOT FOUND: $file" + exit 1 + fi +done
release-1.0/prj/scripts/altvprj.sh Property changes : Added: svn:executable ## -0,0 +1 ## +* \ No newline at end of property Index: release-1.0/prj/scripts/xilinxxst.sh =================================================================== --- release-1.0/prj/scripts/xilinxxst.sh (nonexistent) +++ release-1.0/prj/scripts/xilinxxst.sh (revision 151) @@ -0,0 +1,68 @@ +#!/bin/bash + +#system workings +MINSOC_DIR=`pwd`/.. + +PROJECT=$1 +DIR_OUTPUT=$2 +PROJECT_FILE=$3 +TOP_MODULE_NAME=$4 +TOP_MODULE=$5 + +ENV=`uname -o` + +function adaptpath +{ + if [ "$ENV" == "Cygwin" ] + then + local cygpath=`cygpath -w $1` + echo "$cygpath" + else + echo "$1" + fi +} + +if [ ! -f $PROJECT ] +then + echo "Unexistent project file." + exit 1 +fi + +if [ -z "$DIR_OUTPUT" ] +then + echo "Second argument should be the destintion file for the directory inclusions." + exit 1 +fi +echo -n "" > $DIR_OUTPUT + +source $PROJECT + +echo "set -tmpdir "./xst"" >> $DIR_OUTPUT +echo "run" >> $DIR_OUTPUT + +DIR_PATH="-vlgincdir {" + +for dir in "${PROJECT_DIR[@]}" +do + adapted_dir=`adaptpath $MINSOC_DIR/$dir` + DIR_PATH="$DIR_PATH \"$adapted_dir\" " +done + +DIR_PATH="$DIR_PATH }" +echo $DIR_PATH >> $DIR_OUTPUT + +adapted_project_file=`adaptpath $MINSOC_DIR/prj/xilinx/${PROJECT_FILE}` +echo "-ifn $adapted_project_file" >> $DIR_OUTPUT +echo "-ifmt Verilog" >> $DIR_OUTPUT +echo "-ofn ${TOP_MODULE_NAME}" >> $DIR_OUTPUT +echo "-ofmt NGC" >> $DIR_OUTPUT +echo "-p DEVICE_PART" >> $DIR_OUTPUT +echo "-top ${TOP_MODULE_NAME}" >> $DIR_OUTPUT +echo "-opt_mode Speed" >> $DIR_OUTPUT +echo "-opt_level 1" >> $DIR_OUTPUT +if [ -n "$TOP_MODULE" ] +then + echo "-iobuf yes" >> $DIR_OUTPUT +else + echo "-iobuf no" >> $DIR_OUTPUT +fi
release-1.0/prj/scripts/xilinxxst.sh Property changes : Added: svn:executable ## -0,0 +1 ## +* \ No newline at end of property Index: release-1.0/syn/xilinx/setup.bat =================================================================== --- release-1.0/syn/xilinx/setup.bat (nonexistent) +++ release-1.0/syn/xilinx/setup.bat (revision 151) @@ -0,0 +1,13 @@ +@echo off +set /p xilinx_settings=Input the Xilinx "settings32|64.bat" file along with its absolute path: +if EXIST %xilinx_settings% ( +%xilinx_settings% +make all +echo Finished... +set /p exit=Press ENTER to close this window... +make clean +) ELSE ( +echo %xilinx_settings% could not be found. +set /p exit=Press ENTER to close this window... +) +
release-1.0/syn/xilinx/setup.bat Property changes : Added: svn:executable ## -0,0 +1 ## +* \ No newline at end of property Index: release-1.0/syn/xilinx/Makefile =================================================================== --- release-1.0/syn/xilinx/Makefile (nonexistent) +++ release-1.0/syn/xilinx/Makefile (revision 151) @@ -0,0 +1,84 @@ +MINSOC = ../ +MINSOC_DEFINES = ${MINSOC}/backend +MINSOC_RTL = ${MINSOC}/rtl/verilog +MINSOC_STARTUP_RTL = ${MINSOC_RTL}/minsoc_startup +UART_RTL = ${MINSOC_RTL}/uart16550/rtl/verilog +ADV_DEBUG_ROOT = ${MINSOC_RTL}/adv_debug_sys/Hardware +DEBUG_RTL = ${ADV_DEBUG_ROOT}/adv_dbg_if/rtl/verilog +OR1200_RTL = ${MINSOC_RTL}/or1200/rtl/verilog +ETH_RTL = ${MINSOC_RTL}/ethmac/rtl/verilog +BUILD_SUPPORT = $(MINSOC)/syn/buildSupport +PROJECT_DIR = $(MINSOC)/prj/xilinx + +help: + @echo " all: Synthesize and implement the SoC, then generate a bit stream" + @echo "" + @echo " soc: Synthesize the SoC" + @echo " translate: Convert the SoC's ngc file to an ngd file for mapping" + @echo " map: Express the SoC netlist in the target hardware" + @echo " par: Place the target hardware, then route the wires" + @echo " bitgen: Generate a programming file for the target FPGA" + @echo "" + @echo " modules: Synthesize OR1200 processor, debug interface, UART and Ethernet controllers" + @echo " or1200: Synthesize the OR1200 processor" + @echo " debug: Synthesize the debug interface" + @echo " uart: Synthesize the UART" + @echo " eth: Synthesize the Ethernet controller" + @echo "" + @echo " clean: Delete all superfluous files generated by Xilinx tools" + @echo " distclean: Delete all generated files" + +all: minsoc.bit +soc: minsoc_top.ngc +translate: minsoc.ngd +map: minsoc.ncd +par: minsoc_par.ncd +bitgen: minsoc.bit +modules: or1200 debug uart eth +MODULES = or1200_top.ngc adbg_top.ngc uart_top.ngc ethmac.ngc + +prepare: + rm -rf xst + mkdir xst +clean: + rm -rf _xmsgs xst xlnx_auto_0_xdb + rm -rf *.xst *.xrpt *.srp *.lso *.log *.bld *.lst *.twr *.ise *.map *.mrp *.ngm *.pcf *.psr *.xml *.pad *.par *.ptwx *.bgn *.unroutes *.xpi minsoc_par_pad* *.xwbt *.html +distclean: + rm -rf *.ngc *.ncd *.ngd *.bit + make clean + +minsoc_top.ngc: ${MINSOC_RTL}/*.v ${MINSOC_DEFINES}/minsoc_defines.v $(BUILD_SUPPORT)/minsoc_top.xst $(PROJECT_DIR)/minsoc_top.prj + make prepare + xst -ifn "$(BUILD_SUPPORT)/minsoc_top.xst" + +uart: uart_top.ngc +uart_top.ngc: ${UART_RTL}/*.v $(BUILD_SUPPORT)/uart_top.xst $(PROJECT_DIR)/uart_top.prj + make prepare + xst -ifn "$(BUILD_SUPPORT)/uart_top.xst" + +eth: ethmac.ngc +ethmac.ngc: ${ETH_RTL}/*.v $(BUILD_SUPPORT)/ethmac.xst $(PROJECT_DIR)/ethmac.prj + make prepare + xst -ifn "$(BUILD_SUPPORT)/ethmac.xst" + +debug: adbg_top.ngc +adbg_top.ngc: ${DEBUG_RTL}/*.v $(BUILD_SUPPORT)/adbg_top.xst $(PROJECT_DIR)/adbg_top.prj + make prepare + xst -ifn "$(BUILD_SUPPORT)/adbg_top.xst" + +or1200: or1200_top.ngc +or1200_top.ngc: ${OR1200_RTL}/*.v $(BUILD_SUPPORT)/or1200_top.xst $(PROJECT_DIR)/or1200_top.prj + make prepare + xst -ifn "$(BUILD_SUPPORT)/or1200_top.xst" + +minsoc.ngd: ${MINSOC}/backend/CONSTRAINT_FILE minsoc_top.ngc $(MODULES) + ngdbuild -p DEVICE_PART -uc ${MINSOC}/backend/CONSTRAINT_FILE -aul minsoc_top.ngc minsoc.ngd + +minsoc.ncd: minsoc.ngd + map -bp -timing -cm speed -equivalent_register_removal on -logic_opt on -ol high -power off -register_duplication on -retiming on -w -xe n minsoc.ngd + +minsoc_par.ncd: minsoc.ncd + par -ol high -w -xe n minsoc.ncd minsoc_par.ncd + +minsoc.bit: minsoc_par.ncd + bitgen -d -w minsoc_par.ncd minsoc.bit Index: release-1.0/syn/altera/setup.bat =================================================================== --- release-1.0/syn/altera/setup.bat (nonexistent) +++ release-1.0/syn/altera/setup.bat (revision 151) @@ -0,0 +1,12 @@ +@echo off +set /p quartus_path=Input the path to Quartus e.g. C:\altera\11.0sp1\quartus: +if EXIST %quartus_path% ( +set path=%path%;%quartus_path%\bin\cygwin\bin;%quartus_path%\bin +make all +echo Finished... +set /p exit=Press ENTER to close this window... +make clean +) ELSE ( +echo %quartus_path% could not be found. +set /p exit=Press ENTER to close this window... +) \ No newline at end of file
release-1.0/syn/altera/setup.bat Property changes : Added: svn:executable ## -0,0 +1 ## +* \ No newline at end of property Index: release-1.0/syn/altera/minsoc_top.qsf =================================================================== --- release-1.0/syn/altera/minsoc_top.qsf (nonexistent) +++ release-1.0/syn/altera/minsoc_top.qsf (revision 151) @@ -0,0 +1,37 @@ +set_global_assignment -name FAMILY "FAMILY_PART" +set_global_assignment -name DEVICE DEVICE_PART +set_global_assignment -name TOP_LEVEL_ENTITY minsoc_top +#set_global_assignment -name ORIGINAL_QUARTUS_VERSION SW_VERSION +#set_global_assignment -name LAST_QUARTUS_VERSION SW_VERSION +set_global_assignment -name MIN_CORE_JUNCTION_TEMP 0 +set_global_assignment -name MAX_CORE_JUNCTION_TEMP 85 +set_global_assignment -name DEVICE_FILTER_PIN_COUNT 240 +set_global_assignment -name ERROR_CHECK_FREQUENCY_DIVISOR 2 +set_global_assignment -name PARTITION_NETLIST_TYPE SOURCE -section_id Top +set_global_assignment -name PARTITION_FITTER_PRESERVATION_LEVEL PLACEMENT_AND_ROUTING -section_id Top +set_global_assignment -name PARTITION_COLOR 16764057 -section_id Top +set_global_assignment -name STRATIX_DEVICE_IO_STANDARD "2.5 V" +#set_global_assignment -name MISC_FILE ./minsoc_top.dpf +set_global_assignment -name USE_CONFIGURATION_DEVICE OFF +set_global_assignment -name CRC_ERROR_OPEN_DRAIN OFF +set_global_assignment -name FORCE_CONFIGURATION_VCCIO ON +set_global_assignment -name OUTPUT_IO_TIMING_NEAR_END_VMEAS "HALF VCCIO" -rise +set_global_assignment -name OUTPUT_IO_TIMING_NEAR_END_VMEAS "HALF VCCIO" -fall +set_global_assignment -name OUTPUT_IO_TIMING_FAR_END_VMEAS "HALF SIGNAL SWING" -rise +set_global_assignment -name OUTPUT_IO_TIMING_FAR_END_VMEAS "HALF SIGNAL SWING" -fall +set_global_assignment -name RESERVE_DATA1_AFTER_CONFIGURATION "USE AS REGULAR IO" +set_global_assignment -name RESERVE_FLASH_NCE_AFTER_CONFIGURATION "USE AS REGULAR IO" +set_global_assignment -name EDA_BOARD_DESIGN_BOUNDARY_SCAN_TOOL "BSDL (Boundary Scan)" +set_global_assignment -name EDA_OUTPUT_DATA_FORMAT BSDL -section_id eda_board_design_boundary_scan +set_global_assignment -name EDA_BOARD_BOUNDARY_SCAN_OPERATION POST_CONFIG -section_id eda_board_design_boundary_scan +set_global_assignment -name POWER_PRESET_COOLING_SOLUTION "23 MM HEAT SINK WITH 200 LFPM AIRFLOW" +set_global_assignment -name POWER_BOARD_THERMAL_MODEL "NONE (CONSERVATIVE)" +set_global_assignment -name EDA_TIMING_ANALYSIS_TOOL "" +set_global_assignment -name EDA_TIME_SCALE "1 ps" -section_id eda_timing_analysis +set_global_assignment -name EDA_RUN_TOOL_AUTOMATICALLY OFF -section_id eda_timing_analysis +set_global_assignment -name EDA_OUTPUT_DATA_FORMAT NONE -section_id eda_timing_analysis +set_global_assignment -name EDA_LAUNCH_CMD_LINE_TOOL OFF -section_id eda_timing_analysis + +set_global_assignment -name SDC_FILE minsoc_top.sdc +set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -section_id Top + Index: release-1.0/syn/altera/Makefile =================================================================== --- release-1.0/syn/altera/Makefile (nonexistent) +++ release-1.0/syn/altera/Makefile (revision 151) @@ -0,0 +1,60 @@ +MINSOC = .. +MINSOC_DEFINES = ${MINSOC}/backend +MINSOC_RTL = ${MINSOC}/rtl/verilog +MINSOC_STARTUP_RTL = ${MINSOC_RTL}/minsoc_startup +UART_RTL = ${MINSOC_RTL}/uart16550/rtl/verilog +ADV_DEBUG_ROOT = ${MINSOC_RTL}/adv_debug_sys/Hardware +DEBUG_RTL = ${ADV_DEBUG_ROOT}/adv_dbg_if/rtl/verilog +OR1200_RTL = ${MINSOC_RTL}/or1200/rtl/verilog +ETH_RTL = ${MINSOC_RTL}/ethmac/rtl/verilog +BUILD_SUPPORT = $(MINSOC)/syn/buildSupport +PROJECT_DIR = $(MINSOC)/prj/altera +QSF_FILE = $(BUILD_SUPPORT)/minsoc_top +help: + @echo " all: Synthesize and implement the SoC, then generate a bit stream" + @echo "" + @echo " bitgen: Generate a programming file for the target FPGA" + @echo " map: Express the SoC netlist in the target hardware" + @echo " fit: Place the target hardware, then route the wires" + @echo " sta: Perfom a timming analysis" + @echo " eda: Generate a netlist of the hardware" + @echo " config: Load the bitstream into the device using ALTERA USB Blaster and JTAG configuration" + @echo "" + @echo " clean: Delete all superfluous files generated by Altera tools" + @echo " distclean: Delete all generated files" + +all: bitgen eda sta +map: $(BUILD_SUPPORT)/minsoc_top.map.summary +fit: $(BUILD_SUPPORT)/minsoc_top.fit.summary +bitgen: minsoc_top.sof +eda: $(BUILD_SUPPORT)/minsoc_top.eda.summary +sta: $(BUILD_SUPPORT)/minsoc_top.sta.summary + +#minsoc_top.map.summary: ${MINSOC_RTL}/*.v $(UART_RTL)/*.v $(ADV_DEBUG_ROOT)/*.v $(DEBUG_RTL)/*.v $(OR1200_RTL)/*.v $(ETH_RTL)/*.v ${MINSOC_DEFINES}/minsoc_defines.v minsoc_top.qsf +$(BUILD_SUPPORT)/minsoc_top.map.summary: ${MINSOC_DEFINES}/minsoc_defines.v $(BUILD_SUPPORT)/minsoc_top.qsf + + quartus_map $(QSF_FILE) --write_settings_files=off + +$(BUILD_SUPPORT)/minsoc_top.fit.summary: $(BUILD_SUPPORT)/minsoc_top.map.summary + quartus_fit $(QSF_FILE) --write_Settings_files=off --pack_register=minimize_area + +minsoc_top.sof: $(BUILD_SUPPORT)/minsoc_top.fit.summary + quartus_asm $(QSF_FILE) + mv $(BUILD_SUPPORT)/*.sof . + +$(BUILD_SUPPORT)/minsoc_top.sta.summary: $(BUILD_SUPPORT)/minsoc_top.fit.summary + quartus_sta $(QSF_FILE) + +$(BUILD_SUPPORT)/minsoc_top.eda.summary: $(BUILD_SUPPORT)/minsoc_top.fit.summary + quartus_eda $(QSF_FILE) --write_settings_files=off + +config: minsoc_top.sof + quartus_pgm -c USB-Blaster -m jtag -o "p;minsoc_top.sof" + +distclean: + $(RM) *.sof + make clean + +clean: + $(RM) $(BUILD_SUPPORT)/*.rpt $(BUILD_SUPPORT)/*.summary $(BUILD_SUPPORT)/*.jdi $(BUILD_SUPPORT)/*.smsg $(BUILD_SUPPORT)/*.pin $(BUILD_SUPPORT)/*.qpf + $(RM) -r $(BUILD_SUPPORT)/db $(BUILD_SUPPORT)/incremental_db Index: release-1.0/syn/doc/guideTop.pdf =================================================================== Cannot display: file marked as a binary type. svn:mime-type = application/octet-stream Index: release-1.0/syn/doc/guideTop.pdf =================================================================== --- release-1.0/syn/doc/guideTop.pdf (nonexistent) +++ release-1.0/syn/doc/guideTop.pdf (revision 151)
release-1.0/syn/doc/guideTop.pdf Property changes : Added: svn:mime-type ## -0,0 +1 ## +application/octet-stream \ No newline at end of property Index: release-1.0/rtl/verilog/xilinx_dcm.v =================================================================== --- release-1.0/rtl/verilog/xilinx_dcm.v (nonexistent) +++ release-1.0/rtl/verilog/xilinx_dcm.v (revision 151) @@ -0,0 +1,226 @@ + +`include "minsoc_defines.v" + +module xilinx_dcm( + clk_i, + clk_o +); + +// +// Parameters +// + parameter divisor = 2; + +input clk_i; +output clk_o; + + +`ifdef SPARTAN2 + `define XILINX_DLL +`elsif VIRTEX + `define XILINX_DLL +`endif // !SPARTAN2/VIRTEX + +`ifdef SPARTAN3 + `define XILINX_DCM +`elsif VIRTEX2 + `define XILINX_DCM +`endif // !SPARTAN3/VIRTEX2 + +`ifdef SPARTAN3E + `define XILINX_DCM_SP +`elsif SPARTAN3A + `define XILINX_DCM_SP +`endif // !SPARTAN3E/SPARTAN3A + +`ifdef VIRTEX4 + `define XILINX_DCM_ADV + `define XILINX_DCM_COMPONENT "VIRTEX4" +`elsif VIRTEX5 + `define XILINX_DCM_ADV + `define XILINX_DCM_COMPONENT "VIRTEX5" +`endif // !VIRTEX4/VIRTEX5 + + +wire CLKIN_IN; +wire CLKDV_OUT; + +assign CLKIN_IN = clk_i; +assign clk_o = CLKDV_OUT; + +wire CLKIN_IBUFG; +wire CLK0_BUF; +wire CLKFB_IN; +wire CLKDV_BUF; + +`ifdef XILINX_FPGA + +IBUFG CLKIN_IBUFG_INST ( + .I(CLKIN_IN), + .O(CLKIN_IBUFG) +); + +BUFG CLK0_BUFG_INST ( + .I(CLK0_BUF), + .O(CLKFB_IN) +); + +BUFG CLKDV_BUFG_INST ( + .I(CLKDV_BUF), + .O(CLKDV_OUT) +); + +`ifdef XILINX_DLL + +CLKDLL #( + .CLKDV_DIVIDE(divisor), // Divide by: 1.5,2.0,2.5,3.0,4.0,5.0,8.0 or 16.0 + .DUTY_CYCLE_CORRECTION("TRUE"), // Duty cycle correction, TRUE or FALSE + .FACTORY_JF(16'hC080), // FACTORY JF Values + .STARTUP_WAIT("FALSE") // Delay config DONE until DLL LOCK, TRUE/FALSE +) CLKDLL_inst ( + .CLK0(CLK0_BUF), // 0 degree DLL CLK output + .CLK180(), // 180 degree DLL CLK output + .CLK270(), // 270 degree DLL CLK output + .CLK2X(), // 2X DLL CLK output + .CLK90(), // 90 degree DLL CLK output + .CLKDV(CLKDV_BUF), // Divided DLL CLK out (CLKDV_DIVIDE) + .LOCKED(), // DLL LOCK status output + .CLKFB(CLKFB_IN), // DLL clock feedback + .CLKIN(CLKIN_IBUFG), // Clock input (from IBUFG, BUFG or DLL) + .RST(1'b0) // DLL asynchronous reset input +); + +`elsif XILINX_DCM + +DCM #( + .SIM_MODE("SAFE"), // Simulation: "SAFE" vs. "FAST", see "Synthesis and Simulation Design Guide" for details + .CLKDV_DIVIDE(divisor), // Divide by: 1.5,2.0,2.5,3.0,3.5,4.0,4.5,5.0,5.5,6.0,6.5 + // 7.0,7.5,8.0,9.0,10.0,11.0,12.0,13.0,14.0,15.0 or 16.0 + .CLKFX_DIVIDE(1), // Can be any integer from 1 to 32 + .CLKFX_MULTIPLY(4), // Can be any integer from 2 to 32 + .CLKIN_DIVIDE_BY_2("FALSE"), // TRUE/FALSE to enable CLKIN divide by two feature + .CLKIN_PERIOD(0.0), // Specify period of input clock + .CLKOUT_PHASE_SHIFT("NONE"), // Specify phase shift of NONE, FIXED or VARIABLE + .CLK_FEEDBACK("1X"), // Specify clock feedback of NONE, 1X or 2X + .DESKEW_ADJUST("SYSTEM_SYNCHRONOUS"), // SOURCE_SYNCHRONOUS, SYSTEM_SYNCHRONOUS or + // an integer from 0 to 15 + .DFS_FREQUENCY_MODE("LOW"), // HIGH or LOW frequency mode for frequency synthesis + .DLL_FREQUENCY_MODE("LOW"), // HIGH or LOW frequency mode for DLL + .DUTY_CYCLE_CORRECTION("TRUE"), // Duty cycle correction, TRUE or FALSE + .FACTORY_JF(16'hC080), // FACTORY JF values + .PHASE_SHIFT(0), // Amount of fixed phase shift from -255 to 255 + .STARTUP_WAIT("FALSE") // Delay configuration DONE until DCM LOCK, TRUE/FALSE +) DCM_inst ( + .CLK0(CLK0_BUF), // 0 degree DCM CLK output + .CLK180(), // 180 degree DCM CLK output + .CLK270(), // 270 degree DCM CLK output + .CLK2X(), // 2X DCM CLK output + .CLK2X180(), // 2X, 180 degree DCM CLK out + .CLK90(), // 90 degree DCM CLK output + .CLKDV(CLKDV_BUF), // Divided DCM CLK out (CLKDV_DIVIDE) + .CLKFX(), // DCM CLK synthesis out (M/D) + .CLKFX180(), // 180 degree CLK synthesis out + .LOCKED(), // DCM LOCK status output + .PSDONE(), // Dynamic phase adjust done output + .STATUS(), // 8-bit DCM status bits output + .CLKFB(CLKFB_IN), // DCM clock feedback + .CLKIN(CLKIN_IBUFG), // Clock input (from IBUFG, BUFG or DCM) + .PSCLK(1'b0), // Dynamic phase adjust clock input + .PSEN(1'b0), // Dynamic phase adjust enable input + .PSINCDEC(1'b0), // Dynamic phase adjust increment/decrement + .RST(1'b0) // DCM asynchronous reset input +); + +`elsif XILINX_DCM_SP + +DCM_SP #( + .CLKDV_DIVIDE(divisor), // Divide by: 1.5,2.0,2.5,3.0,3.5,4.0,4.5,5.0,5.5,6.0,6.5 + // 7.0,7.5,8.0,9.0,10.0,11.0,12.0,13.0,14.0,15.0 or 16.0 + .CLKFX_DIVIDE(1), // Can be any integer from 1 to 32 + .CLKFX_MULTIPLY(4), // Can be any integer from 2 to 32 + .CLKIN_DIVIDE_BY_2("FALSE"), // TRUE/FALSE to enable CLKIN divide by two feature + .CLKIN_PERIOD(0.0), // Specify period of input clock + .CLKOUT_PHASE_SHIFT("NONE"), // Specify phase shift of NONE, FIXED or VARIABLE + .CLK_FEEDBACK("1X"), // Specify clock feedback of NONE, 1X or 2X + .DESKEW_ADJUST("SYSTEM_SYNCHRONOUS"), // SOURCE_SYNCHRONOUS, SYSTEM_SYNCHRONOUS or + // an integer from 0 to 15 + .DLL_FREQUENCY_MODE("LOW"), // HIGH or LOW frequency mode for DLL + .DUTY_CYCLE_CORRECTION("TRUE"), // Duty cycle correction, TRUE or FALSE + .PHASE_SHIFT(0), // Amount of fixed phase shift from -255 to 255 + .STARTUP_WAIT("FALSE") // Delay configuration DONE until DCM LOCK, TRUE/FALSE +) DCM_SP_inst ( + .CLK0(CLK0_BUF), // 0 degree DCM CLK output + .CLK180(), // 180 degree DCM CLK output + .CLK270(), // 270 degree DCM CLK output + .CLK2X(), // 2X DCM CLK output + .CLK2X180(), // 2X, 180 degree DCM CLK out + .CLK90(), // 90 degree DCM CLK output + .CLKDV(CLKDV_BUF), // Divided DCM CLK out (CLKDV_DIVIDE) + .CLKFX(), // DCM CLK synthesis out (M/D) + .CLKFX180(), // 180 degree CLK synthesis out + .LOCKED(), // DCM LOCK status output + .PSDONE(), // Dynamic phase adjust done output + .STATUS(), // 8-bit DCM status bits output + .CLKFB(CLKFB_IN), // DCM clock feedback + .CLKIN(CLKIN_IBUFG), // Clock input (from IBUFG, BUFG or DCM) + .PSCLK(1'b0), // Dynamic phase adjust clock input + .PSEN(1'b0), // Dynamic phase adjust enable input + .PSINCDEC(1'b0), // Dynamic phase adjust increment/decrement + .RST(1'b0) // DCM asynchronous reset input +); + +`elsif XILINX_DCM_ADV + +DCM_ADV #( + .CLKDV_DIVIDE(divisor), // Divide by: 1.5,2.0,2.5,3.0,3.5,4.0,4.5,5.0,5.5,6.0,6.5 + // 7.0,7.5,8.0,9.0,10.0,11.0,12.0,13.0,14.0,15.0 or 16.0 + .CLKFX_DIVIDE(1), // Can be any integer from 1 to 32 + .CLKFX_MULTIPLY(4), // Can be any integer from 2 to 32 + .CLKIN_DIVIDE_BY_2("FALSE"), // TRUE/FALSE to enable CLKIN divide by two feature + .CLKIN_PERIOD(10.0), // Specify period of input clock in ns from 1.25 to 1000.00 + .CLKOUT_PHASE_SHIFT("NONE"), // Specify phase shift mode of NONE, FIXED, + // VARIABLE_POSITIVE, VARIABLE_CENTER or DIRECT + .CLK_FEEDBACK("1X"), // Specify clock feedback of NONE, 1X or 2X + .DCM_AUTOCALIBRATION("TRUE"), // DCM calibration circuitry "TRUE"/"FALSE" + .DCM_PERFORMANCE_MODE("MAX_SPEED"), // Can be MAX_SPEED or MAX_RANGE + .DESKEW_ADJUST("SYSTEM_SYNCHRONOUS"), // SOURCE_SYNCHRONOUS, SYSTEM_SYNCHRONOUS or + // an integer from 0 to 15 + .DFS_FREQUENCY_MODE("LOW"), // HIGH or LOW frequency mode for frequency synthesis + .DLL_FREQUENCY_MODE("LOW"), // LOW, HIGH, or HIGH_SER frequency mode for DLL + .DUTY_CYCLE_CORRECTION("TRUE"), // Duty cycle correction, "TRUE"/"FALSE" + .FACTORY_JF(16'hf0f0), // FACTORY JF value suggested to be set to 16’hf0f0 + .PHASE_SHIFT(0), // Amount of fixed phase shift from -255 to 1023 + .SIM_DEVICE(`XILINX_DCM_COMPONENT), // Set target device, "VIRTEX4" or "VIRTEX5" + .STARTUP_WAIT("FALSE") // Delay configuration DONE until DCM LOCK, "TRUE"/"FALSE" +) DCM_ADV_inst ( + .CLK0(CLK0_BUF), // 0 degree DCM CLK output + .CLK180(), // 180 degree DCM CLK output + .CLK270(), // 270 degree DCM CLK output + .CLK2X(), // 2X DCM CLK output + .CLK2X180(), // 2X, 180 degree DCM CLK out + .CLK90(), // 90 degree DCM CLK output + .CLKDV(CLKDV_BUF), // Divided DCM CLK out (CLKDV_DIVIDE) + .CLKFX(), // DCM CLK synthesis out (M/D) + .CLKFX180(), // 180 degree CLK synthesis out + .DO(), // 16-bit data output for Dynamic Reconfiguration Port (DRP) + .DRDY(), // Ready output signal from the DRP + .LOCKED(), // DCM LOCK status output + .PSDONE(), // Dynamic phase adjust done output + .CLKFB(CLKFB_IN), // DCM clock feedback + .CLKIN(CLKIN_IBUFG), // Clock input (from IBUFG, BUFG or DCM) + .DADDR(7'h00), // 7-bit address for the DRP + .DCLK(1'b0), // Clock for the DRP + .DEN(1'b0), // Enable input for the DRP + .DI(16'h0000), // 16-bit data input for the DRP + .DWE(1'b0), // Active high allows for writing configuration memory + .PSCLK(1'b0), // Dynamic phase adjust clock input + .PSEN(1'b0), // Dynamic phase adjust enable input + .PSINCDEC(1'b0), // Dynamic phase adjust increment/decrement + .RST(1'b0) // DCM asynchronous reset input +); + +`endif // !XILINX_DLL/XILINX_DCM/XILINX_DCM_SP/XILINX_DCM_ADV +`endif // !XILINX_FPGA + + +endmodule Index: release-1.0/rtl/verilog/minsoc_top.v =================================================================== --- release-1.0/rtl/verilog/minsoc_top.v (nonexistent) +++ release-1.0/rtl/verilog/minsoc_top.v (revision 151) @@ -0,0 +1,998 @@ +`include "minsoc_defines.v" +`include "or1200_defines.v" + +module minsoc_top ( + clk,reset + + //JTAG ports +`ifdef GENERIC_TAP + , jtag_tdi,jtag_tms,jtag_tck, + jtag_tdo,jtag_vref,jtag_gnd +`endif + + //SPI ports +`ifdef START_UP + , spi_flash_mosi, spi_flash_miso, spi_flash_sclk, spi_flash_ss +`endif + + //UART ports +`ifdef UART + , uart_stx,uart_srx +`endif + + // Ethernet ports +`ifdef ETHERNET + , eth_col, eth_crs, eth_trste, eth_tx_clk, + eth_tx_en, eth_tx_er, eth_txd, eth_rx_clk, + eth_rx_dv, eth_rx_er, eth_rxd, eth_fds_mdint, + eth_mdc, eth_mdio +`endif +); + +// +// I/O Ports +// + + input clk; + input reset; + +// +// SPI controller external i/f wires +// +`ifdef START_UP +output spi_flash_mosi; +input spi_flash_miso; +output spi_flash_sclk; +output [1:0] spi_flash_ss; +`endif + +// +// UART +// +`ifdef UART + output uart_stx; + input uart_srx; +`endif + +// +// Ethernet +// +`ifdef ETHERNET +output eth_tx_er; +input eth_tx_clk; +output eth_tx_en; +output [3:0] eth_txd; +input eth_rx_er; +input eth_rx_clk; +input eth_rx_dv; +input [3:0] eth_rxd; +input eth_col; +input eth_crs; +output eth_trste; +input eth_fds_mdint; +inout eth_mdio; +output eth_mdc; +`endif + +// +// JTAG +// +`ifdef GENERIC_TAP + input jtag_tdi; + input jtag_tms; + input jtag_tck; + output jtag_tdo; + output jtag_vref; + output jtag_gnd; + + +assign jtag_vref = 1'b1; +assign jtag_gnd = 1'b0; +`endif + +wire rstn; + +`ifdef POSITIVE_RESET +assign rstn = ~reset; +`elsif NEGATIVE_RESET +assign rstn = reset; +`endif + +// +// Internal wires +// + +// +// Debug core master i/f wires +// +wire [31:0] wb_dm_adr_o; +wire [31:0] wb_dm_dat_i; +wire [31:0] wb_dm_dat_o; +wire [3:0] wb_dm_sel_o; +wire wb_dm_we_o; +wire wb_dm_stb_o; +wire wb_dm_cyc_o; +wire wb_dm_ack_i; +wire wb_dm_err_i; + +// +// Debug <-> RISC wires +// +wire [3:0] dbg_lss; +wire [1:0] dbg_is; +wire [10:0] dbg_wp; +wire dbg_bp; +wire [31:0] dbg_dat_dbg; +wire [31:0] dbg_dat_risc; +wire [31:0] dbg_adr; +wire dbg_ewt; +wire dbg_stall; +wire dbg_we; +wire dbg_stb; +wire dbg_ack; + +// +// RISC instruction master i/f wires +// +wire [31:0] wb_rim_adr_o; +wire wb_rim_cyc_o; +wire [31:0] wb_rim_dat_i; +wire [31:0] wb_rim_dat_o; +wire [3:0] wb_rim_sel_o; +wire wb_rim_ack_i; +wire wb_rim_err_i; +wire wb_rim_rty_i = 1'b0; +wire wb_rim_we_o; +wire wb_rim_stb_o; +wire [31:0] wb_rif_dat_i; +wire wb_rif_ack_i; + +// +// RISC data master i/f wires +// +wire [31:0] wb_rdm_adr_o; +wire wb_rdm_cyc_o; +wire [31:0] wb_rdm_dat_i; +wire [31:0] wb_rdm_dat_o; +wire [3:0] wb_rdm_sel_o; +wire wb_rdm_ack_i; +wire wb_rdm_err_i; +wire wb_rdm_rty_i = 1'b0; +wire wb_rdm_we_o; +wire wb_rdm_stb_o; + +// +// RISC misc +// +wire [`OR1200_PIC_INTS-1:0] pic_ints; + +// +// Flash controller slave i/f wires +// +wire [31:0] wb_fs_dat_i; +wire [31:0] wb_fs_dat_o; +wire [31:0] wb_fs_adr_i; +wire [3:0] wb_fs_sel_i; +wire wb_fs_we_i; +wire wb_fs_cyc_i; +wire wb_fs_stb_i; +wire wb_fs_ack_o; +wire wb_fs_err_o; + +// +// SPI controller slave i/f wires +// +wire [31:0] wb_sp_dat_i; +wire [31:0] wb_sp_dat_o; +wire [31:0] wb_sp_adr_i; +wire [3:0] wb_sp_sel_i; +wire wb_sp_we_i; +wire wb_sp_cyc_i; +wire wb_sp_stb_i; +wire wb_sp_ack_o; +wire wb_sp_err_o; + +// +// SPI controller external i/f wires +// +wire spi_flash_mosi; +wire spi_flash_miso; +wire spi_flash_sclk; +wire [1:0] spi_flash_ss; + +// +// SRAM controller slave i/f wires +// +wire [31:0] wb_ss_dat_i; +wire [31:0] wb_ss_dat_o; +wire [31:0] wb_ss_adr_i; +wire [3:0] wb_ss_sel_i; +wire wb_ss_we_i; +wire wb_ss_cyc_i; +wire wb_ss_stb_i; +wire wb_ss_ack_o; +wire wb_ss_err_o; + +// +// Ethernet core master i/f wires +// +wire [31:0] wb_em_adr_o; +wire [31:0] wb_em_dat_i; +wire [31:0] wb_em_dat_o; +wire [3:0] wb_em_sel_o; +wire wb_em_we_o; +wire wb_em_stb_o; +wire wb_em_cyc_o; +wire wb_em_ack_i; +wire wb_em_err_i; + +// +// Ethernet core slave i/f wires +// +wire [31:0] wb_es_dat_i; +wire [31:0] wb_es_dat_o; +wire [31:0] wb_es_adr_i; +wire [3:0] wb_es_sel_i; +wire wb_es_we_i; +wire wb_es_cyc_i; +wire wb_es_stb_i; +wire wb_es_ack_o; +wire wb_es_err_o; + +// +// Ethernet external i/f wires +// +wire eth_mdo; +wire eth_mdoe; + +// +// UART16550 core slave i/f wires +// +wire [31:0] wb_us_dat_i; +wire [31:0] wb_us_dat_o; +wire [31:0] wb_us_adr_i; +wire [3:0] wb_us_sel_i; +wire wb_us_we_i; +wire wb_us_cyc_i; +wire wb_us_stb_i; +wire wb_us_ack_o; +wire wb_us_err_o; + +// +// UART external i/f wires +// +wire uart_stx; +wire uart_srx; + +// +// Reset debounce +// +reg rst_r; +reg wb_rst; + +// +// Global clock +// +wire wb_clk; + +// +// Reset debounce +// +always @(posedge wb_clk or negedge rstn) + if (~rstn) + rst_r <= 1'b1; + else + rst_r <= #1 1'b0; + +// +// Reset debounce +// +always @(posedge wb_clk) + wb_rst <= #1 rst_r; + +// +// Clock Divider +// +minsoc_clock_manager # +( + .divisor(`CLOCK_DIVISOR) +) +clk_adjust ( + .clk_i(clk), + .clk_o(wb_clk) +); + +// +// Unused WISHBONE signals +// +assign wb_us_err_o = 1'b0; +assign wb_fs_err_o = 1'b0; +assign wb_sp_err_o = 1'b0; + +// +// Unused interrupts +// +assign pic_ints[`APP_INT_RES1] = 'b0; +assign pic_ints[`APP_INT_RES2] = 'b0; +assign pic_ints[`APP_INT_RES3] = 'b0; +assign pic_ints[`APP_INT_PS2] = 'b0; + +// +// Ethernet tri-state +// +`ifdef ETHERNET +assign eth_mdio = eth_mdoe ? eth_mdo : 1'bz; +assign eth_trste = `ETH_RESET; +`endif + + +// +// RISC Instruction address for Flash +// +// Until first access to real Flash area, +// CPU instruction is fixed to jump to the Flash area. +// After Flash area is accessed, CPU instructions +// come from the tc_top (wishbone "switch"). +// +`ifdef START_UP +reg jump_flash; +reg [3:0] rif_counter; +reg [31:0] rif_dat_int; +reg rif_ack_int; + +always @(posedge wb_clk or negedge rstn) +begin + if (!rstn) begin + jump_flash <= #1 1'b1; + rif_counter <= 4'h0; + rif_ack_int <= 1'b0; + end + else begin + rif_ack_int <= 1'b0; + + if (wb_rim_cyc_o && (wb_rim_adr_o[31:32-`APP_ADDR_DEC_W] == `APP_ADDR_FLASH)) + jump_flash <= #1 1'b0; + + if ( jump_flash == 1'b1 ) begin + if ( wb_rim_cyc_o && wb_rim_stb_o && ~wb_rim_we_o ) + rif_ack_int <= 1'b1; + + if ( rif_ack_int == 1'b1 ) begin + rif_counter <= rif_counter + 1'b1; + rif_ack_int <= 1'b0; + end + end + end +end + +always @ (rif_counter) +begin + case ( rif_counter ) + 4'h0: rif_dat_int = { `OR1200_OR32_MOVHI , 5'h01 , 4'h0 , 1'b0 , `APP_ADDR_FLASH , 8'h00 }; + 4'h1: rif_dat_int = { `OR1200_OR32_ORI , 5'h01 , 5'h01 , 16'h0000 }; + 4'h2: rif_dat_int = { `OR1200_OR32_JR , 10'h000 , 5'h01 , 11'h000 }; + 4'h3: rif_dat_int = { `OR1200_OR32_NOP , 10'h000 , 16'h0000 }; + default: rif_dat_int = 32'h0000_0000; + endcase +end + +assign wb_rif_dat_i = jump_flash ? rif_dat_int : wb_rim_dat_i; + +assign wb_rif_ack_i = jump_flash ? rif_ack_int : wb_rim_ack_i; + +`else +assign wb_rif_dat_i = wb_rim_dat_i; +assign wb_rif_ack_i = wb_rim_ack_i; +`endif + + +// +// TAP<->dbg_interface +// +wire jtag_tck; +wire debug_tdi; +wire debug_tdo; +wire capture_dr; +wire shift_dr; +wire pause_dr; +wire update_dr; + +wire debug_select; +wire test_logic_reset; + +// +// Instantiation of the development i/f +// +adbg_top dbg_top ( + + // JTAG pins + .tck_i ( jtag_tck ), + .tdi_i ( debug_tdi ), + .tdo_o ( debug_tdo ), + .rst_i ( test_logic_reset ), //cable without rst + + // Boundary Scan signals + .capture_dr_i ( capture_dr ), + .shift_dr_i ( shift_dr ), + .pause_dr_i ( pause_dr ), + .update_dr_i ( update_dr ), + + .debug_select_i( debug_select ), + // WISHBONE common + .wb_clk_i ( wb_clk ), + + // WISHBONE master interface + .wb_adr_o ( wb_dm_adr_o ), + .wb_dat_i ( wb_dm_dat_i ), + .wb_dat_o ( wb_dm_dat_o ), + .wb_sel_o ( wb_dm_sel_o ), + .wb_we_o ( wb_dm_we_o ), + .wb_stb_o ( wb_dm_stb_o ), + .wb_cyc_o ( wb_dm_cyc_o ), + .wb_ack_i ( wb_dm_ack_i ), + .wb_err_i ( wb_dm_err_i ), + .wb_cti_o ( ), + .wb_bte_o ( ), + + // RISC signals + .cpu0_clk_i ( wb_clk ), + .cpu0_addr_o ( dbg_adr ), + .cpu0_data_i ( dbg_dat_risc ), + .cpu0_data_o ( dbg_dat_dbg ), + .cpu0_bp_i ( dbg_bp ), + .cpu0_stall_o( dbg_stall ), + .cpu0_stb_o ( dbg_stb ), + .cpu0_we_o ( dbg_we ), + .cpu0_ack_i ( dbg_ack ), + .cpu0_rst_o ( ) + +); + +// +// JTAG TAP controller instantiation +// +`ifdef GENERIC_TAP +tap_top tap_top( + // JTAG pads + .tms_pad_i(jtag_tms), + .tck_pad_i(jtag_tck), + .trstn_pad_i(rstn), + .tdi_pad_i(jtag_tdi), + .tdo_pad_o(jtag_tdo), + .tdo_padoe_o( ), + + // TAP states + .test_logic_reset_o( test_logic_reset ), + .run_test_idle_o(), + .shift_dr_o(shift_dr), + .pause_dr_o(pause_dr), + .update_dr_o(update_dr), + .capture_dr_o(capture_dr), + + // Select signals for boundary scan or mbist + .extest_select_o(), + .sample_preload_select_o(), + .mbist_select_o(), + .debug_select_o(debug_select), + + // TDO signal that is connected to TDI of sub-modules. + .tdi_o(debug_tdi), + + // TDI signals from sub-modules + .debug_tdo_i(debug_tdo), // from debug module + .bs_chain_tdo_i(1'b0), // from Boundary Scan Chain + .mbist_tdo_i(1'b0) // from Mbist Chain +); +`elsif FPGA_TAP +`ifdef ALTERA_FPGA +altera_virtual_jtag tap_top( + .tck_o(jtag_tck), + .debug_tdo_i(debug_tdo), + .tdi_o(debug_tdi), + .test_logic_reset_o(test_logic_reset), + .run_test_idle_o(), + .shift_dr_o(shift_dr), + .capture_dr_o(capture_dr), + .pause_dr_o(pause_dr), + .update_dr_o(update_dr), + .debug_select_o(debug_select) +); +`elsif XILINX_FPGA +minsoc_xilinx_internal_jtag tap_top( + .tck_o( jtag_tck ), + .debug_tdo_i( debug_tdo ), + .tdi_o( debug_tdi ), + + .test_logic_reset_o( test_logic_reset ), + .run_test_idle_o( ), + + .shift_dr_o( shift_dr ), + .capture_dr_o( capture_dr ), + .pause_dr_o( pause_dr ), + .update_dr_o( update_dr ), + .debug_select_o( debug_select ) +); +`endif // !FPGA_TAP + +`endif // !GENERIC_TAP + +// +// Instantiation of the OR1200 RISC +// +or1200_top or1200_top ( + + // Common + .rst_i ( wb_rst ), + .clk_i ( wb_clk ), +`ifdef OR1200_CLMODE_1TO2 + .clmode_i ( 2'b01 ), +`else +`ifdef OR1200_CLMODE_1TO4 + .clmode_i ( 2'b11 ), +`else + .clmode_i ( 2'b00 ), +`endif +`endif + + // WISHBONE Instruction Master + .iwb_clk_i ( wb_clk ), + .iwb_rst_i ( wb_rst ), + .iwb_cyc_o ( wb_rim_cyc_o ), + .iwb_adr_o ( wb_rim_adr_o ), + .iwb_dat_i ( wb_rif_dat_i ), + .iwb_dat_o ( wb_rim_dat_o ), + .iwb_sel_o ( wb_rim_sel_o ), + .iwb_ack_i ( wb_rif_ack_i ), + .iwb_err_i ( wb_rim_err_i ), + .iwb_rty_i ( wb_rim_rty_i ), + .iwb_we_o ( wb_rim_we_o ), + .iwb_stb_o ( wb_rim_stb_o ), + + // WISHBONE Data Master + .dwb_clk_i ( wb_clk ), + .dwb_rst_i ( wb_rst ), + .dwb_cyc_o ( wb_rdm_cyc_o ), + .dwb_adr_o ( wb_rdm_adr_o ), + .dwb_dat_i ( wb_rdm_dat_i ), + .dwb_dat_o ( wb_rdm_dat_o ), + .dwb_sel_o ( wb_rdm_sel_o ), + .dwb_ack_i ( wb_rdm_ack_i ), + .dwb_err_i ( wb_rdm_err_i ), + .dwb_rty_i ( wb_rdm_rty_i ), + .dwb_we_o ( wb_rdm_we_o ), + .dwb_stb_o ( wb_rdm_stb_o ), + + // Debug + .dbg_stall_i ( dbg_stall ), + .dbg_dat_i ( dbg_dat_dbg ), + .dbg_adr_i ( dbg_adr ), + .dbg_ewt_i ( 1'b0 ), + .dbg_lss_o ( dbg_lss ), + .dbg_is_o ( dbg_is ), + .dbg_wp_o ( dbg_wp ), + .dbg_bp_o ( dbg_bp ), + .dbg_dat_o ( dbg_dat_risc ), + .dbg_ack_o ( dbg_ack ), + .dbg_stb_i ( dbg_stb ), + .dbg_we_i ( dbg_we ), + + // Power Management + .pm_clksd_o ( ), + .pm_cpustall_i ( 1'b0 ), + .pm_dc_gate_o ( ), + .pm_ic_gate_o ( ), + .pm_dmmu_gate_o ( ), + .pm_immu_gate_o ( ), + .pm_tt_gate_o ( ), + .pm_cpu_gate_o ( ), + .pm_wakeup_o ( ), + .pm_lvolt_o ( ), + + // Interrupts + .pic_ints_i ( pic_ints ) +); + +// +// Startup OR1k +// +`ifdef START_UP +OR1K_startup OR1K_startup0 +( + .wb_adr_i(wb_fs_adr_i[6:2]), + .wb_stb_i(wb_fs_stb_i), + .wb_cyc_i(wb_fs_cyc_i), + .wb_dat_o(wb_fs_dat_o), + .wb_ack_o(wb_fs_ack_o), + .wb_clk(wb_clk), + .wb_rst(wb_rst) +); + +spi_flash_top # +( + .divider(0), + .divider_len(2) +) +spi_flash_top0 +( + .wb_clk_i(wb_clk), + .wb_rst_i(wb_rst), + .wb_adr_i(wb_sp_adr_i[4:2]), + .wb_dat_i(wb_sp_dat_i), + .wb_dat_o(wb_sp_dat_o), + .wb_sel_i(wb_sp_sel_i), + .wb_we_i(wb_sp_we_i), + .wb_stb_i(wb_sp_stb_i), + .wb_cyc_i(wb_sp_cyc_i), + .wb_ack_o(wb_sp_ack_o), + + .mosi_pad_o(spi_flash_mosi), + .miso_pad_i(spi_flash_miso), + .sclk_pad_o(spi_flash_sclk), + .ss_pad_o(spi_flash_ss) +); +`else +assign wb_fs_dat_o = 32'h0000_0000; +assign wb_fs_ack_o = 1'b0; +assign wb_sp_dat_o = 32'h0000_0000; +assign wb_sp_ack_o = 1'b0; +`endif + +// +// Instantiation of the SRAM controller +// +`ifdef MEMORY_MODEL +minsoc_memory_model # +`else +minsoc_onchip_ram_top # +`endif +( + .adr_width(`MEMORY_ADR_WIDTH) //16 blocks of 2048 bytes memory 32768 +) +onchip_ram_top ( + + // WISHBONE common + .wb_clk_i ( wb_clk ), + .wb_rst_i ( wb_rst ), + + // WISHBONE slave + .wb_dat_i ( wb_ss_dat_i ), + .wb_dat_o ( wb_ss_dat_o ), + .wb_adr_i ( wb_ss_adr_i ), + .wb_sel_i ( wb_ss_sel_i ), + .wb_we_i ( wb_ss_we_i ), + .wb_cyc_i ( wb_ss_cyc_i ), + .wb_stb_i ( wb_ss_stb_i ), + .wb_ack_o ( wb_ss_ack_o ), + .wb_err_o ( wb_ss_err_o ) +); + +// +// Instantiation of the UART16550 +// +`ifdef UART +uart_top uart_top ( + + // WISHBONE common + .wb_clk_i ( wb_clk ), + .wb_rst_i ( wb_rst ), + + // WISHBONE slave + .wb_adr_i ( wb_us_adr_i[4:0] ), + .wb_dat_i ( wb_us_dat_i ), + .wb_dat_o ( wb_us_dat_o ), + .wb_we_i ( wb_us_we_i ), + .wb_stb_i ( wb_us_stb_i ), + .wb_cyc_i ( wb_us_cyc_i ), + .wb_ack_o ( wb_us_ack_o ), + .wb_sel_i ( wb_us_sel_i ), + + // Interrupt request + .int_o ( pic_ints[`APP_INT_UART] ), + + // UART signals + // serial input/output + .stx_pad_o ( uart_stx ), + .srx_pad_i ( uart_srx ), + + // modem signals + .rts_pad_o ( ), + .cts_pad_i ( 1'b0 ), + .dtr_pad_o ( ), + .dsr_pad_i ( 1'b0 ), + .ri_pad_i ( 1'b0 ), + .dcd_pad_i ( 1'b0 ) +); +`else +assign wb_us_dat_o = 32'h0000_0000; +assign wb_us_ack_o = 1'b0; + +assign pic_ints[`APP_INT_UART] = 1'b0; +`endif + +// +// Instantiation of the Ethernet 10/100 MAC +// +`ifdef ETHERNET +ethmac ethmac ( + + // WISHBONE common + .wb_clk_i ( wb_clk ), + .wb_rst_i ( wb_rst ), + + // WISHBONE slave + .wb_dat_i ( wb_es_dat_i ), + .wb_dat_o ( wb_es_dat_o ), + .wb_adr_i ( wb_es_adr_i[11:2] ), + .wb_sel_i ( wb_es_sel_i ), + .wb_we_i ( wb_es_we_i ), + .wb_cyc_i ( wb_es_cyc_i ), + .wb_stb_i ( wb_es_stb_i ), + .wb_ack_o ( wb_es_ack_o ), + .wb_err_o ( wb_es_err_o ), + + // WISHBONE master + .m_wb_adr_o ( wb_em_adr_o ), + .m_wb_sel_o ( wb_em_sel_o ), + .m_wb_we_o ( wb_em_we_o ), + .m_wb_dat_o ( wb_em_dat_o ), + .m_wb_dat_i ( wb_em_dat_i ), + .m_wb_cyc_o ( wb_em_cyc_o ), + .m_wb_stb_o ( wb_em_stb_o ), + .m_wb_ack_i ( wb_em_ack_i ), + .m_wb_err_i ( wb_em_err_i ), + + // TX + .mtx_clk_pad_i ( eth_tx_clk ), + .mtxd_pad_o ( eth_txd ), + .mtxen_pad_o ( eth_tx_en ), + .mtxerr_pad_o ( eth_tx_er ), + + // RX + .mrx_clk_pad_i ( eth_rx_clk ), + .mrxd_pad_i ( eth_rxd ), + .mrxdv_pad_i ( eth_rx_dv ), + .mrxerr_pad_i ( eth_rx_er ), + .mcoll_pad_i ( eth_col ), + .mcrs_pad_i ( eth_crs ), + + // MIIM + .mdc_pad_o ( eth_mdc ), + .md_pad_i ( eth_mdio ), + .md_pad_o ( eth_mdo ), + .md_padoe_o ( eth_mdoe ), + + // Interrupt + .int_o ( pic_ints[`APP_INT_ETH] ) +); +`else +assign wb_es_dat_o = 32'h0000_0000; +assign wb_es_ack_o = 1'b0; +assign wb_es_err_o = 1'b0; + +assign wb_em_adr_o = 32'h0000_0000; +assign wb_em_sel_o = 4'h0; +assign wb_em_we_o = 1'b0; +assign wb_em_dat_o = 32'h0000_0000; +assign wb_em_cyc_o = 1'b0; +assign wb_em_stb_o = 1'b0; + +assign pic_ints[`APP_INT_ETH] = 1'b0; +`endif + +// +// Instantiation of the Traffic COP +// +minsoc_tc_top #(`APP_ADDR_DEC_W, + `APP_ADDR_SRAM, + `APP_ADDR_DEC_W, + `APP_ADDR_FLASH, + `APP_ADDR_DECP_W, + `APP_ADDR_PERIP, + `APP_ADDR_DEC_W, + `APP_ADDR_SPI, + `APP_ADDR_ETH, + `APP_ADDR_AUDIO, + `APP_ADDR_UART, + `APP_ADDR_PS2, + `APP_ADDR_RES1, + `APP_ADDR_RES2 + ) tc_top ( + + // WISHBONE common + .wb_clk_i ( wb_clk ), + .wb_rst_i ( wb_rst ), + + // WISHBONE Initiator 0 + .i0_wb_cyc_i ( 1'b0 ), + .i0_wb_stb_i ( 1'b0 ), + .i0_wb_adr_i ( 32'h0000_0000 ), + .i0_wb_sel_i ( 4'b0000 ), + .i0_wb_we_i ( 1'b0 ), + .i0_wb_dat_i ( 32'h0000_0000 ), + .i0_wb_dat_o ( ), + .i0_wb_ack_o ( ), + .i0_wb_err_o ( ), + + // WISHBONE Initiator 1 + .i1_wb_cyc_i ( wb_em_cyc_o ), + .i1_wb_stb_i ( wb_em_stb_o ), + .i1_wb_adr_i ( wb_em_adr_o ), + .i1_wb_sel_i ( wb_em_sel_o ), + .i1_wb_we_i ( wb_em_we_o ), + .i1_wb_dat_i ( wb_em_dat_o ), + .i1_wb_dat_o ( wb_em_dat_i ), + .i1_wb_ack_o ( wb_em_ack_i ), + .i1_wb_err_o ( wb_em_err_i ), + + // WISHBONE Initiator 2 + .i2_wb_cyc_i ( 1'b0 ), + .i2_wb_stb_i ( 1'b0 ), + .i2_wb_adr_i ( 32'h0000_0000 ), + .i2_wb_sel_i ( 4'b0000 ), + .i2_wb_we_i ( 1'b0 ), + .i2_wb_dat_i ( 32'h0000_0000 ), + .i2_wb_dat_o ( ), + .i2_wb_ack_o ( ), + .i2_wb_err_o ( ), + + // WISHBONE Initiator 3 + .i3_wb_cyc_i ( wb_dm_cyc_o ), + .i3_wb_stb_i ( wb_dm_stb_o ), + .i3_wb_adr_i ( wb_dm_adr_o ), + .i3_wb_sel_i ( wb_dm_sel_o ), + .i3_wb_we_i ( wb_dm_we_o ), + .i3_wb_dat_i ( wb_dm_dat_o ), + .i3_wb_dat_o ( wb_dm_dat_i ), + .i3_wb_ack_o ( wb_dm_ack_i ), + .i3_wb_err_o ( wb_dm_err_i ), + + // WISHBONE Initiator 4 + .i4_wb_cyc_i ( wb_rdm_cyc_o ), + .i4_wb_stb_i ( wb_rdm_stb_o ), + .i4_wb_adr_i ( wb_rdm_adr_o ), + .i4_wb_sel_i ( wb_rdm_sel_o ), + .i4_wb_we_i ( wb_rdm_we_o ), + .i4_wb_dat_i ( wb_rdm_dat_o ), + .i4_wb_dat_o ( wb_rdm_dat_i ), + .i4_wb_ack_o ( wb_rdm_ack_i ), + .i4_wb_err_o ( wb_rdm_err_i ), + + // WISHBONE Initiator 5 + .i5_wb_cyc_i ( wb_rim_cyc_o ), + .i5_wb_stb_i ( wb_rim_stb_o ), + .i5_wb_adr_i ( wb_rim_adr_o ), + .i5_wb_sel_i ( wb_rim_sel_o ), + .i5_wb_we_i ( wb_rim_we_o ), + .i5_wb_dat_i ( wb_rim_dat_o ), + .i5_wb_dat_o ( wb_rim_dat_i ), + .i5_wb_ack_o ( wb_rim_ack_i ), + .i5_wb_err_o ( wb_rim_err_i ), + + // WISHBONE Initiator 6 + .i6_wb_cyc_i ( 1'b0 ), + .i6_wb_stb_i ( 1'b0 ), + .i6_wb_adr_i ( 32'h0000_0000 ), + .i6_wb_sel_i ( 4'b0000 ), + .i6_wb_we_i ( 1'b0 ), + .i6_wb_dat_i ( 32'h0000_0000 ), + .i6_wb_dat_o ( ), + .i6_wb_ack_o ( ), + .i6_wb_err_o ( ), + + // WISHBONE Initiator 7 + .i7_wb_cyc_i ( 1'b0 ), + .i7_wb_stb_i ( 1'b0 ), + .i7_wb_adr_i ( 32'h0000_0000 ), + .i7_wb_sel_i ( 4'b0000 ), + .i7_wb_we_i ( 1'b0 ), + .i7_wb_dat_i ( 32'h0000_0000 ), + .i7_wb_dat_o ( ), + .i7_wb_ack_o ( ), + .i7_wb_err_o ( ), + + // WISHBONE Target 0 + .t0_wb_cyc_o ( wb_ss_cyc_i ), + .t0_wb_stb_o ( wb_ss_stb_i ), + .t0_wb_adr_o ( wb_ss_adr_i ), + .t0_wb_sel_o ( wb_ss_sel_i ), + .t0_wb_we_o ( wb_ss_we_i ), + .t0_wb_dat_o ( wb_ss_dat_i ), + .t0_wb_dat_i ( wb_ss_dat_o ), + .t0_wb_ack_i ( wb_ss_ack_o ), + .t0_wb_err_i ( wb_ss_err_o ), + + // WISHBONE Target 1 + .t1_wb_cyc_o ( wb_fs_cyc_i ), + .t1_wb_stb_o ( wb_fs_stb_i ), + .t1_wb_adr_o ( wb_fs_adr_i ), + .t1_wb_sel_o ( wb_fs_sel_i ), + .t1_wb_we_o ( wb_fs_we_i ), + .t1_wb_dat_o ( wb_fs_dat_i ), + .t1_wb_dat_i ( wb_fs_dat_o ), + .t1_wb_ack_i ( wb_fs_ack_o ), + .t1_wb_err_i ( wb_fs_err_o ), + + // WISHBONE Target 2 + .t2_wb_cyc_o ( wb_sp_cyc_i ), + .t2_wb_stb_o ( wb_sp_stb_i ), + .t2_wb_adr_o ( wb_sp_adr_i ), + .t2_wb_sel_o ( wb_sp_sel_i ), + .t2_wb_we_o ( wb_sp_we_i ), + .t2_wb_dat_o ( wb_sp_dat_i ), + .t2_wb_dat_i ( wb_sp_dat_o ), + .t2_wb_ack_i ( wb_sp_ack_o ), + .t2_wb_err_i ( wb_sp_err_o ), + + // WISHBONE Target 3 + .t3_wb_cyc_o ( wb_es_cyc_i ), + .t3_wb_stb_o ( wb_es_stb_i ), + .t3_wb_adr_o ( wb_es_adr_i ), + .t3_wb_sel_o ( wb_es_sel_i ), + .t3_wb_we_o ( wb_es_we_i ), + .t3_wb_dat_o ( wb_es_dat_i ), + .t3_wb_dat_i ( wb_es_dat_o ), + .t3_wb_ack_i ( wb_es_ack_o ), + .t3_wb_err_i ( wb_es_err_o ), + + // WISHBONE Target 4 + .t4_wb_cyc_o ( ), + .t4_wb_stb_o ( ), + .t4_wb_adr_o ( ), + .t4_wb_sel_o ( ), + .t4_wb_we_o ( ), + .t4_wb_dat_o ( ), + .t4_wb_dat_i ( 32'h0000_0000 ), + .t4_wb_ack_i ( 1'b0 ), + .t4_wb_err_i ( 1'b1 ), + + // WISHBONE Target 5 + .t5_wb_cyc_o ( wb_us_cyc_i ), + .t5_wb_stb_o ( wb_us_stb_i ), + .t5_wb_adr_o ( wb_us_adr_i ), + .t5_wb_sel_o ( wb_us_sel_i ), + .t5_wb_we_o ( wb_us_we_i ), + .t5_wb_dat_o ( wb_us_dat_i ), + .t5_wb_dat_i ( wb_us_dat_o ), + .t5_wb_ack_i ( wb_us_ack_o ), + .t5_wb_err_i ( wb_us_err_o ), + + // WISHBONE Target 6 + .t6_wb_cyc_o ( ), + .t6_wb_stb_o ( ), + .t6_wb_adr_o ( ), + .t6_wb_sel_o ( ), + .t6_wb_we_o ( ), + .t6_wb_dat_o ( ), + .t6_wb_dat_i ( 32'h0000_0000 ), + .t6_wb_ack_i ( 1'b0 ), + .t6_wb_err_i ( 1'b1 ), + + // WISHBONE Target 7 + .t7_wb_cyc_o ( ), + .t7_wb_stb_o ( ), + .t7_wb_adr_o ( ), + .t7_wb_sel_o ( ), + .t7_wb_we_o ( ), + .t7_wb_dat_o ( ), + .t7_wb_dat_i ( 32'h0000_0000 ), + .t7_wb_ack_i ( 1'b0 ), + .t7_wb_err_i ( 1'b1 ), + + // WISHBONE Target 8 + .t8_wb_cyc_o ( ), + .t8_wb_stb_o ( ), + .t8_wb_adr_o ( ), + .t8_wb_sel_o ( ), + .t8_wb_we_o ( ), + .t8_wb_dat_o ( ), + .t8_wb_dat_i ( 32'h0000_0000 ), + .t8_wb_ack_i ( 1'b0 ), + .t8_wb_err_i ( 1'b1 ) +); + +//initial begin +// $dumpvars(0); +// $dumpfile("dump.vcd"); +//end + +endmodule
release-1.0/rtl/verilog/minsoc_top.v Property changes : Added: svn:executable ## -0,0 +1 ## +* \ No newline at end of property Index: release-1.0/rtl/verilog/timescale.v =================================================================== --- release-1.0/rtl/verilog/timescale.v (nonexistent) +++ release-1.0/rtl/verilog/timescale.v (revision 151) @@ -0,0 +1 @@ +`timescale 10ns/1ns Index: release-1.0/rtl/verilog/altera_pll.v =================================================================== --- release-1.0/rtl/verilog/altera_pll.v (nonexistent) +++ release-1.0/rtl/verilog/altera_pll.v (revision 151) @@ -0,0 +1,158 @@ + +`include "minsoc_defines.v" + +module altera_pll ( + inclk0, + c0); + + parameter FREQ_MULT = 1; + parameter FREQ_DIV = 1; + + input inclk0; + output c0; + + +`ifdef ARRIA_GX + localparam FAMILY = "Arria GX"; +`elsif ARRIA_II_GX + localparam FAMILY = "Arria II GX"; +`elsif CYCLONE_I + localparam FAMILY = "Cyclone I"; +`elsif CYCLONE_II + localparam FAMILY = "Cyclone II"; +`elsif CYCLONE_III + localparam FAMILY = "Cyclone III"; +`elsif CYCLONE_III_LS + localparam FAMILY = "Cyclone III LS"; +`elsif CYCLONE_IV_E + localparam FAMILY = "Cyclone IV E"; +`elsif CYCLONE_IV_GS + localparam FAMILY = "Cyclone IV GS"; +`elsif MAX_II + localparam FAMILY = "MAX II"; +`elsif MAX_V + localparam FAMILY = "MAX V"; +`elsif MAX3000A + localparam FAMILY = "MAX3000A"; +`elsif MAX7000AE + localparam FAMILY = "MAX7000AE"; +`elsif MAX7000B + localparam FAMILY = "MAX7000B"; +`elsif MAX7000S + localparam FAMILY = "MAX7000S"; +`elsif STRATIX + localparam FAMILY = "Stratix"; +`elsif STRATIX_II + defapram systemPll.FAMILY = "Stratix II"; +`elsif STRATIX_II_GX + localparam FAMILY = "Stratix II GX"; +`elsif STRATIX_III + localparam FAMILY = "Stratix III" +`endif + + + wire [4:0] sub_wire0; + wire [0:0] sub_wire4 = 1'h0; + wire [0:0] sub_wire1 = sub_wire0[0:0]; + wire c0 = sub_wire1; + wire sub_wire2 = inclk0; + wire [1:0] sub_wire3 = {sub_wire4, sub_wire2}; + +`ifdef ALTERA_FPGA + altpll altpll_component ( + .inclk (sub_wire3), + .clk (sub_wire0), + .activeclock (), + .areset (1'b0), + .clkbad (), + .clkena ({6{1'b1}}), + .clkloss (), + .clkswitch (1'b0), + .configupdate (1'b0), + .enable0 (), + .enable1 (), + .extclk (), + .extclkena ({4{1'b1}}), + .fbin (1'b1), + .fbmimicbidir (), + .fbout (), + .fref (), + .icdrclk (), + .locked (), + .pfdena (1'b1), + .phasecounterselect ({4{1'b1}}), + .phasedone (), + .phasestep (1'b1), + .phaseupdown (1'b1), + .pllena (1'b1), + .scanaclr (1'b0), + .scanclk (1'b0), + .scanclkena (1'b1), + .scandata (1'b0), + .scandataout (), + .scandone (), + .scanread (1'b0), + .scanwrite (1'b0), + .sclkout0 (), + .sclkout1 (), + .vcooverrange (), + .vcounderrange ()); + defparam + altpll_component.bandwidth_type = "AUTO", + altpll_component.clk0_divide_by = FREQ_DIV, + altpll_component.clk0_duty_cycle = 50, + altpll_component.clk0_multiply_by = FREQ_MULT, + altpll_component.clk0_phase_shift = "0", + altpll_component.compensate_clock = "CLK0", + altpll_component.inclk0_input_frequency = 20000, + altpll_component.intended_device_family = FAMILY, + altpll_component.lpm_hint = "CBX_MODULE_PREFIX=minsocPll", + altpll_component.lpm_type = "altpll", + altpll_component.operation_mode = "NORMAL", + altpll_component.pll_type = "AUTO", + altpll_component.port_activeclock = "PORT_UNUSED", + altpll_component.port_areset = "PORT_UNUSED", + altpll_component.port_clkbad0 = "PORT_UNUSED", + altpll_component.port_clkbad1 = "PORT_UNUSED", + altpll_component.port_clkloss = "PORT_UNUSED", + altpll_component.port_clkswitch = "PORT_UNUSED", + altpll_component.port_configupdate = "PORT_UNUSED", + altpll_component.port_fbin = "PORT_UNUSED", + altpll_component.port_inclk0 = "PORT_USED", + altpll_component.port_inclk1 = "PORT_UNUSED", + altpll_component.port_locked = "PORT_UNUSED", + altpll_component.port_pfdena = "PORT_UNUSED", + altpll_component.port_phasecounterselect = "PORT_UNUSED", + altpll_component.port_phasedone = "PORT_UNUSED", + altpll_component.port_phasestep = "PORT_UNUSED", + altpll_component.port_phaseupdown = "PORT_UNUSED", + altpll_component.port_pllena = "PORT_UNUSED", + altpll_component.port_scanaclr = "PORT_UNUSED", + altpll_component.port_scanclk = "PORT_UNUSED", + altpll_component.port_scanclkena = "PORT_UNUSED", + altpll_component.port_scandata = "PORT_UNUSED", + altpll_component.port_scandataout = "PORT_UNUSED", + altpll_component.port_scandone = "PORT_UNUSED", + altpll_component.port_scanread = "PORT_UNUSED", + altpll_component.port_scanwrite = "PORT_UNUSED", + altpll_component.port_clk0 = "PORT_USED", + altpll_component.port_clk1 = "PORT_UNUSED", + altpll_component.port_clk2 = "PORT_UNUSED", + altpll_component.port_clk3 = "PORT_UNUSED", + altpll_component.port_clk4 = "PORT_UNUSED", + altpll_component.port_clk5 = "PORT_UNUSED", + altpll_component.port_clkena0 = "PORT_UNUSED", + altpll_component.port_clkena1 = "PORT_UNUSED", + altpll_component.port_clkena2 = "PORT_UNUSED", + altpll_component.port_clkena3 = "PORT_UNUSED", + altpll_component.port_clkena4 = "PORT_UNUSED", + altpll_component.port_clkena5 = "PORT_UNUSED", + altpll_component.port_extclk0 = "PORT_UNUSED", + altpll_component.port_extclk1 = "PORT_UNUSED", + altpll_component.port_extclk2 = "PORT_UNUSED", + altpll_component.port_extclk3 = "PORT_UNUSED", + altpll_component.width_clock = 5; +`endif + +endmodule + Index: release-1.0/rtl/verilog/minsoc_clock_manager.v =================================================================== --- release-1.0/rtl/verilog/minsoc_clock_manager.v (nonexistent) +++ release-1.0/rtl/verilog/minsoc_clock_manager.v (revision 151) @@ -0,0 +1,60 @@ + +`include "minsoc_defines.v" + +module minsoc_clock_manager( + clk_i, + clk_o +); + +// +// Parameters +// + parameter divisor = 2; + +input clk_i; +output clk_o; + +`ifdef NO_CLOCK_DIVISION +assign clk_o = clk_i; + +`elsif GENERIC_CLOCK_DIVISION +reg [31:0] clock_divisor; +reg clk_int; +always @ (posedge clk_i) +begin + clock_divisor <= clock_divisor + 1'b1; + if ( clock_divisor >= divisor/2 - 1 ) begin + clk_int <= ~clk_int; + clock_divisor <= 32'h0000_0000; + end +end +assign clk_o = clk_int; + +`elsif FPGA_CLOCK_DIVISION +`ifdef ALTERA_FPGA +altera_pll # +( + .FREQ_DIV(divisor) +) +minsoc_altera_pll +( + .inclk0(clk_i), + .c0(clk_o) +); + +`elsif XILINX_FPGA +xilinx_dcm # +( + .divisor(divisor) +) +minsoc_xilinx_dcm +( + .clk_i(clk_i), + .clk_o(clk_o) +); + +`endif // !ALTERA_FPGA/XILINX_FPGA +`endif // !NO_CLOCK_DIVISION/GENERIC_CLOCK_DIVISION/FPGA_CLOCK_DIVISION + + +endmodule
release-1.0/rtl/verilog/minsoc_clock_manager.v Property changes : Added: svn:executable ## -0,0 +1 ## +* \ No newline at end of property Index: release-1.0/rtl/verilog/minsoc_startup/spi_top.v =================================================================== --- release-1.0/rtl/verilog/minsoc_startup/spi_top.v (nonexistent) +++ release-1.0/rtl/verilog/minsoc_startup/spi_top.v (revision 151) @@ -0,0 +1,224 @@ +////////////////////////////////////////////////////////////////////// +//// //// +//// spi_top.v //// +//// //// +//// This file is part of the SPI IP core project //// +//// http://www.opencores.org/projects/spi/ //// +//// //// +//// Author(s): //// +//// - Simon Srot (simons@opencores.org) //// +//// //// +//// All additional information is avaliable in the Readme.txt //// +//// file. //// +//// //// +////////////////////////////////////////////////////////////////////// +//// //// +//// Copyright (C) 2002 Authors //// +//// //// +//// This source file may be used and distributed without //// +//// restriction provided that this copyright statement is not //// +//// removed from the file and that any derivative work contains //// +//// the original copyright notice and the associated disclaimer. //// +//// //// +//// This source file is free software; you can redistribute it //// +//// and/or modify it under the terms of the GNU Lesser General //// +//// Public License as published by the Free Software Foundation; //// +//// either version 2.1 of the License, or (at your option) any //// +//// later version. //// +//// //// +//// This source is distributed in the hope that it will be //// +//// useful, but WITHOUT ANY WARRANTY; without even the implied //// +//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR //// +//// PURPOSE. See the GNU Lesser General Public License for more //// +//// details. //// +//// //// +//// You should have received a copy of the GNU Lesser General //// +//// Public License along with this source; if not, download it //// +//// from http://www.opencores.org/lgpl.shtml //// +//// //// +////////////////////////////////////////////////////////////////////// + + +`include "spi_defines.v" +`include "timescale.v" + +module spi_flash_top + ( + // Wishbone signals + wb_clk_i, wb_rst_i, wb_adr_i, wb_dat_i, wb_dat_o, wb_sel_i, + wb_we_i, wb_stb_i, wb_cyc_i, wb_ack_o, + // SPI signals + ss_pad_o, sclk_pad_o, mosi_pad_o, miso_pad_i + ); + + parameter divider_len = 2; + parameter divider = 0; + + parameter Tp = 1; + + // Wishbone signals + input wb_clk_i; // master clock input + input wb_rst_i; // synchronous active high reset + input [4:2] wb_adr_i; // lower address bits + input [31:0] wb_dat_i; // databus input + output [31:0] wb_dat_o; // databus output + input [3:0] wb_sel_i; // byte select inputs + input wb_we_i; // write enable input + input wb_stb_i; // stobe/core select signal + input wb_cyc_i; // valid bus cycle input + output wb_ack_o; // bus cycle acknowledge output + + // SPI signals + output [`SPI_SS_NB-1:0] ss_pad_o; // slave select + output sclk_pad_o; // serial clock + output mosi_pad_o; // master out slave in + input miso_pad_i; // master in slave out + + reg [31:0] wb_dat_o; + reg wb_ack_o; + + // Internal signals + // reg [`SPI_DIVIDER_LEN-1:0] divider; // Divider register + wire [`SPI_CTRL_BIT_NB-1:0] ctrl; // Control and status register + reg [`SPI_SS_NB-1:0] ss; // Slave select register + wire [`SPI_MAX_CHAR-1:0] rx; // Rx register + + wire [5:0] char_len; + reg char_len_ctrl; // char len + reg go; // go + + wire spi_ctrl_sel; // ctrl register select + wire spi_tx_sel; // tx_l register select + wire spi_ss_sel; // ss register select + wire tip; // transfer in progress + wire pos_edge; // recognize posedge of sclk + wire neg_edge; // recognize negedge of sclk + wire last_bit; // marks last character bit + + wire rx_negedge; // miso is sampled on negative edge + wire tx_negedge; // mosi is driven on negative edge + wire lsb; // lsb first on line + wire ass; // automatic slave select + + // Address decoder + assign spi_ctrl_sel = wb_cyc_i & wb_stb_i & (wb_adr_i[`SPI_OFS_BITS] == `SPI_CTRL); + assign spi_tx_sel = wb_cyc_i & wb_stb_i & (wb_adr_i[`SPI_OFS_BITS] == `SPI_TX_0); + assign spi_ss_sel = wb_cyc_i & wb_stb_i & (wb_adr_i[`SPI_OFS_BITS] == `SPI_SS); + + // Read from registers + // Wb data out + always @(posedge wb_clk_i or posedge wb_rst_i) + begin + if (wb_rst_i) + wb_dat_o <= #Tp 32'b0; + else + case (wb_adr_i[`SPI_OFS_BITS]) + `SPI_RX_0: wb_dat_o <= rx; + `SPI_CTRL: wb_dat_o <= {18'd0, ctrl}; + `SPI_DEVIDE: wb_dat_o <= divider; + `SPI_SS: wb_dat_o <= {{32-`SPI_SS_NB{1'b0}}, ss}; + default: wb_dat_o <= rx; + endcase + end + + // Wb acknowledge + always @(posedge wb_clk_i or posedge wb_rst_i) + begin + if (wb_rst_i) + wb_ack_o <= #Tp 1'b0; + else + wb_ack_o <= #Tp wb_cyc_i & wb_stb_i & ~wb_ack_o; + end + + // Ctrl register + always @(posedge wb_clk_i or posedge wb_rst_i) + begin + if (wb_rst_i) + {go,char_len_ctrl} <= #Tp 2'b01; + else if(spi_ctrl_sel && wb_we_i && !tip) + begin + if (wb_sel_i[0]) + char_len_ctrl <= #Tp wb_dat_i[5]; + if (wb_sel_i[1]) + go <= #Tp wb_dat_i[8]; + end + else if(tip && last_bit && pos_edge) + go <= #Tp 1'b0; + end + + assign char_len = char_len_ctrl ? 6'd32 : 6'd8; +`ifdef SPI_CTRL_ASS + assign ass = 1'b1; +`else + assign ass = 1'b0; +`endif +`ifdef SPI_CTRL_LSB + assign lsb = 1'b1; +`else + assign lsb = 1'b0; +`endif +`ifdef SPI_CTRL_RX_NEGEDGE + assign rx_negedge = 1'b1; +`else + assign rx_negedge = 1'b0; +`endif +`ifdef SPI_CTRL_TX_NEGEDGE + assign tx_negedge = 1'b1; +`else + assign tx_negedge = 1'b0; +`endif + + assign ctrl = {ass,1'b0,lsb,tx_negedge,rx_negedge,go,1'b0,1'b0,char_len}; + + // Slave select register + always @(posedge wb_clk_i or posedge wb_rst_i) + if (wb_rst_i) + ss <= #Tp {`SPI_SS_NB{1'b0}}; + else if(spi_ss_sel && wb_we_i && !tip) + if (wb_sel_i[0]) + ss <= #Tp wb_dat_i[`SPI_SS_NB-1:0]; + + assign ss_pad_o = ~((ss & {`SPI_SS_NB{tip & ass}}) | (ss & {`SPI_SS_NB{!ass}})); + + spi_flash_clgen + # + ( + .divider_len(divider_len), + .divider(divider) + ) + clgen + ( + .clk_in(wb_clk_i), + .rst(wb_rst_i), + .go(go), + .enable(tip), + .last_clk(last_bit), + .clk_out(sclk_pad_o), + .pos_edge(pos_edge), + .neg_edge(neg_edge) + ); + + spi_flash_shift shift + ( + .clk(wb_clk_i), + .rst(wb_rst_i), + .len(char_len[`SPI_CHAR_LEN_BITS-1:0]), + .latch(spi_tx_sel & wb_we_i), + .byte_sel(wb_sel_i), + .go(go), + .pos_edge(pos_edge), + .neg_edge(neg_edge), + .lsb(lsb), + .rx_negedge(rx_negedge), + .tx_negedge(tx_negedge), + .tip(tip), + .last(last_bit), + .p_in(wb_dat_i), + .p_out(rx), + .s_clk(sclk_pad_o), + .s_in(miso_pad_i), + .s_out(mosi_pad_o) + ); + +endmodule +
release-1.0/rtl/verilog/minsoc_startup/spi_top.v Property changes : Added: svn:executable ## -0,0 +1 ## +* \ No newline at end of property Index: release-1.0/rtl/verilog/minsoc_startup/spi_clgen.v =================================================================== --- release-1.0/rtl/verilog/minsoc_startup/spi_clgen.v (nonexistent) +++ release-1.0/rtl/verilog/minsoc_startup/spi_clgen.v (revision 151) @@ -0,0 +1,110 @@ +////////////////////////////////////////////////////////////////////// +//// //// +//// spi_clgen.v //// +//// //// +//// This file is part of the SPI IP core project //// +//// http://www.opencores.org/projects/spi/ //// +//// //// +//// Author(s): //// +//// - Simon Srot (simons@opencores.org) //// +//// //// +//// All additional information is avaliable in the Readme.txt //// +//// file. //// +//// //// +////////////////////////////////////////////////////////////////////// +//// //// +//// Copyright (C) 2002 Authors //// +//// //// +//// This source file may be used and distributed without //// +//// restriction provided that this copyright statement is not //// +//// removed from the file and that any derivative work contains //// +//// the original copyright notice and the associated disclaimer. //// +//// //// +//// This source file is free software; you can redistribute it //// +//// and/or modify it under the terms of the GNU Lesser General //// +//// Public License as published by the Free Software Foundation; //// +//// either version 2.1 of the License, or (at your option) any //// +//// later version. //// +//// //// +//// This source is distributed in the hope that it will be //// +//// useful, but WITHOUT ANY WARRANTY; without even the implied //// +//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR //// +//// PURPOSE. See the GNU Lesser General Public License for more //// +//// details. //// +//// //// +//// You should have received a copy of the GNU Lesser General //// +//// Public License along with this source; if not, download it //// +//// from http://www.opencores.org/lgpl.shtml //// +//// //// +////////////////////////////////////////////////////////////////////// + +`include "spi_defines.v" +`include "timescale.v" + +module spi_flash_clgen (clk_in, rst, go, enable, last_clk, clk_out, pos_edge, neg_edge); + + parameter divider_len = 2; + parameter divider = 1; + + parameter Tp = 1; + + input clk_in; // input clock (system clock) + input rst; // reset + input enable; // clock enable + input go; // start transfer + input last_clk; // last clock + //input [spi_divider_len-1:0] divider; // clock divider (output clock is divided by this value) + output clk_out; // output clock + output pos_edge; // pulse marking positive edge of clk_out + output neg_edge; // pulse marking negative edge of clk_out + + reg clk_out; + reg pos_edge; + reg neg_edge; + + reg [divider_len-1:0] cnt; // clock counter + wire cnt_zero; // conter is equal to zero + wire cnt_one; // conter is equal to one + + + assign cnt_zero = cnt == {divider_len{1'b0}}; + assign cnt_one = cnt == {{divider_len-1{1'b0}}, 1'b1}; + + // Counter counts half period + always @(posedge clk_in or posedge rst) + begin + if(rst) + cnt <= #Tp {divider_len{1'b1}}; + else + begin + if(!enable || cnt_zero) + cnt <= #Tp divider; + else + cnt <= #Tp cnt - {{divider_len-1{1'b0}}, 1'b1}; + end + end + + // clk_out is asserted every other half period + always @(posedge clk_in or posedge rst) + begin + if(rst) + clk_out <= #Tp 1'b0; + else + clk_out <= #Tp (enable && cnt_zero && (!last_clk || clk_out)) ? ~clk_out : clk_out; + end + + // Pos and neg edge signals + always @(posedge clk_in or posedge rst) + begin + if(rst) + begin + pos_edge <= #Tp 1'b0; + neg_edge <= #Tp 1'b0; + end + else + begin + pos_edge <= #Tp (enable && !clk_out && cnt_one) || (!(|divider) && clk_out) || (!(|divider) && go && !enable); + neg_edge <= #Tp (enable && clk_out && cnt_one) || (!(|divider) && !clk_out && enable); + end + end +endmodule
release-1.0/rtl/verilog/minsoc_startup/spi_clgen.v Property changes : Added: svn:executable ## -0,0 +1 ## +* \ No newline at end of property Index: release-1.0/rtl/verilog/minsoc_startup/spi_shift.v =================================================================== --- release-1.0/rtl/verilog/minsoc_startup/spi_shift.v (nonexistent) +++ release-1.0/rtl/verilog/minsoc_startup/spi_shift.v (revision 151) @@ -0,0 +1,149 @@ +////////////////////////////////////////////////////////////////////// +//// //// +//// spi_shift.v //// +//// //// +//// This file is part of the SPI IP core project //// +//// http://www.opencores.org/projects/spi/ //// +//// //// +//// Author(s): //// +//// - Simon Srot (simons@opencores.org) //// +//// //// +//// All additional information is avaliable in the Readme.txt //// +//// file. //// +//// //// +////////////////////////////////////////////////////////////////////// +//// //// +//// Copyright (C) 2002 Authors //// +//// //// +//// This source file may be used and distributed without //// +//// restriction provided that this copyright statement is not //// +//// removed from the file and that any derivative work contains //// +//// the original copyright notice and the associated disclaimer. //// +//// //// +//// This source file is free software; you can redistribute it //// +//// and/or modify it under the terms of the GNU Lesser General //// +//// Public License as published by the Free Software Foundation; //// +//// either version 2.1 of the License, or (at your option) any //// +//// later version. //// +//// //// +//// This source is distributed in the hope that it will be //// +//// useful, but WITHOUT ANY WARRANTY; without even the implied //// +//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR //// +//// PURPOSE. See the GNU Lesser General Public License for more //// +//// details. //// +//// //// +//// You should have received a copy of the GNU Lesser General //// +//// Public License along with this source; if not, download it //// +//// from http://www.opencores.org/lgpl.shtml //// +//// //// +////////////////////////////////////////////////////////////////////// + +`include "spi_defines.v" +`include "timescale.v" + +module spi_flash_shift + ( + clk, rst, latch, byte_sel, len, go, + pos_edge, neg_edge, + lsb, rx_negedge, tx_negedge, + tip, last, + p_in, p_out, s_clk, s_in, s_out); + + parameter Tp = 1; + + input clk; // system clock + input rst; // reset + input latch; // latch signal for storing the data in shift register + input [3:0] byte_sel; // byte select signals for storing the data in shift register + input [`SPI_CHAR_LEN_BITS-1:0] len; // data len in bits (minus one) + input lsb; // lbs first on the line + input tx_negedge; + input rx_negedge; + input go; // start stansfer + input pos_edge; // recognize posedge of sclk + input neg_edge; // recognize negedge of sclk + output tip; // transfer in progress + output last; // last bit + input [31:0] p_in; // parallel in + output [`SPI_MAX_CHAR-1:0] p_out; // parallel out + input s_clk; // serial clock + input s_in; // serial in + output s_out; // serial out + + reg s_out; + reg tip; + + reg [`SPI_CHAR_LEN_BITS:0] cnt; // data bit count + reg [`SPI_MAX_CHAR-1:0] data; // shift register + wire [`SPI_CHAR_LEN_BITS:0] tx_bit_pos; // next bit position + wire [`SPI_CHAR_LEN_BITS:0] rx_bit_pos; // next bit position + wire rx_clk; // rx clock enable + wire tx_clk; // tx clock enable + + + assign p_out = data; + + assign tx_bit_pos = lsb ? {!(|len), len} - cnt : cnt - {{`SPI_CHAR_LEN_BITS{1'b0}},1'b1}; + assign rx_bit_pos = lsb ? {!(|len), len} - (rx_negedge ? cnt + {{`SPI_CHAR_LEN_BITS{1'b0}},1'b1} : cnt) : (rx_negedge ? cnt : cnt - {{`SPI_CHAR_LEN_BITS{1'b0}},1'b1}); + + assign last = !(|cnt); + + assign rx_clk = (rx_negedge ? neg_edge : pos_edge) && (!last || s_clk); + + assign tx_clk = (tx_negedge ? neg_edge : pos_edge) && !last; + + // Character bit counter + always @(posedge clk or posedge rst) + begin + if(rst) + cnt <= #Tp {`SPI_CHAR_LEN_BITS+1{1'b0}}; + else + begin + if(tip) + cnt <= #Tp pos_edge ? (cnt - {{`SPI_CHAR_LEN_BITS{1'b0}}, 1'b1}) : cnt; + else + cnt <= #Tp !(|len) ? {1'b1, {`SPI_CHAR_LEN_BITS{1'b0}}} : {1'b0, len}; + end + end + + // Transfer in progress + always @(posedge clk or posedge rst) + begin + if(rst) + tip <= #Tp 1'b0; + else if(go && ~tip) + tip <= #Tp 1'b1; + else if(tip && last && pos_edge) + tip <= #Tp 1'b0; + end + + // Sending bits to the line + always @(posedge clk or posedge rst) + begin + if (rst) + s_out <= #Tp 1'b0; + else + s_out <= #Tp (tx_clk || !tip) ? data[tx_bit_pos[`SPI_CHAR_LEN_BITS-1:0]] : s_out; + end + + // Receiving bits from the line + always @(posedge clk or posedge rst) + if (rst) + data <= #Tp `SPI_CHAR_RST; + else + if (latch & !tip) + begin + if (byte_sel[0]) + data[7:0] <= #Tp p_in[7:0]; + if (byte_sel[1]) + data[15:8] <= #Tp p_in[15:8]; + if (byte_sel[2]) + data[23:16] <= #Tp p_in[23:16]; + if (byte_sel[3]) + data[31:24] <= #Tp p_in[31:24]; + end + else + data[rx_bit_pos[`SPI_CHAR_LEN_BITS-1:0]] <= #Tp rx_clk ? s_in : data[rx_bit_pos[`SPI_CHAR_LEN_BITS-1:0]]; + +endmodule +
release-1.0/rtl/verilog/minsoc_startup/spi_shift.v Property changes : Added: svn:executable ## -0,0 +1 ## +* \ No newline at end of property Index: release-1.0/rtl/verilog/minsoc_startup/spi_defines.v =================================================================== --- release-1.0/rtl/verilog/minsoc_startup/spi_defines.v (nonexistent) +++ release-1.0/rtl/verilog/minsoc_startup/spi_defines.v (revision 151) @@ -0,0 +1,139 @@ +////////////////////////////////////////////////////////////////////// +//// //// +//// spi_define.v //// +//// //// +//// This file is part of the SPI IP core project //// +//// http://www.opencores.org/projects/spi/ //// +//// //// +//// Author(s): //// +//// - Simon Srot (simons@opencores.org) //// +//// //// +//// All additional information is avaliable in the Readme.txt //// +//// file. //// +//// //// +////////////////////////////////////////////////////////////////////// +//// //// +//// Copyright (C) 2002 Authors //// +//// //// +//// This source file may be used and distributed without //// +//// restriction provided that this copyright statement is not //// +//// removed from the file and that any derivative work contains //// +//// the original copyright notice and the associated disclaimer. //// +//// //// +//// This source file is free software; you can redistribute it //// +//// and/or modify it under the terms of the GNU Lesser General //// +//// Public License as published by the Free Software Foundation; //// +//// either version 2.1 of the License, or (at your option) any //// +//// later version. //// +//// //// +//// This source is distributed in the hope that it will be //// +//// useful, but WITHOUT ANY WARRANTY; without even the implied //// +//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR //// +//// PURPOSE. See the GNU Lesser General Public License for more //// +//// details. //// +//// //// +//// You should have received a copy of the GNU Lesser General //// +//// Public License along with this source; if not, download it //// +//// from http://www.opencores.org/lgpl.shtml //// +//// //// +////////////////////////////////////////////////////////////////////// + +// +// Number of bits used for devider register. If used in system with +// low frequency of system clock this can be reduced. +// Use SPI_DIVIDER_LEN for fine tuning theexact number. +// +`define SPI_DIVIDER_LEN_8 +//`define SPI_DIVIDER_LEN_16 +//`define SPI_DIVIDER_LEN_24 +//`define SPI_DIVIDER_LEN_32 + +`ifdef SPI_DIVIDER_LEN_8 + `define SPI_DIVIDER_LEN 4 // Can be set from 1 to 8 +`endif +`ifdef SPI_DIVIDER_LEN_16 + `define SPI_DIVIDER_LEN 16 // Can be set from 9 to 16 +`endif +`ifdef SPI_DIVIDER_LEN_24 + `define SPI_DIVIDER_LEN 24 // Can be set from 17 to 24 +`endif +`ifdef SPI_DIVIDER_LEN_32 + `define SPI_DIVIDER_LEN 32 // Can be set from 25 to 32 +`endif + +// +// Maximum nuber of bits that can be send/received at once. +// Use SPI_MAX_CHAR for fine tuning the exact number, when using +// SPI_MAX_CHAR_32, SPI_MAX_CHAR_24, SPI_MAX_CHAR_16, SPI_MAX_CHAR_8. +// +//`define SPI_MAX_CHAR_128 +//`define SPI_MAX_CHAR_64 +`define SPI_MAX_CHAR_32 +//`define SPI_MAX_CHAR_24 +//`define SPI_MAX_CHAR_16 +//`define SPI_MAX_CHAR_8 + +`ifdef SPI_MAX_CHAR_128 + `define SPI_MAX_CHAR 128 // Can only be set to 128 + `define SPI_CHAR_LEN_BITS 7 +`endif +`ifdef SPI_MAX_CHAR_64 + `define SPI_MAX_CHAR 64 // Can only be set to 64 + `define SPI_CHAR_LEN_BITS 6 +`endif +`ifdef SPI_MAX_CHAR_32 + `define SPI_MAX_CHAR 32 // Can be set from 25 to 32 + `define SPI_CHAR_LEN_BITS 6 + `define SPI_CHAR_RST 32'h03000000 +`endif +`ifdef SPI_MAX_CHAR_24 + `define SPI_MAX_CHAR 24 // Can be set from 17 to 24 + `define SPI_CHAR_LEN_BITS 5 +`endif +`ifdef SPI_MAX_CHAR_16 + `define SPI_MAX_CHAR 16 // Can be set from 9 to 16 + `define SPI_CHAR_LEN_BITS 4 +`endif +`ifdef SPI_MAX_CHAR_8 + `define SPI_MAX_CHAR 8 // Can be set from 1 to 8 + `define SPI_CHAR_LEN_BITS 3 +`endif + +// +// Number of device select signals. Use SPI_SS_NB for fine tuning the +// exact number. +// +`define SPI_SS_NB 2 // Can be set from 1 to 2 + +// +// Bits of WISHBONE address used for partial decoding of SPI registers. +// +`define SPI_OFS_BITS 4:2 + +// +// Register offset +// +`define SPI_RX_0 0 +`define SPI_RX_1 1 +`define SPI_RX_2 2 +`define SPI_RX_3 3 +`define SPI_TX_0 0 +`define SPI_TX_1 1 +`define SPI_TX_2 2 +`define SPI_TX_3 3 +`define SPI_CTRL 4 +`define SPI_DEVIDE 5 +`define SPI_SS 6 + +// +// Number of bits in ctrl register +// +`define SPI_CTRL_BIT_NB 14 +`define SPI_CTRL_BIT_RST 14'h420 +// +// Control register bits +// +//`define SPI_CTRL_LSB +`define SPI_CTRL_TX_NEGEDGE +//`define SPI_CTRL_RX_NEGEDGE +
release-1.0/rtl/verilog/minsoc_startup/spi_defines.v Property changes : Added: svn:executable ## -0,0 +1 ## +* \ No newline at end of property Index: release-1.0/rtl/verilog/minsoc_startup/OR1K_startup_generic.v =================================================================== --- release-1.0/rtl/verilog/minsoc_startup/OR1K_startup_generic.v (nonexistent) +++ release-1.0/rtl/verilog/minsoc_startup/OR1K_startup_generic.v (revision 151) @@ -0,0 +1,60 @@ + +`include "minsoc_defines.v" + +module OR1K_startup + ( + input [6:2] wb_adr_i, + input wb_stb_i, + input wb_cyc_i, + output reg [31:0] wb_dat_o, + output reg wb_ack_o, + input wb_clk, + input wb_rst + ); + + always @ (posedge wb_clk or posedge wb_rst) + if (wb_rst) + wb_dat_o <= 32'h15000000; + else + case (wb_adr_i) + 0 : wb_dat_o <= 32'h18000000; + 1 : wb_dat_o <= 32'hA8200000; + 2 : wb_dat_o <= { 16'h1880 , `APP_ADDR_SPI , 8'h00 }; + 3 : wb_dat_o <= 32'hA8A00520; + 4 : wb_dat_o <= 32'hA8600001; + 5 : wb_dat_o <= 32'h04000014; + 6 : wb_dat_o <= 32'hD4041818; + 7 : wb_dat_o <= 32'h04000012; + 8 : wb_dat_o <= 32'hD4040000; + 9 : wb_dat_o <= 32'hE0431804; + 10 : wb_dat_o <= 32'h0400000F; + 11 : wb_dat_o <= 32'h9C210008; + 12 : wb_dat_o <= 32'h0400000D; + 13 : wb_dat_o <= 32'hE1031804; + 14 : wb_dat_o <= 32'hE4080000; + 15 : wb_dat_o <= 32'h0FFFFFFB; + 16 : wb_dat_o <= 32'hD4081800; + 17 : wb_dat_o <= 32'h04000008; + 18 : wb_dat_o <= 32'h9C210004; + 19 : wb_dat_o <= 32'hD4011800; + 20 : wb_dat_o <= 32'hE4011000; + 21 : wb_dat_o <= 32'h0FFFFFFC; + 22 : wb_dat_o <= 32'hA8C00100; + 23 : wb_dat_o <= 32'h44003000; + 24 : wb_dat_o <= 32'hD4040018; + 25 : wb_dat_o <= 32'hD4042810; + 26 : wb_dat_o <= 32'h84640010; + 27 : wb_dat_o <= 32'hBC030520; + 28 : wb_dat_o <= 32'h13FFFFFE; + 29 : wb_dat_o <= 32'h15000000; + 30 : wb_dat_o <= 32'h44004800; + 31 : wb_dat_o <= 32'h84640000; + endcase + + always @ (posedge wb_clk or posedge wb_rst) + if (wb_rst) + wb_ack_o <= 1'b0; + else + wb_ack_o <= wb_stb_i & wb_cyc_i & !wb_ack_o; + +endmodule // OR1K_startup
release-1.0/rtl/verilog/minsoc_startup/OR1K_startup_generic.v Property changes : Added: svn:executable ## -0,0 +1 ## +* \ No newline at end of property Index: release-1.0/rtl/verilog/minsoc_tc_top.v =================================================================== --- release-1.0/rtl/verilog/minsoc_tc_top.v (nonexistent) +++ release-1.0/rtl/verilog/minsoc_tc_top.v (revision 151) @@ -0,0 +1,1684 @@ +////////////////////////////////////////////////////////////////////// +//// //// +//// Xess Traffic Cop //// +//// //// +//// This file is part of the OR1K test application //// +//// http://www.opencores.org/cores/or1k/ //// +//// //// +//// Description //// +//// This block connectes the RISC and peripheral controller //// +//// cores together. //// +//// //// +//// To Do: //// +//// - nothing really //// +//// //// +//// Author(s): //// +//// - Damjan Lampret, lampret@opencores.org //// +//// //// +////////////////////////////////////////////////////////////////////// +//// //// +//// Copyright (C) 2002 OpenCores //// +//// //// +//// This source file may be used and distributed without //// +//// restriction provided that this copyright statement is not //// +//// removed from the file and that any derivative work contains //// +//// the original copyright notice and the associated disclaimer. //// +//// //// +//// This source file is free software; you can redistribute it //// +//// and/or modify it under the terms of the GNU Lesser General //// +//// Public License as published by the Free Software Foundation; //// +//// either version 2.1 of the License, or (at your option) any //// +//// later version. //// +//// //// +//// This source is distributed in the hope that it will be //// +//// useful, but WITHOUT ANY WARRANTY; without even the implied //// +//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR //// +//// PURPOSE. See the GNU Lesser General Public License for more //// +//// details. //// +//// //// +//// You should have received a copy of the GNU Lesser General //// +//// Public License along with this source; if not, download it //// +//// from http://www.opencores.org/lgpl.shtml //// +//// //// +////////////////////////////////////////////////////////////////////// +// +// CVS Revision History +// +// $Log: tc_top.v,v $ +// Revision 1.4 2004/04/05 08:44:34 lampret +// Merged branch_qmem into main tree. +// +// Revision 1.2 2002/03/29 20:57:30 lampret +// Removed unused ports wb_clki and wb_rst_i +// +// Revision 1.1.1.1 2002/03/21 16:55:44 lampret +// First import of the "new" XESS XSV environment. +// +// +// + +// synopsys translate_off +`include "timescale.v" +// synopsys translate_on + +// +// Width of address bus +// +`define TC_AW 32 + +// +// Width of data bus +// +`define TC_DW 32 + +// +// Width of byte select bus +// +`define TC_BSW 4 + +// +// Width of WB target inputs (coming from WB slave) +// +// data bus width + ack + err +// +`define TC_TIN_W `TC_DW+1+1 + +// +// Width of WB initiator inputs (coming from WB masters) +// +// cyc + stb + address bus width + +// byte select bus width + we + data bus width +// +`define TC_IIN_W 1+1+1+`TC_AW+`TC_BSW+1+`TC_DW + +// +// Traffic Cop Top +// +module minsoc_tc_top ( + wb_clk_i, + wb_rst_i, + + i0_wb_cyc_i, + i0_wb_stb_i, + i0_wb_adr_i, + i0_wb_sel_i, + i0_wb_we_i, + i0_wb_dat_i, + i0_wb_dat_o, + i0_wb_ack_o, + i0_wb_err_o, + + i1_wb_cyc_i, + i1_wb_stb_i, + i1_wb_adr_i, + i1_wb_sel_i, + i1_wb_we_i, + i1_wb_dat_i, + i1_wb_dat_o, + i1_wb_ack_o, + i1_wb_err_o, + + i2_wb_cyc_i, + i2_wb_stb_i, + i2_wb_adr_i, + i2_wb_sel_i, + i2_wb_we_i, + i2_wb_dat_i, + i2_wb_dat_o, + i2_wb_ack_o, + i2_wb_err_o, + + i3_wb_cyc_i, + i3_wb_stb_i, + i3_wb_adr_i, + i3_wb_sel_i, + i3_wb_we_i, + i3_wb_dat_i, + i3_wb_dat_o, + i3_wb_ack_o, + i3_wb_err_o, + + i4_wb_cyc_i, + i4_wb_stb_i, + i4_wb_adr_i, + i4_wb_sel_i, + i4_wb_we_i, + i4_wb_dat_i, + i4_wb_dat_o, + i4_wb_ack_o, + i4_wb_err_o, + + i5_wb_cyc_i, + i5_wb_stb_i, + i5_wb_adr_i, + i5_wb_sel_i, + i5_wb_we_i, + i5_wb_dat_i, + i5_wb_dat_o, + i5_wb_ack_o, + i5_wb_err_o, + + i6_wb_cyc_i, + i6_wb_stb_i, + i6_wb_adr_i, + i6_wb_sel_i, + i6_wb_we_i, + i6_wb_dat_i, + i6_wb_dat_o, + i6_wb_ack_o, + i6_wb_err_o, + + i7_wb_cyc_i, + i7_wb_stb_i, + i7_wb_adr_i, + i7_wb_sel_i, + i7_wb_we_i, + i7_wb_dat_i, + i7_wb_dat_o, + i7_wb_ack_o, + i7_wb_err_o, + + t0_wb_cyc_o, + t0_wb_stb_o, + t0_wb_adr_o, + t0_wb_sel_o, + t0_wb_we_o, + t0_wb_dat_o, + t0_wb_dat_i, + t0_wb_ack_i, + t0_wb_err_i, + + t1_wb_cyc_o, + t1_wb_stb_o, + t1_wb_adr_o, + t1_wb_sel_o, + t1_wb_we_o, + t1_wb_dat_o, + t1_wb_dat_i, + t1_wb_ack_i, + t1_wb_err_i, + + t2_wb_cyc_o, + t2_wb_stb_o, + t2_wb_adr_o, + t2_wb_sel_o, + t2_wb_we_o, + t2_wb_dat_o, + t2_wb_dat_i, + t2_wb_ack_i, + t2_wb_err_i, + + t3_wb_cyc_o, + t3_wb_stb_o, + t3_wb_adr_o, + t3_wb_sel_o, + t3_wb_we_o, + t3_wb_dat_o, + t3_wb_dat_i, + t3_wb_ack_i, + t3_wb_err_i, + + t4_wb_cyc_o, + t4_wb_stb_o, + t4_wb_adr_o, + t4_wb_sel_o, + t4_wb_we_o, + t4_wb_dat_o, + t4_wb_dat_i, + t4_wb_ack_i, + t4_wb_err_i, + + t5_wb_cyc_o, + t5_wb_stb_o, + t5_wb_adr_o, + t5_wb_sel_o, + t5_wb_we_o, + t5_wb_dat_o, + t5_wb_dat_i, + t5_wb_ack_i, + t5_wb_err_i, + + t6_wb_cyc_o, + t6_wb_stb_o, + t6_wb_adr_o, + t6_wb_sel_o, + t6_wb_we_o, + t6_wb_dat_o, + t6_wb_dat_i, + t6_wb_ack_i, + t6_wb_err_i, + + t7_wb_cyc_o, + t7_wb_stb_o, + t7_wb_adr_o, + t7_wb_sel_o, + t7_wb_we_o, + t7_wb_dat_o, + t7_wb_dat_i, + t7_wb_ack_i, + t7_wb_err_i, + + t8_wb_cyc_o, + t8_wb_stb_o, + t8_wb_adr_o, + t8_wb_sel_o, + t8_wb_we_o, + t8_wb_dat_o, + t8_wb_dat_i, + t8_wb_ack_i, + t8_wb_err_i + +); + +// +// Parameters +// +parameter t0_addr_w = 4; +parameter t0_addr = 4'd8; +parameter t1_addr_w = 4; +parameter t1_addr = 4'd0; +parameter t28c_addr_w = 4; +parameter t28_addr = 4'd0; +parameter t28i_addr_w = 4; +parameter t2_addr = 4'd1; +parameter t3_addr = 4'd2; +parameter t4_addr = 4'd3; +parameter t5_addr = 4'd4; +parameter t6_addr = 4'd5; +parameter t7_addr = 4'd6; +parameter t8_addr = 4'd7; + +// +// I/O Ports +// +input wb_clk_i; +input wb_rst_i; + +// +// WB slave i/f connecting initiator 0 +// +input i0_wb_cyc_i; +input i0_wb_stb_i; +input [`TC_AW-1:0] i0_wb_adr_i; +input [`TC_BSW-1:0] i0_wb_sel_i; +input i0_wb_we_i; +input [`TC_DW-1:0] i0_wb_dat_i; +output [`TC_DW-1:0] i0_wb_dat_o; +output i0_wb_ack_o; +output i0_wb_err_o; + +// +// WB slave i/f connecting initiator 1 +// +input i1_wb_cyc_i; +input i1_wb_stb_i; +input [`TC_AW-1:0] i1_wb_adr_i; +input [`TC_BSW-1:0] i1_wb_sel_i; +input i1_wb_we_i; +input [`TC_DW-1:0] i1_wb_dat_i; +output [`TC_DW-1:0] i1_wb_dat_o; +output i1_wb_ack_o; +output i1_wb_err_o; + +// +// WB slave i/f connecting initiator 2 +// +input i2_wb_cyc_i; +input i2_wb_stb_i; +input [`TC_AW-1:0] i2_wb_adr_i; +input [`TC_BSW-1:0] i2_wb_sel_i; +input i2_wb_we_i; +input [`TC_DW-1:0] i2_wb_dat_i; +output [`TC_DW-1:0] i2_wb_dat_o; +output i2_wb_ack_o; +output i2_wb_err_o; + +// +// WB slave i/f connecting initiator 3 +// +input i3_wb_cyc_i; +input i3_wb_stb_i; +input [`TC_AW-1:0] i3_wb_adr_i; +input [`TC_BSW-1:0] i3_wb_sel_i; +input i3_wb_we_i; +input [`TC_DW-1:0] i3_wb_dat_i; +output [`TC_DW-1:0] i3_wb_dat_o; +output i3_wb_ack_o; +output i3_wb_err_o; + +// +// WB slave i/f connecting initiator 4 +// +input i4_wb_cyc_i; +input i4_wb_stb_i; +input [`TC_AW-1:0] i4_wb_adr_i; +input [`TC_BSW-1:0] i4_wb_sel_i; +input i4_wb_we_i; +input [`TC_DW-1:0] i4_wb_dat_i; +output [`TC_DW-1:0] i4_wb_dat_o; +output i4_wb_ack_o; +output i4_wb_err_o; + +// +// WB slave i/f connecting initiator 5 +// +input i5_wb_cyc_i; +input i5_wb_stb_i; +input [`TC_AW-1:0] i5_wb_adr_i; +input [`TC_BSW-1:0] i5_wb_sel_i; +input i5_wb_we_i; +input [`TC_DW-1:0] i5_wb_dat_i; +output [`TC_DW-1:0] i5_wb_dat_o; +output i5_wb_ack_o; +output i5_wb_err_o; + +// +// WB slave i/f connecting initiator 6 +// +input i6_wb_cyc_i; +input i6_wb_stb_i; +input [`TC_AW-1:0] i6_wb_adr_i; +input [`TC_BSW-1:0] i6_wb_sel_i; +input i6_wb_we_i; +input [`TC_DW-1:0] i6_wb_dat_i; +output [`TC_DW-1:0] i6_wb_dat_o; +output i6_wb_ack_o; +output i6_wb_err_o; + +// +// WB slave i/f connecting initiator 7 +// +input i7_wb_cyc_i; +input i7_wb_stb_i; +input [`TC_AW-1:0] i7_wb_adr_i; +input [`TC_BSW-1:0] i7_wb_sel_i; +input i7_wb_we_i; +input [`TC_DW-1:0] i7_wb_dat_i; +output [`TC_DW-1:0] i7_wb_dat_o; +output i7_wb_ack_o; +output i7_wb_err_o; + +// +// WB master i/f connecting target 0 +// +output t0_wb_cyc_o; +output t0_wb_stb_o; +output [`TC_AW-1:0] t0_wb_adr_o; +output [`TC_BSW-1:0] t0_wb_sel_o; +output t0_wb_we_o; +output [`TC_DW-1:0] t0_wb_dat_o; +input [`TC_DW-1:0] t0_wb_dat_i; +input t0_wb_ack_i; +input t0_wb_err_i; + +// +// WB master i/f connecting target 1 +// +output t1_wb_cyc_o; +output t1_wb_stb_o; +output [`TC_AW-1:0] t1_wb_adr_o; +output [`TC_BSW-1:0] t1_wb_sel_o; +output t1_wb_we_o; +output [`TC_DW-1:0] t1_wb_dat_o; +input [`TC_DW-1:0] t1_wb_dat_i; +input t1_wb_ack_i; +input t1_wb_err_i; + +// +// WB master i/f connecting target 2 +// +output t2_wb_cyc_o; +output t2_wb_stb_o; +output [`TC_AW-1:0] t2_wb_adr_o; +output [`TC_BSW-1:0] t2_wb_sel_o; +output t2_wb_we_o; +output [`TC_DW-1:0] t2_wb_dat_o; +input [`TC_DW-1:0] t2_wb_dat_i; +input t2_wb_ack_i; +input t2_wb_err_i; + +// +// WB master i/f connecting target 3 +// +output t3_wb_cyc_o; +output t3_wb_stb_o; +output [`TC_AW-1:0] t3_wb_adr_o; +output [`TC_BSW-1:0] t3_wb_sel_o; +output t3_wb_we_o; +output [`TC_DW-1:0] t3_wb_dat_o; +input [`TC_DW-1:0] t3_wb_dat_i; +input t3_wb_ack_i; +input t3_wb_err_i; + +// +// WB master i/f connecting target 4 +// +output t4_wb_cyc_o; +output t4_wb_stb_o; +output [`TC_AW-1:0] t4_wb_adr_o; +output [`TC_BSW-1:0] t4_wb_sel_o; +output t4_wb_we_o; +output [`TC_DW-1:0] t4_wb_dat_o; +input [`TC_DW-1:0] t4_wb_dat_i; +input t4_wb_ack_i; +input t4_wb_err_i; + +// +// WB master i/f connecting target 5 +// +output t5_wb_cyc_o; +output t5_wb_stb_o; +output [`TC_AW-1:0] t5_wb_adr_o; +output [`TC_BSW-1:0] t5_wb_sel_o; +output t5_wb_we_o; +output [`TC_DW-1:0] t5_wb_dat_o; +input [`TC_DW-1:0] t5_wb_dat_i; +input t5_wb_ack_i; +input t5_wb_err_i; + +// +// WB master i/f connecting target 6 +// +output t6_wb_cyc_o; +output t6_wb_stb_o; +output [`TC_AW-1:0] t6_wb_adr_o; +output [`TC_BSW-1:0] t6_wb_sel_o; +output t6_wb_we_o; +output [`TC_DW-1:0] t6_wb_dat_o; +input [`TC_DW-1:0] t6_wb_dat_i; +input t6_wb_ack_i; +input t6_wb_err_i; + +// +// WB master i/f connecting target 7 +// +output t7_wb_cyc_o; +output t7_wb_stb_o; +output [`TC_AW-1:0] t7_wb_adr_o; +output [`TC_BSW-1:0] t7_wb_sel_o; +output t7_wb_we_o; +output [`TC_DW-1:0] t7_wb_dat_o; +input [`TC_DW-1:0] t7_wb_dat_i; +input t7_wb_ack_i; +input t7_wb_err_i; + +// +// WB master i/f connecting target 8 +// +output t8_wb_cyc_o; +output t8_wb_stb_o; +output [`TC_AW-1:0] t8_wb_adr_o; +output [`TC_BSW-1:0] t8_wb_sel_o; +output t8_wb_we_o; +output [`TC_DW-1:0] t8_wb_dat_o; +input [`TC_DW-1:0] t8_wb_dat_i; +input t8_wb_ack_i; +input t8_wb_err_i; + +// +// Internal wires & registers +// + +// +// Outputs for initiators from both mi_to_st blocks +// +wire [`TC_DW-1:0] xi0_wb_dat_o; +wire xi0_wb_ack_o; +wire xi0_wb_err_o; +wire [`TC_DW-1:0] xi1_wb_dat_o; +wire xi1_wb_ack_o; +wire xi1_wb_err_o; +wire [`TC_DW-1:0] xi2_wb_dat_o; +wire xi2_wb_ack_o; +wire xi2_wb_err_o; +wire [`TC_DW-1:0] xi3_wb_dat_o; +wire xi3_wb_ack_o; +wire xi3_wb_err_o; +wire [`TC_DW-1:0] xi4_wb_dat_o; +wire xi4_wb_ack_o; +wire xi4_wb_err_o; +wire [`TC_DW-1:0] xi5_wb_dat_o; +wire xi5_wb_ack_o; +wire xi5_wb_err_o; +wire [`TC_DW-1:0] xi6_wb_dat_o; +wire xi6_wb_ack_o; +wire xi6_wb_err_o; +wire [`TC_DW-1:0] xi7_wb_dat_o; +wire xi7_wb_ack_o; +wire xi7_wb_err_o; +wire [`TC_DW-1:0] yi0_wb_dat_o; +wire yi0_wb_ack_o; +wire yi0_wb_err_o; +wire [`TC_DW-1:0] yi1_wb_dat_o; +wire yi1_wb_ack_o; +wire yi1_wb_err_o; +wire [`TC_DW-1:0] yi2_wb_dat_o; +wire yi2_wb_ack_o; +wire yi2_wb_err_o; +wire [`TC_DW-1:0] yi3_wb_dat_o; +wire yi3_wb_ack_o; +wire yi3_wb_err_o; +wire [`TC_DW-1:0] yi4_wb_dat_o; +wire yi4_wb_ack_o; +wire yi4_wb_err_o; +wire [`TC_DW-1:0] yi5_wb_dat_o; +wire yi5_wb_ack_o; +wire yi5_wb_err_o; +wire [`TC_DW-1:0] yi6_wb_dat_o; +wire yi6_wb_ack_o; +wire yi6_wb_err_o; +wire [`TC_DW-1:0] yi7_wb_dat_o; +wire yi7_wb_ack_o; +wire yi7_wb_err_o; + +// +// Intermediate signals connecting peripheral channel's +// mi_to_st and si_to_mt blocks. +// +wire z_wb_cyc_i; +wire z_wb_stb_i; +wire [`TC_AW-1:0] z_wb_adr_i; +wire [`TC_BSW-1:0] z_wb_sel_i; +wire z_wb_we_i; +wire [`TC_DW-1:0] z_wb_dat_i; +wire [`TC_DW-1:0] z_wb_dat_t; +wire z_wb_ack_t; +wire z_wb_err_t; + +// +// Outputs for initiators are ORed from both mi_to_st blocks +// +assign i0_wb_dat_o = xi0_wb_dat_o | yi0_wb_dat_o; +assign i0_wb_ack_o = xi0_wb_ack_o | yi0_wb_ack_o; +assign i0_wb_err_o = xi0_wb_err_o | yi0_wb_err_o; +assign i1_wb_dat_o = xi1_wb_dat_o | yi1_wb_dat_o; +assign i1_wb_ack_o = xi1_wb_ack_o | yi1_wb_ack_o; +assign i1_wb_err_o = xi1_wb_err_o | yi1_wb_err_o; +assign i2_wb_dat_o = xi2_wb_dat_o | yi2_wb_dat_o; +assign i2_wb_ack_o = xi2_wb_ack_o | yi2_wb_ack_o; +assign i2_wb_err_o = xi2_wb_err_o | yi2_wb_err_o; +assign i3_wb_dat_o = xi3_wb_dat_o | yi3_wb_dat_o; +assign i3_wb_ack_o = xi3_wb_ack_o | yi3_wb_ack_o; +assign i3_wb_err_o = xi3_wb_err_o | yi3_wb_err_o; +assign i4_wb_dat_o = xi4_wb_dat_o | yi4_wb_dat_o; +assign i4_wb_ack_o = xi4_wb_ack_o | yi4_wb_ack_o; +assign i4_wb_err_o = xi4_wb_err_o | yi4_wb_err_o; +assign i5_wb_dat_o = xi5_wb_dat_o | yi5_wb_dat_o; +assign i5_wb_ack_o = xi5_wb_ack_o | yi5_wb_ack_o; +assign i5_wb_err_o = xi5_wb_err_o | yi5_wb_err_o; +assign i6_wb_dat_o = xi6_wb_dat_o | yi6_wb_dat_o; +assign i6_wb_ack_o = xi6_wb_ack_o | yi6_wb_ack_o; +assign i6_wb_err_o = xi6_wb_err_o | yi6_wb_err_o; +assign i7_wb_dat_o = xi7_wb_dat_o | yi7_wb_dat_o; +assign i7_wb_ack_o = xi7_wb_ack_o | yi7_wb_ack_o; +assign i7_wb_err_o = xi7_wb_err_o | yi7_wb_err_o; + +// +// From initiators to target 0 +// +tc_mi_to_st #(t0_addr_w, t0_addr, + 0, t0_addr_w, t0_addr) t0_ch( + .wb_clk_i(wb_clk_i), + .wb_rst_i(wb_rst_i), + + .i0_wb_cyc_i(i0_wb_cyc_i), + .i0_wb_stb_i(i0_wb_stb_i), + .i0_wb_adr_i(i0_wb_adr_i), + .i0_wb_sel_i(i0_wb_sel_i), + .i0_wb_we_i(i0_wb_we_i), + .i0_wb_dat_i(i0_wb_dat_i), + .i0_wb_dat_o(xi0_wb_dat_o), + .i0_wb_ack_o(xi0_wb_ack_o), + .i0_wb_err_o(xi0_wb_err_o), + + .i1_wb_cyc_i(i1_wb_cyc_i), + .i1_wb_stb_i(i1_wb_stb_i), + .i1_wb_adr_i(i1_wb_adr_i), + .i1_wb_sel_i(i1_wb_sel_i), + .i1_wb_we_i(i1_wb_we_i), + .i1_wb_dat_i(i1_wb_dat_i), + .i1_wb_dat_o(xi1_wb_dat_o), + .i1_wb_ack_o(xi1_wb_ack_o), + .i1_wb_err_o(xi1_wb_err_o), + + .i2_wb_cyc_i(i2_wb_cyc_i), + .i2_wb_stb_i(i2_wb_stb_i), + .i2_wb_adr_i(i2_wb_adr_i), + .i2_wb_sel_i(i2_wb_sel_i), + .i2_wb_we_i(i2_wb_we_i), + .i2_wb_dat_i(i2_wb_dat_i), + .i2_wb_dat_o(xi2_wb_dat_o), + .i2_wb_ack_o(xi2_wb_ack_o), + .i2_wb_err_o(xi2_wb_err_o), + + .i3_wb_cyc_i(i3_wb_cyc_i), + .i3_wb_stb_i(i3_wb_stb_i), + .i3_wb_adr_i(i3_wb_adr_i), + .i3_wb_sel_i(i3_wb_sel_i), + .i3_wb_we_i(i3_wb_we_i), + .i3_wb_dat_i(i3_wb_dat_i), + .i3_wb_dat_o(xi3_wb_dat_o), + .i3_wb_ack_o(xi3_wb_ack_o), + .i3_wb_err_o(xi3_wb_err_o), + + .i4_wb_cyc_i(i4_wb_cyc_i), + .i4_wb_stb_i(i4_wb_stb_i), + .i4_wb_adr_i(i4_wb_adr_i), + .i4_wb_sel_i(i4_wb_sel_i), + .i4_wb_we_i(i4_wb_we_i), + .i4_wb_dat_i(i4_wb_dat_i), + .i4_wb_dat_o(xi4_wb_dat_o), + .i4_wb_ack_o(xi4_wb_ack_o), + .i4_wb_err_o(xi4_wb_err_o), + + .i5_wb_cyc_i(i5_wb_cyc_i), + .i5_wb_stb_i(i5_wb_stb_i), + .i5_wb_adr_i(i5_wb_adr_i), + .i5_wb_sel_i(i5_wb_sel_i), + .i5_wb_we_i(i5_wb_we_i), + .i5_wb_dat_i(i5_wb_dat_i), + .i5_wb_dat_o(xi5_wb_dat_o), + .i5_wb_ack_o(xi5_wb_ack_o), + .i5_wb_err_o(xi5_wb_err_o), + + .i6_wb_cyc_i(i6_wb_cyc_i), + .i6_wb_stb_i(i6_wb_stb_i), + .i6_wb_adr_i(i6_wb_adr_i), + .i6_wb_sel_i(i6_wb_sel_i), + .i6_wb_we_i(i6_wb_we_i), + .i6_wb_dat_i(i6_wb_dat_i), + .i6_wb_dat_o(xi6_wb_dat_o), + .i6_wb_ack_o(xi6_wb_ack_o), + .i6_wb_err_o(xi6_wb_err_o), + + .i7_wb_cyc_i(i7_wb_cyc_i), + .i7_wb_stb_i(i7_wb_stb_i), + .i7_wb_adr_i(i7_wb_adr_i), + .i7_wb_sel_i(i7_wb_sel_i), + .i7_wb_we_i(i7_wb_we_i), + .i7_wb_dat_i(i7_wb_dat_i), + .i7_wb_dat_o(xi7_wb_dat_o), + .i7_wb_ack_o(xi7_wb_ack_o), + .i7_wb_err_o(xi7_wb_err_o), + + .t0_wb_cyc_o(t0_wb_cyc_o), + .t0_wb_stb_o(t0_wb_stb_o), + .t0_wb_adr_o(t0_wb_adr_o), + .t0_wb_sel_o(t0_wb_sel_o), + .t0_wb_we_o(t0_wb_we_o), + .t0_wb_dat_o(t0_wb_dat_o), + .t0_wb_dat_i(t0_wb_dat_i), + .t0_wb_ack_i(t0_wb_ack_i), + .t0_wb_err_i(t0_wb_err_i) + +); + +// +// From initiators to targets 1-8 (upper part) +// +tc_mi_to_st #(t1_addr_w, t1_addr, + 1, t28c_addr_w, t28_addr) t18_ch_upper( + .wb_clk_i(wb_clk_i), + .wb_rst_i(wb_rst_i), + + .i0_wb_cyc_i(i0_wb_cyc_i), + .i0_wb_stb_i(i0_wb_stb_i), + .i0_wb_adr_i(i0_wb_adr_i), + .i0_wb_sel_i(i0_wb_sel_i), + .i0_wb_we_i(i0_wb_we_i), + .i0_wb_dat_i(i0_wb_dat_i), + .i0_wb_dat_o(yi0_wb_dat_o), + .i0_wb_ack_o(yi0_wb_ack_o), + .i0_wb_err_o(yi0_wb_err_o), + + .i1_wb_cyc_i(i1_wb_cyc_i), + .i1_wb_stb_i(i1_wb_stb_i), + .i1_wb_adr_i(i1_wb_adr_i), + .i1_wb_sel_i(i1_wb_sel_i), + .i1_wb_we_i(i1_wb_we_i), + .i1_wb_dat_i(i1_wb_dat_i), + .i1_wb_dat_o(yi1_wb_dat_o), + .i1_wb_ack_o(yi1_wb_ack_o), + .i1_wb_err_o(yi1_wb_err_o), + + .i2_wb_cyc_i(i2_wb_cyc_i), + .i2_wb_stb_i(i2_wb_stb_i), + .i2_wb_adr_i(i2_wb_adr_i), + .i2_wb_sel_i(i2_wb_sel_i), + .i2_wb_we_i(i2_wb_we_i), + .i2_wb_dat_i(i2_wb_dat_i), + .i2_wb_dat_o(yi2_wb_dat_o), + .i2_wb_ack_o(yi2_wb_ack_o), + .i2_wb_err_o(yi2_wb_err_o), + + .i3_wb_cyc_i(i3_wb_cyc_i), + .i3_wb_stb_i(i3_wb_stb_i), + .i3_wb_adr_i(i3_wb_adr_i), + .i3_wb_sel_i(i3_wb_sel_i), + .i3_wb_we_i(i3_wb_we_i), + .i3_wb_dat_i(i3_wb_dat_i), + .i3_wb_dat_o(yi3_wb_dat_o), + .i3_wb_ack_o(yi3_wb_ack_o), + .i3_wb_err_o(yi3_wb_err_o), + + .i4_wb_cyc_i(i4_wb_cyc_i), + .i4_wb_stb_i(i4_wb_stb_i), + .i4_wb_adr_i(i4_wb_adr_i), + .i4_wb_sel_i(i4_wb_sel_i), + .i4_wb_we_i(i4_wb_we_i), + .i4_wb_dat_i(i4_wb_dat_i), + .i4_wb_dat_o(yi4_wb_dat_o), + .i4_wb_ack_o(yi4_wb_ack_o), + .i4_wb_err_o(yi4_wb_err_o), + + .i5_wb_cyc_i(i5_wb_cyc_i), + .i5_wb_stb_i(i5_wb_stb_i), + .i5_wb_adr_i(i5_wb_adr_i), + .i5_wb_sel_i(i5_wb_sel_i), + .i5_wb_we_i(i5_wb_we_i), + .i5_wb_dat_i(i5_wb_dat_i), + .i5_wb_dat_o(yi5_wb_dat_o), + .i5_wb_ack_o(yi5_wb_ack_o), + .i5_wb_err_o(yi5_wb_err_o), + + .i6_wb_cyc_i(i6_wb_cyc_i), + .i6_wb_stb_i(i6_wb_stb_i), + .i6_wb_adr_i(i6_wb_adr_i), + .i6_wb_sel_i(i6_wb_sel_i), + .i6_wb_we_i(i6_wb_we_i), + .i6_wb_dat_i(i6_wb_dat_i), + .i6_wb_dat_o(yi6_wb_dat_o), + .i6_wb_ack_o(yi6_wb_ack_o), + .i6_wb_err_o(yi6_wb_err_o), + + .i7_wb_cyc_i(i7_wb_cyc_i), + .i7_wb_stb_i(i7_wb_stb_i), + .i7_wb_adr_i(i7_wb_adr_i), + .i7_wb_sel_i(i7_wb_sel_i), + .i7_wb_we_i(i7_wb_we_i), + .i7_wb_dat_i(i7_wb_dat_i), + .i7_wb_dat_o(yi7_wb_dat_o), + .i7_wb_ack_o(yi7_wb_ack_o), + .i7_wb_err_o(yi7_wb_err_o), + + .t0_wb_cyc_o(z_wb_cyc_i), + .t0_wb_stb_o(z_wb_stb_i), + .t0_wb_adr_o(z_wb_adr_i), + .t0_wb_sel_o(z_wb_sel_i), + .t0_wb_we_o(z_wb_we_i), + .t0_wb_dat_o(z_wb_dat_i), + .t0_wb_dat_i(z_wb_dat_t), + .t0_wb_ack_i(z_wb_ack_t), + .t0_wb_err_i(z_wb_err_t) + +); + +// +// From initiators to targets 1-8 (lower part) +// +tc_si_to_mt #(t1_addr_w, t1_addr, t28i_addr_w, t2_addr, t3_addr, + t4_addr, t5_addr, t6_addr, t7_addr, t8_addr) t18_ch_lower( + + .i0_wb_cyc_i(z_wb_cyc_i), + .i0_wb_stb_i(z_wb_stb_i), + .i0_wb_adr_i(z_wb_adr_i), + .i0_wb_sel_i(z_wb_sel_i), + .i0_wb_we_i(z_wb_we_i), + .i0_wb_dat_i(z_wb_dat_i), + .i0_wb_dat_o(z_wb_dat_t), + .i0_wb_ack_o(z_wb_ack_t), + .i0_wb_err_o(z_wb_err_t), + + .t0_wb_cyc_o(t1_wb_cyc_o), + .t0_wb_stb_o(t1_wb_stb_o), + .t0_wb_adr_o(t1_wb_adr_o), + .t0_wb_sel_o(t1_wb_sel_o), + .t0_wb_we_o(t1_wb_we_o), + .t0_wb_dat_o(t1_wb_dat_o), + .t0_wb_dat_i(t1_wb_dat_i), + .t0_wb_ack_i(t1_wb_ack_i), + .t0_wb_err_i(t1_wb_err_i), + + .t1_wb_cyc_o(t2_wb_cyc_o), + .t1_wb_stb_o(t2_wb_stb_o), + .t1_wb_adr_o(t2_wb_adr_o), + .t1_wb_sel_o(t2_wb_sel_o), + .t1_wb_we_o(t2_wb_we_o), + .t1_wb_dat_o(t2_wb_dat_o), + .t1_wb_dat_i(t2_wb_dat_i), + .t1_wb_ack_i(t2_wb_ack_i), + .t1_wb_err_i(t2_wb_err_i), + + .t2_wb_cyc_o(t3_wb_cyc_o), + .t2_wb_stb_o(t3_wb_stb_o), + .t2_wb_adr_o(t3_wb_adr_o), + .t2_wb_sel_o(t3_wb_sel_o), + .t2_wb_we_o(t3_wb_we_o), + .t2_wb_dat_o(t3_wb_dat_o), + .t2_wb_dat_i(t3_wb_dat_i), + .t2_wb_ack_i(t3_wb_ack_i), + .t2_wb_err_i(t3_wb_err_i), + + .t3_wb_cyc_o(t4_wb_cyc_o), + .t3_wb_stb_o(t4_wb_stb_o), + .t3_wb_adr_o(t4_wb_adr_o), + .t3_wb_sel_o(t4_wb_sel_o), + .t3_wb_we_o(t4_wb_we_o), + .t3_wb_dat_o(t4_wb_dat_o), + .t3_wb_dat_i(t4_wb_dat_i), + .t3_wb_ack_i(t4_wb_ack_i), + .t3_wb_err_i(t4_wb_err_i), + + .t4_wb_cyc_o(t5_wb_cyc_o), + .t4_wb_stb_o(t5_wb_stb_o), + .t4_wb_adr_o(t5_wb_adr_o), + .t4_wb_sel_o(t5_wb_sel_o), + .t4_wb_we_o(t5_wb_we_o), + .t4_wb_dat_o(t5_wb_dat_o), + .t4_wb_dat_i(t5_wb_dat_i), + .t4_wb_ack_i(t5_wb_ack_i), + .t4_wb_err_i(t5_wb_err_i), + + .t5_wb_cyc_o(t6_wb_cyc_o), + .t5_wb_stb_o(t6_wb_stb_o), + .t5_wb_adr_o(t6_wb_adr_o), + .t5_wb_sel_o(t6_wb_sel_o), + .t5_wb_we_o(t6_wb_we_o), + .t5_wb_dat_o(t6_wb_dat_o), + .t5_wb_dat_i(t6_wb_dat_i), + .t5_wb_ack_i(t6_wb_ack_i), + .t5_wb_err_i(t6_wb_err_i), + + .t6_wb_cyc_o(t7_wb_cyc_o), + .t6_wb_stb_o(t7_wb_stb_o), + .t6_wb_adr_o(t7_wb_adr_o), + .t6_wb_sel_o(t7_wb_sel_o), + .t6_wb_we_o(t7_wb_we_o), + .t6_wb_dat_o(t7_wb_dat_o), + .t6_wb_dat_i(t7_wb_dat_i), + .t6_wb_ack_i(t7_wb_ack_i), + .t6_wb_err_i(t7_wb_err_i), + + .t7_wb_cyc_o(t8_wb_cyc_o), + .t7_wb_stb_o(t8_wb_stb_o), + .t7_wb_adr_o(t8_wb_adr_o), + .t7_wb_sel_o(t8_wb_sel_o), + .t7_wb_we_o(t8_wb_we_o), + .t7_wb_dat_o(t8_wb_dat_o), + .t7_wb_dat_i(t8_wb_dat_i), + .t7_wb_ack_i(t8_wb_ack_i), + .t7_wb_err_i(t8_wb_err_i) + +); + +endmodule + +// +// Multiple initiator to single target +// +module tc_mi_to_st ( + wb_clk_i, + wb_rst_i, + + i0_wb_cyc_i, + i0_wb_stb_i, + i0_wb_adr_i, + i0_wb_sel_i, + i0_wb_we_i, + i0_wb_dat_i, + i0_wb_dat_o, + i0_wb_ack_o, + i0_wb_err_o, + + i1_wb_cyc_i, + i1_wb_stb_i, + i1_wb_adr_i, + i1_wb_sel_i, + i1_wb_we_i, + i1_wb_dat_i, + i1_wb_dat_o, + i1_wb_ack_o, + i1_wb_err_o, + + i2_wb_cyc_i, + i2_wb_stb_i, + i2_wb_adr_i, + i2_wb_sel_i, + i2_wb_we_i, + i2_wb_dat_i, + i2_wb_dat_o, + i2_wb_ack_o, + i2_wb_err_o, + + i3_wb_cyc_i, + i3_wb_stb_i, + i3_wb_adr_i, + i3_wb_sel_i, + i3_wb_we_i, + i3_wb_dat_i, + i3_wb_dat_o, + i3_wb_ack_o, + i3_wb_err_o, + + i4_wb_cyc_i, + i4_wb_stb_i, + i4_wb_adr_i, + i4_wb_sel_i, + i4_wb_we_i, + i4_wb_dat_i, + i4_wb_dat_o, + i4_wb_ack_o, + i4_wb_err_o, + + i5_wb_cyc_i, + i5_wb_stb_i, + i5_wb_adr_i, + i5_wb_sel_i, + i5_wb_we_i, + i5_wb_dat_i, + i5_wb_dat_o, + i5_wb_ack_o, + i5_wb_err_o, + + i6_wb_cyc_i, + i6_wb_stb_i, + i6_wb_adr_i, + i6_wb_sel_i, + i6_wb_we_i, + i6_wb_dat_i, + i6_wb_dat_o, + i6_wb_ack_o, + i6_wb_err_o, + + i7_wb_cyc_i, + i7_wb_stb_i, + i7_wb_adr_i, + i7_wb_sel_i, + i7_wb_we_i, + i7_wb_dat_i, + i7_wb_dat_o, + i7_wb_ack_o, + i7_wb_err_o, + + t0_wb_cyc_o, + t0_wb_stb_o, + t0_wb_adr_o, + t0_wb_sel_o, + t0_wb_we_o, + t0_wb_dat_o, + t0_wb_dat_i, + t0_wb_ack_i, + t0_wb_err_i + +); + +// +// Parameters +// +parameter t0_addr_w = 2; +parameter t0_addr = 2'b00; +parameter multitarg = 1'b0; +parameter t17_addr_w = 2; +parameter t17_addr = 2'b00; + +// +// I/O Ports +// +input wb_clk_i; +input wb_rst_i; + +// +// WB slave i/f connecting initiator 0 +// +input i0_wb_cyc_i; +input i0_wb_stb_i; +input [`TC_AW-1:0] i0_wb_adr_i; +input [`TC_BSW-1:0] i0_wb_sel_i; +input i0_wb_we_i; +input [`TC_DW-1:0] i0_wb_dat_i; +output [`TC_DW-1:0] i0_wb_dat_o; +output i0_wb_ack_o; +output i0_wb_err_o; + +// +// WB slave i/f connecting initiator 1 +// +input i1_wb_cyc_i; +input i1_wb_stb_i; +input [`TC_AW-1:0] i1_wb_adr_i; +input [`TC_BSW-1:0] i1_wb_sel_i; +input i1_wb_we_i; +input [`TC_DW-1:0] i1_wb_dat_i; +output [`TC_DW-1:0] i1_wb_dat_o; +output i1_wb_ack_o; +output i1_wb_err_o; + +// +// WB slave i/f connecting initiator 2 +// +input i2_wb_cyc_i; +input i2_wb_stb_i; +input [`TC_AW-1:0] i2_wb_adr_i; +input [`TC_BSW-1:0] i2_wb_sel_i; +input i2_wb_we_i; +input [`TC_DW-1:0] i2_wb_dat_i; +output [`TC_DW-1:0] i2_wb_dat_o; +output i2_wb_ack_o; +output i2_wb_err_o; + +// +// WB slave i/f connecting initiator 3 +// +input i3_wb_cyc_i; +input i3_wb_stb_i; +input [`TC_AW-1:0] i3_wb_adr_i; +input [`TC_BSW-1:0] i3_wb_sel_i; +input i3_wb_we_i; +input [`TC_DW-1:0] i3_wb_dat_i; +output [`TC_DW-1:0] i3_wb_dat_o; +output i3_wb_ack_o; +output i3_wb_err_o; + +// +// WB slave i/f connecting initiator 4 +// +input i4_wb_cyc_i; +input i4_wb_stb_i; +input [`TC_AW-1:0] i4_wb_adr_i; +input [`TC_BSW-1:0] i4_wb_sel_i; +input i4_wb_we_i; +input [`TC_DW-1:0] i4_wb_dat_i; +output [`TC_DW-1:0] i4_wb_dat_o; +output i4_wb_ack_o; +output i4_wb_err_o; + +// +// WB slave i/f connecting initiator 5 +// +input i5_wb_cyc_i; +input i5_wb_stb_i; +input [`TC_AW-1:0] i5_wb_adr_i; +input [`TC_BSW-1:0] i5_wb_sel_i; +input i5_wb_we_i; +input [`TC_DW-1:0] i5_wb_dat_i; +output [`TC_DW-1:0] i5_wb_dat_o; +output i5_wb_ack_o; +output i5_wb_err_o; + +// +// WB slave i/f connecting initiator 6 +// +input i6_wb_cyc_i; +input i6_wb_stb_i; +input [`TC_AW-1:0] i6_wb_adr_i; +input [`TC_BSW-1:0] i6_wb_sel_i; +input i6_wb_we_i; +input [`TC_DW-1:0] i6_wb_dat_i; +output [`TC_DW-1:0] i6_wb_dat_o; +output i6_wb_ack_o; +output i6_wb_err_o; + +// +// WB slave i/f connecting initiator 7 +// +input i7_wb_cyc_i; +input i7_wb_stb_i; +input [`TC_AW-1:0] i7_wb_adr_i; +input [`TC_BSW-1:0] i7_wb_sel_i; +input i7_wb_we_i; +input [`TC_DW-1:0] i7_wb_dat_i; +output [`TC_DW-1:0] i7_wb_dat_o; +output i7_wb_ack_o; +output i7_wb_err_o; + +// +// WB master i/f connecting target +// +output t0_wb_cyc_o; +output t0_wb_stb_o; +output [`TC_AW-1:0] t0_wb_adr_o; +output [`TC_BSW-1:0] t0_wb_sel_o; +output t0_wb_we_o; +output [`TC_DW-1:0] t0_wb_dat_o; +input [`TC_DW-1:0] t0_wb_dat_i; +input t0_wb_ack_i; +input t0_wb_err_i; + +// +// Internal wires & registers +// +wire [`TC_IIN_W-1:0] i0_in, i1_in, + i2_in, i3_in, + i4_in, i5_in, + i6_in, i7_in; +wire [`TC_TIN_W-1:0] i0_out, i1_out, + i2_out, i3_out, + i4_out, i5_out, + i6_out, i7_out; +wire [`TC_IIN_W-1:0] t0_out; +wire [`TC_TIN_W-1:0] t0_in; +wire [7:0] req_i; +wire [2:0] req_won; +reg req_cont; +reg [2:0] req_r; + +// +// Group WB initiator 0 i/f inputs and outputs +// +assign i0_in = {i0_wb_cyc_i, i0_wb_stb_i, i0_wb_adr_i, + i0_wb_sel_i, i0_wb_we_i, i0_wb_dat_i}; +assign {i0_wb_dat_o, i0_wb_ack_o, i0_wb_err_o} = i0_out; + +// +// Group WB initiator 1 i/f inputs and outputs +// +assign i1_in = {i1_wb_cyc_i, i1_wb_stb_i, i1_wb_adr_i, + i1_wb_sel_i, i1_wb_we_i, i1_wb_dat_i}; +assign {i1_wb_dat_o, i1_wb_ack_o, i1_wb_err_o} = i1_out; + +// +// Group WB initiator 2 i/f inputs and outputs +// +assign i2_in = {i2_wb_cyc_i, i2_wb_stb_i, i2_wb_adr_i, + i2_wb_sel_i, i2_wb_we_i, i2_wb_dat_i}; +assign {i2_wb_dat_o, i2_wb_ack_o, i2_wb_err_o} = i2_out; + +// +// Group WB initiator 3 i/f inputs and outputs +// +assign i3_in = {i3_wb_cyc_i, i3_wb_stb_i, i3_wb_adr_i, + i3_wb_sel_i, i3_wb_we_i, i3_wb_dat_i}; +assign {i3_wb_dat_o, i3_wb_ack_o, i3_wb_err_o} = i3_out; + +// +// Group WB initiator 4 i/f inputs and outputs +// +assign i4_in = {i4_wb_cyc_i, i4_wb_stb_i, i4_wb_adr_i, + i4_wb_sel_i, i4_wb_we_i, i4_wb_dat_i}; +assign {i4_wb_dat_o, i4_wb_ack_o, i4_wb_err_o} = i4_out; + +// +// Group WB initiator 5 i/f inputs and outputs +// +assign i5_in = {i5_wb_cyc_i, i5_wb_stb_i, i5_wb_adr_i, + i5_wb_sel_i, i5_wb_we_i, i5_wb_dat_i}; +assign {i5_wb_dat_o, i5_wb_ack_o, i5_wb_err_o} = i5_out; + +// +// Group WB initiator 6 i/f inputs and outputs +// +assign i6_in = {i6_wb_cyc_i, i6_wb_stb_i, i6_wb_adr_i, + i6_wb_sel_i, i6_wb_we_i, i6_wb_dat_i}; +assign {i6_wb_dat_o, i6_wb_ack_o, i6_wb_err_o} = i6_out; + +// +// Group WB initiator 7 i/f inputs and outputs +// +assign i7_in = {i7_wb_cyc_i, i7_wb_stb_i, i7_wb_adr_i, + i7_wb_sel_i, i7_wb_we_i, i7_wb_dat_i}; +assign {i7_wb_dat_o, i7_wb_ack_o, i7_wb_err_o} = i7_out; + +// +// Group WB target 0 i/f inputs and outputs +// +assign {t0_wb_cyc_o, t0_wb_stb_o, t0_wb_adr_o, + t0_wb_sel_o, t0_wb_we_o, t0_wb_dat_o} = t0_out; +assign t0_in = {t0_wb_dat_i, t0_wb_ack_i, t0_wb_err_i}; + +// +// Assign to WB initiator i/f outputs +// +// Either inputs from the target are assigned or zeros. +// +assign i0_out = (req_won == 3'd0) ? t0_in : {`TC_TIN_W{1'b0}}; +assign i1_out = (req_won == 3'd1) ? t0_in : {`TC_TIN_W{1'b0}}; +assign i2_out = (req_won == 3'd2) ? t0_in : {`TC_TIN_W{1'b0}}; +assign i3_out = (req_won == 3'd3) ? t0_in : {`TC_TIN_W{1'b0}}; +assign i4_out = (req_won == 3'd4) ? t0_in : {`TC_TIN_W{1'b0}}; +assign i5_out = (req_won == 3'd5) ? t0_in : {`TC_TIN_W{1'b0}}; +assign i6_out = (req_won == 3'd6) ? t0_in : {`TC_TIN_W{1'b0}}; +assign i7_out = (req_won == 3'd7) ? t0_in : {`TC_TIN_W{1'b0}}; + +// +// Assign to WB target i/f outputs +// +// Assign inputs from initiator to target outputs according to +// which initiator has won. If there is no request for the target, +// assign zeros. +// +assign t0_out = (req_won == 3'd0) ? i0_in : + (req_won == 3'd1) ? i1_in : + (req_won == 3'd2) ? i2_in : + (req_won == 3'd3) ? i3_in : + (req_won == 3'd4) ? i4_in : + (req_won == 3'd5) ? i5_in : + (req_won == 3'd6) ? i6_in : + (req_won == 3'd7) ? i7_in : {`TC_IIN_W{1'b0}}; + +// +// Determine if an initiator has address of the target. +// +assign req_i[0] = i0_wb_cyc_i & + ((i0_wb_adr_i[`TC_AW-1:`TC_AW-t0_addr_w] == t0_addr) | + multitarg & (i0_wb_adr_i[`TC_AW-1:`TC_AW-t17_addr_w] == t17_addr)); +assign req_i[1] = i1_wb_cyc_i & + ((i1_wb_adr_i[`TC_AW-1:`TC_AW-t0_addr_w] == t0_addr) | + multitarg & (i1_wb_adr_i[`TC_AW-1:`TC_AW-t17_addr_w] == t17_addr)); +assign req_i[2] = i2_wb_cyc_i & + ((i2_wb_adr_i[`TC_AW-1:`TC_AW-t0_addr_w] == t0_addr) | + multitarg & (i2_wb_adr_i[`TC_AW-1:`TC_AW-t17_addr_w] == t17_addr)); +assign req_i[3] = i3_wb_cyc_i & + ((i3_wb_adr_i[`TC_AW-1:`TC_AW-t0_addr_w] == t0_addr) | + multitarg & (i3_wb_adr_i[`TC_AW-1:`TC_AW-t17_addr_w] == t17_addr)); +assign req_i[4] = i4_wb_cyc_i & + ((i4_wb_adr_i[`TC_AW-1:`TC_AW-t0_addr_w] == t0_addr) | + multitarg & (i4_wb_adr_i[`TC_AW-1:`TC_AW-t17_addr_w] == t17_addr)); +assign req_i[5] = i5_wb_cyc_i & + ((i5_wb_adr_i[`TC_AW-1:`TC_AW-t0_addr_w] == t0_addr) | + multitarg & (i5_wb_adr_i[`TC_AW-1:`TC_AW-t17_addr_w] == t17_addr)); +assign req_i[6] = i6_wb_cyc_i & + ((i6_wb_adr_i[`TC_AW-1:`TC_AW-t0_addr_w] == t0_addr) | + multitarg & (i6_wb_adr_i[`TC_AW-1:`TC_AW-t17_addr_w] == t17_addr)); +assign req_i[7] = i7_wb_cyc_i & + ((i7_wb_adr_i[`TC_AW-1:`TC_AW-t0_addr_w] == t0_addr) | + multitarg & (i7_wb_adr_i[`TC_AW-1:`TC_AW-t17_addr_w] == t17_addr)); + +// +// Determine who gets current access to the target. +// +// If current initiator still asserts request, do nothing +// (keep current initiator). +// Otherwise check each initiator's request, starting from initiator 0 +// (highest priority). +// If there is no requests from initiators, park initiator 0. +// +assign req_won = req_cont ? req_r : + req_i[0] ? 3'd0 : + req_i[1] ? 3'd1 : + req_i[2] ? 3'd2 : + req_i[3] ? 3'd3 : + req_i[4] ? 3'd4 : + req_i[5] ? 3'd5 : + req_i[6] ? 3'd6 : + req_i[7] ? 3'd7 : 3'd0; + +// +// Check if current initiator still wants access to the target and if +// it does, assert req_cont. +// +always @(req_r or req_i) + case (req_r) // synopsys parallel_case + 3'd0: req_cont = req_i[0]; + 3'd1: req_cont = req_i[1]; + 3'd2: req_cont = req_i[2]; + 3'd3: req_cont = req_i[3]; + 3'd4: req_cont = req_i[4]; + 3'd5: req_cont = req_i[5]; + 3'd6: req_cont = req_i[6]; + 3'd7: req_cont = req_i[7]; + endcase + +// +// Register who has current access to the target. +// +always @(posedge wb_clk_i or posedge wb_rst_i) + if (wb_rst_i) + req_r <= #1 3'd0; + else + req_r <= #1 req_won; + +endmodule + +// +// Single initiator to multiple targets +// +module tc_si_to_mt ( + + i0_wb_cyc_i, + i0_wb_stb_i, + i0_wb_adr_i, + i0_wb_sel_i, + i0_wb_we_i, + i0_wb_dat_i, + i0_wb_dat_o, + i0_wb_ack_o, + i0_wb_err_o, + + t0_wb_cyc_o, + t0_wb_stb_o, + t0_wb_adr_o, + t0_wb_sel_o, + t0_wb_we_o, + t0_wb_dat_o, + t0_wb_dat_i, + t0_wb_ack_i, + t0_wb_err_i, + + t1_wb_cyc_o, + t1_wb_stb_o, + t1_wb_adr_o, + t1_wb_sel_o, + t1_wb_we_o, + t1_wb_dat_o, + t1_wb_dat_i, + t1_wb_ack_i, + t1_wb_err_i, + + t2_wb_cyc_o, + t2_wb_stb_o, + t2_wb_adr_o, + t2_wb_sel_o, + t2_wb_we_o, + t2_wb_dat_o, + t2_wb_dat_i, + t2_wb_ack_i, + t2_wb_err_i, + + t3_wb_cyc_o, + t3_wb_stb_o, + t3_wb_adr_o, + t3_wb_sel_o, + t3_wb_we_o, + t3_wb_dat_o, + t3_wb_dat_i, + t3_wb_ack_i, + t3_wb_err_i, + + t4_wb_cyc_o, + t4_wb_stb_o, + t4_wb_adr_o, + t4_wb_sel_o, + t4_wb_we_o, + t4_wb_dat_o, + t4_wb_dat_i, + t4_wb_ack_i, + t4_wb_err_i, + + t5_wb_cyc_o, + t5_wb_stb_o, + t5_wb_adr_o, + t5_wb_sel_o, + t5_wb_we_o, + t5_wb_dat_o, + t5_wb_dat_i, + t5_wb_ack_i, + t5_wb_err_i, + + t6_wb_cyc_o, + t6_wb_stb_o, + t6_wb_adr_o, + t6_wb_sel_o, + t6_wb_we_o, + t6_wb_dat_o, + t6_wb_dat_i, + t6_wb_ack_i, + t6_wb_err_i, + + t7_wb_cyc_o, + t7_wb_stb_o, + t7_wb_adr_o, + t7_wb_sel_o, + t7_wb_we_o, + t7_wb_dat_o, + t7_wb_dat_i, + t7_wb_ack_i, + t7_wb_err_i + +); + +// +// Parameters +// +parameter t0_addr_w = 3; +parameter t0_addr = 3'd0; +parameter t17_addr_w = 3; +parameter t1_addr = 3'd1; +parameter t2_addr = 3'd2; +parameter t3_addr = 3'd3; +parameter t4_addr = 3'd4; +parameter t5_addr = 3'd5; +parameter t6_addr = 3'd6; +parameter t7_addr = 3'd7; + +// +// I/O Ports +// + +// +// WB slave i/f connecting initiator 0 +// +input i0_wb_cyc_i; +input i0_wb_stb_i; +input [`TC_AW-1:0] i0_wb_adr_i; +input [`TC_BSW-1:0] i0_wb_sel_i; +input i0_wb_we_i; +input [`TC_DW-1:0] i0_wb_dat_i; +output [`TC_DW-1:0] i0_wb_dat_o; +output i0_wb_ack_o; +output i0_wb_err_o; + +// +// WB master i/f connecting target 0 +// +output t0_wb_cyc_o; +output t0_wb_stb_o; +output [`TC_AW-1:0] t0_wb_adr_o; +output [`TC_BSW-1:0] t0_wb_sel_o; +output t0_wb_we_o; +output [`TC_DW-1:0] t0_wb_dat_o; +input [`TC_DW-1:0] t0_wb_dat_i; +input t0_wb_ack_i; +input t0_wb_err_i; + +// +// WB master i/f connecting target 1 +// +output t1_wb_cyc_o; +output t1_wb_stb_o; +output [`TC_AW-1:0] t1_wb_adr_o; +output [`TC_BSW-1:0] t1_wb_sel_o; +output t1_wb_we_o; +output [`TC_DW-1:0] t1_wb_dat_o; +input [`TC_DW-1:0] t1_wb_dat_i; +input t1_wb_ack_i; +input t1_wb_err_i; + +// +// WB master i/f connecting target 2 +// +output t2_wb_cyc_o; +output t2_wb_stb_o; +output [`TC_AW-1:0] t2_wb_adr_o; +output [`TC_BSW-1:0] t2_wb_sel_o; +output t2_wb_we_o; +output [`TC_DW-1:0] t2_wb_dat_o; +input [`TC_DW-1:0] t2_wb_dat_i; +input t2_wb_ack_i; +input t2_wb_err_i; + +// +// WB master i/f connecting target 3 +// +output t3_wb_cyc_o; +output t3_wb_stb_o; +output [`TC_AW-1:0] t3_wb_adr_o; +output [`TC_BSW-1:0] t3_wb_sel_o; +output t3_wb_we_o; +output [`TC_DW-1:0] t3_wb_dat_o; +input [`TC_DW-1:0] t3_wb_dat_i; +input t3_wb_ack_i; +input t3_wb_err_i; + +// +// WB master i/f connecting target 4 +// +output t4_wb_cyc_o; +output t4_wb_stb_o; +output [`TC_AW-1:0] t4_wb_adr_o; +output [`TC_BSW-1:0] t4_wb_sel_o; +output t4_wb_we_o; +output [`TC_DW-1:0] t4_wb_dat_o; +input [`TC_DW-1:0] t4_wb_dat_i; +input t4_wb_ack_i; +input t4_wb_err_i; + +// +// WB master i/f connecting target 5 +// +output t5_wb_cyc_o; +output t5_wb_stb_o; +output [`TC_AW-1:0] t5_wb_adr_o; +output [`TC_BSW-1:0] t5_wb_sel_o; +output t5_wb_we_o; +output [`TC_DW-1:0] t5_wb_dat_o; +input [`TC_DW-1:0] t5_wb_dat_i; +input t5_wb_ack_i; +input t5_wb_err_i; + +// +// WB master i/f connecting target 6 +// +output t6_wb_cyc_o; +output t6_wb_stb_o; +output [`TC_AW-1:0] t6_wb_adr_o; +output [`TC_BSW-1:0] t6_wb_sel_o; +output t6_wb_we_o; +output [`TC_DW-1:0] t6_wb_dat_o; +input [`TC_DW-1:0] t6_wb_dat_i; +input t6_wb_ack_i; +input t6_wb_err_i; + +// +// WB master i/f connecting target 7 +// +output t7_wb_cyc_o; +output t7_wb_stb_o; +output [`TC_AW-1:0] t7_wb_adr_o; +output [`TC_BSW-1:0] t7_wb_sel_o; +output t7_wb_we_o; +output [`TC_DW-1:0] t7_wb_dat_o; +input [`TC_DW-1:0] t7_wb_dat_i; +input t7_wb_ack_i; +input t7_wb_err_i; + +// +// Internal wires & registers +// +wire [`TC_IIN_W-1:0] i0_in; +wire [`TC_TIN_W-1:0] i0_out; +wire [`TC_IIN_W-1:0] t0_out, t1_out, + t2_out, t3_out, + t4_out, t5_out, + t6_out, t7_out; +wire [`TC_TIN_W-1:0] t0_in, t1_in, + t2_in, t3_in, + t4_in, t5_in, + t6_in, t7_in; +wire [7:0] req_t; + +// +// Group WB initiator 0 i/f inputs and outputs +// +assign i0_in = {i0_wb_cyc_i, i0_wb_stb_i, i0_wb_adr_i, + i0_wb_sel_i, i0_wb_we_i, i0_wb_dat_i}; +assign {i0_wb_dat_o, i0_wb_ack_o, i0_wb_err_o} = i0_out; + +// +// Group WB target 0 i/f inputs and outputs +// +assign {t0_wb_cyc_o, t0_wb_stb_o, t0_wb_adr_o, + t0_wb_sel_o, t0_wb_we_o, t0_wb_dat_o} = t0_out; +assign t0_in = {t0_wb_dat_i, t0_wb_ack_i, t0_wb_err_i}; + +// +// Group WB target 1 i/f inputs and outputs +// +assign {t1_wb_cyc_o, t1_wb_stb_o, t1_wb_adr_o, + t1_wb_sel_o, t1_wb_we_o, t1_wb_dat_o} = t1_out; +assign t1_in = {t1_wb_dat_i, t1_wb_ack_i, t1_wb_err_i}; + +// +// Group WB target 2 i/f inputs and outputs +// +assign {t2_wb_cyc_o, t2_wb_stb_o, t2_wb_adr_o, + t2_wb_sel_o, t2_wb_we_o, t2_wb_dat_o} = t2_out; +assign t2_in = {t2_wb_dat_i, t2_wb_ack_i, t2_wb_err_i}; + +// +// Group WB target 3 i/f inputs and outputs +// +assign {t3_wb_cyc_o, t3_wb_stb_o, t3_wb_adr_o, + t3_wb_sel_o, t3_wb_we_o, t3_wb_dat_o} = t3_out; +assign t3_in = {t3_wb_dat_i, t3_wb_ack_i, t3_wb_err_i}; + +// +// Group WB target 4 i/f inputs and outputs +// +assign {t4_wb_cyc_o, t4_wb_stb_o, t4_wb_adr_o, + t4_wb_sel_o, t4_wb_we_o, t4_wb_dat_o} = t4_out; +assign t4_in = {t4_wb_dat_i, t4_wb_ack_i, t4_wb_err_i}; + +// +// Group WB target 5 i/f inputs and outputs +// +assign {t5_wb_cyc_o, t5_wb_stb_o, t5_wb_adr_o, + t5_wb_sel_o, t5_wb_we_o, t5_wb_dat_o} = t5_out; +assign t5_in = {t5_wb_dat_i, t5_wb_ack_i, t5_wb_err_i}; + +// +// Group WB target 6 i/f inputs and outputs +// +assign {t6_wb_cyc_o, t6_wb_stb_o, t6_wb_adr_o, + t6_wb_sel_o, t6_wb_we_o, t6_wb_dat_o} = t6_out; +assign t6_in = {t6_wb_dat_i, t6_wb_ack_i, t6_wb_err_i}; + +// +// Group WB target 7 i/f inputs and outputs +// +assign {t7_wb_cyc_o, t7_wb_stb_o, t7_wb_adr_o, + t7_wb_sel_o, t7_wb_we_o, t7_wb_dat_o} = t7_out; +assign t7_in = {t7_wb_dat_i, t7_wb_ack_i, t7_wb_err_i}; + +// +// Assign to WB target i/f outputs +// +// Either inputs from the initiator are assigned or zeros. +// +assign t0_out = req_t[0] ? i0_in : {`TC_IIN_W{1'b0}}; +assign t1_out = req_t[1] ? i0_in : {`TC_IIN_W{1'b0}}; +assign t2_out = req_t[2] ? i0_in : {`TC_IIN_W{1'b0}}; +assign t3_out = req_t[3] ? i0_in : {`TC_IIN_W{1'b0}}; +assign t4_out = req_t[4] ? i0_in : {`TC_IIN_W{1'b0}}; +assign t5_out = req_t[5] ? i0_in : {`TC_IIN_W{1'b0}}; +assign t6_out = req_t[6] ? i0_in : {`TC_IIN_W{1'b0}}; +assign t7_out = req_t[7] ? i0_in : {`TC_IIN_W{1'b0}}; + +// +// Assign to WB initiator i/f outputs +// +// Assign inputs from target to initiator outputs according to +// which target is accessed. If there is no request for a target, +// assign zeros. +// +assign i0_out = req_t[0] ? t0_in : + req_t[1] ? t1_in : + req_t[2] ? t2_in : + req_t[3] ? t3_in : + req_t[4] ? t4_in : + req_t[5] ? t5_in : + req_t[6] ? t6_in : + req_t[7] ? t7_in : {`TC_TIN_W{1'b0}}; + +// +// Determine which target is being accessed. +// +assign req_t[0] = i0_wb_cyc_i & (i0_wb_adr_i[`TC_AW-1:`TC_AW-t0_addr_w] == t0_addr); +assign req_t[1] = i0_wb_cyc_i & (i0_wb_adr_i[`TC_AW-1:`TC_AW-t17_addr_w] == t1_addr); +assign req_t[2] = i0_wb_cyc_i & (i0_wb_adr_i[`TC_AW-1:`TC_AW-t17_addr_w] == t2_addr); +assign req_t[3] = i0_wb_cyc_i & (i0_wb_adr_i[`TC_AW-1:`TC_AW-t17_addr_w] == t3_addr); +assign req_t[4] = i0_wb_cyc_i & (i0_wb_adr_i[`TC_AW-1:`TC_AW-t17_addr_w] == t4_addr); +assign req_t[5] = i0_wb_cyc_i & (i0_wb_adr_i[`TC_AW-1:`TC_AW-t17_addr_w] == t5_addr); +assign req_t[6] = i0_wb_cyc_i & (i0_wb_adr_i[`TC_AW-1:`TC_AW-t17_addr_w] == t6_addr); +assign req_t[7] = i0_wb_cyc_i & (i0_wb_adr_i[`TC_AW-1:`TC_AW-t17_addr_w] == t7_addr); + +endmodule
release-1.0/rtl/verilog/minsoc_tc_top.v Property changes : Added: svn:executable ## -0,0 +1 ## +* \ No newline at end of property Index: release-1.0/rtl/verilog/minsoc_onchip_ram.v =================================================================== --- release-1.0/rtl/verilog/minsoc_onchip_ram.v (nonexistent) +++ release-1.0/rtl/verilog/minsoc_onchip_ram.v (revision 151) @@ -0,0 +1,458 @@ +////////////////////////////////////////////////////////////////////// +//// //// +//// Generic Single-Port Synchronous RAM //// +//// //// +//// This file is part of memory library available from //// +//// http://www.opencores.org/cvsweb.shtml/minsoc/ //// +//// //// +//// Description //// +//// This block is a wrapper with common single-port //// +//// synchronous memory interface for different //// +//// types of ASIC and FPGA RAMs. Beside universal memory //// +//// interface it also provides behavioral model of generic //// +//// single-port synchronous RAM. //// +//// It should be used in all OPENCORES designs that want to be //// +//// portable accross different target technologies and //// +//// independent of target memory. //// +//// //// +//// Supported ASIC RAMs are: //// +//// - Artisan Single-Port Sync RAM //// +//// - Avant! Two-Port Sync RAM (*) //// +//// - Virage Single-Port Sync RAM //// +//// - Virtual Silicon Single-Port Sync RAM //// +//// //// +//// Supported FPGA RAMs are: //// +//// - Xilinx Virtex RAMB16 //// +//// - Xilinx Virtex RAMB4 //// +//// - Altera LPM //// +//// //// +//// To Do: //// +//// - fix avant! two-port ram //// +//// - add additional RAMs //// +//// //// +//// Author(s): //// +//// - Raul Fajardo, rfajardo@gmail.com //// +//// - Damjan Lampret, lampret@opencores.org //// +//// //// +////////////////////////////////////////////////////////////////////// +//// //// +//// Copyright (C) 2000 Authors and OPENCORES.ORG //// +//// //// +//// This source file may be used and distributed without //// +//// restriction provided that this copyright statement is not //// +//// removed from the file and that any derivative work contains //// +//// the original copyright notice and the associated disclaimer. //// +//// //// +//// This source file is free software; you can redistribute it //// +//// and/or modify it under the terms of the GNU Lesser General //// +//// Public License as published by the Free Software Foundation; //// +//// either version 2.1 of the License, or (at your option) any //// +//// later version. //// +//// //// +//// This source is distributed in the hope that it will be //// +//// useful, but WITHOUT ANY WARRANTY; without even the implied //// +//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR //// +//// PURPOSE. See the GNU Lesser General Public License for more //// +//// details. //// +//// //// +//// You should have received a copy of the GNU Lesser General //// +//// Public License along with this source; if not, download it //// +//// from http://www.gnu.org/licenses/lgpl.html //// +//// //// +////////////////////////////////////////////////////////////////////// +// +// Revision History +// +// +// Revision 2.1 2009/08/23 16:41:00 fajardo +// Sensitivity of addr_reg and memory write changed back to posedge clk for GENERIC_MEMORY +// This actually models appropriately the behavior of the FPGA internal RAMs +// +// Revision 2.0 2009/09/10 11:30:00 fajardo +// Added tri-state buffering for altera output +// Sensitivity of addr_reg and memory write changed to negedge clk for GENERIC_MEMORY +// +// Revision 1.9 2009/08/18 15:15:00 fajardo +// Added tri-state buffering for xilinx and generic memory output +// +// $Log: not supported by cvs2svn $ +// Revision 1.8 2004/06/08 18:15:32 lampret +// Changed behavior of the simulation generic models +// +// Revision 1.7 2004/04/05 08:29:57 lampret +// Merged branch_qmem into main tree. +// +// Revision 1.3.4.1 2003/12/09 11:46:48 simons +// Mbist nameing changed, Artisan ram instance signal names fixed, some synthesis waning fixed. +// +// Revision 1.3 2003/04/07 01:19:07 lampret +// Added Altera LPM RAMs. Changed generic RAM output when OE inactive. +// +// Revision 1.2 2002/10/17 20:04:40 lampret +// Added BIST scan. Special VS RAMs need to be used to implement BIST. +// +// Revision 1.1 2002/01/03 08:16:15 lampret +// New prefixes for RTL files, prefixed module names. Updated cache controllers and MMUs. +// +// Revision 1.8 2001/11/02 18:57:14 lampret +// Modified virtual silicon instantiations. +// +// Revision 1.7 2001/10/21 17:57:16 lampret +// Removed params from generic_XX.v. Added translate_off/on in sprs.v and id.v. Removed spr_addr from dc.v and ic.v. Fixed CR+LF. +// +// Revision 1.6 2001/10/14 13:12:09 lampret +// MP3 version. +// +// Revision 1.1.1.1 2001/10/06 10:18:36 igorm +// no message +// +// Revision 1.1 2001/08/09 13:39:33 lampret +// Major clean-up. +// +// Revision 1.2 2001/07/30 05:38:02 lampret +// Adding empty directories required by HDL coding guidelines +// +// + +// synopsys translate_off +`include "timescale.v" +// synopsys translate_on +`include "minsoc_defines.v" + +module minsoc_onchip_ram( +`ifdef BIST + // RAM BIST + mbist_si_i, mbist_so_o, mbist_ctrl_i, +`endif + // Generic synchronous single-port RAM interface + clk, rst, ce, we, oe, addr, di, doq +); + +// +// Default address and data buses width +// +parameter aw = 11; +parameter dw = 8; + +`ifdef BIST +// +// RAM BIST +// +input mbist_si_i; +input [`MBIST_CTRL_WIDTH - 1:0] mbist_ctrl_i; +output mbist_so_o; +`endif + +// +// Generic synchronous single-port RAM interface +// +input clk; // Clock +input rst; // Reset +input ce; // Chip enable input +input we; // Write enable input +input oe; // Output enable input +input [aw-1:0] addr; // address bus inputs +input [dw-1:0] di; // input data bus +output [dw-1:0] doq; // output data bus + +// +// Decide memory implementation for Xilinx FPGAs +// +`ifdef SPARTAN2 + `define MINSOC_XILINX_RAMB4 +`elsif VIRTEX + `define MINSOC_XILINX_RAMB4 +`endif // !SPARTAN2/VIRTEX + +`ifdef SPARTAN3 + `define MINSOC_XILINX_RAMB16 +`elsif SPARTAN3E + `define MINSOC_XILINX_RAMB16 +`elsif SPARTAN3A + `define MINSOC_XILINX_RAMB16 +`elsif VIRTEX2 + `define MINSOC_XILINX_RAMB16 +`elsif VIRTEX4 + `define MINSOC_XILINX_RAMB16 +`elsif VIRTEX5 + `define MINSOC_XILINX_RAMB16 +`endif // !SPARTAN3/SPARTAN3E/SPARTAN3A/VIRTEX2/VIRTEX4/VIRTEX5 + + +// +// Internal wires and registers +// + +`ifdef ARTISAN_SSP +`else +`ifdef VIRTUALSILICON_SSP +`else +`ifdef BIST +assign mbist_so_o = mbist_si_i; +`endif +`endif +`endif + + +`ifdef GENERIC_MEMORY +// +// Generic single-port synchronous RAM model +// + +// +// Generic RAM's registers and wires +// +reg [dw-1:0] mem [(1<
release-1.0/rtl/verilog/minsoc_onchip_ram.v Property changes : Added: svn:executable ## -0,0 +1 ## +* \ No newline at end of property Index: release-1.0/rtl/verilog/minsoc_onchip_ram_top.v =================================================================== --- release-1.0/rtl/verilog/minsoc_onchip_ram_top.v (nonexistent) +++ release-1.0/rtl/verilog/minsoc_onchip_ram_top.v (revision 151) @@ -0,0 +1,259 @@ +////////////////////////////////////////////////////////////////////// +//// //// +//// Generic Wishbone controller for //// +//// Single-Port Synchronous RAM //// +//// //// +//// This file is part of memory library available from //// +//// http://www.opencores.org/cvsweb.shtml/minsoc/ //// +//// //// +//// Description //// +//// This Wishbone controller connects to the wrapper of //// +//// the single-port synchronous memory interface. //// +//// Besides universal memory due to onchip_ram it provides a //// +//// generic way to set the depth of the memory. //// +//// //// +//// To Do: //// +//// //// +//// Author(s): //// +//// - Raul Fajardo, rfajardo@gmail.com //// +//// //// +////////////////////////////////////////////////////////////////////// +//// //// +//// Copyright (C) 2000 Authors and OPENCORES.ORG //// +//// //// +//// This source file may be used and distributed without //// +//// restriction provided that this copyright statement is not //// +//// removed from the file and that any derivative work contains //// +//// the original copyright notice and the associated disclaimer. //// +//// //// +//// This source file is free software; you can redistribute it //// +//// and/or modify it under the terms of the GNU Lesser General //// +//// Public License as published by the Free Software Foundation; //// +//// either version 2.1 of the License, or (at your option) any //// +//// later version. //// +//// //// +//// This source is distributed in the hope that it will be //// +//// useful, but WITHOUT ANY WARRANTY; without even the implied //// +//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR //// +//// PURPOSE. See the GNU Lesser General Public License for more //// +//// details. //// +//// //// +//// You should have received a copy of the GNU Lesser General //// +//// Public License along with this source; if not, download it //// +//// from http://www.gnu.org/licenses/lgpl.html //// +//// //// +////////////////////////////////////////////////////////////////////// +// +// Revision History +// +// Revision 1.1 2009/10/02 16:49 fajardo +// Not using the oe signal (output enable) from +// memories, instead multiplexing the outputs +// between the different instantiated blocks +// +// +// Revision 1.0 2009/08/18 15:15:00 fajardo +// Created interface and tested +// + + +module minsoc_onchip_ram_top ( + wb_clk_i, wb_rst_i, + + wb_dat_i, wb_dat_o, wb_adr_i, wb_sel_i, wb_we_i, wb_cyc_i, + wb_stb_i, wb_ack_o, wb_err_o +); + +// +// Parameters +// +parameter adr_width = 13; //Memory address width, is composed by blocks of aw_int, is not allowed to be less than 12 +localparam aw_int = 11; //11 = 2048 +localparam blocks = (1<<(adr_width-aw_int)); //generated memory contains "blocks" memory blocks of 2048x32 2048 depth x32 bit data + +// +// I/O Ports +// +input wb_clk_i; +input wb_rst_i; + +// +// WB slave i/f +// +input [31:0] wb_dat_i; +output [31:0] wb_dat_o; +input [31:0] wb_adr_i; +input [3:0] wb_sel_i; +input wb_we_i; +input wb_cyc_i; +input wb_stb_i; +output wb_ack_o; +output wb_err_o; + +// +// Internal regs and wires +// +wire we; +wire [3:0] be_i; +wire [31:0] wb_dat_o; +reg ack_we; +reg ack_re; +// +// Aliases and simple assignments +// +assign wb_ack_o = ack_re | ack_we; +assign wb_err_o = wb_cyc_i & wb_stb_i & (|wb_adr_i[23:adr_width+2]); // If Access to > (8-bit leading prefix ignored) +assign we = wb_cyc_i & wb_stb_i & wb_we_i & (|wb_sel_i[3:0]); +assign be_i = (wb_cyc_i & wb_stb_i) * wb_sel_i; + +// +// Write acknowledge +// +always @ (negedge wb_clk_i or posedge wb_rst_i) +begin +if (wb_rst_i) + ack_we <= 1'b0; + else + if (wb_cyc_i & wb_stb_i & wb_we_i & ~ack_we) + ack_we <= #1 1'b1; + else + ack_we <= #1 1'b0; +end + +// +// read acknowledge +// +always @ (posedge wb_clk_i or posedge wb_rst_i) +begin + if (wb_rst_i) + ack_re <= 1'b0; + else + if (wb_cyc_i & wb_stb_i & ~wb_err_o & ~wb_we_i & ~ack_re) + ack_re <= #1 1'b1; + else + ack_re <= #1 1'b0; +end + +//Generic (multiple inputs x 1 output) MUX +localparam mux_in_nr = blocks; +localparam slices = adr_width-aw_int; +localparam mux_out_nr = blocks-1; + +wire [31:0] int_dat_o[0:mux_in_nr-1]; +wire [31:0] mux_out[0:mux_out_nr-1]; + +generate +genvar j, k; + for (j=0; j>(j+1)); k=k+1) begin : MUX + if (j==0) begin + mux2 # + ( + .dw(32) + ) + mux_int( + .sel( wb_adr_i[aw_int+2+j] ), + .in1( int_dat_o[k*2] ), + .in2( int_dat_o[k*2+1] ), + .out( mux_out[k] ) + ); + end + else begin + mux2 # + ( + .dw(32) + ) + mux_int( + .sel( wb_adr_i[aw_int+2+j] ), + .in1( mux_out[(mux_in_nr-(mux_in_nr>>(j-1)))+k*2] ), + .in2( mux_out[(mux_in_nr-(mux_in_nr>>(j-1)))+k*2+1] ), + .out( mux_out[(mux_in_nr-(mux_in_nr>>j))+k] ) + ); + end + end + end +endgenerate + +//last output = total output +assign wb_dat_o = mux_out[mux_out_nr-1]; + +//(mux_in_nr-(mux_in_nr>>j)): +//-Given sum of 2^i | i = x -> y series can be resumed to 2^(y+1)-2^x +//so, with this expression I'm evaluating how many times the internal loop has been run + +wire [blocks-1:0] bank; + +generate +genvar i; + for (i=0; i < blocks; i=i+1) begin : MEM + + assign bank[i] = wb_adr_i[adr_width+1:aw_int+2] == i; + + //BANK0 + minsoc_onchip_ram block_ram_0 ( + .clk(wb_clk_i), + .rst(wb_rst_i), + .addr(wb_adr_i[aw_int+1:2]), + .di(wb_dat_i[7:0]), + .doq(int_dat_o[i][7:0]), + .we(we & bank[i]), + .oe(1'b1), + .ce(be_i[0]) + ); + + + minsoc_onchip_ram block_ram_1 ( + .clk(wb_clk_i), + .rst(wb_rst_i), + .addr(wb_adr_i[aw_int+1:2]), + .di(wb_dat_i[15:8]), + .doq(int_dat_o[i][15:8]), + .we(we & bank[i]), + .oe(1'b1), + .ce(be_i[1]) + ); + + minsoc_onchip_ram block_ram_2 ( + .clk(wb_clk_i), + .rst(wb_rst_i), + .addr(wb_adr_i[aw_int+1:2]), + .di(wb_dat_i[23:16]), + .doq(int_dat_o[i][23:16]), + .we(we & bank[i]), + .oe(1'b1), + .ce(be_i[2]) + ); + + minsoc_onchip_ram block_ram_3 ( + .clk(wb_clk_i), + .rst(wb_rst_i), + .addr(wb_adr_i[aw_int+1:2]), + .di(wb_dat_i[31:24]), + .doq(int_dat_o[i][31:24]), + .we(we & bank[i]), + .oe(1'b1), + .ce(be_i[3]) + ); + + end +endgenerate + +endmodule + +module mux2(sel,in1,in2,out); + +parameter dw = 32; + +input sel; +input [dw-1:0] in1, in2; +output reg [dw-1:0] out; + +always @ (sel or in1 or in2) +begin + case (sel) + 1'b0: out = in1; + 1'b1: out = in2; + endcase +end + +endmodule
release-1.0/rtl/verilog/minsoc_onchip_ram_top.v Property changes : Added: svn:executable ## -0,0 +1 ## +* \ No newline at end of property Index: release-1.0/rtl/verilog/minsoc_xilinx_internal_jtag.v =================================================================== --- release-1.0/rtl/verilog/minsoc_xilinx_internal_jtag.v (nonexistent) +++ release-1.0/rtl/verilog/minsoc_xilinx_internal_jtag.v (revision 151) @@ -0,0 +1,441 @@ +/////////////////////////////////////////////////////////////////////// +//// //// +//// xilinx_internal_jtag.v //// +//// //// +//// //// +//// //// +//// Author(s): //// +//// Nathan Yawn (nathan.yawn@opencores.org) //// +//// //// +//// //// +//// //// +////////////////////////////////////////////////////////////////////// +//// //// +//// Copyright (C) 2008 Authors //// +//// //// +//// This source file may be used and distributed without //// +//// restriction provided that this copyright statement is not //// +//// removed from the file and that any derivative work contains //// +//// the original copyright notice and the associated disclaimer. //// +//// //// +//// This source file is free software; you can redistribute it //// +//// and/or modify it under the terms of the GNU Lesser General //// +//// Public License as published by the Free Software Foundation; //// +//// either version 2.1 of the License, or (at your option) any //// +//// later version. //// +//// //// +//// This source is distributed in the hope that it will be //// +//// useful, but WITHOUT ANY WARRANTY; without even the implied //// +//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR //// +//// PURPOSE. See the GNU Lesser General Public License for more //// +//// details. //// +//// //// +//// You should have received a copy of the GNU Lesser General //// +//// Public License along with this source; if not, download it //// +//// from http://www.opencores.org/lgpl.shtml //// +//// //// +////////////////////////////////////////////////////////////////////// +// // +// This file is a wrapper for the various Xilinx internal BSCAN // +// TAP devices. It is designed to take the place of a separate TAP // +// controller in Xilinx systems, to allow a user to access a CPU // +// debug module (such as that of the OR1200) through the FPGA's // +// dedicated JTAG / configuration port. // +// // +////////////////////////////////////////////////////////////////////// +// +// CVS Revision History +// +// $Log: xilinx_internal_jtag.v,v $ +// Revision 1.3 2009/06/16 02:54:23 Nathan +// Changed some signal names for better consistency between different hardware modules. +// +// Revision 1.2 2009/05/17 20:54:16 Nathan +// Changed email address to opencores.org +// +// Revision 1.1 2008/07/18 20:07:32 Nathan +// Changed the directory structure to match existing projects. +// +// Revision 1.4 2008/07/11 08:26:10 Nathan +// Ran through dos2unix +// +// Revision 1.3 2008/07/11 08:25:52 Nathan +// Added logic to provide CAPTURE_DR signal when necessary, and to provide a TCK while UPDATE_DR is asserted. Note that there is no TCK event between SHIFT_DR and UPDATE_DR, and no TCK event between UPDATE_DR and the next CAPTURE_DR; the Xilinx BSCAN devices do not provide it. Tested successfully with the adv_dbg_if on Virtex-4. +// +// Revision 1.2 2008/06/09 19:34:14 Nathan +// Syntax and functional fixes made after compiling each type of BSCAN module using Xilinx tools. +// +// Revision 1.1 2008/05/22 19:54:07 Nathan +// Initial version +// + + +`include "minsoc_defines.v" + +// Note that the SPARTAN BSCAN controllers have more than one channel. +// This implementation always uses channel 1, this is not configurable. +// If you want to use another channel, then it is probably because you +// want to attach multiple devices to the BSCAN device, which means +// you'll be making changes to this file anyway. +// Virtex BSCAN devices are instantiated separately for each channel. +// To select something other than the default (1), change the parameter +// "virtex_jtag_chain". + + +module minsoc_xilinx_internal_jtag ( + tck_o, + debug_tdo_i, + tdi_o, + test_logic_reset_o, + run_test_idle_o, + shift_dr_o, + capture_dr_o, + pause_dr_o, + update_dr_o, + debug_select_o +); + +// May be 1, 2, 3, or 4 +// Only used for Virtex 4/5 devices +parameter virtex_jtag_chain = 1; + +input debug_tdo_i; +output tck_o; +output tdi_o; +output test_logic_reset_o; +output run_test_idle_o; +output shift_dr_o; +output capture_dr_o; +output pause_dr_o; +output update_dr_o; +output debug_select_o; + +wire debug_tdo_i; +wire tck_o; +wire drck; +wire tdi_o; +wire test_logic_reset_o; +wire run_test_idle_o; +wire shift_dr_o; +wire pause_dr_o; +wire update_dr_o; +wire debug_select_o; + +`ifdef SPARTAN3E + `define SPARTAN3 +`endif + +`ifdef SPARTAN2 + +// Note that this version is missing three outputs. +// It also does not have a real TCK...DRCK1 is only active when USER1 is selected +// AND the TAP is in SHIFT_DR or CAPTURE_DR states...except there's no +// capture_dr output. + +reg capture_dr_o; +wire update_bscan; +reg update_out; + +BSCAN_SPARTAN2 BSCAN_SPARTAN2_inst ( +.DRCK1(drck), // Data register output for USER1 functions +.DRCK2(), // Data register output for USER2 functions +.RESET(test_logic_reset_o), // Reset output from TAP controller +.SEL1(debug_select_o), // USER1 active output +.SEL2(), // USER2 active output +.SHIFT(shift_dr_o), // SHIFT output from TAP controller +.TDI(tdi_o), // TDI output from TAP controller +.UPDATE(update_bscan), // UPDATE output from TAP controller +.TDO1(debug_tdo_i), // Data input for USER1 function +.TDO2( 1'b0 ) // Data input for USER2 function +); + +assign pause_dr_o = 1'b0; +assign run_test_idle_o = 1'b0; + +// We get one TCK during capture_dr state (low,high,SHIFT goes high on next DRCK high) +// On that negative edge, set capture_dr, and it will get registered on the rising +// edge. +always @ (negedge tck_o) +begin + if(debug_select_o && !shift_dr_o) + capture_dr_o <= 1'b1; + else + capture_dr_o <= 1'b0; +end + +// The & !update_bscan tern will provide a clock edge so update_dr_o can be registered +// The &debug_select term will drop TCK when the module is un-selected (does not happen in the BSCAN block). +// This allows a user to kludge clock ticks in the IDLE state, which is needed by the advanced debug module. +assign tck_o = (drck & debug_select_o & !update_bscan); + +// This will hold the update_dr output so it can be registered on the rising edge +// of the clock created above. +always @(posedge update_bscan or posedge capture_dr_o or negedge debug_select_o) +begin + if(update_bscan) update_out <= 1'b1; + else if(capture_dr_o) update_out <= 1'b0; + else if(!debug_select_o) update_out <= 1'b0; +end + +assign update_dr_o = update_out; + +`else +`ifdef SPARTAN3 +// Note that this version is missing two outputs. +// It also does not have a real TCK...DRCK1 is only active when USER1 is selected. + +wire capture_dr_o; +wire update_bscan; +reg update_out; + +BSCAN_SPARTAN3 BSCAN_SPARTAN3_inst ( +.CAPTURE(capture_dr_o), // CAPTURE output from TAP controller +.DRCK1(drck), // Data register output for USER1 functions +.DRCK2(), // Data register output for USER2 functions +.RESET(test_logic_reset_o), // Reset output from TAP controller +.SEL1(debug_select_o), // USER1 active output +.SEL2(), // USER2 active output +.SHIFT(shift_dr_o), // SHIFT output from TAP controller +.TDI(tdi_o), // TDI output from TAP controller +.UPDATE(update_bscan), // UPDATE output from TAP controller +.TDO1(debug_tdo_i), // Data input for USER1 function +.TDO2(1'b0) // Data input for USER2 function +); + +assign pause_dr_o = 1'b0; +assign run_test_idle_o = 1'b0; + +// The & !update_bscan tern will provide a clock edge so update_dr_o can be registered +// The &debug_select term will drop TCK when the module is un-selected (does not happen in the BSCAN block). +// This allows a user to kludge clock ticks in the IDLE state, which is needed by the advanced debug module. +assign tck_o = (drck & debug_select_o & !update_bscan); + +// This will hold the update_dr output so it can be registered on the rising edge +// of the clock created above. +always @(posedge update_bscan or posedge capture_dr_o or negedge debug_select_o) +begin + if(update_bscan) update_out <= 1'b1; + else if(capture_dr_o) update_out <= 1'b0; + else if(!debug_select_o) update_out <= 1'b0; +end + +assign update_dr_o = update_out; + +`ifdef SPARTAN3E + `undef SPARTAN3 +`endif + +`else +`ifdef SPARTAN3A +// Note that this version is missing two outputs. +// At least it has a real TCK. + +wire capture_dr_o; + +BSCAN_SPARTAN3A BSCAN_SPARTAN3A_inst ( +.CAPTURE(capture_dr_o), // CAPTURE output from TAP controller +.DRCK1(), // Data register output for USER1 functions +.DRCK2(), // Data register output for USER2 functions +.RESET(test_logic_reset_o), // Reset output from TAP controller +.SEL1(debug_select_o), // USER1 active output +.SEL2(), // USER2 active output +.SHIFT(shift_dr_o), // SHIFT output from TAP controller +.TCK(tck_o), // TCK output from TAP controller +.TDI(tdi_o), // TDI output from TAP controller +.TMS(), // TMS output from TAP controller +.UPDATE(update_dr_o), // UPDATE output from TAP controller +.TDO1(debug_tdo_i), // Data input for USER1 function +.TDO2( 1'b0) // Data input for USER2 function +); + +assign pause_dr_o = 1'b0; +assign run_test_idle_o = 1'b0; + +`else +`ifdef VIRTEX + +// Note that this version is missing three outputs. +// It also does not have a real TCK...DRCK1 is only active when USER1 is selected. + +reg capture_dr_o; +wire update_bscan; +reg update_out; + +BSCAN_VIRTEX BSCAN_VIRTEX_inst ( +.DRCK1(drck), // Data register output for USER1 functions +.DRCK2(), // Data register output for USER2 functions +.RESET(test_logic_reset_o), // Reset output from TAP controller +.SEL1(debug_select_o), // USER1 active output +.SEL2(), // USER2 active output +.SHIFT(shift_dr_o), // SHIFT output from TAP controller +.TDI(tdi_o), // TDI output from TAP controller +.UPDATE(update_bscan), // UPDATE output from TAP controller +.TDO1(debug_tdo_i), // Data input for USER1 function +.TDO2( 1'b0) // Data input for USER2 function +); + +assign pause_dr_o = 1'b0; +assign run_test_idle_o = 1'b0; + +// We get one TCK during capture_dr state (low,high,SHIFT goes high on next DRCK low) +// On that negative edge, set capture_dr, and it will get registered on the rising +// edge, then de-asserted on the same edge that SHIFT goes high. +always @ (negedge tck_o) +begin + if(debug_select_o && !shift_dr_o) + capture_dr_o <= 1'b1; + else + capture_dr_o <= 1'b0; +end + +// The & !update_bscan tern will provide a clock edge so update_dr_o can be registered +// The &debug_select term will drop TCK when the module is un-selected (does not happen in the BSCAN block). +// This allows a user to kludge clock ticks in the IDLE state, which is needed by the advanced debug module. +assign tck_o = (drck & debug_select_o & !update_bscan); + +// This will hold the update_dr output so it can be registered on the rising edge +// of the clock created above. +always @(posedge update_bscan or posedge capture_dr_o or negedge debug_select_o) +begin + if(update_bscan) update_out <= 1'b1; + else if(capture_dr_o) update_out <= 1'b0; + else if(!debug_select_o) update_out <= 1'b0; +end + +assign update_dr_o = update_out; + +`else +`ifdef VIRTEX2 + +// Note that this version is missing two outputs. +// It also does not have a real TCK...DRCK1 is only active when USER1 is selected. + +wire capture_dr_o; +wire update_bscan; +reg update_out; + +BSCAN_VIRTEX2 BSCAN_VIRTEX2_inst ( +.CAPTURE(capture_dr_o), // CAPTURE output from TAP controller +.DRCK1(drck), // Data register output for USER1 functions +.DRCK2(), // Data register output for USER2 functions +.RESET(test_logic_reset_o), // Reset output from TAP controller +.SEL1(debug_select_o), // USER1 active output +.SEL2(), // USER2 active output +.SHIFT(shift_dr_o), // SHIFT output from TAP controller +.TDI(tdi_o), // TDI output from TAP controller +.UPDATE(update_bscan), // UPDATE output from TAP controller +.TDO1(debug_tdo_i), // Data input for USER1 function +.TDO2( 1'b0 ) // Data input for USER2 function +); + +assign pause_dr_o = 1'b0; +assign run_test_idle_o = 1'b0; + +// The & !update_bscan tern will provide a clock edge so update_dr_o can be registered +// The &debug_select term will drop TCK when the module is un-selected (does not happen in the BSCAN block). +// This allows a user to kludge clock ticks in the IDLE state, which is needed by the advanced debug module. +assign tck_o = (drck & debug_select_o & !update_bscan); + +// This will hold the update_dr output so it can be registered on the rising edge +// of the clock created above. +always @(posedge update_bscan or posedge capture_dr_o or negedge debug_select_o) +begin + if(update_bscan) update_out <= 1'b1; + else if(capture_dr_o) update_out <= 1'b0; + else if(!debug_select_o) update_out <= 1'b0; +end + +assign update_dr_o = update_out; + +`else +`ifdef VIRTEX4 +// Note that this version is missing two outputs. +// It also does not have a real TCK...DRCK is only active when USERn is selected. + +wire capture_dr_o; +wire update_bscan; +reg update_out; + +BSCAN_VIRTEX4 #( +.JTAG_CHAIN(virtex_jtag_chain) +) BSCAN_VIRTEX4_inst ( +.CAPTURE(capture_dr_o), // CAPTURE output from TAP controller +.DRCK(drck), // Data register output for USER function +.RESET(test_logic_reset_o), // Reset output from TAP controller +.SEL(debug_select_o), // USER active output +.SHIFT(shift_dr_o), // SHIFT output from TAP controller +.TDI(tdi_o), // TDI output from TAP controller +.UPDATE(update_bscan), // UPDATE output from TAP controller +.TDO( debug_tdo_i ) // Data input for USER function +); + +assign pause_dr_o = 1'b0; +assign run_test_idle_o = 1'b0; + +// The & !update_bscan tern will provide a clock edge so update_dr_o can be registered +// The &debug_select term will drop TCK when the module is un-selected (does not happen in the BSCAN block). +// This allows a user to kludge clock ticks in the IDLE state, which is needed by the advanced debug module. +assign tck_o = (drck & debug_select_o & !update_bscan); + +// This will hold the update_dr output so it can be registered on the rising edge +// of the clock created above. +always @(posedge update_bscan or posedge capture_dr_o or negedge debug_select_o) +begin + if(update_bscan) update_out <= 1'b1; + else if(capture_dr_o) update_out <= 1'b0; + else if(!debug_select_o) update_out <= 1'b0; +end + +assign update_dr_o = update_out; + +`else +`ifdef VIRTEX5 +// Note that this version is missing two outputs. +// It also does not have a real TCK...DRCK is only active when USERn is selected. + +wire capture_dr_o; +wire update_bscan; +reg update_out; + +BSCAN_VIRTEX5 #( +.JTAG_CHAIN(virtex_jtag_chain) +) BSCAN_VIRTEX5_inst ( +.CAPTURE(capture_dr_o), // CAPTURE output from TAP controller +.DRCK(drck), // Data register output for USER function +.RESET(test_logic_reset), // Reset output from TAP controller +.SEL(debug_select_o), // USER active output +.SHIFT(shift_dr_o), // SHIFT output from TAP controller +.TDI(tdi_o), // TDI output from TAP controller +.UPDATE(update_bscan), // UPDATE output from TAP controller +.TDO(debug_tdo_i) // Data input for USER function +); + +assign pause_dr_o = 1'b0; +assign run_test_idle_o = 1'b0; + +// The & !update_bscan tern will provide a clock edge so update_dr_o can be registered +// The &debug_select term will drop TCK when the module is un-selected (does not happen in the BSCAN block). +// This allows a user to kludge clock ticks in the IDLE state, which is needed by the advanced debug module. +assign tck_o = (drck & debug_select_o & !update_bscan); + +// This will hold the update_dr output so it can be registered on the rising edge +// of the clock created above. +always @(posedge update_bscan or posedge capture_dr_o or negedge debug_select_o) +begin + if(update_bscan) update_out <= 1'b1; + else if(capture_dr_o) update_out <= 1'b0; + else if(!debug_select_o) update_out <= 1'b0; +end + +assign update_dr_o = update_out; + + +`endif +`endif +`endif +`endif +`endif +`endif +`endif + +endmodule
release-1.0/rtl/verilog/minsoc_xilinx_internal_jtag.v Property changes : Added: svn:executable ## -0,0 +1 ## +* \ No newline at end of property Index: release-1.0/rtl/verilog =================================================================== --- release-1.0/rtl/verilog (nonexistent) +++ release-1.0/rtl/verilog (revision 151)
release-1.0/rtl/verilog Property changes : Added: svn:externals ## -0,0 +1,5 ## +adv_debug_sys -r58 http://opencores.org/ocsvn/adv_debug_sys/adv_debug_sys/trunk +ethmac -r366 http://opencores.org/ocsvn/ethmac/ethmac/trunk +or1200 http://opencores.org/ocsvn/openrisc/openrisc/tags/or1200/rel1 +uart16550 -r108 http://opencores.org/ocsvn/uart16550/uart16550/trunk + Index: release-1.0/doc/README.txt =================================================================== --- release-1.0/doc/README.txt (nonexistent) +++ release-1.0/doc/README.txt (revision 151) @@ -0,0 +1,22 @@ +Welcome to MinSoC. + +In order to put the system up and running, you should first visit MinSoC's Wiki +that can be found at (http://www.minsoc.com). There, you will find guidance +to retrieve and install the required tools, simulate and synthesize the design, +and to run and debug the first firmware on your FPGA. + +IMPORTANT: By any arisen problems, doubts or special requirements, take a look +into the FAQ pages (also in this very Wiki). It includes possible adaptations +you can easily make to the system, solutions for the most reported problems +using MinSoC and the Advanced Debug System, and even some tweak possibilities. +If you have a problem which is not described there or you cannot make it work, +please send us an email to . + +FINALLY: My system is up and running, what do I do next? The real system +documentation is the minsoc.pdf document. It gives a thorough insight into +MinSoC, its goals, design and ideas. It helps you to better understand the +system and can give you a good idea of what to do next, after your system is up +and running. + +Enjoy your time, +Raul Fajardo Index: release-1.0/doc/src/minsoc.odt =================================================================== Cannot display: file marked as a binary type. svn:mime-type = application/octet-stream Index: release-1.0/doc/src/minsoc.odt =================================================================== --- release-1.0/doc/src/minsoc.odt (nonexistent) +++ release-1.0/doc/src/minsoc.odt (revision 151)
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release-1.0/doc/minsoc.pdf Property changes : Added: svn:executable ## -0,0 +1 ## +* \ No newline at end of property Added: svn:mime-type ## -0,0 +1 ## +application/octet-stream \ No newline at end of property Index: release-1.0/doc/lgpl-3.0.txt =================================================================== --- release-1.0/doc/lgpl-3.0.txt (nonexistent) +++ release-1.0/doc/lgpl-3.0.txt (revision 151) @@ -0,0 +1,165 @@ + GNU LESSER GENERAL PUBLIC LICENSE + Version 3, 29 June 2007 + + Copyright (C) 2007 Free Software Foundation, Inc. + Everyone is permitted to copy and distribute verbatim copies + of this license document, but changing it is not allowed. + + + This version of the GNU Lesser General Public License incorporates +the terms and conditions of version 3 of the GNU General Public +License, supplemented by the additional permissions listed below. + + 0. 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