URL
https://opencores.org/ocsvn/minsoc/minsoc/trunk
Subversion Repositories minsoc
Compare Revisions
- This comparison shows the changes necessary to convert path
/minsoc/trunk/backend/altera_3c25_board
- from Rev 105 to Rev 141
- ↔ Reverse comparison
Rev 105 → Rev 141
/configure
17,7 → 17,7
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PROJECT_FILE=minsoc_top.qsf |
|
SYN_FILES=(adbg_top.prj jtag_top.prj or1200_top.prj uart_top.prj minsoc_top.prj altera_virtual_jtag.prj) |
SYN_FILES=(adbg_top.vprj jtag_top.vprj or1200_top.vprj uart_top.vprj minsoc_top.vprj altera_virtual_jtag.vhdprj) |
MAKEFILE=Makefile |
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FIND_PART='DEVICE_PART' |
52,15 → 52,31
echo "" |
echo "" |
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echo "Copying board specific SoC files from $BOARD_DIR to $BACKEND_DIR directory." |
echo "__________________________________________________________________________" |
echo "" |
for file in "${BOARD_FILES[@]}" |
do |
if [ $file != NONE ] |
then |
echo "Copying $file, to backend directory..." |
cp $BOARD_DIR/$file $BACKEND_DIR |
fi |
done |
|
echo "Generating project files for simulation and synthesis..." |
echo "__________________________________________________________________________" |
echo "" |
make -C $MINSOC_DIR/prj |
echo "Generation complete." |
echo "__________________________________________________________________________" |
echo "" |
echo "" |
|
if [ $CONSTRAINT_FILE == 'NONE' ] |
then |
echo "Skipping synthesis preparation. Standard implementation can only be simulated." |
echo "" |
echo "" |
else |
echo "Device part and family for files under $SYNSRC_DIR will patched and stored " |
echo "temporarily." |
88,21 → 104,9
echo "Copying Makefile from $MAKEFILE_DIR to synthesis directory, $SYN_DIR..." |
cp $MAKEFILE_DIR/$MAKEFILE $SYN_DIR/$MAKEFILE |
cp $MAKEFILE_DIR/setup.bat $SYN_DIR/setup.bat |
echo "For synthesis help go to $SYN_DIR and type \"make\"." |
echo "" |
|
echo "Copying board specific SoC files from $BOARD_DIR to $BACKEND_DIR directory." |
echo "__________________________________________________________________________" |
echo "" |
for file in "${BOARD_FILES[@]}" |
do |
if [ $file != NONE ] |
then |
echo "Copying $file, to backend directory..." |
cp $BOARD_DIR/$file $BACKEND_DIR |
fi |
done |
echo "" |
echo "Configuration done." |
echo "For synthesis help go to $SYN_DIR and type \"make\"." |
fi |
|
echo "Configuration done." |
/minsoc_bench_defines.v
4,7 → 4,7
`define NO_CLOCK_DIVISION //if commented out, generic clock division is implemented (odd divisors are rounded down) |
//~set RTL for simulation, override FPGA specific definitions (JTAG TAP, MEMORY and CLOCK DIVIDER) |
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`define FREQ_NUM_FOR_NS 1000000000 |
`define FREQ_NUM_FOR_NS 100000000 |
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`define FREQ 25000000 |
`define CLK_PERIOD (`FREQ_NUM_FOR_NS/`FREQ) |
24,3 → 24,6
//only use with the memory model. |
//If you use the original memory (`define MEMORY_MODEL |
//commented out), comment this too. |
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`define TEST_UART |
//`define TEST_ETHERNET |