URL
https://opencores.org/ocsvn/minsoc/minsoc/trunk
Subversion Repositories minsoc
Compare Revisions
- This comparison shows the changes necessary to convert path
/minsoc/trunk/backend/std
- from Rev 65 to Rev 69
- ↔ Reverse comparison
Rev 65 → Rev 69
/configure
19,7 → 19,7
FIND_CONSTRAINT='CONSTRAINT_FILE' |
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BOARD_DIR=$BACKEND_DIR/$BOARD |
BOARD_FILES=(board.h orp.ld minsoc_defines.v $CONSTRAINT_FILE) |
BOARD_FILES=(board.h orp.ld minsoc_defines.v minsoc_bench_defines.v gcc-opt.mk $CONSTRAINT_FILE) |
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in_minsoc=`pwd | grep minsoc/backend/${BOARD}$` |
if [ -z $in_minsoc ] |
/gcc-opt.mk
0,0 → 1,7
GCC_OPT=-mhard-mul -mhard-div -g -nostdlib |
/minsoc_bench_defines.v
0,0 → 1,29
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`timescale 1ns/100ps |
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//set RTL for simulation, override FPGA specific definitions (JTAG TAP, MEMORY and CLOCK DIVIDER) |
`define GENERIC_FPGA |
`define MEMORY_MODEL //simulation uses a memory model enabling INITIALIZE_MEMORY_MODEL. If you comment this, START_UP might be interesting. |
`define NO_CLOCK_DIVISION //if commented out, generic clock division is implemented (odd divisors are rounded down) |
//~set RTL for simulation, override FPGA specific definitions (JTAG TAP, MEMORY and CLOCK DIVIDER) |
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`define FREQ_NUM_FOR_NS 1000000000 |
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`define FREQ 25000000 |
`define CLK_PERIOD (`FREQ_NUM_FOR_NS/`FREQ) |
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`define ETH_PHY_FREQ 25000000 |
`define ETH_PHY_PERIOD (`FREQ_NUM_FOR_NS/`ETH_PHY_FREQ) //40ns |
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`define UART_BAUDRATE 115200 |
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`define VPI_DEBUG |
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//`define VCD_OUTPUT |
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//`define START_UP //pass firmware over spi to or1k_startup |
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`define INITIALIZE_MEMORY_MODEL //instantaneously initialize memory model with firmware |
//only use with the memory model. |
//If you use the original memory (`define MEMORY_MODEL |
//commented out), comment this too. |
minsoc_bench_defines.v
Property changes :
Added: svn:executable
## -0,0 +1 ##
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