URL
https://opencores.org/ocsvn/minsoc/minsoc/trunk
Subversion Repositories minsoc
Compare Revisions
- This comparison shows the changes necessary to convert path
/minsoc/trunk/backend
- from Rev 63 to Rev 64
- ↔ Reverse comparison
Rev 63 → Rev 64
/ml509.ucf
File deleted
/spartan3e_starter_kit.ucf
File deleted
spartan3e_starter_kit.ucf
Property changes :
Deleted: svn:executable
## -1 +0,0 ##
-*
\ No newline at end of property
Index: spartan3a_dsp_kit.ucf
===================================================================
--- spartan3a_dsp_kit.ucf (revision 63)
+++ spartan3a_dsp_kit.ucf (nonexistent)
@@ -1,72 +0,0 @@
-###########################
-##
-## Global signals
-##
-net "clk" loc = "f13"; #125MHz clock
-net "reset" loc = "j17"; #SW5
-###########################
-
-###########################
-##
-## JTAG
-##
-#net "jtag_tms" loc = "aa23"; #SAM D0
-#net "jtag_tdi" loc = "u20"; #SAM D2
-#net "jtag_tdo" loc = "aa25"; #SAM D4
-#net "jtag_tck" loc = "u18" | CLOCK_DEDICATED_ROUTE = FALSE; #SAM D6
-#net "jtag_gnd" loc = "y23"; #SAM D8
-#net "jtag_vref" loc = "t20"; #SAM D10
-###########################
-
-#############################
-##
-## SPI Flash External Memory
-##
-#NET "spi_flash_mosi" LOC = "ab15";
-#NET "spi_flash_miso" LOC = "af24";
-#NET "spi_flash_sclk" LOC = "ae24";
-#NET "spi_flash_ss(1)" LOC = "ac25";
-#NET "spi_flash_ss(0)" LOC = "aa7";
-###########################
-
-###########################
-##
-## UART
-##
-net "uart_stx" loc = "p22";
-net "uart_srx" loc = "n21";
-###########################
-
-###########################
-##
-## ETH
-##
-#NET "eth_txd(3)" LOC = "b1";
-#NET "eth_txd(2)" LOC = "b2";
-#NET "eth_txd(1)" LOC = "j9";
-#NET "eth_txd(0)" LOC = "j8";
-#
-#NET "eth_tx_en" LOC = "d3";
-#NET "eth_tx_clk" LOC = "p2";
-#NET "eth_tx_er" LOC = "e4";
-#
-#NET "eth_rxd(3)" LOC = "d2";
-#NET "eth_rxd(2)" LOC = "g5";
-#NET "eth_rxd(1)" LOC = "g2";
-#NET "eth_rxd(0)" LOC = "c2";
-#
-#NET "eth_rx_er" LOC = "j3";
-#NET "eth_rx_dv" LOC = "d1";
-#
-#NET "eth_rx_clk" LOC = "p1";
-#
-#NET "eth_mdio" LOC = "f5" | PULLUP;
-#NET "eth_crs" LOC = "g1";
-#NET "eth_col" LOC = "y3";
-#NET "eth_mdc" LOC = "f4";
-#
-#NET "eth_trste" LOC = "g4";
-#
-#NET "eth_fds_mdint" LOC = "j1";
-###########################
-
spartan3a_dsp_kit.ucf
Property changes :
Deleted: svn:executable
## -1 +0,0 ##
-*
\ No newline at end of property
Index: ml509/ml509.ucf
===================================================================
--- ml509/ml509.ucf (nonexistent)
+++ ml509/ml509.ucf (revision 64)
@@ -0,0 +1,45 @@
+NET clk LOC="AH15" | PERIOD=10ns | IOSTANDARD=LVCMOS33; # Bank 4, Vcco=3.3V, No DCI
+NET reset LOC="E9" | PULLUP | IOSTANDARD=LVDCI_33; # Bank 20, Vcco=3.3V, DCI using 49.9 ohm resistors
+NET uart_srx LOC="AG15" | IOSTANDARD=LVCMOS33; # Bank 4, Vcco=3.3V, No DCI
+NET uart_stx LOC="AG20" | IOSTANDARD=LVCMOS33; # Bank 4, Vcco=3.3V, No DCI
+
+## #------------------------------------------------------------------------------
+## # IO Pad Location Constraints / Properties for Ethernet
+## #------------------------------------------------------------------------------
+
+#NET eth_col LOC = B32 | IOSTANDARD = LVCMOS25 | IOBDELAY=NONE;
+#NET eth_crs LOC = E34 | IOSTANDARD = LVCMOS25 | IOBDELAY=NONE;
+#NET eth_rx_dv LOC = E32 | IOSTANDARD = LVCMOS25 | IOBDELAY=NONE;
+#NET eth_rx_clk LOC = H17 | IOSTANDARD = LVCMOS25;
+#NET eth_rxd<3> LOC = C32 | IOSTANDARD = LVCMOS25 | IOBDELAY=NONE;
+#NET eth_rxd<2> LOC = C33 | IOSTANDARD = LVCMOS25 | IOBDELAY=NONE;
+#NET eth_rxd<1> LOC = B33 | IOSTANDARD = LVCMOS25 | IOBDELAY=NONE;
+#NET eth_rxd<0> LOC = A33 | IOSTANDARD = LVCMOS25 | IOBDELAY=NONE;
+
+#NET eth_rx_er LOC = E33 | IOSTANDARD = LVCMOS25 | IOBDELAY=NONE;
+#NET eth_tx_clk LOC = K17 | IOSTANDARD = LVCMOS25;
+#NET eth_trste LOC = J14 | IOSTANDARD = LVCMOS25 | PULLUP | TIG; # PHY_RESET pin on phy
+#NET eth_txd<3> LOC = AH10 | IOSTANDARD = LVDCI_33;
+#NET eth_txd<2> LOC = AH9 | IOSTANDARD = LVDCI_33;
+#NET eth_txd<1> LOC = AE11 | IOSTANDARD = LVDCI_33;
+#NET eth_txd<0> LOC = AF11 | IOSTANDARD = LVDCI_33;
+#NET eth_tx_en LOC = AJ10 | IOSTANDARD = LVDCI_33;
+#NET eth_tx_er LOC = AJ9 | IOSTANDARD = LVDCI_33;
+
+## PHY Serial Management Interface pins
+#NET eth_mdc LOC = H19 | IOSTANDARD = LVCMOS25;
+#NET eth_mdio LOC = H13 | IOSTANDARD = LVCMOS25;
+
+## # Timing Constraints (these are recommended in documentation and
+## # are unaltered except for the TIG)
+#NET "eth_rx_clk_BUFGP" TNM_NET = "RXCLK_GRP";
+#NET "eth_tx_clk_BUFGP" TNM_NET = "TXCLK_GRP";
+#TIMESPEC "TSTXOUT" = FROM "TXCLK_GRP" TO "PADS" 10 ns;
+#TIMESPEC "TSRXIN" = FROM "PADS" TO "RXCLK_GRP" 6 ns;
+
+## # Timing ignores (to specify unconstrained paths)
+#FIXME? NET "*clkgen0/wb_clk_o" TNM_NET = "sys_clk"; # Wishbone clock
+#TIMESPEC "TS_PHYTX_OPB" = FROM "TXCLK_GRP" TO "sys_clk" TIG;
+#TIMESPEC "TS_OPB_PHYTX" = FROM "sys_clk" TO "TXCLK_GRP" TIG;
+#TIMESPEC "TS_PHYRX_OPB" = FROM "RXCLK_GRP" TO "sys_clk" TIG;
+#TIMESPEC "TS_OPB_PHYRX" = FROM "sys_clk" TO "RXCLK_GRP" TIG;
Index: spartan3a_dsp_kit/configure
===================================================================
--- spartan3a_dsp_kit/configure (nonexistent)
+++ spartan3a_dsp_kit/configure (revision 64)
@@ -0,0 +1,81 @@
+#!/bin/bash
+
+#new boards have to udpate this
+BOARD=spartan3a_dsp_kit #this has to have the name of the directory this file is in
+DEVICE_PART='xc3sd1800a-4-fg676'
+CONSTRAINT_FILE='spartan3a_dsp_kit.ucf'
+#~new boards update
+
+#system workings
+MINSOC_DIR=`pwd`/../..
+BACKEND_DIR=$MINSOC_DIR/backend
+SYN_DIR=$MINSOC_DIR/syn
+SYNSRC_DIR=$SYN_DIR/src
+SYNSUPPORT_DIR=$SYN_DIR/buildSupport
+
+SYN_FILES=(eth_top.xst uart_top.xst adbg_top.xst or1200_top.xst minsoc_top.xst Makefile)
+
+FIND_PART='DEVICE_PART'
+FIND_CONSTRAINT='CONSTRAINT_FILE'
+
+BOARD_DIR=$BACKEND_DIR/$BOARD
+BOARD_FILES=(board.h orp.ld minsoc_defines.v $CONSTRAINT_FILE)
+
+in_minsoc=`pwd | grep minsoc/backend/${BOARD}$`
+if [ -z $in_minsoc ]
+then
+ echo ""
+ echo " !!!WARNING!!!"
+ echo "This script cannot be run out of a board directory inside minsoc/backend,"
+ echo "because it relies on the directory structure of the minsoc system."
+ echo ""
+ exit 1
+fi
+
+echo ""
+echo "Configuring SoC board's specific files for firmware compilation, "
+echo "testbench generation and synthesis."
+echo "Firmware and testbench looks for board specific files under minsoc/backend."
+echo "Synthesis work under minsoc/syn."
+echo ""
+echo ""
+
+if [ $CONSTRAINT_FILE == 'NONE' ]
+then
+ echo "Skipping synthesis preparation. Standard implementation can only be simulated."
+else
+ echo "Device part for files under minsoc/syn/src will be patched and stored "
+ echo "temporarily."
+ echo "Afterwards, they are copied to minsoc/syn/buildSupport."
+ echo "__________________________________________________________________________"
+ echo ""
+ for file in "${SYN_FILES[@]}"
+ do
+ echo "Updating synthesis file, $file..."
+ echo "Copying $file to synthesis directory..."
+ echo ""
+ sed "s/$FIND_PART/$DEVICE_PART/g" $SYNSRC_DIR/$file > TMPFILE
+ sed "s/$FIND_CONSTRAINT/$CONSTRAINT_FILE/g" TMPFILE > TMPFILE2 && mv TMPFILE2 $SYNSUPPORT_DIR/$file
+ rm TMPFILE
+ done
+
+ echo "Moving Makefile back from minsoc/syn/buildSupport to minsoc/syn..."
+ mv $SYNSUPPORT_DIR/Makefile $SYN_DIR
+fi
+echo ""
+echo ""
+
+
+echo "Copying board specific SoC files to backend directory."
+echo "__________________________________________________________________________"
+echo ""
+for file in "${BOARD_FILES[@]}"
+do
+ if [ $file != NONE ]
+ then
+ echo "Copying $file, to backend directory..."
+ cp $BOARD_DIR/$file $BACKEND_DIR
+ fi
+done
+echo ""
+echo ""
spartan3a_dsp_kit/configure
Property changes :
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Index: spartan3a_dsp_kit/spartan3a_dsp_kit.ucf
===================================================================
--- spartan3a_dsp_kit/spartan3a_dsp_kit.ucf (nonexistent)
+++ spartan3a_dsp_kit/spartan3a_dsp_kit.ucf (revision 64)
@@ -0,0 +1,72 @@
+###########################
+##
+## Global signals
+##
+net "clk" loc = "f13"; #125MHz clock
+net "reset" loc = "j17"; #SW5
+###########################
+
+###########################
+##
+## JTAG
+##
+#net "jtag_tms" loc = "aa23"; #SAM D0
+#net "jtag_tdi" loc = "u20"; #SAM D2
+#net "jtag_tdo" loc = "aa25"; #SAM D4
+#net "jtag_tck" loc = "u18" | CLOCK_DEDICATED_ROUTE = FALSE; #SAM D6
+#net "jtag_gnd" loc = "y23"; #SAM D8
+#net "jtag_vref" loc = "t20"; #SAM D10
+###########################
+
+#############################
+##
+## SPI Flash External Memory
+##
+NET "spi_flash_mosi" LOC = "ab15";
+NET "spi_flash_miso" LOC = "af24";
+NET "spi_flash_sclk" LOC = "ae24";
+NET "spi_flash_ss(1)" LOC = "ac25";
+NET "spi_flash_ss(0)" LOC = "aa7";
+###########################
+
+###########################
+##
+## UART
+##
+net "uart_stx" loc = "p22";
+net "uart_srx" loc = "n21";
+###########################
+
+###########################
+##
+## ETH
+##
+NET "eth_txd(3)" LOC = "b1";
+NET "eth_txd(2)" LOC = "b2";
+NET "eth_txd(1)" LOC = "j9";
+NET "eth_txd(0)" LOC = "j8";
+
+NET "eth_tx_en" LOC = "d3";
+NET "eth_tx_clk" LOC = "p2";
+NET "eth_tx_er" LOC = "e4";
+
+NET "eth_rxd(3)" LOC = "d2";
+NET "eth_rxd(2)" LOC = "g5";
+NET "eth_rxd(1)" LOC = "g2";
+NET "eth_rxd(0)" LOC = "c2";
+
+NET "eth_rx_er" LOC = "j3";
+NET "eth_rx_dv" LOC = "d1";
+
+NET "eth_rx_clk" LOC = "p1";
+
+NET "eth_mdio" LOC = "f5" | PULLUP;
+NET "eth_crs" LOC = "g1";
+NET "eth_col" LOC = "y3";
+NET "eth_mdc" LOC = "f4";
+
+NET "eth_trste" LOC = "g4";
+
+NET "eth_fds_mdint" LOC = "j1";
+###########################
+
spartan3a_dsp_kit/spartan3a_dsp_kit.ucf
Property changes :
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Index: spartan3a_dsp_kit/minsoc_defines.v
===================================================================
--- spartan3a_dsp_kit/minsoc_defines.v (nonexistent)
+++ spartan3a_dsp_kit/minsoc_defines.v (revision 64)
@@ -0,0 +1,148 @@
+//
+// Define FPGA manufacturer
+//
+//`define GENERIC_FPGA
+//`define ALTERA_FPGA
+`define XILINX_FPGA
+
+//
+// Define Xilinx FPGA family
+//
+`ifdef XILINX_FPGA
+//`define SPARTAN2
+//`define SPARTAN3
+//`define SPARTAN3E
+`define SPARTAN3A
+//`define VIRTEX
+//`define VIRTEX2
+//`define VIRTEX4
+//`define VIRTEX5
+
+//
+// Define Altera FPGA family
+//
+`elsif ALTERA_FPGA
+//`define ARRIA_GX
+//`define ARRIA_II_GX
+//`define CYCLONE_I
+//`define CYCLONE_II
+`define CYCLONE_III
+//`define CYCLONE_III_LS
+//`define CYCLONE_IV_E
+//`define CYCLONE_IV_GS
+//`define MAX_II
+//`define MAX_V
+//`define MAX3000A
+//`define MAX7000AE
+//`define MAX7000B
+//`define MAX7000S
+//`define STRATIX
+//`define STRATIX_II
+//`define STRATIX_II_GX
+//`define STRATIX_III
+`endif
+
+//
+// Memory
+//
+`define MEMORY_ADR_WIDTH 13 //MEMORY_ADR_WIDTH IS NOT ALLOWED TO BE LESS THAN 12,
+ //memory is composed by blocks of address width 11
+ //Address width of memory -> select memory depth,
+ //2 powers MEMORY_ADR_WIDTH defines the memory depth
+ //the memory data width is 32 bit,
+ //memory amount in Bytes = 4*memory depth
+
+//
+// Memory type (uncomment something if ASIC or generic memory)
+//
+//`define GENERIC_MEMORY
+//`define AVANT_ATP
+//`define VIRAGE_SSP
+//`define VIRTUALSILICON_SSP
+
+
+//
+// TAP selection
+//
+//`define GENERIC_TAP
+`define FPGA_TAP
+
+//
+// Clock Division selection
+//
+//`define NO_CLOCK_DIVISION
+//`define GENERIC_CLOCK_DIVISION
+`define FPGA_CLOCK_DIVISION // For Altera ALTPLL, only CYCLONE_III family has been tested.
+
+//
+// Define division
+//
+`define CLOCK_DIVISOR 5 //in case of GENERIC_CLOCK_DIVISION the real value will be rounded
+ //down to an even value in FPGA case, check minsoc_clock_manager
+ //for allowed divisors.
+ //DO NOT USE CLOCK_DIVISOR = 1 COMMENT THE CLOCK DIVISION SELECTION
+ //INSTEAD.
+
+//
+// Reset polarity
+//
+//`define NEGATIVE_RESET //rstn
+`define POSITIVE_RESET //rst
+
+//
+// Start-up circuit (only necessary later to load firmware automatically from SPI memory)
+//
+//`define START_UP
+
+//
+// Connected modules
+//
+`define UART
+`define ETHERNET
+
+//
+// Ethernet reset
+//
+//`define ETH_RESET 1'b0
+`define ETH_RESET 1'b1
+
+//
+// Interrupts
+//
+`define APP_INT_RES1 1:0
+`define APP_INT_UART 2
+`define APP_INT_RES2 3
+`define APP_INT_ETH 4
+`define APP_INT_PS2 5
+`define APP_INT_RES3 19:6
+
+//
+// Address map
+//
+`define APP_ADDR_DEC_W 8
+`define APP_ADDR_SRAM `APP_ADDR_DEC_W'h00
+`define APP_ADDR_FLASH `APP_ADDR_DEC_W'h04
+`define APP_ADDR_DECP_W 4
+`define APP_ADDR_PERIP `APP_ADDR_DECP_W'h9
+`define APP_ADDR_SPI `APP_ADDR_DEC_W'h97
+`define APP_ADDR_ETH `APP_ADDR_DEC_W'h92
+`define APP_ADDR_AUDIO `APP_ADDR_DEC_W'h9d
+`define APP_ADDR_UART `APP_ADDR_DEC_W'h90
+`define APP_ADDR_PS2 `APP_ADDR_DEC_W'h94
+`define APP_ADDR_RES1 `APP_ADDR_DEC_W'h9e
+`define APP_ADDR_RES2 `APP_ADDR_DEC_W'h9f
+
+//
+// Set-up GENERIC_TAP, GENERIC_MEMORY if GENERIC_FPGA was chosen
+// and GENERIC_CLOCK_DIVISION if NO_CLOCK_DIVISION was not set
+//
+`ifdef GENERIC_FPGA
+ `undef FPGA_TAP
+ `undef FPGA_CLOCK_DIVISION
+
+ `define GENERIC_TAP
+ `define GENERIC_MEMORY
+ `ifndef NO_CLOCK_DIVISION
+ `define GENERIC_CLOCK_DIVISION
+ `endif
+`endif
Index: spartan3a_dsp_kit/board.h
===================================================================
--- spartan3a_dsp_kit/board.h (nonexistent)
+++ spartan3a_dsp_kit/board.h (revision 64)
@@ -0,0 +1,40 @@
+#ifndef _BOARD_H_
+#define _BOARD_H_
+
+#define MC_ENABLED 0
+
+#define IC_ENABLE 0
+#define IC_SIZE 8192
+#define DC_ENABLE 0
+#define DC_SIZE 8192
+
+
+#define IN_CLK 25000000
+
+
+#define STACK_SIZE 0x01000
+
+#define UART_BAUD_RATE 115200
+
+#define UART_BASE 0x90000000
+#define UART_IRQ 2
+#define ETH_BASE 0x92000000
+#define ETH_IRQ 4
+#define I2C_BASE 0x9D000000
+#define I2C_IRQ 3
+#define CAN_BASE 0x94000000
+#define CAN_IRQ 5
+
+#define MC_BASE_ADDR 0x60000000
+#define SPI_BASE 0xa0000000
+
+#define ETH_DATA_BASE 0xa8000000 /* Address for ETH_DATA */
+
+#define ETH_MACADDR0 0x00
+#define ETH_MACADDR1 0x12
+#define ETH_MACADDR2 0x34
+#define ETH_MACADDR3 0x56
+#define ETH_MACADDR4 0x78
+#define ETH_MACADDR5 0x9a
+
+#endif
spartan3a_dsp_kit/board.h
Property changes :
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Index: spartan3a_dsp_kit/orp.ld
===================================================================
--- spartan3a_dsp_kit/orp.ld (nonexistent)
+++ spartan3a_dsp_kit/orp.ld (revision 64)
@@ -0,0 +1,60 @@
+MEMORY
+ {
+ reset : ORIGIN = 0x00000000, LENGTH = 0x00000200
+ vectors : ORIGIN = 0x00000200, LENGTH = 0x00001000
+ ram : ORIGIN = 0x00001200, LENGTH = 0x0001EE00 /*0x20000 total*/
+ }
+
+SECTIONS
+{
+ .reset :
+ {
+ *(.reset)
+ } > reset
+
+
+
+ .vectors :
+ {
+ _vec_start = .;
+ *(.vectors)
+ _vec_end = .;
+ } > vectors
+
+ .text :
+ {
+ *(.text)
+ } > ram
+
+ .rodata :
+ {
+ *(.rodata)
+ *(.rodata.*)
+ } > ram
+
+ .icm :
+ {
+ _icm_start = .;
+ *(.icm)
+ _icm_end = .;
+ } > ram
+
+ .data :
+ {
+ _dst_beg = .;
+ *(.data)
+ _dst_end = .;
+ } > ram
+
+ .bss :
+ {
+ *(.bss)
+ } > ram
+
+ .stack (NOLOAD) :
+ {
+ *(.stack)
+ _src_addr = .;
+ } > ram
+
+}
spartan3a_dsp_kit/orp.ld
Property changes :
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Index: std/minsoc_defines.v
===================================================================
--- std/minsoc_defines.v (nonexistent)
+++ std/minsoc_defines.v (revision 64)
@@ -0,0 +1,148 @@
+//
+// Define FPGA manufacturer
+//
+`define GENERIC_FPGA
+//`define ALTERA_FPGA
+//`define XILINX_FPGA
+
+//
+// Define Xilinx FPGA family
+//
+`ifdef XILINX_FPGA
+//`define SPARTAN2
+//`define SPARTAN3
+//`define SPARTAN3E
+`define SPARTAN3A
+//`define VIRTEX
+//`define VIRTEX2
+//`define VIRTEX4
+//`define VIRTEX5
+
+//
+// Define Altera FPGA family
+//
+`elsif ALTERA_FPGA
+//`define ARRIA_GX
+//`define ARRIA_II_GX
+//`define CYCLONE_I
+//`define CYCLONE_II
+`define CYCLONE_III
+//`define CYCLONE_III_LS
+//`define CYCLONE_IV_E
+//`define CYCLONE_IV_GS
+//`define MAX_II
+//`define MAX_V
+//`define MAX3000A
+//`define MAX7000AE
+//`define MAX7000B
+//`define MAX7000S
+//`define STRATIX
+//`define STRATIX_II
+//`define STRATIX_II_GX
+//`define STRATIX_III
+`endif
+
+//
+// Memory
+//
+`define MEMORY_ADR_WIDTH 13 //MEMORY_ADR_WIDTH IS NOT ALLOWED TO BE LESS THAN 12,
+ //memory is composed by blocks of address width 11
+ //Address width of memory -> select memory depth,
+ //2 powers MEMORY_ADR_WIDTH defines the memory depth
+ //the memory data width is 32 bit,
+ //memory amount in Bytes = 4*memory depth
+
+//
+// Memory type (uncomment something if ASIC or generic memory)
+//
+//`define GENERIC_MEMORY
+//`define AVANT_ATP
+//`define VIRAGE_SSP
+//`define VIRTUALSILICON_SSP
+
+
+//
+// TAP selection
+//
+//`define GENERIC_TAP
+`define FPGA_TAP
+
+//
+// Clock Division selection
+//
+//`define NO_CLOCK_DIVISION
+//`define GENERIC_CLOCK_DIVISION
+`define FPGA_CLOCK_DIVISION // For Altera ALTPLL, only CYCLONE_III family has been tested.
+
+//
+// Define division
+//
+`define CLOCK_DIVISOR 5 //in case of GENERIC_CLOCK_DIVISION the real value will be rounded
+ //down to an even value in FPGA case, check minsoc_clock_manager
+ //for allowed divisors.
+ //DO NOT USE CLOCK_DIVISOR = 1 COMMENT THE CLOCK DIVISION SELECTION
+ //INSTEAD.
+
+//
+// Reset polarity
+//
+`define NEGATIVE_RESET //rstn
+//`define POSITIVE_RESET //rst
+
+//
+// Start-up circuit (only necessary later to load firmware automatically from SPI memory)
+//
+//`define START_UP
+
+//
+// Connected modules
+//
+`define UART
+`define ETHERNET
+
+//
+// Ethernet reset
+//
+`define ETH_RESET 1'b0
+//`define ETH_RESET 1'b1
+
+//
+// Interrupts
+//
+`define APP_INT_RES1 1:0
+`define APP_INT_UART 2
+`define APP_INT_RES2 3
+`define APP_INT_ETH 4
+`define APP_INT_PS2 5
+`define APP_INT_RES3 19:6
+
+//
+// Address map
+//
+`define APP_ADDR_DEC_W 8
+`define APP_ADDR_SRAM `APP_ADDR_DEC_W'h00
+`define APP_ADDR_FLASH `APP_ADDR_DEC_W'h04
+`define APP_ADDR_DECP_W 4
+`define APP_ADDR_PERIP `APP_ADDR_DECP_W'h9
+`define APP_ADDR_SPI `APP_ADDR_DEC_W'h97
+`define APP_ADDR_ETH `APP_ADDR_DEC_W'h92
+`define APP_ADDR_AUDIO `APP_ADDR_DEC_W'h9d
+`define APP_ADDR_UART `APP_ADDR_DEC_W'h90
+`define APP_ADDR_PS2 `APP_ADDR_DEC_W'h94
+`define APP_ADDR_RES1 `APP_ADDR_DEC_W'h9e
+`define APP_ADDR_RES2 `APP_ADDR_DEC_W'h9f
+
+//
+// Set-up GENERIC_TAP, GENERIC_MEMORY if GENERIC_FPGA was chosen
+// and GENERIC_CLOCK_DIVISION if NO_CLOCK_DIVISION was not set
+//
+`ifdef GENERIC_FPGA
+ `undef FPGA_TAP
+ `undef FPGA_CLOCK_DIVISION
+
+ `define GENERIC_TAP
+ `define GENERIC_MEMORY
+ `ifndef NO_CLOCK_DIVISION
+ `define GENERIC_CLOCK_DIVISION
+ `endif
+`endif
std/minsoc_defines.v
Property changes :
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Index: std/board.h
===================================================================
--- std/board.h (nonexistent)
+++ std/board.h (revision 64)
@@ -0,0 +1,40 @@
+#ifndef _BOARD_H_
+#define _BOARD_H_
+
+#define MC_ENABLED 0
+
+#define IC_ENABLE 0
+#define IC_SIZE 8192
+#define DC_ENABLE 0
+#define DC_SIZE 8192
+
+
+#define IN_CLK 25000000
+
+
+#define STACK_SIZE 0x01000
+
+#define UART_BAUD_RATE 115200
+
+#define UART_BASE 0x90000000
+#define UART_IRQ 2
+#define ETH_BASE 0x92000000
+#define ETH_IRQ 4
+#define I2C_BASE 0x9D000000
+#define I2C_IRQ 3
+#define CAN_BASE 0x94000000
+#define CAN_IRQ 5
+
+#define MC_BASE_ADDR 0x60000000
+#define SPI_BASE 0xa0000000
+
+#define ETH_DATA_BASE 0xa8000000 /* Address for ETH_DATA */
+
+#define ETH_MACADDR0 0x00
+#define ETH_MACADDR1 0x12
+#define ETH_MACADDR2 0x34
+#define ETH_MACADDR3 0x56
+#define ETH_MACADDR4 0x78
+#define ETH_MACADDR5 0x9a
+
+#endif
std/board.h
Property changes :
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Index: std/orp.ld
===================================================================
--- std/orp.ld (nonexistent)
+++ std/orp.ld (revision 64)
@@ -0,0 +1,60 @@
+MEMORY
+ {
+ reset : ORIGIN = 0x00000000, LENGTH = 0x00000200
+ vectors : ORIGIN = 0x00000200, LENGTH = 0x00001000
+ ram : ORIGIN = 0x00001200, LENGTH = 0x00006E00 /*0x8000 total*/
+ }
+
+SECTIONS
+{
+ .reset :
+ {
+ *(.reset)
+ } > reset
+
+
+
+ .vectors :
+ {
+ _vec_start = .;
+ *(.vectors)
+ _vec_end = .;
+ } > vectors
+
+ .text :
+ {
+ *(.text)
+ } > ram
+
+ .rodata :
+ {
+ *(.rodata)
+ *(.rodata.*)
+ } > ram
+
+ .icm :
+ {
+ _icm_start = .;
+ *(.icm)
+ _icm_end = .;
+ } > ram
+
+ .data :
+ {
+ _dst_beg = .;
+ *(.data)
+ _dst_end = .;
+ } > ram
+
+ .bss :
+ {
+ *(.bss)
+ } > ram
+
+ .stack (NOLOAD) :
+ {
+ *(.stack)
+ _src_addr = .;
+ } > ram
+
+}
std/orp.ld
Property changes :
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Index: spartan3e_starter_kit/configure
===================================================================
--- spartan3e_starter_kit/configure (nonexistent)
+++ spartan3e_starter_kit/configure (revision 64)
@@ -0,0 +1,81 @@
+#!/bin/bash
+
+#new boards have to udpate this
+BOARD=spartan3e_starter_kit #this has to have the name of the directory this file is in
+DEVICE_PART='xc3s500e-4-fg320'
+CONSTRAINT_FILE='spartan3e_starter_kit.ucf'
+#~new boards update
+
+#system workings
+MINSOC_DIR=`pwd`/../..
+BACKEND_DIR=$MINSOC_DIR/backend
+SYN_DIR=$MINSOC_DIR/syn
+SYNSRC_DIR=$SYN_DIR/src
+SYNSUPPORT_DIR=$SYN_DIR/buildSupport
+
+SYN_FILES=(eth_top.xst uart_top.xst adbg_top.xst or1200_top.xst minsoc_top.xst Makefile)
+
+FIND_PART='DEVICE_PART'
+FIND_CONSTRAINT='CONSTRAINT_FILE'
+
+BOARD_DIR=$BACKEND_DIR/$BOARD
+BOARD_FILES=(board.h orp.ld minsoc_defines.v $CONSTRAINT_FILE)
+
+in_minsoc=`pwd | grep minsoc/backend/${BOARD}$`
+if [ -z $in_minsoc ]
+then
+ echo ""
+ echo " !!!WARNING!!!"
+ echo "This script cannot be run out of a board directory inside minsoc/backend,"
+ echo "because it relies on the directory structure of the minsoc system."
+ echo ""
+ exit 1
+fi
+
+echo ""
+echo "Configuring SoC board's specific files for firmware compilation, "
+echo "testbench generation and synthesis."
+echo "Firmware and testbench looks for board specific files under minsoc/backend."
+echo "Synthesis work under minsoc/syn."
+echo ""
+echo ""
+
+if [ $CONSTRAINT_FILE == 'NONE' ]
+then
+ echo "Skipping synthesis preparation. Standard implementation can only be simulated."
+else
+ echo "Device part for files under minsoc/syn/src will be patched and stored "
+ echo "temporarily."
+ echo "Afterwards, they are copied to minsoc/syn/buildSupport."
+ echo "__________________________________________________________________________"
+ echo ""
+ for file in "${SYN_FILES[@]}"
+ do
+ echo "Updating synthesis file, $file..."
+ echo "Copying $file to synthesis directory..."
+ echo ""
+ sed "s/$FIND_PART/$DEVICE_PART/g" $SYNSRC_DIR/$file > TMPFILE
+ sed "s/$FIND_CONSTRAINT/$CONSTRAINT_FILE/g" TMPFILE > TMPFILE2 && mv TMPFILE2 $SYNSUPPORT_DIR/$file
+ rm TMPFILE
+ done
+
+ echo "Moving Makefile back from minsoc/syn/buildSupport to minsoc/syn..."
+ mv $SYNSUPPORT_DIR/Makefile $SYN_DIR
+fi
+echo ""
+echo ""
+
+
+echo "Copying board specific SoC files to backend directory."
+echo "__________________________________________________________________________"
+echo ""
+for file in "${BOARD_FILES[@]}"
+do
+ if [ $file != NONE ]
+ then
+ echo "Copying $file, to backend directory..."
+ cp $BOARD_DIR/$file $BACKEND_DIR
+ fi
+done
+echo ""
+echo ""
spartan3e_starter_kit/configure
Property changes :
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Index: spartan3e_starter_kit/spartan3e_starter_kit.ucf
===================================================================
--- spartan3e_starter_kit/spartan3e_starter_kit.ucf (nonexistent)
+++ spartan3e_starter_kit/spartan3e_starter_kit.ucf (revision 64)
@@ -0,0 +1,64 @@
+#
+# Soldered 50MHz clock.
+#
+NET "clk" LOC = "C9";
+
+#
+# Use button "south" as reset.
+#
+NET "reset" LOC = "K17" | PULLDOWN ;
+
+#
+# UART serial port (RS232 DCE) - connector DB9 female.
+#
+NET "uart_srx" LOC = "R7";
+NET "uart_stx" LOC = "M14" | DRIVE = 8 | SLEW = SLOW ;
+
+###########################
+##
+## ETH
+##
+#NET "eth_txd(3)" LOC = "t5";
+#NET "eth_txd(2)" LOC = "r5";
+#NET "eth_txd(1)" LOC = "t15";
+#NET "eth_txd(0)" LOC = "r11";
+#
+#NET "eth_tx_en" LOC = "p15";
+#NET "eth_tx_clk" LOC = "t7" | CLOCK_DEDICATED_ROUTE = FALSE;
+#NET "eth_tx_er" LOC = "r6";
+#
+#NET "eth_rxd(3)" LOC = "v14";
+#NET "eth_rxd(2)" LOC = "u11";
+#NET "eth_rxd(1)" LOC = "t11";
+#NET "eth_rxd(0)" LOC = "v8";
+#
+#NET "eth_rx_er" LOC = "u14";
+#NET "eth_rx_dv" LOC = "v2";
+#
+#NET "eth_rx_clk" LOC = "v3" | CLOCK_DEDICATED_ROUTE = FALSE;
+#
+#NET "eth_mdio" LOC = "u5" | PULLUP;
+#NET "eth_crs" LOC = "u13";
+#NET "eth_col" LOC = "u6";
+#NET "eth_mdc" LOC = "p9";
+#
+#NET "eth_trste" LOC = "p13"; #put it to a non connected FPGA pin (starter kit schematic BANK3)
+#
+#NET "eth_fds_mdint" LOC = "r13" | PULLUP; #put it to a non connected FPGA pin (starter kit schematic BANK3)(pullup not to generate interrupts)
+###########################
+
+#
+# JTAG signals - on J4 6-pin accessory header.
+#
+
+#NET "jtag_tms" LOC = "D7" | PULLDOWN ;
+#NET "jtag_tdi" LOC = "C7" | PULLDOWN ;
+#NET "jtag_tdo" LOC = "F8" | SLEW = FAST | DRIVE = 8 ;
+#NET "jtag_tck" LOC = "E8" | PULLDOWN ;
+
+#net "jtag_gnd" loc = "k2"; #put it to a non connected FPGA pin (starter kit schematic BANK3)
+#net "jtag_vref" loc = "k7"; #put it to a non connected FPGA pin (starter kit schematic BANK3)
+
+#
+# End of file.
+#
spartan3e_starter_kit/spartan3e_starter_kit.ucf
Property changes :
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Index: spartan3e_starter_kit/minsoc_defines.v
===================================================================
--- spartan3e_starter_kit/minsoc_defines.v (nonexistent)
+++ spartan3e_starter_kit/minsoc_defines.v (revision 64)
@@ -0,0 +1,148 @@
+//
+// Define FPGA manufacturer
+//
+//`define GENERIC_FPGA
+//`define ALTERA_FPGA
+`define XILINX_FPGA
+
+//
+// Define Xilinx FPGA family
+//
+`ifdef XILINX_FPGA
+//`define SPARTAN2
+//`define SPARTAN3
+`define SPARTAN3E
+//`define SPARTAN3A
+//`define VIRTEX
+//`define VIRTEX2
+//`define VIRTEX4
+//`define VIRTEX5
+
+//
+// Define Altera FPGA family
+//
+`elsif ALTERA_FPGA
+//`define ARRIA_GX
+//`define ARRIA_II_GX
+//`define CYCLONE_I
+//`define CYCLONE_II
+`define CYCLONE_III
+//`define CYCLONE_III_LS
+//`define CYCLONE_IV_E
+//`define CYCLONE_IV_GS
+//`define MAX_II
+//`define MAX_V
+//`define MAX3000A
+//`define MAX7000AE
+//`define MAX7000B
+//`define MAX7000S
+//`define STRATIX
+//`define STRATIX_II
+//`define STRATIX_II_GX
+//`define STRATIX_III
+`endif
+
+//
+// Memory
+//
+`define MEMORY_ADR_WIDTH 13 //MEMORY_ADR_WIDTH IS NOT ALLOWED TO BE LESS THAN 12,
+ //memory is composed by blocks of address width 11
+ //Address width of memory -> select memory depth,
+ //2 powers MEMORY_ADR_WIDTH defines the memory depth
+ //the memory data width is 32 bit,
+ //memory amount in Bytes = 4*memory depth
+
+//
+// Memory type (uncomment something if ASIC or generic memory)
+//
+//`define GENERIC_MEMORY
+//`define AVANT_ATP
+//`define VIRAGE_SSP
+//`define VIRTUALSILICON_SSP
+
+
+//
+// TAP selection
+//
+//`define GENERIC_TAP
+`define FPGA_TAP
+
+//
+// Clock Division selection
+//
+//`define NO_CLOCK_DIVISION
+//`define GENERIC_CLOCK_DIVISION
+`define FPGA_CLOCK_DIVISION // For Altera ALTPLL, only CYCLONE_III family has been tested.
+
+//
+// Define division
+//
+`define CLOCK_DIVISOR 2 //in case of GENERIC_CLOCK_DIVISION the real value will be rounded
+ //down to an even value in FPGA case, check minsoc_clock_manager
+ //for allowed divisors.
+ //DO NOT USE CLOCK_DIVISOR = 1 COMMENT THE CLOCK DIVISION SELECTION
+ //INSTEAD.
+
+//
+// Reset polarity
+//
+//`define NEGATIVE_RESET //rstn
+`define POSITIVE_RESET //rst
+
+//
+// Start-up circuit (only necessary later to load firmware automatically from SPI memory)
+//
+//`define START_UP
+
+//
+// Connected modules
+//
+`define UART
+//`define ETHERNET
+
+//
+// Ethernet reset
+//
+`define ETH_RESET 1'b0
+//`define ETH_RESET 1'b1
+
+//
+// Interrupts
+//
+`define APP_INT_RES1 1:0
+`define APP_INT_UART 2
+`define APP_INT_RES2 3
+`define APP_INT_ETH 4
+`define APP_INT_PS2 5
+`define APP_INT_RES3 19:6
+
+//
+// Address map
+//
+`define APP_ADDR_DEC_W 8
+`define APP_ADDR_SRAM `APP_ADDR_DEC_W'h00
+`define APP_ADDR_FLASH `APP_ADDR_DEC_W'h04
+`define APP_ADDR_DECP_W 4
+`define APP_ADDR_PERIP `APP_ADDR_DECP_W'h9
+`define APP_ADDR_SPI `APP_ADDR_DEC_W'h97
+`define APP_ADDR_ETH `APP_ADDR_DEC_W'h92
+`define APP_ADDR_AUDIO `APP_ADDR_DEC_W'h9d
+`define APP_ADDR_UART `APP_ADDR_DEC_W'h90
+`define APP_ADDR_PS2 `APP_ADDR_DEC_W'h94
+`define APP_ADDR_RES1 `APP_ADDR_DEC_W'h9e
+`define APP_ADDR_RES2 `APP_ADDR_DEC_W'h9f
+
+//
+// Set-up GENERIC_TAP, GENERIC_MEMORY if GENERIC_FPGA was chosen
+// and GENERIC_CLOCK_DIVISION if NO_CLOCK_DIVISION was not set
+//
+`ifdef GENERIC_FPGA
+ `undef FPGA_TAP
+ `undef FPGA_CLOCK_DIVISION
+
+ `define GENERIC_TAP
+ `define GENERIC_MEMORY
+ `ifndef NO_CLOCK_DIVISION
+ `define GENERIC_CLOCK_DIVISION
+ `endif
+`endif
spartan3e_starter_kit/minsoc_defines.v
Property changes :
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Index: spartan3e_starter_kit/board.h
===================================================================
--- spartan3e_starter_kit/board.h (nonexistent)
+++ spartan3e_starter_kit/board.h (revision 64)
@@ -0,0 +1,40 @@
+#ifndef _BOARD_H_
+#define _BOARD_H_
+
+#define MC_ENABLED 0
+
+#define IC_ENABLE 0
+#define IC_SIZE 8192
+#define DC_ENABLE 0
+#define DC_SIZE 8192
+
+
+#define IN_CLK 25000000
+
+
+#define STACK_SIZE 0x01000
+
+#define UART_BAUD_RATE 115200
+
+#define UART_BASE 0x90000000
+#define UART_IRQ 2
+#define ETH_BASE 0x92000000
+#define ETH_IRQ 4
+#define I2C_BASE 0x9D000000
+#define I2C_IRQ 3
+#define CAN_BASE 0x94000000
+#define CAN_IRQ 5
+
+#define MC_BASE_ADDR 0x60000000
+#define SPI_BASE 0xa0000000
+
+#define ETH_DATA_BASE 0xa8000000 /* Address for ETH_DATA */
+
+#define ETH_MACADDR0 0x00
+#define ETH_MACADDR1 0x12
+#define ETH_MACADDR2 0x34
+#define ETH_MACADDR3 0x56
+#define ETH_MACADDR4 0x78
+#define ETH_MACADDR5 0x9a
+
+#endif
spartan3e_starter_kit/board.h
Property changes :
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Index: spartan3e_starter_kit/orp.ld
===================================================================
--- spartan3e_starter_kit/orp.ld (nonexistent)
+++ spartan3e_starter_kit/orp.ld (revision 64)
@@ -0,0 +1,60 @@
+MEMORY
+ {
+ reset : ORIGIN = 0x00000000, LENGTH = 0x00000200
+ vectors : ORIGIN = 0x00000200, LENGTH = 0x00001000
+ ram : ORIGIN = 0x00001200, LENGTH = 0x00006E00 /*0x8000 total*/
+ }
+
+SECTIONS
+{
+ .reset :
+ {
+ *(.reset)
+ } > reset
+
+
+
+ .vectors :
+ {
+ _vec_start = .;
+ *(.vectors)
+ _vec_end = .;
+ } > vectors
+
+ .text :
+ {
+ *(.text)
+ } > ram
+
+ .rodata :
+ {
+ *(.rodata)
+ *(.rodata.*)
+ } > ram
+
+ .icm :
+ {
+ _icm_start = .;
+ *(.icm)
+ _icm_end = .;
+ } > ram
+
+ .data :
+ {
+ _dst_beg = .;
+ *(.data)
+ _dst_end = .;
+ } > ram
+
+ .bss :
+ {
+ *(.bss)
+ } > ram
+
+ .stack (NOLOAD) :
+ {
+ *(.stack)
+ _src_addr = .;
+ } > ram
+
+}
spartan3e_starter_kit/orp.ld
Property changes :
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property