URL
https://opencores.org/ocsvn/minsoc/minsoc/trunk
Subversion Repositories minsoc
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- This comparison shows the changes necessary to convert path
/minsoc/trunk/bench/verilog/sim_lib
- from Rev 10 to Rev 17
- ↔ Reverse comparison
Rev 10 → Rev 17
/fpga_memory_primitives.v
647,7 → 647,7
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endmodule |
// |
// XILINX_RAM32X1D |
// ~XILINX_RAM32X1D |
// |
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697,5 → 697,5
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endmodule |
// |
// USE_RAM16X1D_FOR_RAM32X1D |
// ~USE_RAM16X1D_FOR_RAM32X1D |
// |