URL
https://opencores.org/ocsvn/minsoc/minsoc/trunk
Subversion Repositories minsoc
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/minsoc/trunk/bench/verilog
- from Rev 10 to Rev 11
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Rev 10 → Rev 11
/minsoc_bench.v
54,6 → 54,7
initial begin |
reset = 1'b0; |
clock = 1'b0; |
uart_srx = 1'b1; |
|
//dual and two port rams from FPGA memory instances have to be initialized to |
//0 |