URL
https://opencores.org/ocsvn/minsoc/minsoc/trunk
Subversion Repositories minsoc
Compare Revisions
- This comparison shows the changes necessary to convert path
/minsoc/trunk/prj/altera
- from Rev 85 to Rev 93
- ↔ Reverse comparison
Rev 85 → Rev 93
/adv_dbg.prj
0,0 → 1,?rev2len?
set_global_assignment -name SEARCH_PATH ../rtl/verilog/adv_debug_sys/Hardware/adv_dbg_if/rtl/verilog |
/minsoc_top.qsf
0,0 → 1,37
set_global_assignment -name FAMILY "FAMILY_PART" |
set_global_assignment -name DEVICE DEVICE_PART |
set_global_assignment -name TOP_LEVEL_ENTITY minsoc_top |
#set_global_assignment -name ORIGINAL_QUARTUS_VERSION SW_VERSION |
#set_global_assignment -name LAST_QUARTUS_VERSION SW_VERSION |
set_global_assignment -name MIN_CORE_JUNCTION_TEMP 0 |
set_global_assignment -name MAX_CORE_JUNCTION_TEMP 85 |
set_global_assignment -name DEVICE_FILTER_PIN_COUNT 240 |
set_global_assignment -name ERROR_CHECK_FREQUENCY_DIVISOR 2 |
set_global_assignment -name PARTITION_NETLIST_TYPE SOURCE -section_id Top |
set_global_assignment -name PARTITION_FITTER_PRESERVATION_LEVEL PLACEMENT_AND_ROUTING -section_id Top |
set_global_assignment -name PARTITION_COLOR 16764057 -section_id Top |
set_global_assignment -name STRATIX_DEVICE_IO_STANDARD "2.5 V" |
#set_global_assignment -name MISC_FILE ./minsoc_top.dpf |
set_global_assignment -name USE_CONFIGURATION_DEVICE OFF |
set_global_assignment -name CRC_ERROR_OPEN_DRAIN OFF |
set_global_assignment -name FORCE_CONFIGURATION_VCCIO ON |
set_global_assignment -name OUTPUT_IO_TIMING_NEAR_END_VMEAS "HALF VCCIO" -rise |
set_global_assignment -name OUTPUT_IO_TIMING_NEAR_END_VMEAS "HALF VCCIO" -fall |
set_global_assignment -name OUTPUT_IO_TIMING_FAR_END_VMEAS "HALF SIGNAL SWING" -rise |
set_global_assignment -name OUTPUT_IO_TIMING_FAR_END_VMEAS "HALF SIGNAL SWING" -fall |
set_global_assignment -name RESERVE_DATA1_AFTER_CONFIGURATION "USE AS REGULAR IO" |
set_global_assignment -name RESERVE_FLASH_NCE_AFTER_CONFIGURATION "USE AS REGULAR IO" |
set_global_assignment -name EDA_BOARD_DESIGN_BOUNDARY_SCAN_TOOL "BSDL (Boundary Scan)" |
set_global_assignment -name EDA_OUTPUT_DATA_FORMAT BSDL -section_id eda_board_design_boundary_scan |
set_global_assignment -name EDA_BOARD_BOUNDARY_SCAN_OPERATION POST_CONFIG -section_id eda_board_design_boundary_scan |
set_global_assignment -name POWER_PRESET_COOLING_SOLUTION "23 MM HEAT SINK WITH 200 LFPM AIRFLOW" |
set_global_assignment -name POWER_BOARD_THERMAL_MODEL "NONE (CONSERVATIVE)" |
set_global_assignment -name EDA_TIMING_ANALYSIS_TOOL "<None>" |
set_global_assignment -name EDA_TIME_SCALE "1 ps" -section_id eda_timing_analysis |
set_global_assignment -name EDA_RUN_TOOL_AUTOMATICALLY OFF -section_id eda_timing_analysis |
set_global_assignment -name EDA_OUTPUT_DATA_FORMAT NONE -section_id eda_timing_analysis |
set_global_assignment -name EDA_LAUNCH_CMD_LINE_TOOL OFF -section_id eda_timing_analysis |
|
set_global_assignment -name SDC_FILE minsoc_top.sdc |
set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -section_id Top |
|
/minsoc_top.prj
0,0 → 1,8
set_global_assignment -name VERILOG_FILE ../rtl/verilog/timescale.v |
set_global_assignment -name VERILOG_FILE ../rtl/verilog/minsoc_top.v |
set_global_assignment -name VERILOG_FILE ../rtl/verilog/minsoc_tc_top.v |
set_global_assignment -name VERILOG_FILE ../rtl/verilog/minsoc_onchip_ram_top.v |
set_global_assignment -name VERILOG_FILE ../rtl/verilog/minsoc_onchip_ram.v |
set_global_assignment -name VERILOG_FILE ../rtl/verilog/minsoc_defines.v |
set_global_assignment -name VERILOG_FILE ../rtl/verilog/minsoc_clock_manager.v |
set_global_assignment -name VERILOG_FILE ../rtl/verilog/altera_pll.v |
/or1k.prj
0,0 → 1,8
set_global_assignment -name SEARCH_PATH ../rtl/verilog/or1200/rtl/verilog |
/uart16550.prj
0,0 → 1,8
set_global_assignment -name SEARCH_PATH ../rtl/verilog/uart16550/rtl/verilog |
/altera_jtag.prj
0,0 → 1,8
set_global_assignment -name SEARCH_PATH ../rtl/verilog/adv_debug_sys/Hardware/altera_virtual_jtag/rtl/vhdl |
/ethmac.prj
0,0 → 1,8
set_global_assignment -name SEARCH_PATH ../rtl/verilog/ethmac/rtl/verilog |