URL
https://opencores.org/ocsvn/minsoc/minsoc/trunk
Subversion Repositories minsoc
Compare Revisions
- This comparison shows the changes necessary to convert path
/minsoc/trunk/prj/sim
- from Rev 85 to Rev 88
- ↔ Reverse comparison
Rev 85 → Rev 88
/minsoc_top.src
4,20 → 4,25
+incdir+/home/raul/or1k/minsoc/prj/../bench/verilog/sim_lib |
+incdir+/home/raul/or1k/minsoc/prj/../rtl/verilog |
+incdir+/home/raul/or1k/minsoc/prj/../rtl/verilog/minsoc_startup |
+incdir+/home/raul/or1k/minsoc/prj/../rtl/verilog/or1200/rtl/verilog |
+incdir+/home/raul/or1k/minsoc/prj/../rtl/verilog/adv_debug_sys/Hardware/adv_dbg_if/rtl/verilog |
+incdir+/home/raul/or1k/minsoc/prj/../rtl/verilog/ethmac/rtl/verilog |
+incdir+/home/raul/or1k/minsoc/prj/../rtl/verilog/uart16550/rtl/verilog |
/home/raul/or1k/minsoc/prj/../backend/minsoc_defines.v |
/home/raul/or1k/minsoc/prj/../backend/minsoc_bench_defines.v |
/home/raul/or1k/minsoc/prj/../bench/verilog/minsoc_bench.v |
/home/raul/or1k/minsoc/prj/../bench/verilog/minsoc_memory_model.v |
/home/raul/or1k/minsoc/prj/../bench/verilog/vpi/dbg_comm_vpi.v |
/home/raul/or1k/minsoc/prj/../bench/verilog/sim_lib/fpga_memory_primitives.v |
/home/raul/or1k/minsoc/prj/../rtl/verilog/timescale.v |
/home/raul/or1k/minsoc/prj/../rtl/verilog/or1200/rtl/verilog/timescale.v |
/home/raul/or1k/minsoc/prj/../rtl/verilog/ethmac/rtl/verilog/timescale.v |
/home/raul/or1k/minsoc/prj/../rtl/verilog/uart16550/rtl/verilog/timescale.v |
/home/raul/or1k/minsoc/prj/../rtl/verilog/minsoc_top.v |
/home/raul/or1k/minsoc/prj/../rtl/verilog/minsoc_tc_top.v |
/home/raul/or1k/minsoc/prj/../rtl/verilog/minsoc_onchip_ram.v |
/home/raul/or1k/minsoc/prj/../rtl/verilog/minsoc_onchip_ram_top.v |
/home/raul/or1k/minsoc/prj/../rtl/verilog/minsoc_clock_manager.v |
/home/raul/or1k/minsoc/prj/../rtl/verilog/altera_pll.v |
/home/raul/or1k/minsoc/prj/../rtl/verilog/xilinx_dcm.v |
/home/raul/or1k/minsoc/prj/../rtl/verilog/minsoc_xilinx_internal_jtag.v |
/home/raul/or1k/minsoc/prj/../rtl/verilog/minsoc_startup/spi_top.v |
/home/raul/or1k/minsoc/prj/../rtl/verilog/minsoc_startup/spi_defines.v |
/home/raul/or1k/minsoc/prj/../rtl/verilog/minsoc_startup/spi_shift.v |
/home/raul/or1k/minsoc/prj/../rtl/verilog/minsoc_startup/spi_clgen.v |
/home/raul/or1k/minsoc/prj/../rtl/verilog/minsoc_startup/OR1K_startup_generic.v |
/home/raul/or1k/minsoc/prj/../rtl/verilog/minsoc_tc_top.v |
/home/raul/or1k/minsoc/prj/../rtl/verilog/minsoc_onchip_ram.v |
/home/raul/or1k/minsoc/prj/../rtl/verilog/minsoc_clock_manager.v |
/home/raul/or1k/minsoc/prj/../rtl/verilog/minsoc_onchip_ram_top.v |
/minsoc.src
3,8 → 3,6
+incdir+/home/raul/or1k/minsoc/prj/../bench/verilog/vpi |
+incdir+/home/raul/or1k/minsoc/prj/../bench/verilog/sim_lib |
+incdir+/home/raul/or1k/minsoc/prj/../rtl/verilog |
+incdir+/home/raul/or1k/minsoc/prj/../rtl/verilog/minsoc_startup |
/home/raul/or1k/minsoc/prj/../backend/minsoc_defines.v |
/home/raul/or1k/minsoc/prj/../backend/minsoc_bench_defines.v |
/home/raul/or1k/minsoc/prj/../bench/verilog/minsoc_bench.v |
/home/raul/or1k/minsoc/prj/../bench/verilog/minsoc_memory_model.v |
11,16 → 9,34
/home/raul/or1k/minsoc/prj/../bench/verilog/vpi/dbg_comm_vpi.v |
/home/raul/or1k/minsoc/prj/../bench/verilog/sim_lib/fpga_memory_primitives.v |
/home/raul/or1k/minsoc/prj/../rtl/verilog/timescale.v |
+incdir+/home/raul/or1k/minsoc/prj/../backend |
+incdir+/home/raul/or1k/minsoc/prj/../bench/verilog |
+incdir+/home/raul/or1k/minsoc/prj/../bench/verilog/vpi |
+incdir+/home/raul/or1k/minsoc/prj/../bench/verilog/sim_lib |
+incdir+/home/raul/or1k/minsoc/prj/../rtl/verilog |
+incdir+/home/raul/or1k/minsoc/prj/../rtl/verilog/minsoc_startup |
+incdir+/home/raul/or1k/minsoc/prj/../rtl/verilog/or1200/rtl/verilog |
+incdir+/home/raul/or1k/minsoc/prj/../rtl/verilog/adv_debug_sys/Hardware/adv_dbg_if/rtl/verilog |
+incdir+/home/raul/or1k/minsoc/prj/../rtl/verilog/ethmac/rtl/verilog |
+incdir+/home/raul/or1k/minsoc/prj/../rtl/verilog/uart16550/rtl/verilog |
/home/raul/or1k/minsoc/prj/../backend/minsoc_defines.v |
/home/raul/or1k/minsoc/prj/../rtl/verilog/timescale.v |
/home/raul/or1k/minsoc/prj/../rtl/verilog/or1200/rtl/verilog/timescale.v |
/home/raul/or1k/minsoc/prj/../rtl/verilog/ethmac/rtl/verilog/timescale.v |
/home/raul/or1k/minsoc/prj/../rtl/verilog/uart16550/rtl/verilog/timescale.v |
/home/raul/or1k/minsoc/prj/../rtl/verilog/minsoc_top.v |
/home/raul/or1k/minsoc/prj/../rtl/verilog/minsoc_tc_top.v |
/home/raul/or1k/minsoc/prj/../rtl/verilog/minsoc_onchip_ram.v |
/home/raul/or1k/minsoc/prj/../rtl/verilog/minsoc_onchip_ram_top.v |
/home/raul/or1k/minsoc/prj/../rtl/verilog/minsoc_clock_manager.v |
/home/raul/or1k/minsoc/prj/../rtl/verilog/altera_pll.v |
/home/raul/or1k/minsoc/prj/../rtl/verilog/xilinx_dcm.v |
/home/raul/or1k/minsoc/prj/../rtl/verilog/minsoc_xilinx_internal_jtag.v |
/home/raul/or1k/minsoc/prj/../rtl/verilog/minsoc_startup/spi_top.v |
/home/raul/or1k/minsoc/prj/../rtl/verilog/minsoc_startup/spi_defines.v |
/home/raul/or1k/minsoc/prj/../rtl/verilog/minsoc_startup/spi_shift.v |
/home/raul/or1k/minsoc/prj/../rtl/verilog/minsoc_startup/spi_clgen.v |
/home/raul/or1k/minsoc/prj/../rtl/verilog/minsoc_startup/OR1K_startup_generic.v |
/home/raul/or1k/minsoc/prj/../rtl/verilog/minsoc_tc_top.v |
/home/raul/or1k/minsoc/prj/../rtl/verilog/minsoc_onchip_ram.v |
/home/raul/or1k/minsoc/prj/../rtl/verilog/minsoc_clock_manager.v |
/home/raul/or1k/minsoc/prj/../rtl/verilog/minsoc_onchip_ram_top.v |
+incdir+/home/raul/or1k/minsoc/prj/../rtl/verilog/or1200/rtl/verilog |
/home/raul/or1k/minsoc/prj/../rtl/verilog/or1200/rtl/verilog/or1200_spram_512x20.v |
/home/raul/or1k/minsoc/prj/../rtl/verilog/or1200/rtl/verilog/or1200_spram_64x24.v |