URL
https://opencores.org/ocsvn/minsoc/minsoc/trunk
Subversion Repositories minsoc
Compare Revisions
- This comparison shows the changes necessary to convert path
/minsoc/trunk/prj/xilinx
- from Rev 85 to Rev 88
- ↔ Reverse comparison
Rev 85 → Rev 88
/or1200_top.xst
1,7 → 1,7
set -tmpdir ./xst |
run |
-vlgincdir { "/home/raul/or1k/minsoc/prj/../rtl/verilog/or1200/rtl/verilog" } |
-ifn /home/raul/or1k/minsoc/prj/../prj/or1200_top.prj |
-ifn /home/raul/or1k/minsoc/prj/../prj/xilinx/or1200_top.prj |
-ifmt Verilog |
-ofn or1200_top |
-ofmt NGC |
/jtag_top.xst
1,7 → 1,7
set -tmpdir ./xst |
run |
-vlgincdir { "/home/raul/or1k/minsoc/prj/../rtl/verilog/adv_debug_sys/Hardware/jtag/tap/rtl/verilog" } |
-ifn /home/raul/or1k/minsoc/prj/../prj/jtag_top.prj |
-ifn /home/raul/or1k/minsoc/prj/../prj/xilinx/jtag_top.prj |
-ifmt Verilog |
-ofn jtag_top |
-ofmt NGC |
/minsoc_top.prj
1,20 → 1,21
`include "/home/raul/or1k/minsoc/prj/../backend/minsoc_defines.v" |
`include "/home/raul/or1k/minsoc/prj/../backend/minsoc_bench_defines.v" |
`include "/home/raul/or1k/minsoc/prj/../bench/verilog/minsoc_bench.v" |
`include "/home/raul/or1k/minsoc/prj/../bench/verilog/minsoc_memory_model.v" |
`include "/home/raul/or1k/minsoc/prj/../bench/verilog/vpi/dbg_comm_vpi.v" |
`include "/home/raul/or1k/minsoc/prj/../bench/verilog/sim_lib/fpga_memory_primitives.v" |
`include "/home/raul/or1k/minsoc/prj/../rtl/verilog/timescale.v" |
`include "/home/raul/or1k/minsoc/prj/../rtl/verilog/or1200/rtl/verilog/timescale.v" |
`include "/home/raul/or1k/minsoc/prj/../rtl/verilog/ethmac/rtl/verilog/timescale.v" |
`include "/home/raul/or1k/minsoc/prj/../rtl/verilog/uart16550/rtl/verilog/timescale.v" |
`include "/home/raul/or1k/minsoc/prj/../rtl/verilog/minsoc_top.v" |
`include "/home/raul/or1k/minsoc/prj/../rtl/verilog/minsoc_tc_top.v" |
`include "/home/raul/or1k/minsoc/prj/../rtl/verilog/minsoc_onchip_ram.v" |
`include "/home/raul/or1k/minsoc/prj/../rtl/verilog/minsoc_onchip_ram_top.v" |
`include "/home/raul/or1k/minsoc/prj/../rtl/verilog/minsoc_clock_manager.v" |
`include "/home/raul/or1k/minsoc/prj/../rtl/verilog/altera_pll.v" |
`include "/home/raul/or1k/minsoc/prj/../rtl/verilog/xilinx_dcm.v" |
`include "/home/raul/or1k/minsoc/prj/../rtl/verilog/minsoc_xilinx_internal_jtag.v" |
`include "/home/raul/or1k/minsoc/prj/../rtl/verilog/minsoc_startup/spi_top.v" |
`include "/home/raul/or1k/minsoc/prj/../rtl/verilog/minsoc_startup/spi_defines.v" |
`include "/home/raul/or1k/minsoc/prj/../rtl/verilog/minsoc_startup/spi_shift.v" |
`include "/home/raul/or1k/minsoc/prj/../rtl/verilog/minsoc_startup/spi_clgen.v" |
`include "/home/raul/or1k/minsoc/prj/../rtl/verilog/minsoc_startup/OR1K_startup_generic.v" |
`include "/home/raul/or1k/minsoc/prj/../rtl/verilog/minsoc_tc_top.v" |
`include "/home/raul/or1k/minsoc/prj/../rtl/verilog/minsoc_onchip_ram.v" |
`include "/home/raul/or1k/minsoc/prj/../rtl/verilog/minsoc_clock_manager.v" |
`include "/home/raul/or1k/minsoc/prj/../rtl/verilog/minsoc_onchip_ram_top.v" |
`include "/home/raul/or1k/minsoc/prj/src/blackboxes/adbg_top.v" |
`include "/home/raul/or1k/minsoc/prj/src/blackboxes/ethmac.v" |
`include "/home/raul/or1k/minsoc/prj/src/blackboxes/or1200_top.v" |
/minsoc_top.xst
1,7 → 1,7
set -tmpdir ./xst |
run |
-vlgincdir { "/home/raul/or1k/minsoc/prj/../backend" "/home/raul/or1k/minsoc/prj/../bench/verilog" "/home/raul/or1k/minsoc/prj/../bench/verilog/vpi" "/home/raul/or1k/minsoc/prj/../bench/verilog/sim_lib" "/home/raul/or1k/minsoc/prj/../rtl/verilog" "/home/raul/or1k/minsoc/prj/../rtl/verilog/minsoc_startup" } |
-ifn /home/raul/or1k/minsoc/prj/../prj/minsoc_top.prj |
-vlgincdir { "/home/raul/or1k/minsoc/prj/../backend" "/home/raul/or1k/minsoc/prj/../bench/verilog" "/home/raul/or1k/minsoc/prj/../bench/verilog/vpi" "/home/raul/or1k/minsoc/prj/../bench/verilog/sim_lib" "/home/raul/or1k/minsoc/prj/../rtl/verilog" "/home/raul/or1k/minsoc/prj/../rtl/verilog/minsoc_startup" "/home/raul/or1k/minsoc/prj/../rtl/verilog/or1200/rtl/verilog" "/home/raul/or1k/minsoc/prj/../rtl/verilog/adv_debug_sys/Hardware/adv_dbg_if/rtl/verilog" "/home/raul/or1k/minsoc/prj/../rtl/verilog/ethmac/rtl/verilog" "/home/raul/or1k/minsoc/prj/../rtl/verilog/uart16550/rtl/verilog" } |
-ifn /home/raul/or1k/minsoc/prj/../prj/xilinx/minsoc_top.prj |
-ifmt Verilog |
-ofn minsoc_top |
-ofmt NGC |
/uart_top.xst
1,7 → 1,7
set -tmpdir ./xst |
run |
-vlgincdir { "/home/raul/or1k/minsoc/prj/../rtl/verilog/uart16550/rtl/verilog" } |
-ifn /home/raul/or1k/minsoc/prj/../prj/uart_top.prj |
-ifn /home/raul/or1k/minsoc/prj/../prj/xilinx/uart_top.prj |
-ifmt Verilog |
-ofn uart_top |
-ofmt NGC |
/adbg_top.xst
1,7 → 1,7
set -tmpdir ./xst |
run |
-vlgincdir { "/home/raul/or1k/minsoc/prj/../rtl/verilog/adv_debug_sys/Hardware/adv_dbg_if/rtl/verilog" } |
-ifn /home/raul/or1k/minsoc/prj/../prj/adbg_top.prj |
-ifn /home/raul/or1k/minsoc/prj/../prj/xilinx/adbg_top.prj |
-ifmt Verilog |
-ofn adbg_top |
-ofmt NGC |
/ethmac.xst
1,7 → 1,7
set -tmpdir ./xst |
run |
-vlgincdir { "/home/raul/or1k/minsoc/prj/../rtl/verilog/ethmac/rtl/verilog" } |
-ifn /home/raul/or1k/minsoc/prj/../prj/ethmac.prj |
-ifn /home/raul/or1k/minsoc/prj/../prj/xilinx/ethmac.prj |
-ifmt Verilog |
-ofn ethmac |
-ofmt NGC |