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URL https://opencores.org/ocsvn/minsoc/minsoc/trunk

Subversion Repositories minsoc

Compare Revisions

  • This comparison shows the changes necessary to convert path 
    /minsoc/trunk/prj
    from Rev 94 to Rev 95
    ↔ Reverse comparison
  •

Rev 94 → Rev 95

/altera/minsoc_top.qsf File deleted
/altera/uart16550.prj File deleted
/altera/or1k.prj File deleted
/altera/adv_dbg.prj File deleted
/altera/altera_jtag.prj File deleted
/altera/or1200_top.prj
0,0 → 1,64
set_global_assignment -name SEARCH_PATH ../../rtl/verilog/or1200/rtl/verilog
set_global_assignment -name VERILOG_FILE ../../rtl/verilog/or1200/rtl/verilog/or1200_spram_512x20.v
set_global_assignment -name VERILOG_FILE ../../rtl/verilog/or1200/rtl/verilog/or1200_spram_64x24.v
set_global_assignment -name VERILOG_FILE ../../rtl/verilog/or1200/rtl/verilog/or1200_du.v
set_global_assignment -name VERILOG_FILE ../../rtl/verilog/or1200/rtl/verilog/or1200_spram_2048x32_bw.v
set_global_assignment -name VERILOG_FILE ../../rtl/verilog/or1200/rtl/verilog/or1200_rf.v
set_global_assignment -name VERILOG_FILE ../../rtl/verilog/or1200/rtl/verilog/or1200_alu.v
set_global_assignment -name VERILOG_FILE ../../rtl/verilog/or1200/rtl/verilog/or1200_dmmu_top.v
set_global_assignment -name VERILOG_FILE ../../rtl/verilog/or1200/rtl/verilog/or1200_lsu.v
set_global_assignment -name VERILOG_FILE ../../rtl/verilog/or1200/rtl/verilog/or1200_spram_1024x32.v
set_global_assignment -name VERILOG_FILE ../../rtl/verilog/or1200/rtl/verilog/or1200_dc_top.v
set_global_assignment -name VERILOG_FILE ../../rtl/verilog/or1200/rtl/verilog/or1200_cpu.v
set_global_assignment -name VERILOG_FILE ../../rtl/verilog/or1200/rtl/verilog/or1200_gmultp2_32x32.v
set_global_assignment -name VERILOG_FILE ../../rtl/verilog/or1200/rtl/verilog/or1200_immu_top.v
set_global_assignment -name VERILOG_FILE ../../rtl/verilog/or1200/rtl/verilog/or1200_dpram_256x32.v
set_global_assignment -name VERILOG_FILE ../../rtl/verilog/or1200/rtl/verilog/or1200_tt.v
set_global_assignment -name VERILOG_FILE ../../rtl/verilog/or1200/rtl/verilog/or1200_iwb_biu.v
set_global_assignment -name VERILOG_FILE ../../rtl/verilog/or1200/rtl/verilog/or1200_rfram_generic.v
set_global_assignment -name VERILOG_FILE ../../rtl/verilog/or1200/rtl/verilog/or1200_dc_tag.v
set_global_assignment -name VERILOG_FILE ../../rtl/verilog/or1200/rtl/verilog/or1200_spram_2048x8.v
set_global_assignment -name VERILOG_FILE ../../rtl/verilog/or1200/rtl/verilog/or1200_immu_tlb.v
set_global_assignment -name VERILOG_FILE ../../rtl/verilog/or1200/rtl/verilog/or1200_ic_tag.v
set_global_assignment -name VERILOG_FILE ../../rtl/verilog/or1200/rtl/verilog/or1200_spram_64x14.v
set_global_assignment -name VERILOG_FILE ../../rtl/verilog/or1200/rtl/verilog/or1200_spram_32x24.v
set_global_assignment -name VERILOG_FILE ../../rtl/verilog/or1200/rtl/verilog/or1200_dpram_32x32.v
set_global_assignment -name VERILOG_FILE ../../rtl/verilog/or1200/rtl/verilog/or1200_xcv_ram32x8d.v
set_global_assignment -name VERILOG_FILE ../../rtl/verilog/or1200/rtl/verilog/or1200_spram_1024x8.v
set_global_assignment -name VERILOG_FILE ../../rtl/verilog/or1200/rtl/verilog/or1200_mem2reg.v
set_global_assignment -name VERILOG_FILE ../../rtl/verilog/or1200/rtl/verilog/or1200_pm.v
set_global_assignment -name VERILOG_FILE ../../rtl/verilog/or1200/rtl/verilog/or1200_spram_256x21.v
set_global_assignment -name VERILOG_FILE ../../rtl/verilog/or1200/rtl/verilog/or1200_operandmuxes.v
set_global_assignment -name VERILOG_FILE ../../rtl/verilog/or1200/rtl/verilog/or1200_pic.v
set_global_assignment -name VERILOG_FILE ../../rtl/verilog/or1200/rtl/verilog/or1200_cfgr.v
set_global_assignment -name VERILOG_FILE ../../rtl/verilog/or1200/rtl/verilog/or1200_if.v
set_global_assignment -name VERILOG_FILE ../../rtl/verilog/or1200/rtl/verilog/or1200_qmem_top.v
set_global_assignment -name VERILOG_FILE ../../rtl/verilog/or1200/rtl/verilog/or1200_genpc.v
set_global_assignment -name VERILOG_FILE ../../rtl/verilog/or1200/rtl/verilog/or1200_defines.v
set_global_assignment -name VERILOG_FILE ../../rtl/verilog/or1200/rtl/verilog/or1200_wbmux.v
set_global_assignment -name VERILOG_FILE ../../rtl/verilog/or1200/rtl/verilog/or1200_ic_ram.v
set_global_assignment -name VERILOG_FILE ../../rtl/verilog/or1200/rtl/verilog/or1200_dmmu_tlb.v
set_global_assignment -name VERILOG_FILE ../../rtl/verilog/or1200/rtl/verilog/or1200_sb_fifo.v
set_global_assignment -name VERILOG_FILE ../../rtl/verilog/or1200/rtl/verilog/or1200_sprs.v
set_global_assignment -name VERILOG_FILE ../../rtl/verilog/or1200/rtl/verilog/or1200_tpram_32x32.v
set_global_assignment -name VERILOG_FILE ../../rtl/verilog/or1200/rtl/verilog/or1200_ctrl.v
set_global_assignment -name VERILOG_FILE ../../rtl/verilog/or1200/rtl/verilog/or1200_sb.v
set_global_assignment -name VERILOG_FILE ../../rtl/verilog/or1200/rtl/verilog/or1200_mult_mac.v
set_global_assignment -name VERILOG_FILE ../../rtl/verilog/or1200/rtl/verilog/or1200_ic_fsm.v
set_global_assignment -name VERILOG_FILE ../../rtl/verilog/or1200/rtl/verilog/or1200_amultp2_32x32.v
set_global_assignment -name VERILOG_FILE ../../rtl/verilog/or1200/rtl/verilog/or1200_reg2mem.v
set_global_assignment -name VERILOG_FILE ../../rtl/verilog/or1200/rtl/verilog/or1200_spram_2048x32.v
set_global_assignment -name VERILOG_FILE ../../rtl/verilog/or1200/rtl/verilog/or1200_except.v
set_global_assignment -name VERILOG_FILE ../../rtl/verilog/or1200/rtl/verilog/or1200_top.v
set_global_assignment -name VERILOG_FILE ../../rtl/verilog/or1200/rtl/verilog/or1200_ic_top.v
set_global_assignment -name VERILOG_FILE ../../rtl/verilog/or1200/rtl/verilog/or1200_dc_ram.v
set_global_assignment -name VERILOG_FILE ../../rtl/verilog/or1200/rtl/verilog/or1200_spram_1024x32_bw.v
set_global_assignment -name VERILOG_FILE ../../rtl/verilog/or1200/rtl/verilog/or1200_freeze.v
set_global_assignment -name VERILOG_FILE ../../rtl/verilog/or1200/rtl/verilog/or1200_spram_128x32.v
set_global_assignment -name VERILOG_FILE ../../rtl/verilog/or1200/rtl/verilog/or1200_dc_fsm.v
set_global_assignment -name VERILOG_FILE ../../rtl/verilog/or1200/rtl/verilog/or1200_wb_biu.v
set_global_assignment -name VERILOG_FILE ../../rtl/verilog/or1200/rtl/verilog/or1200_spram_64x22.v
set_global_assignment -name VERILOG_FILE ../../rtl/verilog/or1200/rtl/verilog/or1200_fpu.v
set_global_assignment -name VERILOG_FILE ../../rtl/verilog/or1200/rtl/verilog/or1200_spram.v
set_global_assignment -name VERILOG_FILE ../../rtl/verilog/or1200/rtl/verilog/or1200_spram_32_bw.v
set_global_assignment -name VERILOG_FILE ../../rtl/verilog/or1200/rtl/verilog/or1200_dpram.v
/altera/jtag_top.prj
0,0 → 1,3
set_global_assignment -name SEARCH_PATH /home/javieralso/repos/personales/Proyectos/svn/opencores/minsoc/setup/minsoc/prj/../rtl/verilog/adv_debug_sys/Hardware/jtag/tap/rtl/verilog
set_global_assignment -name VERILOG_FILE /home/javieralso/repos/personales/Proyectos/svn/opencores/minsoc/setup/minsoc/prj/../rtl/verilog/adv_debug_sys/Hardware/jtag/tap/rtl/verilog/tap_top.v
set_global_assignment -name VERILOG_FILE /home/javieralso/repos/personales/Proyectos/svn/opencores/minsoc/setup/minsoc/prj/../rtl/verilog/adv_debug_sys/Hardware/jtag/tap/rtl/verilog/tap_defines.v
/altera/minsoc_bench.prj
0,0 → 1,11
set_global_assignment -name SEARCH_PATH ../../backend
set_global_assignment -name SEARCH_PATH ../../bench/verilog
set_global_assignment -name SEARCH_PATH ../../bench/verilog/vpi
set_global_assignment -name SEARCH_PATH ../../bench/verilog/sim_lib
set_global_assignment -name SEARCH_PATH ../../rtl/verilog
set_global_assignment -name VERILOG_FILE ../../backend/minsoc_bench_defines.v
set_global_assignment -name VERILOG_FILE ../../bench/verilog/minsoc_bench.v
set_global_assignment -name VERILOG_FILE ../../bench/verilog/minsoc_memory_model.v
set_global_assignment -name VERILOG_FILE ../../bench/verilog/vpi/dbg_comm_vpi.v
set_global_assignment -name VERILOG_FILE ../../bench/verilog/sim_lib/fpga_memory_primitives.v
set_global_assignment -name VERILOG_FILE ../../rtl/verilog/timescale.v
/altera/minsoc_top.prj
1,8 → 1,22
set_global_assignment -name VERILOG_FILE ../rtl/verilog/timescale.v
set_global_assignment -name VERILOG_FILE ../rtl/verilog/minsoc_top.v
set_global_assignment -name VERILOG_FILE ../rtl/verilog/minsoc_tc_top.v
set_global_assignment -name VERILOG_FILE ../rtl/verilog/minsoc_onchip_ram_top.v
set_global_assignment -name VERILOG_FILE ../rtl/verilog/minsoc_onchip_ram.v
set_global_assignment -name VERILOG_FILE ../rtl/verilog/minsoc_clock_manager.v
set_global_assignment -name VERILOG_FILE ../rtl/verilog/altera_pll.v
set_global_assignment -name SEARCH_PATH ../backend/
set_global_assignment -name SEARCH_PATH ../../backend
set_global_assignment -name SEARCH_PATH ../../rtl/verilog
set_global_assignment -name SEARCH_PATH ../../rtl/verilog/minsoc_startup
set_global_assignment -name SEARCH_PATH ../../rtl/verilog/or1200/rtl/verilog
set_global_assignment -name SEARCH_PATH ../../rtl/verilog/adv_debug_sys/Hardware/adv_dbg_if/rtl/verilog
set_global_assignment -name SEARCH_PATH ../../rtl/verilog/ethmac/rtl/verilog
set_global_assignment -name SEARCH_PATH ../../rtl/verilog/uart16550/rtl/verilog
set_global_assignment -name VERILOG_FILE ../../backend/minsoc_defines.v
set_global_assignment -name VERILOG_FILE ../../rtl/verilog/timescale.v
set_global_assignment -name VERILOG_FILE ../../rtl/verilog/minsoc_top.v
set_global_assignment -name VERILOG_FILE ../../rtl/verilog/minsoc_tc_top.v
set_global_assignment -name VERILOG_FILE ../../rtl/verilog/minsoc_onchip_ram.v
set_global_assignment -name VERILOG_FILE ../../rtl/verilog/minsoc_onchip_ram_top.v
set_global_assignment -name VERILOG_FILE ../../rtl/verilog/minsoc_clock_manager.v
set_global_assignment -name VERILOG_FILE ../../rtl/verilog/altera_pll.v
set_global_assignment -name VERILOG_FILE ../../rtl/verilog/xilinx_dcm.v
set_global_assignment -name VERILOG_FILE ../../rtl/verilog/minsoc_xilinx_internal_jtag.v
set_global_assignment -name VERILOG_FILE ../../rtl/verilog/minsoc_startup/spi_top.v
set_global_assignment -name VERILOG_FILE ../../rtl/verilog/minsoc_startup/spi_defines.v
set_global_assignment -name VERILOG_FILE ../../rtl/verilog/minsoc_startup/spi_shift.v
set_global_assignment -name VERILOG_FILE ../../rtl/verilog/minsoc_startup/spi_clgen.v
set_global_assignment -name VERILOG_FILE ../../rtl/verilog/minsoc_startup/OR1K_startup_generic.v
/altera/uart_top.prj
0,0 → 1,12
set_global_assignment -name SEARCH_PATH ../../rtl/verilog/uart16550/rtl/verilog
set_global_assignment -name VERILOG_FILE ../../rtl/verilog/uart16550/rtl/verilog/uart_top.v
set_global_assignment -name VERILOG_FILE ../../rtl/verilog/uart16550/rtl/verilog/uart_sync_flops.v
set_global_assignment -name VERILOG_FILE ../../rtl/verilog/uart16550/rtl/verilog/uart_transmitter.v
set_global_assignment -name VERILOG_FILE ../../rtl/verilog/uart16550/rtl/verilog/uart_debug_if.v
set_global_assignment -name VERILOG_FILE ../../rtl/verilog/uart16550/rtl/verilog/uart_wb.v
set_global_assignment -name VERILOG_FILE ../../rtl/verilog/uart16550/rtl/verilog/uart_receiver.v
set_global_assignment -name VERILOG_FILE ../../rtl/verilog/uart16550/rtl/verilog/uart_tfifo.v
set_global_assignment -name VERILOG_FILE ../../rtl/verilog/uart16550/rtl/verilog/uart_regs.v
set_global_assignment -name VERILOG_FILE ../../rtl/verilog/uart16550/rtl/verilog/uart_rfifo.v
set_global_assignment -name VERILOG_FILE ../../rtl/verilog/uart16550/rtl/verilog/uart_defines.v
set_global_assignment -name VERILOG_FILE ../../rtl/verilog/uart16550/rtl/verilog/raminfr.v
/altera/adbg_top.prj
0,0 → 1,11
set_global_assignment -name SEARCH_PATH ../../rtl/verilog/adv_debug_sys/Hardware/adv_dbg_if/rtl/verilog
set_global_assignment -name VERILOG_FILE ../../rtl/verilog/adv_debug_sys/Hardware/adv_dbg_if/rtl/verilog/adbg_wb_biu.v
set_global_assignment -name VERILOG_FILE ../../rtl/verilog/adv_debug_sys/Hardware/adv_dbg_if/rtl/verilog/adbg_wb_module.v
set_global_assignment -name VERILOG_FILE ../../rtl/verilog/adv_debug_sys/Hardware/adv_dbg_if/rtl/verilog/adbg_or1k_module.v
set_global_assignment -name VERILOG_FILE ../../rtl/verilog/adv_debug_sys/Hardware/adv_dbg_if/rtl/verilog/adbg_wb_defines.v
set_global_assignment -name VERILOG_FILE ../../rtl/verilog/adv_debug_sys/Hardware/adv_dbg_if/rtl/verilog/adbg_defines.v
set_global_assignment -name VERILOG_FILE ../../rtl/verilog/adv_debug_sys/Hardware/adv_dbg_if/rtl/verilog/adbg_crc32.v
set_global_assignment -name VERILOG_FILE ../../rtl/verilog/adv_debug_sys/Hardware/adv_dbg_if/rtl/verilog/adbg_or1k_biu.v
set_global_assignment -name VERILOG_FILE ../../rtl/verilog/adv_debug_sys/Hardware/adv_dbg_if/rtl/verilog/adbg_or1k_defines.v
set_global_assignment -name VERILOG_FILE ../../rtl/verilog/adv_debug_sys/Hardware/adv_dbg_if/rtl/verilog/adbg_or1k_status_reg.v
set_global_assignment -name VERILOG_FILE ../../rtl/verilog/adv_debug_sys/Hardware/adv_dbg_if/rtl/verilog/adbg_top.v
/altera/ethmac.prj
1,0 → 26,11
set_global_assignment -name SEARCH_PATH ../rtl/verilog/ethmac/rtl/verilog
set_global_assignment -name SEARCH_PATH ../../rtl/verilog/ethmac/rtl/verilog
set_global_assignment -name VERILOG_FILE ../../rtl/verilog/ethmac/rtl/verilog/eth_cop.v
set_global_assignment -name VERILOG_FILE ../../rtl/verilog/ethmac/rtl/verilog/eth_registers.v
set_global_assignment -name VERILOG_FILE ../../rtl/verilog/ethmac/rtl/verilog/eth_rxethmac.v
set_global_assignment -name VERILOG_FILE ../../rtl/verilog/ethmac/rtl/verilog/eth_miim.v
set_global_assignment -name VERILOG_FILE ../../rtl/verilog/ethmac/rtl/verilog/ethmac.v
set_global_assignment -name VERILOG_FILE ../../rtl/verilog/ethmac/rtl/verilog/eth_rxaddrcheck.v
set_global_assignment -name VERILOG_FILE ../../rtl/verilog/ethmac/rtl/verilog/eth_outputcontrol.v
set_global_assignment -name VERILOG_FILE ../../rtl/verilog/ethmac/rtl/verilog/eth_rxstatem.v
set_global_assignment -name VERILOG_FILE ../../rtl/verilog/ethmac/rtl/verilog/eth_txethmac.v
set_global_assignment -name VERILOG_FILE ../../rtl/verilog/ethmac/rtl/verilog/eth_wishbone.v
set_global_assignment -name VERILOG_FILE ../../rtl/verilog/ethmac/rtl/verilog/eth_maccontrol.v
set_global_assignment -name VERILOG_FILE ../../rtl/verilog/ethmac/rtl/verilog/eth_txstatem.v
set_global_assignment -name VERILOG_FILE ../../rtl/verilog/ethmac/rtl/verilog/ethmac_defines.v
set_global_assignment -name VERILOG_FILE ../../rtl/verilog/ethmac/rtl/verilog/eth_spram_256x32.v
set_global_assignment -name VERILOG_FILE ../../rtl/verilog/ethmac/rtl/verilog/eth_shiftreg.v
set_global_assignment -name VERILOG_FILE ../../rtl/verilog/ethmac/rtl/verilog/eth_clockgen.v
set_global_assignment -name VERILOG_FILE ../../rtl/verilog/ethmac/rtl/verilog/eth_crc.v
set_global_assignment -name VERILOG_FILE ../../rtl/verilog/ethmac/rtl/verilog/eth_rxcounters.v
set_global_assignment -name VERILOG_FILE ../../rtl/verilog/ethmac/rtl/verilog/eth_macstatus.v
set_global_assignment -name VERILOG_FILE ../../rtl/verilog/ethmac/rtl/verilog/eth_random.v
set_global_assignment -name VERILOG_FILE ../../rtl/verilog/ethmac/rtl/verilog/eth_register.v
set_global_assignment -name VERILOG_FILE ../../rtl/verilog/ethmac/rtl/verilog/eth_fifo.v
set_global_assignment -name VERILOG_FILE ../../rtl/verilog/ethmac/rtl/verilog/eth_receivecontrol.v
set_global_assignment -name VERILOG_FILE ../../rtl/verilog/ethmac/rtl/verilog/eth_transmitcontrol.v
set_global_assignment -name VERILOG_FILE ../../rtl/verilog/ethmac/rtl/verilog/eth_txcounters.v
/Makefile
10,11 → 10,12
SIMULATION_FILES = $(addprefix $(SIMULATION_DIR)/, $(addsuffix .src, $(basename $(PROJECTS))))
XILINX_PRJ_FILES = $(addprefix $(XILINX_DIR)/, $(addsuffix .prj, $(basename $(PROJECTS))))
XILINX_XST_FILES = $(addprefix $(XILINX_DIR)/, $(addsuffix .xst, $(basename $(PROJECTS))))
ALTERA_PRJ_FILES = $(addprefix $(ALTERA_DIR)/, $(addsuffix .prj, $(basename $(PROJECTS))))
 
all: $(SIMULATION_DIR)/minsoc.src $(XILINX_PRJ_FILES) $(XILINX_XST_FILES)
all: $(SIMULATION_DIR)/minsoc.src $(XILINX_PRJ_FILES) $(XILINX_XST_FILES) $(ALTERA_PRJ_FILES)
 
clean:
rm -rf $(SIMULATION_DIR)/*.src $(XILINX_DIR)/*.prj $(XILINX_DIR)/*.xst
rm -rf $(SIMULATION_DIR)/*.src $(XILINX_DIR)/*.prj $(XILINX_DIR)/*.xst $(ALTERA_DIR)/*.prj
 
$(XILINX_DIR)/minsoc_top.xst: $(SRC_DIR)/minsoc_top.prj
bash $(SCRIPTS_DIR)/xilinxxst.sh $^ $@ minsoc_top.prj minsoc_top topmodule
28,6 → 29,9
$(XILINX_DIR)/%.prj: $(SRC_DIR)/%.prj
bash $(SCRIPTS_DIR)/xilinxprj.sh $^ $@
 
$(ALTERA_DIR)/%.prj: $(SRC_DIR)/%.prj
bash $(SCRIPTS_DIR)/altprj.sh $^ $@
 
$(SIMULATION_DIR)/minsoc.src: $(SIMULATION_FILES)
cat $(SIMULATION_FILES) > $(SIMULATION_DIR)/minsoc.src
 

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